Skip to content
Permalink

Comparing changes

This is a direct comparison between two commits made in this repository or its related repositories. View the default comparison for this range or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: xdslproject/xdsl
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 9f8f818f92911a48dd8dfe1b38653d1167817a8e
Choose a base ref
..
head repository: xdslproject/xdsl
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 6afbf6af0f34cc262a720f9c72c201a144a95488
Choose a head ref
3 changes: 3 additions & 0 deletions .github/workflows/update-lockfile-bot.yml
Original file line number Diff line number Diff line change
@@ -2,6 +2,9 @@ name: Update Lockfile Bot

on:
workflow_dispatch:
pull_request:
branches:
- 'dependabot/**'

permissions:
contents: write
4 changes: 2 additions & 2 deletions docs/marimo/linalg_snitch.py
Original file line number Diff line number Diff line change
@@ -499,7 +499,7 @@ def _(TypedPtr, a_shape, b_shape, c_shape, ctx, mo, riscv_module):
riscv_c_shaped = ShapedArray(TypedPtr.new_float64([0.0] * c_len), c_shape)

riscv_op_counter = OpCounter()
riscv_interpreter = Interpreter(riscv_module, listener=riscv_op_counter)
riscv_interpreter = Interpreter(riscv_module, listeners=(riscv_op_counter,))

register_implementations(riscv_interpreter, ctx, include_wgpu=False, include_onnx=False)

@@ -549,7 +549,7 @@ def _(
):
snitch_op_counter = OpCounter()
snitch_interpreter = Interpreter(
snitch_stream_module, listener=snitch_op_counter
snitch_stream_module, listeners=(snitch_op_counter,)
)

snitch_c_shaped = ShapedArray(TypedPtr.new_float64([0.0] * c_len), c_shape)
2 changes: 1 addition & 1 deletion pyproject.toml
Original file line number Diff line number Diff line change
@@ -26,7 +26,7 @@ dev = [
"lit<19.0.0",
"marimo==0.10.9",
"pre-commit==4.0.1",
"ruff==0.8.5",
"ruff==0.8.6",
"asv<0.7",
"nbconvert>=7.7.2,<8.0.0",
"textual-dev==1.7.0",
5 changes: 3 additions & 2 deletions tests/filecheck/mlir-conversion/with-mlir/mlir_opt_fail.mlir
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// RUN: xdsl-opt %s -p mlir-opt{arguments='--hello','--mlir-print-op-generic'} --print-op-generic --verify-diagnostics | filecheck %s
// RUN: xdsl-opt %s -p mlir-opt{arguments='--hello','--mlir-print-op-generic'} --print-op-generic --verify-diagnostics | filecheck %s --check-prefix=CHECK-PARSING
// RUN: xdsl-opt %s -p mlir-opt[this-probably-will-never-be-an-MLIR-pass-name] --print-op-generic --verify-diagnostics | filecheck %s
// RUN: xdsl-opt %s -p mlir-opt{executable='"false"'} --print-op-generic --verify-diagnostics | filecheck %s

@@ -10,4 +10,5 @@
}) : () -> ()


// CHECK: Error executing mlir-opt pass
// CHECK-PARSING: Error parsing mlir-opt pass output
// CHECK: Error executing mlir-opt pass
12 changes: 12 additions & 0 deletions tests/filecheck/transforms/memref-to-dsd.mlir
Original file line number Diff line number Diff line change
@@ -120,6 +120,18 @@ builtin.module {
// CHECK-NEXT: %31 = memref.load %b[%13] : memref<510xf32>
// CHECK-NEXT: "test.op"(%31) : (f32) -> ()

%39 = memref.alloc() {"alignment" = 64 : i64} : memref<3x64xf32>
%40 = "memref.subview"(%39, %0) <{"operandSegmentSizes" = array<i32: 1, 1, 0, 0>, "static_offsets" = array<i64: 2, -9223372036854775808>, "static_sizes" = array<i64: 1, 32>, "static_strides" = array<i64: 1, 1>}> : (memref<3x64xf32>, index) -> memref<32xf32, strided<[1], offset: ?>>

// CHECK-NEXT: %32 = "csl.zeros"() : () -> memref<3x64xf32>
// CHECK-NEXT: %33 = arith.constant 3 : i16
// CHECK-NEXT: %34 = arith.constant 64 : i16
// CHECK-NEXT: %35 = "csl.get_mem_dsd"(%32, %33, %34) : (memref<3x64xf32>, i16, i16) -> !csl<dsd mem4d_dsd>
// CHECK-NEXT: %36 = arith.constant 32 : i16
// CHECK-NEXT: %37 = "csl.get_mem_dsd"(%32, %36) <{"tensor_access" = affine_map<(d0) -> (2, d0)>}> : (memref<3x64xf32>, i16) -> !csl<dsd mem1d_dsd>
// CHECK-NEXT: %38 = arith.index_cast %0 : index to si16
// CHECK-NEXT: %39 = "csl.increment_dsd_offset"(%37, %38) <{"elem_type" = f32}> : (!csl<dsd mem1d_dsd>, si16) -> !csl<dsd mem1d_dsd>

}) {sym_name = "program"} : () -> ()
}
// CHECK-NEXT: }) {"sym_name" = "program"} : () -> ()
2 changes: 1 addition & 1 deletion tests/interpreters/test_scf_interpreter.py
Original file line number Diff line number Diff line change
@@ -81,7 +81,7 @@ def false_region():

def test_tracer():
tracer = OpCounter()
interpreter = Interpreter(sum_to_for_op.clone(), listener=tracer)
interpreter = Interpreter(sum_to_for_op.clone(), listeners=(tracer,))
interpreter.register_implementations(ScfFunctions())
interpreter.register_implementations(FuncFunctions())
interpreter.register_implementations(ArithFunctions())
31 changes: 31 additions & 0 deletions tests/test_interpreter.py
Original file line number Diff line number Diff line change
@@ -243,3 +243,34 @@ def index_value(

assert i.value_for_attribute(IntegerAttr(1, i32), i32) == 1
assert i.value_for_attribute(IntegerAttr(1, i32), index) == 1


def test_combined_listener():
@dataclass
class DemoListener(Interpreter.Listener):
strings: list[str]
key: str

def will_interpret_op(self, op: Operation, args: PythonValues) -> None:
self.strings.append("will " + self.key)

def did_interpret_op(self, op: Operation, results: PythonValues) -> None:
self.strings.append("did " + self.key)

@dataclass
@register_impls
class TestFunctions(InterpreterFunctions):
@impl(test.TestOp)
def run_test(
self, interpreter: Interpreter, op: test.TestOp, args: PythonValues
) -> PythonValues:
return ()

strings: list[str] = []
da = DemoListener(strings, "A")
db = DemoListener(strings, "B")
interpreter = Interpreter(ModuleOp([]), listeners=(da, db))
interpreter.register_implementations(TestFunctions())
interpreter.run_op(test.TestOp())

assert strings == ["will A", "will B", "did A", "did B"]
Loading