ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
+
+
+
+Function Pointers
+
+ - ADC1_2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- BusFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel5_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel6_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DMA1_Channel7_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- DebugMon_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI15_10_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI4_IRQHandler from nvic.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- EXTI9_5_IRQHandler from nvic.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- FLASH_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- HardFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C1_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C1_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C2_ER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- I2C2_EV_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- MemManage_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- NMI_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- PVD_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- PendSV_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RCC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RTCAlarm_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- RTC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- Reset_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SPI1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SPI2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SVC_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SysTick_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- SystemInit from system_stm32f10x.o(.text) referenced from startup_stm32f10x_md.o(.text)
+
- TAMPER_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_BRK_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_CC_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM1_UP_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- TIM4_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USART1_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USART2_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USART3_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USBWakeUp_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- USB_LP_CAN1_RX0_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- UsageFault_Handler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- WWDG_IRQHandler from startup_stm32f10x_md.o(.text) referenced from startup_stm32f10x_md.o(RESET)
+
- __main from __main.o(!!!main) referenced from startup_stm32f10x_md.o(.text)
+
+
+
+Global Symbols
+
+__main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main))
+
[Calls]
- >> __rt_entry
+
- >> __scatterload
+
+
+__scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter))
+
[Called By]
+
+__scatterload_rt2 (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
[Calls]
+
+__scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
+
__scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
+
__scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
+
[Calls]
+
[Called By]
+
+__scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
+
+
__rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
+
[Called By]
+
+__rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
+
+
__rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
+
+
__rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
+
+
__rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
+
+
__rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
+
+
__rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
+
+
__rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002))
+
+
__rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
+
+
__rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
+
+
__rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
+
+
__rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
+
+
__rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
+
+
__rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
+
+
__rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
+
+
__rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
+
+
__rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
+
+
__rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
+
+
__rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033))
+
+
__rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
+
+
__rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
+
+
__rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
+
+
__rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
+
[Called By]
+
+__rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
+
+
__rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007))
+
+
__rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F))
+
+
__rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010))
+
+
__rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A))
+
+
__rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
+
+
__rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
+
+
__rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000))
+
[Called By]
- >> __main
+
- >> __scatterload_rt2
+
+
+__rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
+
+
__rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap
+
+
[Calls]- >> __user_setup_stackheap
+
+
+__rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A))
+
[Calls]
+
+__rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
+
+
__rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
+
[Stack]
- Max Depth = 200 + Unknown Stack Size
+
- Call Chain = __rt_entry_main ⇒ main ⇒ Show_Str ⇒ LCD_ShowChar ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]
+
+__rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
+
+
__rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
+
[Called By]
+
+__rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003))
+
[Calls]
+
+__rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
+
+
__rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
+
[Calls]
+
+WFI_SET (Thumb, 2 bytes, Stack size 0 bytes, sys.o(.emb_text), UNUSED)
+
[Called By]
+
+INTX_DISABLE (Thumb, 2 bytes, Stack size 0 bytes, sys.o(.emb_text), UNUSED)
+
+
INTX_ENABLE (Thumb, 2 bytes, Stack size 0 bytes, sys.o(.emb_text), UNUSED)
+
+
MSR_MSP (Thumb, 6 bytes, Stack size 0 bytes, sys.o(.emb_text), UNUSED)
+
+
main (Thumb, 630 bytes, Stack size 16 bytes, main.o(.text))
+
[Stack]
- Max Depth = 200
- Call Chain = main ⇒ Show_Str ⇒ LCD_ShowChar ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> delay_init
+
- >> SystemInit
+
- >> Show_Str
+
- >> NVIC_Configuration
+
- >> LCD_ShowNum
+
- >> LCD_ShowChar
+
- >> LCD_Init
+
- >> LCD_DrawRectangle
+
- >> LCD_DrawLine
+
- >> LCD_Clear
+
- >> KEYPAD4x4_Read
+
- >> KEYPAD4x4_Init
+
- >> KEYPAD4x4_INT_INIT
+
+
[Called By]
+
+GUI_DrawPoint (Thumb, 24 bytes, Stack size 16 bytes, gui.o(.text), UNUSED)
+
[Calls]
- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetCursor
+
+
[Called By]
+
+LCD_Fill (Thumb, 114 bytes, Stack size 40 bytes, gui.o(.text), UNUSED)
+
[Calls]
- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetWindows
+
+
[Called By]- >> LCD_DrawFillRectangle
+
+
+LCD_DrawLine (Thumb, 176 bytes, Stack size 72 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 128
- Call Chain = LCD_DrawLine ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]
+
[Called By]- >> LCD_DrawRectangle
+
- >> main
+
+
+LCD_DrawRectangle (Thumb, 64 bytes, Stack size 24 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 152
- Call Chain = LCD_DrawRectangle ⇒ LCD_DrawLine ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]
+
[Called By]
+
+LCD_DrawFillRectangle (Thumb, 30 bytes, Stack size 24 bytes, gui.o(.text), UNUSED)
+
[Calls]
+
+_draw_circle_8 (Thumb, 132 bytes, Stack size 24 bytes, gui.o(.text), UNUSED)
+
[Calls]
+
[Called By]
+
+gui_circle (Thumb, 154 bytes, Stack size 56 bytes, gui.o(.text), UNUSED)
+
[Calls]
+
+LCD_ShowChar (Thumb, 280 bytes, Stack size 64 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 120
- Call Chain = LCD_ShowChar ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WR_DATA
+
- >> LCD_SetWindows
+
- >> LCD_DrawPoint
+
+
[Called By]- >> LCD_ShowString
+
- >> Show_Str
+
- >> LCD_ShowNum
+
- >> main
+
+
+LCD_ShowNum2412 (Thumb, 240 bytes, Stack size 48 bytes, gui.o(.text), UNUSED)
+
[Calls]
+
+LCD_ShowString (Thumb, 94 bytes, Stack size 40 bytes, gui.o(.text), UNUSED)
+
[Calls]
+
+mypow (Thumb, 22 bytes, Stack size 8 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = mypow
+
+
[Called By]
+
+LCD_ShowNum (Thumb, 168 bytes, Stack size 64 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 184
- Call Chain = LCD_ShowNum ⇒ LCD_ShowChar ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> mypow
+
- >> LCD_ShowChar
+
+
[Called By]
+
+GUI_DrawFont16 (Thumb, 252 bytes, Stack size 48 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 104
- Call Chain = GUI_DrawFont16 ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetWindows
+
- >> LCD_DrawPoint
+
+
[Called By]
+
+GUI_DrawFont24 (Thumb, 268 bytes, Stack size 48 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 104
- Call Chain = GUI_DrawFont24 ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetWindows
+
- >> LCD_DrawPoint
+
+
[Called By]
+
+GUI_DrawFont32 (Thumb, 276 bytes, Stack size 48 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 104
- Call Chain = GUI_DrawFont32 ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetWindows
+
- >> LCD_DrawPoint
+
+
[Called By]
+
+Show_Str (Thumb, 268 bytes, Stack size 64 bytes, gui.o(.text))
+
[Stack]
- Max Depth = 184
- Call Chain = Show_Str ⇒ LCD_ShowChar ⇒ LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> GUI_DrawFont32
+
- >> GUI_DrawFont24
+
- >> GUI_DrawFont16
+
- >> LCD_ShowChar
+
+
[Called By]- >> Gui_StrCenter
+
- >> main
+
+
+Gui_StrCenter (Thumb, 68 bytes, Stack size 64 bytes, gui.o(.text), UNUSED)
+
[Calls]
+
+Gui_Drawbmp16 (Thumb, 90 bytes, Stack size 32 bytes, gui.o(.text), UNUSED)
+
[Calls]
- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetWindows
+
+
+delay_init (Thumb, 52 bytes, Stack size 8 bytes, delay.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = delay_init
+
+
[Calls]- >> SysTick_CLKSourceConfig
+
+
[Called By]
+
+delay_ms (Thumb, 56 bytes, Stack size 0 bytes, delay.o(.text))
+
[Called By]
- >> LCD_RESET
+
- >> LCD_Init
+
- >> KEYPAD4x4_Read
+
+
+delay_us (Thumb, 56 bytes, Stack size 0 bytes, delay.o(.text), UNUSED)
+
+
SystemInit (Thumb, 78 bytes, Stack size 8 bytes, system_stm32f10x.o(.text))
+
[Stack]
- Max Depth = 28
- Call Chain = SystemInit ⇒ SetSysClock ⇒ SetSysClockTo72
+
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(.text)
+
+SystemCoreClockUpdate (Thumb, 142 bytes, Stack size 8 bytes, system_stm32f10x.o(.text), UNUSED)
+
+
MY_NVIC_SetVectorTable (Thumb, 12 bytes, Stack size 0 bytes, sys.o(.text), UNUSED)
+
[Called By]
+
+MY_NVIC_PriorityGroupConfig (Thumb, 36 bytes, Stack size 0 bytes, sys.o(.text), UNUSED)
+
[Called By]
+
+MY_NVIC_Init (Thumb, 146 bytes, Stack size 32 bytes, sys.o(.text), UNUSED)
+
[Calls]
- >> MY_NVIC_PriorityGroupConfig
+
+
+Ex_NVIC_Config (Thumb, 146 bytes, Stack size 16 bytes, sys.o(.text), UNUSED)
+
+
MYRCC_DeInit (Thumb, 90 bytes, Stack size 4 bytes, sys.o(.text), UNUSED)
+
[Calls]
- >> MY_NVIC_SetVectorTable
+
+
[Called By]
+
+Sys_Standby (Thumb, 68 bytes, Stack size 8 bytes, sys.o(.text), UNUSED)
+
[Calls]
+
+Sys_Soft_Reset (Thumb, 12 bytes, Stack size 0 bytes, sys.o(.text), UNUSED)
+
+
JTAG_Set (Thumb, 42 bytes, Stack size 0 bytes, sys.o(.text), UNUSED)
+
+
Stm32_Clock_Init (Thumb, 134 bytes, Stack size 12 bytes, sys.o(.text), UNUSED)
+
[Calls]
+
+NVIC_Configuration (Thumb, 12 bytes, Stack size 8 bytes, sys.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = NVIC_Configuration
+
+
[Calls]- >> NVIC_PriorityGroupConfig
+
+
[Called By]
+
+SPIv_WriteData (Thumb, 60 bytes, Stack size 0 bytes, lcd.o(.text), UNUSED)
+
+
SPI_WriteByte (Thumb, 76 bytes, Stack size 0 bytes, lcd.o(.text))
+
[Called By]
- >> LCD_WR_REG
+
- >> LCD_WR_DATA_16Bit
+
- >> LCD_WR_DATA
+
+
+SPI_SetSpeed (Thumb, 38 bytes, Stack size 0 bytes, lcd.o(.text), UNUSED)
+
+
SPI2_Init (Thumb, 208 bytes, Stack size 32 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 56
- Call Chain = SPI2_Init ⇒ GPIO_Init
+
+
[Calls]- >> SPI_Init
+
- >> SPI_Cmd
+
- >> RCC_APB1PeriphClockCmd
+
- >> GPIO_ResetBits
+
- >> RCC_APB2PeriphClockCmd
+
- >> GPIO_Init
+
+
[Called By]
+
+LCD_WR_REG (Thumb, 38 bytes, Stack size 8 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = LCD_WR_REG
+
+
[Calls]
+
[Called By]- >> LCD_WriteRAM_Prepare
+
- >> LCD_WriteReg
+
- >> LCD_SetWindows
+
- >> LCD_Init
+
+
+LCD_WR_DATA (Thumb, 40 bytes, Stack size 8 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = LCD_WR_DATA
+
+
[Calls]
+
[Called By]- >> LCD_WriteReg
+
- >> LCD_SetWindows
+
- >> LCD_ShowChar
+
- >> LCD_Init
+
+
+LCD_WR_DATA_16Bit (Thumb, 50 bytes, Stack size 8 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = LCD_WR_DATA_16Bit
+
+
[Calls]
+
[Called By]- >> LCD_DrawPoint
+
- >> Gui_Drawbmp16
+
- >> GUI_DrawFont32
+
- >> GUI_DrawFont24
+
- >> GUI_DrawFont16
+
- >> LCD_Fill
+
- >> GUI_DrawPoint
+
- >> LCD_Clear
+
+
+LCD_WriteReg (Thumb, 20 bytes, Stack size 12 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = LCD_WriteReg ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WR_REG
+
- >> LCD_WR_DATA
+
+
[Called By]
+
+LCD_WriteRAM_Prepare (Thumb, 12 bytes, Stack size 4 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 12
- Call Chain = LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]
+
[Called By]
+
+LCD_SetWindows (Thumb, 88 bytes, Stack size 20 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 32
- Call Chain = LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WriteRAM_Prepare
+
- >> LCD_WR_REG
+
- >> LCD_WR_DATA
+
+
[Called By]- >> LCD_SetCursor
+
- >> Gui_Drawbmp16
+
- >> GUI_DrawFont32
+
- >> GUI_DrawFont24
+
- >> GUI_DrawFont16
+
- >> LCD_Fill
+
- >> LCD_ShowChar
+
- >> LCD_Clear
+
+
+LCD_SetCursor (Thumb, 20 bytes, Stack size 12 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 44
- Call Chain = LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]
+
[Called By]- >> LCD_DrawPoint
+
- >> GUI_DrawPoint
+
+
+LCD_DrawPoint (Thumb, 24 bytes, Stack size 12 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 56
- Call Chain = LCD_DrawPoint ⇒ LCD_SetCursor ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetCursor
+
+
[Called By]- >> GUI_DrawFont32
+
- >> GUI_DrawFont24
+
- >> GUI_DrawFont16
+
- >> LCD_ShowNum2412
+
- >> LCD_ShowChar
+
- >> LCD_DrawLine
+
+
+LCD_GPIOInit (Thumb, 42 bytes, Stack size 8 bytes, lcd.o(.text), UNUSED)
+
[Calls]
- >> RCC_APB2PeriphClockCmd
+
- >> GPIO_Init
+
+
+LCD_RESET (Thumb, 16 bytes, Stack size 8 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = LCD_RESET
+
+
[Calls]
+
[Called By]
+
+LCD_SetParam (Thumb, 36 bytes, Stack size 4 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 24
- Call Chain = LCD_SetParam ⇒ LCD_WriteReg ⇒ LCD_WR_REG
+
+
[Calls]
+
[Called By]
+
+LCD_Init (Thumb, 570 bytes, Stack size 8 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 64
- Call Chain = LCD_Init ⇒ SPI2_Init ⇒ GPIO_Init
+
+
[Calls]- >> LCD_SetParam
+
- >> LCD_RESET
+
- >> LCD_WR_REG
+
- >> SPI2_Init
+
- >> delay_ms
+
- >> LCD_WR_DATA
+
+
[Called By]
+
+LCD_Clear (Thumb, 68 bytes, Stack size 16 bytes, lcd.o(.text))
+
[Stack]
- Max Depth = 48
- Call Chain = LCD_Clear ⇒ LCD_SetWindows ⇒ LCD_WriteRAM_Prepare ⇒ LCD_WR_REG
+
+
[Calls]- >> LCD_WR_DATA_16Bit
+
- >> LCD_SetWindows
+
+
[Called By]
+
+KEYPAD4x4_Init (Thumb, 66 bytes, Stack size 8 bytes, keypad4x4.o(.text))
+
[Stack]
- Max Depth = 32
- Call Chain = KEYPAD4x4_Init ⇒ GPIO_Init
+
+
[Calls]- >> GPIO_SetBits
+
- >> GPIO_ResetBits
+
- >> GPIO_Init
+
+
[Called By]- >> KEYPAD4x4_Read
+
- >> main
+
+
+KEYPAD4x4_Init2 (Thumb, 66 bytes, Stack size 8 bytes, keypad4x4.o(.text))
+
[Stack]
- Max Depth = 32
- Call Chain = KEYPAD4x4_Init2 ⇒ GPIO_Init
+
+
[Calls]- >> GPIO_SetBits
+
- >> GPIO_ResetBits
+
- >> GPIO_Init
+
+
[Called By]
+
+KEYPAD4x4_Read (Thumb, 330 bytes, Stack size 16 bytes, keypad4x4.o(.text))
+
[Stack]
- Max Depth = 48
- Call Chain = KEYPAD4x4_Read ⇒ KEYPAD4x4_Init2 ⇒ GPIO_Init
+
+
[Calls]- >> GPIO_ReadInputData
+
- >> KEYPAD4x4_Init2
+
- >> GPIO_ReadInputDataBit
+
- >> delay_ms
+
- >> KEYPAD4x4_Init
+
+
[Called By]
+
+KEYPAD4x4_INT_INIT (Thumb, 276 bytes, Stack size 16 bytes, nvic.o(.text))
+
[Stack]
- Max Depth = 32
- Call Chain = KEYPAD4x4_INT_INIT ⇒ NVIC_Init
+
+
[Calls]- >> NVIC_Init
+
- >> GPIO_EXTILineConfig
+
- >> EXTI_Init
+
- >> RCC_APB2PeriphClockCmd
+
+
[Called By]
+
+EXTI4_IRQHandler (Thumb, 24 bytes, Stack size 8 bytes, nvic.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = EXTI4_IRQHandler
+
+
[Calls]- >> EXTI_GetITStatus
+
- >> EXTI_ClearITPendingBit
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 64 bytes, Stack size 8 bytes, nvic.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = EXTI9_5_IRQHandler
+
+
[Calls]- >> EXTI_GetITStatus
+
- >> EXTI_ClearITPendingBit
+
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_md.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+USB_LP_CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_md.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_md.o(RESET)
+
+__user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f10x_md.o(.text))
+
[Called By]
- >> __user_setup_stackheap
+
+
+NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(.text))
+
[Called By]
+
+NVIC_Init (Thumb, 100 bytes, Stack size 16 bytes, misc.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = NVIC_Init
+
+
[Called By]
+
+NVIC_SetVectorTable (Thumb, 14 bytes, Stack size 0 bytes, misc.o(.text), UNUSED)
+
+
NVIC_SystemLPConfig (Thumb, 34 bytes, Stack size 0 bytes, misc.o(.text), UNUSED)
+
+
SysTick_CLKSourceConfig (Thumb, 40 bytes, Stack size 0 bytes, misc.o(.text))
+
[Called By]
+
+GPIO_DeInit (Thumb, 172 bytes, Stack size 8 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
[Calls]
- >> RCC_APB2PeriphResetCmd
+
+
+GPIO_AFIODeInit (Thumb, 20 bytes, Stack size 8 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
[Calls]
- >> RCC_APB2PeriphResetCmd
+
+
+GPIO_Init (Thumb, 278 bytes, Stack size 24 bytes, stm32f10x_gpio.o(.text))
+
[Stack]
- Max Depth = 24
- Call Chain = GPIO_Init
+
+
[Called By]- >> KEYPAD4x4_Init2
+
- >> LCD_GPIOInit
+
- >> SPI2_Init
+
- >> KEYPAD4x4_Init
+
+
+GPIO_StructInit (Thumb, 16 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_ReadInputDataBit (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text))
+
[Called By]
+
+GPIO_ReadInputData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text))
+
[Called By]
+
+GPIO_ReadOutputDataBit (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_ReadOutputData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text))
+
[Called By]
- >> KEYPAD4x4_Init2
+
- >> KEYPAD4x4_Init
+
+
+GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text))
+
[Called By]
- >> KEYPAD4x4_Init2
+
- >> SPI2_Init
+
- >> KEYPAD4x4_Init
+
+
+GPIO_WriteBit (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_Write (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_PinLockConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_EventOutputConfig (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_EventOutputCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_PinRemapConfig (Thumb, 138 bytes, Stack size 20 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
GPIO_EXTILineConfig (Thumb, 66 bytes, Stack size 12 bytes, stm32f10x_gpio.o(.text))
+
[Stack]
- Max Depth = 12
- Call Chain = GPIO_EXTILineConfig
+
+
[Called By]
+
+GPIO_ETH_MediaInterfaceConfig (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_gpio.o(.text), UNUSED)
+
+
RCC_DeInit (Thumb, 64 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_HSEConfig (Thumb, 70 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_GetFlagStatus (Thumb, 56 bytes, Stack size 8 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
[Called By]
- >> RCC_WaitForHSEStartUp
+
+
+RCC_WaitForHSEStartUp (Thumb, 56 bytes, Stack size 16 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
[Calls]
+
+RCC_AdjustHSICalibrationValue (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_HSICmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_PLLConfig (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_PLLCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_SYSCLKConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_GetSYSCLKSource (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_HCLKConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_PCLK1Config (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_PCLK2Config (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_ITConfig (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_USBCLKConfig (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_ADCCLKConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_LSEConfig (Thumb, 50 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_LSICmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_RTCCLKConfig (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_RTCCLKCmd (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_GetClocksFreq (Thumb, 192 bytes, Stack size 12 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
[Called By]
+
+RCC_AHBPeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_APB2PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text))
+
[Called By]
- >> LCD_GPIOInit
+
- >> SPI2_Init
+
- >> KEYPAD4x4_INT_INIT
+
+
+RCC_APB1PeriphClockCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text))
+
[Called By]
+
+RCC_APB2PeriphResetCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
[Called By]
- >> SPI_I2S_DeInit
+
- >> GPIO_AFIODeInit
+
- >> GPIO_DeInit
+
+
+RCC_APB1PeriphResetCmd (Thumb, 26 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
[Called By]
+
+RCC_BackupResetCmd (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_ClockSecuritySystemCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_MCOConfig (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_ClearFlag (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_GetITStatus (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
RCC_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(.text), UNUSED)
+
+
SPI_I2S_DeInit (Thumb, 76 bytes, Stack size 8 bytes, stm32f10x_spi.o(.text), UNUSED)
+
[Calls]
- >> RCC_APB1PeriphResetCmd
+
- >> RCC_APB2PeriphResetCmd
+
+
+SPI_Init (Thumb, 60 bytes, Stack size 8 bytes, stm32f10x_spi.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = SPI_Init
+
+
[Called By]
+
+I2S_Init (Thumb, 226 bytes, Stack size 56 bytes, stm32f10x_spi.o(.text), UNUSED)
+
[Calls]
+
+SPI_StructInit (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
I2S_StructInit (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text))
+
[Called By]
+
+I2S_Cmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_ITConfig (Thumb, 32 bytes, Stack size 12 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_DMACmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_ReceiveData (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_NSSInternalSoftwareConfig (Thumb, 30 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_SSOutputCmd (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_DataSizeConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_TransmitCRC (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_CalculateCRC (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_GetCRC (Thumb, 16 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_GetCRCPolynomial (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_BiDirectionalLineConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_GetFlagStatus (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_ClearFlag (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_GetITStatus (Thumb, 52 bytes, Stack size 20 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
SPI_I2S_ClearITPendingBit (Thumb, 20 bytes, Stack size 8 bytes, stm32f10x_spi.o(.text), UNUSED)
+
+
EXTI_DeInit (Thumb, 28 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text), UNUSED)
+
+
EXTI_Init (Thumb, 142 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text))
+
[Called By]
+
+EXTI_StructInit (Thumb, 16 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text), UNUSED)
+
+
EXTI_GenerateSWInterrupt (Thumb, 16 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text), UNUSED)
+
+
EXTI_GetFlagStatus (Thumb, 22 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text), UNUSED)
+
+
EXTI_ClearFlag (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text), UNUSED)
+
+
EXTI_GetITStatus (Thumb, 34 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text))
+
[Called By]
- >> EXTI9_5_IRQHandler
+
- >> EXTI4_IRQHandler
+
+
+EXTI_ClearITPendingBit (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_exti.o(.text))
+
[Called By]
- >> EXTI9_5_IRQHandler
+
- >> EXTI4_IRQHandler
+
+
+strlen (Thumb, 62 bytes, Stack size 8 bytes, strlen.o(.text), UNUSED)
+
[Called By]
+
+__use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __user_setup_stackheap
+
+
[Calls]- >> __user_perproc_libspace
+
- >> __user_initial_stackheap
+
+
[Called By]
+
+exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = exit
+
+
[Calls]
+
[Called By]
+
+__user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+
+
__user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
+
[Called By]
- >> __user_setup_stackheap
+
+
+__user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+
+
_sys_exit (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text))
+
[Called By]
+
+__I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+
+
__use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+
+
__semihosting_library_function (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED)
+
+
+Local Symbols
+
+SetSysClockTo72 (Thumb, 214 bytes, Stack size 12 bytes, system_stm32f10x.o(.text))
+
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
+
+
[Called By]
+
+SetSysClock (Thumb, 8 bytes, Stack size 8 bytes, system_stm32f10x.o(.text))
+
[Stack]
- Max Depth = 20
- Call Chain = SetSysClock ⇒ SetSysClockTo72
+
+
[Calls]
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.lnp" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.lnp"
new file mode 100644
index 0000000..b6715a6
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.lnp"
@@ -0,0 +1,24 @@
+--cpu Cortex-M3
+"..\obj\main.o"
+"..\obj\gui.o"
+"..\obj\delay.o"
+"..\obj\system_stm32f10x.o"
+"..\obj\sys.o"
+"..\obj\key.o"
+"..\obj\lcd.o"
+"..\obj\myiic.o"
+"..\obj\24cxx.o"
+"..\obj\keypad4x4.o"
+"..\obj\nvic.o"
+"..\obj\core_cm3.o"
+"..\obj\startup_stm32f10x_md.o"
+"..\obj\misc.o"
+"..\obj\stm32f10x_gpio.o"
+"..\obj\stm32f10x_rcc.o"
+"..\obj\stm32f10x_spi.o"
+"..\obj\stm32f10x_usart.o"
+"..\obj\stm32f10x_exti.o"
+--strict --scatter "..\OBJ\TOUCH.sct"
+--summary_stderr --info summarysizes --map --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\TOUCH.map" -o ..\OBJ\TOUCH.axf
\ No newline at end of file
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.plg" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.plg"
new file mode 100644
index 0000000..c22af5e
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.plg"
@@ -0,0 +1,181 @@
+
+
+
+礦ision Build Log
+Project:
+E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\USER\TFT_Demo.uvproj
+Project File Date: 08/04/2015
+
+Output:
+Rebuild target 'Target 1'
+compiling main.c...
+compiling GUI.c...
+compiling delay.c...
+compiling system_stm32f10x.c...
+compiling key.c...
+compiling lcd.c...
+compiling myiic.c...
+compiling 24cxx.c...
+compiling core_cm3.c...
+assembling startup_stm32f10x_md.s...
+compiling misc.c...
+compiling stm32f10x_gpio.c...
+compiling stm32f10x_rcc.c...
+compiling stm32f10x_spi.c...
+compiling stm32f10x_usart.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Rebuild target 'Target 1'
+compiling main.c...
+compiling GUI.c...
+compiling delay.c...
+compiling system_stm32f10x.c...
+compiling key.c...
+compiling lcd.c...
+compiling myiic.c...
+compiling 24cxx.c...
+compiling core_cm3.c...
+assembling startup_stm32f10x_md.s...
+compiling misc.c...
+compiling stm32f10x_gpio.c...
+compiling stm32f10x_rcc.c...
+compiling stm32f10x_spi.c...
+compiling stm32f10x_usart.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Rebuild target 'Target 1'
+compiling main.c...
+compiling GUI.c...
+compiling delay.c...
+compiling system_stm32f10x.c...
+compiling key.c...
+compiling lcd.c...
+compiling myiic.c...
+compiling 24cxx.c...
+compiling core_cm3.c...
+assembling startup_stm32f10x_md.s...
+compiling misc.c...
+compiling stm32f10x_gpio.c...
+compiling stm32f10x_rcc.c...
+compiling stm32f10x_spi.c...
+compiling stm32f10x_usart.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+compiling main.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+compiling main.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Rebuild target 'Target 1'
+compiling main.c...
+compiling GUI.c...
+compiling delay.c...
+compiling system_stm32f10x.c...
+compiling key.c...
+compiling lcd.c...
+compiling myiic.c...
+compiling 24cxx.c...
+compiling core_cm3.c...
+assembling startup_stm32f10x_md.s...
+compiling misc.c...
+compiling stm32f10x_gpio.c...
+compiling stm32f10x_rcc.c...
+compiling stm32f10x_spi.c...
+compiling stm32f10x_usart.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Rebuild target 'Target 1'
+compiling main.c...
+compiling GUI.c...
+compiling delay.c...
+compiling system_stm32f10x.c...
+compiling key.c...
+compiling lcd.c...
+compiling myiic.c...
+compiling 24cxx.c...
+compiling core_cm3.c...
+assembling startup_stm32f10x_md.s...
+compiling misc.c...
+compiling stm32f10x_gpio.c...
+compiling stm32f10x_rcc.c...
+compiling stm32f10x_spi.c...
+compiling stm32f10x_usart.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Rebuild target 'Target 1'
+compiling main.c...
+compiling GUI.c...
+compiling delay.c...
+compiling system_stm32f10x.c...
+compiling key.c...
+compiling lcd.c...
+compiling myiic.c...
+compiling 24cxx.c...
+compiling core_cm3.c...
+assembling startup_stm32f10x_md.s...
+compiling misc.c...
+compiling stm32f10x_gpio.c...
+compiling stm32f10x_rcc.c...
+compiling stm32f10x_spi.c...
+compiling stm32f10x_usart.c...
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
+Build target 'Target 1'
+linking...
+Program Size: Code=8350 RO-data=4618 RW-data=52 ZI-data=1652
+FromELF: creating hex file...
+"..\OBJ\TOUCH.axf" - 0 Errors, 0 Warning(s).
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.sct" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.sct"
new file mode 100644
index 0000000..c26b647
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.sct"
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00005000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.tra" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.tra"
new file mode 100644
index 0000000..3c35ec9
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/TOUCH.tra"
@@ -0,0 +1,35 @@
+*** Creating Trace Output File '..\OBJ\TOUCH.tra' Ok.
+### Preparing for ADS-LD.
+### Creating ADS-LD Command Line
+### List of Objects: adding '"..\obj\main.o"'
+### List of Objects: adding '"..\obj\test.o"'
+### List of Objects: adding '"..\obj\gui.o"'
+### List of Objects: adding '"..\obj\delay.o"'
+### List of Objects: adding '"..\obj\system_stm32f10x.o"'
+### List of Objects: adding '"..\obj\key.o"'
+### List of Objects: adding '"..\obj\lcd.o"'
+### List of Objects: adding '"..\obj\myiic.o"'
+### List of Objects: adding '"..\obj\24cxx.o"'
+### List of Objects: adding '"..\obj\touch.o"'
+### List of Objects: adding '"..\obj\core_cm3.o"'
+### List of Objects: adding '"..\obj\startup_stm32f10x_md.o"'
+### List of Objects: adding '"..\obj\misc.o"'
+### List of Objects: adding '"..\obj\stm32f10x_gpio.o"'
+### List of Objects: adding '"..\obj\stm32f10x_rcc.o"'
+### List of Objects: adding '"..\obj\stm32f10x_spi.o"'
+### List of Objects: adding '"..\obj\stm32f10x_usart.o"'
+### ADS-LD Command completed:
+--cpu Cortex-M3 "..\obj\main.o" "..\obj\test.o" "..\obj\gui.o" "..\obj\delay.o" "..\obj\system_stm32f10x.o" "..\obj\key.o" "..\obj\lcd.o" "..\obj\myiic.o" "..\obj\24cxx.o" "..\obj\touch.o" "..\obj\core_cm3.o" "..\obj\startup_stm32f10x_md.o" "..\obj\misc.o" "..\obj\stm32f10x_gpio.o" "..\obj\stm32f10x_rcc.o" "..\obj\stm32f10x_spi.o" "..\obj\stm32f10x_usart.o" --strict --scatter "..\OBJ\TOUCH.sct"
+--autoat --summary_stderr --info summarysizes --map --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+ --list ".\TOUCH.map" -o "..\OBJ\TOUCH.axf"### Preparing Environment (PrepEnvAds)
+### ADS-LD Output File: '..\OBJ\TOUCH.axf'
+### ADS-LD Command File: '..\OBJ\TOUCH.lnp'
+### Checking for dirty Components...
+### Creating CmdFile '..\OBJ\TOUCH.lnp', Handle=0x000003A0
+### Writing '.lnp' file
+### ADS-LD Command file '..\OBJ\TOUCH.lnp' is ready.
+### ADS-LD: About to start ADS-LD Thread.
+### ADS-LD: executed with 0 errors
+### Updating obj list
+### LDADS_file() completed.
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.crf"
new file mode 100644
index 0000000..ce82945
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.d"
new file mode 100644
index 0000000..ab24b0f
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.d"
@@ -0,0 +1,2 @@
+..\obj\core_cm3.o: ..\CORE\core_cm3.c
+..\obj\core_cm3.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.o"
new file mode 100644
index 0000000..a7d4b42
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/core_cm3.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.crf"
new file mode 100644
index 0000000..db02b04
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.d"
new file mode 100644
index 0000000..c4e93b1
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.d"
@@ -0,0 +1,31 @@
+..\obj\delay.o: ..\SYSTEM\delay\delay.c
+..\obj\delay.o: ..\SYSTEM\delay\delay.h
+..\obj\delay.o: ..\USER\stm32f10x.h
+..\obj\delay.o: ..\CORE\core_cm3.h
+..\obj\delay.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\delay.o: ..\USER\system_stm32f10x.h
+..\obj\delay.o: ..\USER\stm32f10x_conf.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\delay.o: ..\USER\stm32f10x.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\delay.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.o"
new file mode 100644
index 0000000..f8ea54d
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/delay.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.crf"
new file mode 100644
index 0000000..07d51d3
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.d"
new file mode 100644
index 0000000..9d89280
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.d"
@@ -0,0 +1,37 @@
+..\obj\gui.o: GUI.c
+..\obj\gui.o: ..\HARDWARE\LCD\lcd.h
+..\obj\gui.o: ..\SYSTEM\sys\sys.h
+..\obj\gui.o: ..\USER\stm32f10x.h
+..\obj\gui.o: ..\CORE\core_cm3.h
+..\obj\gui.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\gui.o: ..\USER\system_stm32f10x.h
+..\obj\gui.o: ..\USER\stm32f10x_conf.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\gui.o: ..\USER\stm32f10x.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\gui.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\gui.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
+..\obj\gui.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
+..\obj\gui.o: ..\HARDWARE\LCD\font.h
+..\obj\gui.o: ..\SYSTEM\delay\delay.h
+..\obj\gui.o: gui.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.o"
new file mode 100644
index 0000000..9799c98
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/gui.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.crf"
new file mode 100644
index 0000000..dd5f991
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.d"
new file mode 100644
index 0000000..fc96e29
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.d"
@@ -0,0 +1,33 @@
+..\obj\key.o: ..\HARDWARE\KEY\key.c
+..\obj\key.o: ..\HARDWARE\KEY\key.h
+..\obj\key.o: ..\SYSTEM\sys\sys.h
+..\obj\key.o: ..\USER\stm32f10x.h
+..\obj\key.o: ..\CORE\core_cm3.h
+..\obj\key.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\key.o: ..\USER\system_stm32f10x.h
+..\obj\key.o: ..\USER\stm32f10x_conf.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\key.o: ..\USER\stm32f10x.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\key.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\key.o: ..\SYSTEM\delay\delay.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.o"
new file mode 100644
index 0000000..157045f
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/key.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.crf"
new file mode 100644
index 0000000..4908802
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.d"
new file mode 100644
index 0000000..e99b08e
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.d"
@@ -0,0 +1,33 @@
+..\obj\keypad4x4.o: ..\HARDWARE\KEYPAD4x4\KEYPAD4x4.c
+..\obj\keypad4x4.o: ..\HARDWARE\KEYPAD4x4\KEYPAD4x4.h
+..\obj\keypad4x4.o: ..\SYSTEM\sys\sys.h
+..\obj\keypad4x4.o: ..\USER\stm32f10x.h
+..\obj\keypad4x4.o: ..\CORE\core_cm3.h
+..\obj\keypad4x4.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\keypad4x4.o: ..\USER\system_stm32f10x.h
+..\obj\keypad4x4.o: ..\USER\stm32f10x_conf.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\keypad4x4.o: ..\USER\stm32f10x.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\keypad4x4.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\keypad4x4.o: ..\SYSTEM\delay\delay.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.o"
new file mode 100644
index 0000000..ad44612
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/keypad4x4.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.crf"
new file mode 100644
index 0000000..7a4fd5c
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.d"
new file mode 100644
index 0000000..4f01be7
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.d"
@@ -0,0 +1,36 @@
+..\obj\lcd.o: ..\HARDWARE\LCD\lcd.c
+..\obj\lcd.o: ..\HARDWARE\LCD\lcd.h
+..\obj\lcd.o: ..\SYSTEM\sys\sys.h
+..\obj\lcd.o: ..\USER\stm32f10x.h
+..\obj\lcd.o: ..\CORE\core_cm3.h
+..\obj\lcd.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\lcd.o: ..\USER\system_stm32f10x.h
+..\obj\lcd.o: ..\USER\stm32f10x_conf.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\lcd.o: ..\USER\stm32f10x.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\lcd.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\lcd.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
+..\obj\lcd.o: ..\SYSTEM\usart\usart.h
+..\obj\lcd.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+..\obj\lcd.o: ..\SYSTEM\delay\delay.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.o"
new file mode 100644
index 0000000..5daac2e
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/lcd.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.crf"
new file mode 100644
index 0000000..8cd432b
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.d"
new file mode 100644
index 0000000..010f5fc
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.d"
@@ -0,0 +1,39 @@
+..\obj\main.o: main.c
+..\obj\main.o: ..\SYSTEM\delay\delay.h
+..\obj\main.o: ..\USER\stm32f10x.h
+..\obj\main.o: ..\CORE\core_cm3.h
+..\obj\main.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\main.o: ..\USER\system_stm32f10x.h
+..\obj\main.o: ..\USER\stm32f10x_conf.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\main.o: ..\USER\stm32f10x.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\main.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\main.o: ..\SYSTEM\sys\sys.h
+..\obj\main.o: ..\HARDWARE\LCD\lcd.h
+..\obj\main.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
+..\obj\main.o: ..\HARDWARE\TOUCH\touch.h
+..\obj\main.o: gui.h
+..\obj\main.o: test.h
+..\obj\main.o: ..\HARDWARE\KEYPAD4x4\KEYPAD4x4.h
+..\obj\main.o: ..\SYSTEM\nvic\NVIC.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.o"
new file mode 100644
index 0000000..7e06304
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/main.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.crf"
new file mode 100644
index 0000000..f81d099
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.d"
new file mode 100644
index 0000000..3c4a054
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.d"
@@ -0,0 +1,31 @@
+..\obj\misc.o: ..\STM32F10x_FWLib\src\misc.c
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\misc.o: ..\USER\stm32f10x.h
+..\obj\misc.o: ..\CORE\core_cm3.h
+..\obj\misc.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\misc.o: ..\USER\system_stm32f10x.h
+..\obj\misc.o: ..\USER\stm32f10x_conf.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\misc.o: ..\USER\stm32f10x.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\misc.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.o"
new file mode 100644
index 0000000..b1256b1
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/misc.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.crf"
new file mode 100644
index 0000000..928ca2f
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.d"
new file mode 100644
index 0000000..c3d07c3
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.d"
@@ -0,0 +1,33 @@
+..\obj\myiic.o: ..\HARDWARE\IIC\myiic.c
+..\obj\myiic.o: ..\HARDWARE\IIC\myiic.h
+..\obj\myiic.o: ..\SYSTEM\sys\sys.h
+..\obj\myiic.o: ..\USER\stm32f10x.h
+..\obj\myiic.o: ..\CORE\core_cm3.h
+..\obj\myiic.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\myiic.o: ..\USER\system_stm32f10x.h
+..\obj\myiic.o: ..\USER\stm32f10x_conf.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\myiic.o: ..\USER\stm32f10x.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\myiic.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\myiic.o: ..\SYSTEM\delay\delay.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.o"
new file mode 100644
index 0000000..eb2de6e
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/myiic.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.crf"
new file mode 100644
index 0000000..c00565e
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.d"
new file mode 100644
index 0000000..a986f76
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.d"
@@ -0,0 +1,32 @@
+..\obj\nvic.o: ..\SYSTEM\nvic\NVIC.c
+..\obj\nvic.o: ..\SYSTEM\nvic\NVIC.h
+..\obj\nvic.o: ..\SYSTEM\sys\sys.h
+..\obj\nvic.o: ..\USER\stm32f10x.h
+..\obj\nvic.o: ..\CORE\core_cm3.h
+..\obj\nvic.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\nvic.o: ..\USER\system_stm32f10x.h
+..\obj\nvic.o: ..\USER\stm32f10x_conf.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\nvic.o: ..\USER\stm32f10x.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\nvic.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.o"
new file mode 100644
index 0000000..cfad492
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/nvic.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/startup_stm32f10x_md.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/startup_stm32f10x_md.d"
new file mode 100644
index 0000000..d4c85a2
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/startup_stm32f10x_md.d"
@@ -0,0 +1 @@
+..\obj\startup_stm32f10x_md.o: ..\CORE\startup_stm32f10x_md.s
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/startup_stm32f10x_md.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/startup_stm32f10x_md.o"
new file mode 100644
index 0000000..8b7dde9
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/startup_stm32f10x_md.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.crf"
new file mode 100644
index 0000000..2e891a0
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.d"
new file mode 100644
index 0000000..54a755a
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.d"
@@ -0,0 +1,31 @@
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\src\stm32f10x_exti.c
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\stm32f10x_exti.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_exti.o: ..\CORE\core_cm3.h
+..\obj\stm32f10x_exti.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\stm32f10x_exti.o: ..\USER\system_stm32f10x.h
+..\obj\stm32f10x_exti.o: ..\USER\stm32f10x_conf.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\stm32f10x_exti.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.o"
new file mode 100644
index 0000000..7ba365b
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_exti.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.crf"
new file mode 100644
index 0000000..cf25da8
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.d"
new file mode 100644
index 0000000..adbbc26
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.d"
@@ -0,0 +1,31 @@
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\src\stm32f10x_gpio.c
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\stm32f10x_gpio.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_gpio.o: ..\CORE\core_cm3.h
+..\obj\stm32f10x_gpio.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\stm32f10x_gpio.o: ..\USER\system_stm32f10x.h
+..\obj\stm32f10x_gpio.o: ..\USER\stm32f10x_conf.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\stm32f10x_gpio.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.o"
new file mode 100644
index 0000000..e9d0c51
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_gpio.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.crf"
new file mode 100644
index 0000000..4f93623
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.d"
new file mode 100644
index 0000000..05808f2
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.d"
@@ -0,0 +1,31 @@
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\src\stm32f10x_rcc.c
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\stm32f10x_rcc.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_rcc.o: ..\CORE\core_cm3.h
+..\obj\stm32f10x_rcc.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\stm32f10x_rcc.o: ..\USER\system_stm32f10x.h
+..\obj\stm32f10x_rcc.o: ..\USER\stm32f10x_conf.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\stm32f10x_rcc.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.o"
new file mode 100644
index 0000000..abb2893
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_rcc.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.crf"
new file mode 100644
index 0000000..e7840db
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.d"
new file mode 100644
index 0000000..80ace10
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.d"
@@ -0,0 +1,31 @@
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\src\stm32f10x_spi.c
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\stm32f10x_spi.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_spi.o: ..\CORE\core_cm3.h
+..\obj\stm32f10x_spi.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\stm32f10x_spi.o: ..\USER\system_stm32f10x.h
+..\obj\stm32f10x_spi.o: ..\USER\stm32f10x_conf.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\stm32f10x_spi.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.o"
new file mode 100644
index 0000000..78a949f
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_spi.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.crf"
new file mode 100644
index 0000000..4fa1b0a
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.d"
new file mode 100644
index 0000000..4b0ac83
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.d"
@@ -0,0 +1,31 @@
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\src\stm32f10x_tim.c
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\OBJ\stm32f10x_tim.o: ..\USER\stm32f10x.h
+..\OBJ\stm32f10x_tim.o: ..\CORE\core_cm3.h
+..\OBJ\stm32f10x_tim.o: d:\Keil\ARM\RV31\INC\stdint.h
+..\OBJ\stm32f10x_tim.o: ..\USER\system_stm32f10x.h
+..\OBJ\stm32f10x_tim.o: ..\USER\stm32f10x_conf.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\OBJ\stm32f10x_tim.o: ..\USER\stm32f10x.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\OBJ\stm32f10x_tim.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.o"
new file mode 100644
index 0000000..8aebe29
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_tim.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.crf"
new file mode 100644
index 0000000..489040b
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.d"
new file mode 100644
index 0000000..2e275d9
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.d"
@@ -0,0 +1,31 @@
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\src\stm32f10x_usart.c
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\stm32f10x_usart.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_usart.o: ..\CORE\core_cm3.h
+..\obj\stm32f10x_usart.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\stm32f10x_usart.o: ..\USER\system_stm32f10x.h
+..\obj\stm32f10x_usart.o: ..\USER\stm32f10x_conf.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\stm32f10x_usart.o: ..\USER\stm32f10x.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.o"
new file mode 100644
index 0000000..8d0927e
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/stm32f10x_usart.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.crf"
new file mode 100644
index 0000000..1987fb3
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.d"
new file mode 100644
index 0000000..ce840e5
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.d"
@@ -0,0 +1,31 @@
+..\obj\sys.o: ..\SYSTEM\sys\sys.c
+..\obj\sys.o: ..\SYSTEM\sys\sys.h
+..\obj\sys.o: ..\USER\stm32f10x.h
+..\obj\sys.o: ..\CORE\core_cm3.h
+..\obj\sys.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\sys.o: ..\USER\system_stm32f10x.h
+..\obj\sys.o: ..\USER\stm32f10x_conf.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\sys.o: ..\USER\stm32f10x.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\sys.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.o"
new file mode 100644
index 0000000..c5e5292
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/sys.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.crf"
new file mode 100644
index 0000000..5c65901
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.d"
new file mode 100644
index 0000000..2029ce5
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.d"
@@ -0,0 +1,30 @@
+..\obj\system_stm32f10x.o: system_stm32f10x.c
+..\obj\system_stm32f10x.o: stm32f10x.h
+..\obj\system_stm32f10x.o: ..\CORE\core_cm3.h
+..\obj\system_stm32f10x.o: D:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+..\obj\system_stm32f10x.o: system_stm32f10x.h
+..\obj\system_stm32f10x.o: stm32f10x_conf.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\system_stm32f10x.o: ..\USER\stm32f10x.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\system_stm32f10x.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.o"
new file mode 100644
index 0000000..f056b7b
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/system_stm32f10x.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.crf"
new file mode 100644
index 0000000..89e9622
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.d"
new file mode 100644
index 0000000..8d504be
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.d"
@@ -0,0 +1,40 @@
+..\OBJ\test.o: test.c
+..\OBJ\test.o: ..\HARDWARE\LCD\lcd.h
+..\OBJ\test.o: ..\SYSTEM\sys\sys.h
+..\OBJ\test.o: ..\USER\stm32f10x.h
+..\OBJ\test.o: ..\CORE\core_cm3.h
+..\OBJ\test.o: d:\Keil\ARM\RV31\INC\stdint.h
+..\OBJ\test.o: ..\USER\system_stm32f10x.h
+..\OBJ\test.o: ..\USER\stm32f10x_conf.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\OBJ\test.o: ..\USER\stm32f10x.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\OBJ\test.o: ..\STM32F10x_FWLib\inc\misc.h
+..\OBJ\test.o: d:\Keil\ARM\RV31\INC\stdlib.h
+..\OBJ\test.o: ..\SYSTEM\delay\delay.h
+..\OBJ\test.o: gui.h
+..\OBJ\test.o: test.h
+..\OBJ\test.o: ..\HARDWARE\TOUCH\touch.h
+..\OBJ\test.o: ..\HARDWARE\KEY\key.h
+..\OBJ\test.o: ..\HARDWARE\LED\led.h
+..\OBJ\test.o: pic.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.o"
new file mode 100644
index 0000000..a1504ba
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/test.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.__i" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.__i"
new file mode 100644
index 0000000..7febf5c
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.__i"
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O0 --apcs=interwork -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\EXTI -I..\HARDWARE\WDG -I..\HARDWARE\TIMER -I..\HARDWARE\PWM -I..\HARDWARE\LCD -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\TSensor -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\TOUCH -I "d:\Keil\ARM\INC" -I "d:\Keil\ARM\INC\ST\STM32F10x" -DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o "..\OBJ\timer.o" --omf_browse "..\OBJ\timer.crf" --depend "..\OBJ\timer.d" "..\HARDWARE\TIMER\timer.c"
\ No newline at end of file
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.crf"
new file mode 100644
index 0000000..90dd249
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.d"
new file mode 100644
index 0000000..497078a
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.d"
@@ -0,0 +1,35 @@
+..\OBJ\timer.o: ..\HARDWARE\TIMER\timer.c
+..\OBJ\timer.o: ..\HARDWARE\TIMER\timer.h
+..\OBJ\timer.o: ..\SYSTEM\sys\sys.h
+..\OBJ\timer.o: ..\USER\stm32f10x.h
+..\OBJ\timer.o: ..\CORE\core_cm3.h
+..\OBJ\timer.o: d:\Keil\ARM\RV31\INC\stdint.h
+..\OBJ\timer.o: ..\USER\system_stm32f10x.h
+..\OBJ\timer.o: ..\USER\stm32f10x_conf.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\OBJ\timer.o: ..\USER\stm32f10x.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\OBJ\timer.o: ..\STM32F10x_FWLib\inc\misc.h
+..\OBJ\timer.o: ..\HARDWARE\LED\led.h
+..\OBJ\timer.o: ..\SYSTEM\usart\usart.h
+..\OBJ\timer.o: d:\Keil\ARM\RV31\INC\stdio.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.o"
new file mode 100644
index 0000000..a79f56b
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/timer.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.crf"
new file mode 100644
index 0000000..cfbeb3b
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.d"
new file mode 100644
index 0000000..0eb32c9
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.d"
@@ -0,0 +1,39 @@
+..\obj\touch.o: ..\HARDWARE\TOUCH\touch.c
+..\obj\touch.o: ..\HARDWARE\TOUCH\touch.h
+..\obj\touch.o: ..\SYSTEM\sys\sys.h
+..\obj\touch.o: ..\USER\stm32f10x.h
+..\obj\touch.o: ..\CORE\core_cm3.h
+..\obj\touch.o: C:\Keil\ARM\ARMCC\bin\..\include\stdint.h
+..\obj\touch.o: ..\USER\system_stm32f10x.h
+..\obj\touch.o: ..\USER\stm32f10x_conf.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+..\obj\touch.o: ..\USER\stm32f10x.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+..\obj\touch.o: ..\STM32F10x_FWLib\inc\misc.h
+..\obj\touch.o: ..\HARDWARE\LCD\lcd.h
+..\obj\touch.o: C:\Keil\ARM\ARMCC\bin\..\include\stdlib.h
+..\obj\touch.o: ..\SYSTEM\delay\delay.h
+..\obj\touch.o: C:\Keil\ARM\ARMCC\bin\..\include\math.h
+..\obj\touch.o: ..\HARDWARE\24CXX\24cxx.h
+..\obj\touch.o: ..\HARDWARE\IIC\myiic.h
+..\obj\touch.o: ..\USER\gui.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.o"
new file mode 100644
index 0000000..5250c3f
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/OBJ/touch.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/misc.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/misc.h"
new file mode 100644
index 0000000..9a6bd07
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/misc.h"
@@ -0,0 +1,220 @@
+/**
+ ******************************************************************************
+ * @file misc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete STM32 Devices IRQ Channels list, please
+ refer to stm32f10x.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_adc.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_adc.h"
new file mode 100644
index 0000000..c465d33
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_adc.h"
@@ -0,0 +1,483 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
+ dual mode.
+ This parameter can be a value of @ref ADC_mode */
+
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC2) || \
+ ((PERIPH) == ADC3))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode
+ * @{
+ */
+
+#define ADC_Mode_Independent ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+ ((MODE) == ADC_Mode_RegInjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult) || \
+ ((MODE) == ADC_Mode_FastInterl) || \
+ ((MODE) == ADC_Mode_SlowInterl) || \
+ ((MODE) == ADC_Mode_AlterTrig))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+
+#define ADC_Channel_0 ((uint8_t)0x00)
+#define ADC_Channel_1 ((uint8_t)0x01)
+#define ADC_Channel_2 ((uint8_t)0x02)
+#define ADC_Channel_3 ((uint8_t)0x03)
+#define ADC_Channel_4 ((uint8_t)0x04)
+#define ADC_Channel_5 ((uint8_t)0x05)
+#define ADC_Channel_6 ((uint8_t)0x06)
+#define ADC_Channel_7 ((uint8_t)0x07)
+#define ADC_Channel_8 ((uint8_t)0x08)
+#define ADC_Channel_9 ((uint8_t)0x09)
+#define ADC_Channel_10 ((uint8_t)0x0A)
+#define ADC_Channel_11 ((uint8_t)0x0B)
+#define ADC_Channel_12 ((uint8_t)0x0C)
+#define ADC_Channel_13 ((uint8_t)0x0D)
+#define ADC_Channel_14 ((uint8_t)0x0E)
+#define ADC_Channel_15 ((uint8_t)0x0F)
+#define ADC_Channel_16 ((uint8_t)0x10)
+#define ADC_Channel_17 ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+ ((TIME) == ADC_SampleTime_7Cycles5) || \
+ ((TIME) == ADC_SampleTime_13Cycles5) || \
+ ((TIME) == ADC_SampleTime_28Cycles5) || \
+ ((TIME) == ADC_SampleTime_41Cycles5) || \
+ ((TIME) == ADC_SampleTime_55Cycles5) || \
+ ((TIME) == ADC_SampleTime_71Cycles5) || \
+ ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+ ((CHANNEL) == ADC_InjectedChannel_2) || \
+ ((CHANNEL) == ADC_InjectedChannel_3) || \
+ ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_IT_EOC ((uint16_t)0x0220)
+#define ADC_IT_AWD ((uint16_t)0x0140)
+#define ADC_IT_JEOC ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+ ((IT) == ADC_IT_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWD ((uint8_t)0x01)
+#define ADC_FLAG_EOC ((uint8_t)0x02)
+#define ADC_FLAG_JEOC ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)
+#define ADC_FLAG_STRT ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+ ((FLAG) == ADC_FLAG_STRT))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_offset
+ * @{
+ */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_length
+ * @{
+ */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_rank
+ * @{
+ */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_ADC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_bkp.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_bkp.h"
new file mode 100644
index 0000000..275c5e1
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_bkp.h"
@@ -0,0 +1,195 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the BKP firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup BKP
+ * @{
+ */
+
+/** @defgroup BKP_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Tamper_Pin_active_level
+ * @{
+ */
+
+#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+ ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
+ * @{
+ */
+
+#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+ ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+ * @}
+ */
+
+/** @defgroup Data_Backup_Register
+ * @{
+ */
+
+#define BKP_DR1 ((uint16_t)0x0004)
+#define BKP_DR2 ((uint16_t)0x0008)
+#define BKP_DR3 ((uint16_t)0x000C)
+#define BKP_DR4 ((uint16_t)0x0010)
+#define BKP_DR5 ((uint16_t)0x0014)
+#define BKP_DR6 ((uint16_t)0x0018)
+#define BKP_DR7 ((uint16_t)0x001C)
+#define BKP_DR8 ((uint16_t)0x0020)
+#define BKP_DR9 ((uint16_t)0x0024)
+#define BKP_DR10 ((uint16_t)0x0028)
+#define BKP_DR11 ((uint16_t)0x0040)
+#define BKP_DR12 ((uint16_t)0x0044)
+#define BKP_DR13 ((uint16_t)0x0048)
+#define BKP_DR14 ((uint16_t)0x004C)
+#define BKP_DR15 ((uint16_t)0x0050)
+#define BKP_DR16 ((uint16_t)0x0054)
+#define BKP_DR17 ((uint16_t)0x0058)
+#define BKP_DR18 ((uint16_t)0x005C)
+#define BKP_DR19 ((uint16_t)0x0060)
+#define BKP_DR20 ((uint16_t)0x0064)
+#define BKP_DR21 ((uint16_t)0x0068)
+#define BKP_DR22 ((uint16_t)0x006C)
+#define BKP_DR23 ((uint16_t)0x0070)
+#define BKP_DR24 ((uint16_t)0x0074)
+#define BKP_DR25 ((uint16_t)0x0078)
+#define BKP_DR26 ((uint16_t)0x007C)
+#define BKP_DR27 ((uint16_t)0x0080)
+#define BKP_DR28 ((uint16_t)0x0084)
+#define BKP_DR29 ((uint16_t)0x0088)
+#define BKP_DR30 ((uint16_t)0x008C)
+#define BKP_DR31 ((uint16_t)0x0090)
+#define BKP_DR32 ((uint16_t)0x0094)
+#define BKP_DR33 ((uint16_t)0x0098)
+#define BKP_DR34 ((uint16_t)0x009C)
+#define BKP_DR35 ((uint16_t)0x00A0)
+#define BKP_DR36 ((uint16_t)0x00A4)
+#define BKP_DR37 ((uint16_t)0x00A8)
+#define BKP_DR38 ((uint16_t)0x00AC)
+#define BKP_DR39 ((uint16_t)0x00B0)
+#define BKP_DR40 ((uint16_t)0x00B4)
+#define BKP_DR41 ((uint16_t)0x00B8)
+#define BKP_DR42 ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
+ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
+ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
+ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Functions
+ * @{
+ */
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_BKP_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_can.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_can.h"
new file mode 100644
index 0000000..d185aa2
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_can.h"
@@ -0,0 +1,697 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the CAN firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+ ((PERIPH) == CAN2))
+
+/**
+ * @brief CAN init structure definition
+ */
+
+typedef struct
+{
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
+ It ranges from 1 to 1024. */
+
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of
+ @ref CAN_operating_mode */
+
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of
+ @ref CAN_synchronisation_jump_width */
+
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
+ Segment 1. This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
+ Segment 2.
+ This parameter can be a value of
+ @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
+ communication mode. This parameter can be set
+ either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
+ management. This parameter can be set either
+ to ENABLE or DISABLE. */
+
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or
+ DISABLE. */
+
+ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
+ retransmission mode. This parameter can be
+ set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set either to ENABLE
+ or DISABLE. */
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+
+typedef struct
+{
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be transmitted. This parameter can be a value
+ of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will
+ be transmitted. This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be
+ transmitted. This parameter can be a value between
+ 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+ to 0xFF. */
+} CanTxMsg;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that
+ will be received. This parameter can be a value of
+ @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of
+ @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+ 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in
+ the mailbox passes through. This parameter can be a
+ value between 0 to 0xFF */
+} CanRxMsg;
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mode
+ * @{
+ */
+
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+ ((MODE) == CAN_Mode_LoopBack)|| \
+ ((MODE) == CAN_Mode_Silent) || \
+ ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+ * @}
+ */
+
+
+/**
+ * @defgroup CAN_Operating_Mode
+ * @{
+ */
+#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+ ((MODE) == CAN_OperatingMode_Normal)|| \
+ ((MODE) == CAN_OperatingMode_Sleep))
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Mode_Status
+ * @{
+ */
+
+#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#else
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+ ((MODE) == CAN_FilterMode_IdList))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+ ((SCALE) == CAN_FilterScale_32bit))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+ ((FIFO) == CAN_FilterFIFO1))
+/**
+ * @}
+ */
+
+/** @defgroup Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+ ((IDTYPE) == CAN_Id_Extended))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+
+#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+
+#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup CAN_Error_Code_constants
+ * @{
+ */
+
+#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
+#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
+#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
+#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
+#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
+#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
+#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
+#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
+#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
+#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
+#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
+ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+ * @}
+ */
+
+
+/** @defgroup CAN_interrupts
+ * @{
+ */
+
+
+
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0 CAN_IT_TME
+#define CAN_IT_RQCP1 CAN_IT_TME
+#define CAN_IT_RQCP2 CAN_IT_TME
+
+
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Legacy
+ * @{
+ */
+#define CANINITFAILED CAN_InitStatus_Failed
+#define CANINITOK CAN_InitStatus_Success
+#define CAN_FilterFIFO0 CAN_Filter_FIFO0
+#define CAN_FilterFIFO1 CAN_Filter_FIFO1
+#define CAN_ID_STD CAN_Id_Standard
+#define CAN_ID_EXT CAN_Id_Extended
+#define CAN_RTR_DATA CAN_RTR_Data
+#define CAN_RTR_REMOTE CAN_RTR_Remote
+#define CANTXFAILE CAN_TxStatus_Failed
+#define CANTXOK CAN_TxStatus_Ok
+#define CANTXPENDING CAN_TxStatus_Pending
+#define CAN_NO_MB CAN_TxStatus_NoMailBox
+#define CANSLEEPFAILED CAN_Sleep_Failed
+#define CANSLEEPOK CAN_Sleep_Ok
+#define CANWAKEUPFAILED CAN_WakeUp_Failed
+#define CANWAKEUPOK CAN_WakeUp_Ok
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions
+ * @{
+ */
+/* Function used to set the CAN configuration to the default reset state *****/
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* Transmit functions *********************************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* Receive functions **********************************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* Error management functions *************************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CAN_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_cec.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_cec.h"
new file mode 100644
index 0000000..7ce6896
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_cec.h"
@@ -0,0 +1,210 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_cec.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the CEC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CEC_H
+#define __STM32F10x_CEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CEC
+ * @{
+ */
+
+
+/** @defgroup CEC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief CEC Init structure definition
+ */
+typedef struct
+{
+ uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode.
+ This parameter can be a value of @ref CEC_BitTiming_Mode */
+ uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode.
+ This parameter can be a value of @ref CEC_BitPeriod_Mode */
+}CEC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CEC_BitTiming_Mode
+ * @{
+ */
+#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
+
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \
+ ((MODE) == CEC_BitTimingErrFreeMode))
+/**
+ * @}
+ */
+
+/** @defgroup CEC_BitPeriod_Mode
+ * @{
+ */
+#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \
+ ((MODE) == CEC_BitPeriodFlexibleMode))
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_interrupts_definition
+ * @{
+ */
+#define CEC_IT_TERR CEC_CSR_TERR
+#define CEC_IT_TBTRF CEC_CSR_TBTRF
+#define CEC_IT_RERR CEC_CSR_RERR
+#define CEC_IT_RBTF CEC_CSR_RBTF
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \
+ ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Own_Address
+ * @{
+ */
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Prescaler
+ * @{
+ */
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_flags_definition
+ * @{
+ */
+
+/**
+ * @brief ESR register flags
+ */
+#define CEC_FLAG_BTE ((uint32_t)0x10010000)
+#define CEC_FLAG_BPE ((uint32_t)0x10020000)
+#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)
+#define CEC_FLAG_SBE ((uint32_t)0x10080000)
+#define CEC_FLAG_ACKE ((uint32_t)0x10100000)
+#define CEC_FLAG_LINE ((uint32_t)0x10200000)
+#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)
+
+/**
+ * @brief CSR register flags
+ */
+#define CEC_FLAG_TEOM ((uint32_t)0x00000002)
+#define CEC_FLAG_TERR ((uint32_t)0x00000004)
+#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)
+#define CEC_FLAG_RSOM ((uint32_t)0x00000010)
+#define CEC_FLAG_REOM ((uint32_t)0x00000020)
+#define CEC_FLAG_RERR ((uint32_t)0x00000040)
+#define CEC_FLAG_RBTF ((uint32_t)0x00000080)
+
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \
+ ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \
+ ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \
+ ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \
+ ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \
+ ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \
+ ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CEC_Exported_Functions
+ * @{
+ */
+void CEC_DeInit(void);
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
+void CEC_Cmd(FunctionalState NewState);
+void CEC_ITConfig(FunctionalState NewState);
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);
+void CEC_SendDataByte(uint8_t Data);
+uint8_t CEC_ReceiveDataByte(void);
+void CEC_StartOfMessage(void);
+void CEC_EndOfMessageCmd(FunctionalState NewState);
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);
+void CEC_ClearFlag(uint32_t CEC_FLAG);
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);
+void CEC_ClearITPendingBit(uint16_t CEC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CEC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_crc.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_crc.h"
new file mode 100644
index 0000000..3362fca
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_crc.h"
@@ -0,0 +1,94 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the CRC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CRC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dac.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dac.h"
new file mode 100644
index 0000000..174773c
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dac.h"
@@ -0,0 +1,317 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in High-density devices*/
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in Connectivity line, Medium-density and Low-density Value Line devices */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
+ only in Medium-density and Low-density Value Line devices*/
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+ ((STATE) == DAC_OutputBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignment
+ * @{
+ */
+
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/** @defgroup DAC_interrupts_definition
+ * @{
+ */
+
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+ * @}
+ */
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+#endif
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DAC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h"
new file mode 100644
index 0000000..89ceb9a
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dbgmcu.h"
@@ -0,0 +1,119 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the DBGMCU
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DBGMCU_H
+#define __STM32F10x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBGMCU
+ * @{
+ */
+
+/** @defgroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
+#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
+#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
+#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
+#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
+#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
+#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
+#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
+#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
+#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
+#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_DBGMCU_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dma.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dma.h"
new file mode 100644
index 0000000..14275fe
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_dma.h"
@@ -0,0 +1,439 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+ ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+ ((STATE) == DMA_PeripheralInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+ ((STATE) == DMA_MemoryInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Circular ((uint32_t)0x00000020)
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
+#define DMA_Priority_High ((uint32_t)0x00002000)
+#define DMA_Priority_Medium ((uint32_t)0x00001000)
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Enable ((uint32_t)0x00004000)
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DMA_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_exti.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_exti.h"
new file mode 100644
index 0000000..bb9d7f6
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_exti.h"
@@ -0,0 +1,184 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the EXTI firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
+ Wakeup from suspend event */
+#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_EXTI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_flash.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_flash.h"
new file mode 100644
index 0000000..63720de
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_flash.h"
@@ -0,0 +1,426 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_PG,
+ FLASH_ERROR_WRP,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1) || \
+ ((LATENCY) == FLASH_Latency_2))
+/**
+ * @}
+ */
+
+/** @defgroup Half_Cycle_Enable_Disable
+ * @{
+ */
+
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+ ((STATE) == FLASH_HalfCycleAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+ ((STATE) == FLASH_PrefetchBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+
+/* Values to be used with STM32 Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with STM32 Medium-density devices */
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
+#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:
+ Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
+#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */
+
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+#ifdef STM32F10X_XL
+/**
+ * @}
+ */
+/** @defgroup FLASH_Boot
+ * @{
+ */
+#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position
+ and this parameter is selected the device will boot from Bank1(Default) */
+#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position
+ and this parameter is selected the device will boot from Bank 2 or Bank 1,
+ depending on the activation of the bank */
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))
+#endif
+/**
+ * @}
+ */
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
+#ifdef STM32F10X_XL
+#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */
+#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */
+
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#else
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
+
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+#ifdef STM32F10X_XL
+#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */
+#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */
+#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */
+#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */
+
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
+
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_OPTERR)|| \
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \
+ ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))
+#else
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_OPTERR))
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions
+ * @{
+ */
+
+/*------------ Functions used for all STM32F10x devices -----*/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+/*------------ New function used for all STM32F10x devices -----*/
+void FLASH_UnlockBank1(void);
+void FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef STM32F10X_XL
+/*---- New Functions used only with STM32F10x_XL density devices -----*/
+void FLASH_UnlockBank2(void);
+void FLASH_LockBank2(void);
+FLASH_Status FLASH_EraseAllBank2Pages(void);
+FLASH_Status FLASH_GetBank2Status(void);
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_FLASH_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_fsmc.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_fsmc.h"
new file mode 100644
index 0000000..6e1769d
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_fsmc.h"
@@ -0,0 +1,733 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the FSMC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FSMC_H
+#define __STM32F10x_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC
+ * @{
+ */
+
+/** @defgroup FSMC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief Timing parameters For NOR/SRAM Banks
+ */
+
+typedef struct
+{
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories. */
+
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories.*/
+
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between 0 and 0xFF.
+ @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is only used for multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+ This parameter can be a value between 1 and 0xF.
+ @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The value of this parameter depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don't care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between 0 and 0xF in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/**
+ * @brief FSMC NOR/SRAM Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the databus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory bank.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
+ valid only with asynchronous Flash memories.
+ This parameter can be a value of @ref FSMC_AsynchronousWait */
+
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
+}FSMC_NORSRAMInitTypeDef;
+
+/**
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks
+ */
+
+typedef struct
+{
+ uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between 0 and 0xFF.*/
+
+ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command deassertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ databus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/**
+ * @brief FSMC NAND Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FSMC_ECC */
+
+ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/**
+ * @brief FSMC PCCARD Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
+}FSMC_PCCARDInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FSMC_NORSRAM_Bank
+ * @{
+ */
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Bank
+ * @{
+ */
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Bank
+ * @{
+ */
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
+/**
+ * @}
+ */
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \
+ ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+/** @defgroup NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+ ((MUX) == FSMC_DataAddressMux_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Memory_Type
+ * @{
+ */
+
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+ ((MEMORY) == FSMC_MemoryType_NOR))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Width
+ * @{
+ */
+
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+ ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_AsynchronousWait
+ * @{
+ */
+#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+ ((STATE) == FSMC_AsynchronousWait_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal_Polarity
+ * @{
+ */
+
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+ ((POLARITY) == FSMC_WaitSignalPolarity_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode
+ * @{
+ */
+
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+ ((MODE) == FSMC_WrapMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing
+ * @{
+ */
+
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation
+ * @{
+ */
+
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+ ((OPERATION) == FSMC_WriteOperation_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal
+ * @{
+ */
+
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+ ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode
+ * @{
+ */
+
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+ ((MODE) == FSMC_ExtendedMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst
+ * @{
+ */
+
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+ ((BURST) == FSMC_WriteBurst_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration
+ * @{
+ */
+
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_CLK_Division
+ * @{
+ */
+
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Latency
+ * @{
+ */
+
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Access_Mode
+ * @{
+ */
+
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B ((uint32_t)0x10000000)
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+ ((MODE) == FSMC_AccessMode_B) || \
+ ((MODE) == FSMC_AccessMode_C) || \
+ ((MODE) == FSMC_AccessMode_D))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_PCCARD_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Wait_feature
+ * @{
+ */
+
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+ ((FEATURE) == FSMC_Waitfeature_Enable))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_ECC
+ * @{
+ */
+
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+ ((STATE) == FSMC_ECC_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC_Page_Size
+ * @{
+ */
+
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TCLR_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TAR_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Hold_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_HiZ_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Interrupt_sources
+ * @{
+ */
+
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
+#define FSMC_IT_Level ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+ ((IT) == FSMC_IT_Level) || \
+ ((IT) == FSMC_IT_FallingEdge))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Flags
+ * @{
+ */
+
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+ ((FLAG) == FSMC_FLAG_Level) || \
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \
+ ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Functions
+ * @{
+ */
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_PCCARDDeInit(void);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_FSMC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_gpio.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_gpio.h"
new file mode 100644
index 0000000..dd28da8
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_gpio.h"
@@ -0,0 +1,385 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_GPIO_H
+#define __STM32F10x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF) || \
+ ((PERIPH) == GPIOG))
+
+/**
+ * @brief Output Maximum frequency selection
+ */
+
+typedef enum
+{
+ GPIO_Speed_10MHz = 1,
+ GPIO_Speed_2MHz,
+ GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+ ((SPEED) == GPIO_Speed_50MHz))
+
+/**
+ * @brief Configuration Mode enumeration
+ */
+
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+ GPIO_Mode_IN_FLOATING = 0x04,
+ GPIO_Mode_IPD = 0x28,
+ GPIO_Mode_IPU = 0x48,
+ GPIO_Mode_Out_OD = 0x14,
+ GPIO_Mode_Out_PP = 0x10,
+ GPIO_Mode_AF_OD = 0x1C,
+ GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
+ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
+ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
+ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Remap_define
+ * @{
+ */
+
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ to TIM2 Internal Trigger 1 for calibration
+ (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */
+#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
+
+#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */
+#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */
+#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */
+#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */
+
+#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
+#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */
+#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
+ only for High density Value line devices) */
+
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
+ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
+ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
+ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
+ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
+ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
+ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
+ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
+ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
+ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
+ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
+ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \
+ ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \
+ ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \
+ ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \
+ ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \
+ ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \
+ ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \
+ ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+
+/**
+ * @}
+ */
+
+/** @defgroup Ethernet_Media_Interface
+ * @{
+ */
+#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
+
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
+ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_GPIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_i2c.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_i2c.h"
new file mode 100644
index 0000000..60e4b14
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_i2c.h"
@@ -0,0 +1,684 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+ ((CYCLE) == I2C_DutyCycle_2))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_Ack_Enable ((uint16_t)0x0400)
+#define I2C_Ack_Disable ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+ ((STATE) == I2C_Ack_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_Direction_Transmitter ((uint8_t)0x00)
+#define I2C_Direction_Receiver ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_registers
+ * @{
+ */
+
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_DR ((uint8_t)0x10)
+#define I2C_Register_SR1 ((uint8_t)0x14)
+#define I2C_Register_SR2 ((uint8_t)0x18)
+#define I2C_Register_CCR ((uint8_t)0x1C)
+#define I2C_Register_TRISE ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_DR) || \
+ ((REGISTER) == I2C_Register_SR1) || \
+ ((REGISTER) == I2C_Register_SR2) || \
+ ((REGISTER) == I2C_Register_CCR) || \
+ ((REGISTER) == I2C_Register_TRISE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+ ((ALERT) == I2C_SMBusAlert_High))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PECPosition_Next ((uint16_t)0x0800)
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+ ((POSITION) == I2C_PECPosition_Current))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_NCAK_position
+ * @{
+ */
+
+#define I2C_NACKPosition_Next ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
+ ((POSITION) == I2C_NACKPosition_Current))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_BUF ((uint16_t)0x0400)
+#define I2C_IT_EVT ((uint16_t)0x0200)
+#define I2C_IT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
+#define I2C_IT_PECERR ((uint32_t)0x01001000)
+#define I2C_IT_OVR ((uint32_t)0x01000800)
+#define I2C_IT_AF ((uint32_t)0x01000400)
+#define I2C_IT_ARLO ((uint32_t)0x01000200)
+#define I2C_IT_BERR ((uint32_t)0x01000100)
+#define I2C_IT_TXE ((uint32_t)0x06000080)
+#define I2C_IT_RXNE ((uint32_t)0x06000040)
+#define I2C_IT_STOPF ((uint32_t)0x02000010)
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)
+#define I2C_IT_BTF ((uint32_t)0x02000004)
+#define I2C_IT_ADDR ((uint32_t)0x02000002)
+#define I2C_IT_SB ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief SR2 register flags
+ */
+
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)
+
+/**
+ * @brief SR1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)
+#define I2C_FLAG_AF ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
+#define I2C_FLAG_SB ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Events
+ * @{
+ */
+
+/*========================================
+
+ I2C Master Events (Events grouped in order of communication)
+ ==========================================*/
+/**
+ * @brief Communication start
+ *
+ * After sending the START condition (I2C_GenerateSTART() function) the master
+ * has to wait for this event. It means that the Start condition has been correctly
+ * released on the I2C bus (the bus is free, no other devices is communicating).
+ *
+ */
+/* --EV5 */
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief Address Acknowledge
+ *
+ * After checking on EV5 (start condition correctly released on the bus), the
+ * master sends the address of the slave(s) with which it will communicate
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication:
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will
+ * be set:
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
+ * function). Then master should wait on EV9. It means that the 10-bit addressing
+ * header has been correctly sent on the bus. Then master should send the second part of
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
+ * should wait for event EV6.
+ *
+ */
+
+/* --EV6 */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief Communication events
+ *
+ * If a communication is established (START condition generated and slave address
+ * acknowledged) then the master has to check on one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read
+ * the data received from the slave (I2C_ReceiveData() function).
+ *
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData()
+ * function) then to wait on event EV8 or EV8_2.
+ * These two events are similar:
+ * - EV8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EV8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EV8 is sufficient for the application.
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission
+ * (before Stop condition generation).
+ *
+ * @note In case the user software does not guarantee that this event EV7 is
+ * managed before the current byte end of transfer, then user may check on EV7
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Master RECEIVER mode -----------------------------*/
+/* --EV7 */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/*========================================
+
+ I2C Slave Events (Events grouped in order of communication)
+ ==========================================*/
+
+/**
+ * @brief Communication start events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a Start condition on the bus (generated by master
+ * device) followed by the peripheral address. The peripheral generates an ACK
+ * condition on the bus (if the acknowledge feature is enabled through function
+ * I2C_AcknowledgeConfig()) and the events listed above are set :
+ *
+ * 1) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * 2) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * 3) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
+ *
+ */
+
+/* --EV1 (all the events below are variants of EV1) */
+/* 1) Case of One Single Address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief Communication events
+ *
+ * Wait on one of these events when EV1 has already been checked and:
+ *
+ * - Slave RECEIVER mode:
+ * - EV2: When the application is expecting a data byte to be received.
+ * - EV4: When the application is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
+ * used when the user software doesn't guarantee the EV3 is managed before the
+ * current byte end of transfer.
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission
+ * shall end (before sending the STOP condition). In this case slave has to stop sending
+ * data bytes and expect a Stop condition on the bus.
+ *
+ * @note In case the user software does not guarantee that the event EV2 is
+ * managed before the current byte end of transfer, then user may check on EV2
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+ * In this case the communication may be slower.
+ *
+ */
+
+/* Slave RECEIVER mode --------------------------*/
+/* --EV2 */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+/* --EV4 */
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
+
+/*=========================== End of Events Description ==========================================*/
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_clock_speed
+ * @{
+ */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (SR1 and SR2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occurred.
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the limitations of I2C_GetFlagStatus() function (see below).
+ * The returned value could be compared to events already defined in the
+ * library (stm32f10x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlagStatus() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+/**
+ *
+ *******************************************************************************
+ */
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_iwdg.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_iwdg.h"
new file mode 100644
index 0000000..25b0bb5
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_iwdg.h"
@@ -0,0 +1,140 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IWDG_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_pwr.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_pwr.h"
new file mode 100644
index 0000000..1c025e2
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_pwr.h"
@@ -0,0 +1,156 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the PWR firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
+ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
+ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+/**
+ * @}
+ */
+
+/** @defgroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_Regulator_ON ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+ ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+ * @}
+ */
+
+/** @defgroup STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+
+#define PWR_FLAG_WU ((uint32_t)0x00000001)
+#define PWR_FLAG_SB ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+ ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_PWR_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_rcc.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_rcc.h"
new file mode 100644
index 0000000..1149c34
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_rcc.h"
@@ -0,0 +1,727 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the RCC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint32_t)0x00000000)
+#define RCC_HSE_ON ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/**
+ * @}
+ */
+
+/** @defgroup PLL_entry_clock_source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
+ #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
+ #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div2))
+#else
+ #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_PREDIV1))
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+/** @defgroup PLL_multiplication_factor
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define RCC_PLLMul_2 ((uint32_t)0x00000000)
+ #define RCC_PLLMul_3 ((uint32_t)0x00040000)
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_10 ((uint32_t)0x00200000)
+ #define RCC_PLLMul_11 ((uint32_t)0x00240000)
+ #define RCC_PLLMul_12 ((uint32_t)0x00280000)
+ #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
+ #define RCC_PLLMul_14 ((uint32_t)0x00300000)
+ #define RCC_PLLMul_15 ((uint32_t)0x00340000)
+ #define RCC_PLLMul_16 ((uint32_t)0x00380000)
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
+
+#else
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
+
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_6_5))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup PREDIV1_division_factor
+ * @{
+ */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
+ #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
+ #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
+ #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
+ #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
+ #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
+ #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
+ #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
+ #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
+ #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
+ #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
+ #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
+ #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
+ #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
+ #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
+
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+#endif
+/**
+ * @}
+ */
+
+
+/** @defgroup PREDIV1_clock_source
+ * @{
+ */
+#ifdef STM32F10X_CL
+/* PREDIV1 clock source (for STM32 connectivity line devices) */
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
+ ((SOURCE) == RCC_PREDIV1_Source_PLL2))
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/* PREDIV1 clock source (for STM32 Value line devices) */
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
+#endif
+/**
+ * @}
+ */
+
+#ifdef STM32F10X_CL
+/** @defgroup PREDIV2_division_factor
+ * @{
+ */
+
+ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
+ #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
+ #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
+ #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
+ #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
+ #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
+ #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
+ #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
+ #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
+ #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
+ #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
+ #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
+ #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
+ #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
+ #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
+
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
+ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
+ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
+ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
+ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
+ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
+ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
+ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL2_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
+ #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
+ #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
+ #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
+ #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
+ #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
+ #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
+ #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
+ #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
+
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
+ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
+ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
+ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
+ ((MUL) == RCC_PLL2Mul_20))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL3_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
+ #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
+ #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
+ #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
+ #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
+ #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
+ #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
+ #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
+ #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
+
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
+ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
+ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
+ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
+ ((MUL) == RCC_PLL3Mul_20))
+/**
+ * @}
+ */
+
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+#else
+ #define RCC_IT_PLL2RDY ((uint8_t)0x20)
+ #define RCC_IT_PLL3RDY ((uint8_t)0x40)
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+#endif /* STM32F10X_CL */
+
+
+/**
+ * @}
+ */
+
+#ifndef STM32F10X_CL
+/** @defgroup USB_Device_clock_source
+ * @{
+ */
+
+ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
+ #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
+
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+/**
+ * @}
+ */
+#else
+/** @defgroup USB_OTG_FS_clock_source
+ * @{
+ */
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
+
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
+ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
+/**
+ * @}
+ */
+#endif /* STM32F10X_CL */
+
+
+#ifdef STM32F10X_CL
+/** @defgroup I2S2_clock_source
+ * @{
+ */
+ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+
+/** @defgroup I2S3_clock_source
+ * @{
+ */
+ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+/**
+ * @}
+ */
+
+/** @defgroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_Bypass ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+/**
+ * @}
+ */
+
+/** @defgroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
+#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
+#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NoClock ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2))
+#else
+ #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
+ #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
+ #define RCC_MCO_XT1 ((uint8_t)0x0A)
+ #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
+
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
+ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
+ ((MCO) == RCC_MCO_PLL3CLK))
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#else
+ #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
+ #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#endif /* STM32F10X_CL */
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+#endif
+
+#ifdef STM32F10X_CL
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+ void RCC_PLL2Cmd(FunctionalState NewState);
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+ void RCC_PLL3Cmd(FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+
+#ifndef STM32F10X_CL
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+#else
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+
+#ifdef STM32F10X_CL
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+#ifdef STM32F10X_CL
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RCC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_rtc.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_rtc.h"
new file mode 100644
index 0000000..fd8beb5
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_rtc.h"
@@ -0,0 +1,135 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the RTC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RTC_interrupts_define
+ * @{
+ */
+
+#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
+#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
+#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
+ ((IT) == RTC_IT_SEC))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_interrupts_flags
+ * @{
+ */
+
+#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
+#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
+#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
+ ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
+ ((FLAG) == RTC_FLAG_SEC))
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions
+ * @{
+ */
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RTC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_sdio.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_sdio.h"
new file mode 100644
index 0000000..81c058a
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_sdio.h"
@@ -0,0 +1,531 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the SDIO firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SDIO_H
+#define __STM32F10x_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @defgroup SDIO_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between 0x00 and 0xFF. */
+
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register */
+
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SDIO_Clock_Edge
+ * @{
+ */
+
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+ ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Bypass
+ * @{
+ */
+
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+ ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Power_Save
+ * @{
+ */
+
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+ ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Bus_Wide
+ * @{
+ */
+
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+ ((WIDE) == SDIO_BusWide_8b))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Power_State
+ * @{
+ */
+
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+/**
+ * @}
+ */
+
+
+/** @defgroup SDIO_Interrupt_sources
+ * @{
+ */
+
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Command_Index
+ * @{
+ */
+
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Type
+ * @{
+ */
+
+#define SDIO_Response_No ((uint32_t)0x00000000)
+#define SDIO_Response_Short ((uint32_t)0x00000040)
+#define SDIO_Response_Long ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+ ((RESPONSE) == SDIO_Response_Short) || \
+ ((RESPONSE) == SDIO_Response_Long))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+ ((WAIT) == SDIO_Wait_Pend))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_CPSM_State
+ * @{
+ */
+
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Registers
+ * @{
+ */
+
+#define SDIO_RESP1 ((uint32_t)0x00000000)
+#define SDIO_RESP2 ((uint32_t)0x00000004)
+#define SDIO_RESP3 ((uint32_t)0x00000008)
+#define SDIO_RESP4 ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Length
+ * @{
+ */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Block_Size
+ * @{
+ */
+
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+ ((SIZE) == SDIO_DataBlockSize_2b) || \
+ ((SIZE) == SDIO_DataBlockSize_4b) || \
+ ((SIZE) == SDIO_DataBlockSize_8b) || \
+ ((SIZE) == SDIO_DataBlockSize_16b) || \
+ ((SIZE) == SDIO_DataBlockSize_32b) || \
+ ((SIZE) == SDIO_DataBlockSize_64b) || \
+ ((SIZE) == SDIO_DataBlockSize_128b) || \
+ ((SIZE) == SDIO_DataBlockSize_256b) || \
+ ((SIZE) == SDIO_DataBlockSize_512b) || \
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \
+ ((SIZE) == SDIO_DataBlockSize_16384b))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Direction
+ * @{
+ */
+
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+ ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Type
+ * @{
+ */
+
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+ ((MODE) == SDIO_TransferMode_Block))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_DPSM_State
+ * @{
+ */
+
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Flags
+ * @{
+ */
+
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \
+ ((FLAG) == SDIO_FLAG_CMDREND) || \
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \
+ ((FLAG) == SDIO_FLAG_DATAEND) || \
+ ((FLAG) == SDIO_FLAG_STBITERR) || \
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \
+ ((FLAG) == SDIO_FLAG_CMDACT) || \
+ ((FLAG) == SDIO_FLAG_TXACT) || \
+ ((FLAG) == SDIO_FLAG_RXACT) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \
+ ((FLAG) == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+ ((IT) == SDIO_IT_DCRCFAIL) || \
+ ((IT) == SDIO_IT_CTIMEOUT) || \
+ ((IT) == SDIO_IT_DTIMEOUT) || \
+ ((IT) == SDIO_IT_TXUNDERR) || \
+ ((IT) == SDIO_IT_RXOVERR) || \
+ ((IT) == SDIO_IT_CMDREND) || \
+ ((IT) == SDIO_IT_CMDSENT) || \
+ ((IT) == SDIO_IT_DATAEND) || \
+ ((IT) == SDIO_IT_STBITERR) || \
+ ((IT) == SDIO_IT_DBCKEND) || \
+ ((IT) == SDIO_IT_CMDACT) || \
+ ((IT) == SDIO_IT_TXACT) || \
+ ((IT) == SDIO_IT_RXACT) || \
+ ((IT) == SDIO_IT_TXFIFOHE) || \
+ ((IT) == SDIO_IT_RXFIFOHF) || \
+ ((IT) == SDIO_IT_TXFIFOF) || \
+ ((IT) == SDIO_IT_RXFIFOF) || \
+ ((IT) == SDIO_IT_TXFIFOE) || \
+ ((IT) == SDIO_IT_RXFIFOE) || \
+ ((IT) == SDIO_IT_TXDAVL) || \
+ ((IT) == SDIO_IT_RXDAVL) || \
+ ((IT) == SDIO_IT_SDIOIT) || \
+ ((IT) == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Read_Wait_Mode
+ * @{
+ */
+
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+ ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Functions
+ * @{
+ */
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_SDIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_spi.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_spi.h"
new file mode 100644
index 0000000..23cc26d
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_spi.h"
@@ -0,0 +1,487 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the SPI firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_data_direction */
+
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be a value of @ref SPI_mode */
+
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
+ This parameter can be a value of @ref SPI_data_size */
+
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_Clock_Polarity */
+
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_Clock_Phase */
+
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_Slave_Select_management */
+
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
+
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
+
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
+
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
+
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
+
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+ ((MODE) == SPI_Direction_1Line_Rx) || \
+ ((MODE) == SPI_Direction_1Line_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+ ((MODE) == SPI_Mode_Slave))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DataSize_16b ((uint16_t)0x0800)
+#define SPI_DataSize_8b ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+ ((DATASIZE) == SPI_DataSize_8b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+ ((CPOL) == SPI_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+ ((CPHA) == SPI_CPHA_2Edge))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_Soft ((uint16_t)0x0200)
+#define SPI_NSS_Hard ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+ ((NSS) == SPI_NSS_Hard))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+ ((BIT) == SPI_FirstBit_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode
+ * @{
+ */
+
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+ ((MODE) == I2S_Mode_SlaveRx) || \
+ ((MODE) == I2S_Mode_MasterTx) || \
+ ((MODE) == I2S_Mode_MasterRx) )
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard
+ * @{
+ */
+
+#define I2S_Standard_Phillips ((uint16_t)0x0000)
+#define I2S_Standard_MSB ((uint16_t)0x0010)
+#define I2S_Standard_LSB ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+ ((STANDARD) == I2S_Standard_MSB) || \
+ ((STANDARD) == I2S_Standard_LSB) || \
+ ((STANDARD) == I2S_Standard_PCMShort) || \
+ ((STANDARD) == I2S_Standard_PCMLong))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DataFormat_16b ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+#define I2S_DataFormat_24b ((uint16_t)0x0003)
+#define I2S_DataFormat_32b ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+ ((FORMAT) == I2S_DataFormat_16bextended) || \
+ ((FORMAT) == I2S_DataFormat_24b) || \
+ ((FORMAT) == I2S_DataFormat_32b))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+ ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AudioFreq_192k ((uint32_t)192000)
+#define I2S_AudioFreq_96k ((uint32_t)96000)
+#define I2S_AudioFreq_48k ((uint32_t)48000)
+#define I2S_AudioFreq_44k ((uint32_t)44100)
+#define I2S_AudioFreq_32k ((uint32_t)32000)
+#define I2S_AudioFreq_22k ((uint32_t)22050)
+#define I2S_AudioFreq_16k ((uint32_t)16000)
+#define I2S_AudioFreq_11k ((uint32_t)11025)
+#define I2S_AudioFreq_8k ((uint32_t)8000)
+#define I2S_AudioFreq_Default ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+ ((FREQ) <= I2S_AudioFreq_192k)) || \
+ ((FREQ) == I2S_AudioFreq_Default))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CPOL_Low ((uint16_t)0x0000)
+#define I2S_CPOL_High ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+ ((CPOL) == I2S_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSS_internal_software_management
+ * @{
+ */
+
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+ ((DIRECTION) == SPI_Direction_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_RXNE) || \
+ ((IT) == SPI_I2S_IT_ERR))
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_IT_CRCERR ((uint8_t)0x54)
+#define I2S_IT_UDR ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
+ ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+#define I2S_FLAG_UDR ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+#define SPI_FLAG_MODF ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_SPI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_tim.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_tim.h"
new file mode 100644
index 0000000..65bf76a
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_tim.h"
@@ -0,0 +1,1164 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the TIM firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM_H
+#define __STM32F10x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This structure is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/**
+ * @brief BDTR structure definition
+ * @note This structure is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM10)|| \
+ ((PERIPH) == TIM11)|| \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM13)|| \
+ ((PERIPH) == TIM14)|| \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST1: TIM 1 and 8 */
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM8))
+
+/* LIST2: TIM 1, 8, 15 16 and 17 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8))
+
+/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15))
+
+/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM15))
+
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM15))
+
+/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM9) || \
+ ((PERIPH) == TIM10)|| \
+ ((PERIPH) == TIM11)|| \
+ ((PERIPH) == TIM12)|| \
+ ((PERIPH) == TIM13)|| \
+ ((PERIPH) == TIM14)|| \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
+#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8) || \
+ ((PERIPH) == TIM15)|| \
+ ((PERIPH) == TIM16)|| \
+ ((PERIPH) == TIM17))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMode_Timing ((uint16_t)0x0000)
+#define TIM_OCMode_Active ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_ForcedAction_Active) || \
+ ((MODE) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+ ((MODE) == TIM_OPMode_Repetitive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3) || \
+ ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+ ((DIV) == TIM_CKD_DIV2) || \
+ ((DIV) == TIM_CKD_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+ ((MODE) == TIM_CounterMode_Down) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+ ((POLARITY) == TIM_OCPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+ ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+ ((STATE) == TIM_OutputState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+ ((STATE) == TIM_OutputNState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+ ((CCX) == TIM_CCx_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CCxN_Enable ((uint16_t)0x0004)
+#define TIM_CCxN_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+ ((CCXN) == TIM_CCxN_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break_Enable ((uint16_t)0x1000)
+#define TIM_Break_Disable ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+ ((STATE) == TIM_Break_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+ ((POLARITY) == TIM_BreakPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+ ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+ ((LEVEL) == TIM_LOCKLevel_1) || \
+ ((LEVEL) == TIM_LOCKLevel_2) || \
+ ((LEVEL) == TIM_LOCKLevel_3))
+/**
+ * @}
+ */
+
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+ ((STATE) == TIM_OSSIState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+ ((STATE) == TIM_OSSRState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+ ((STATE) == TIM_OCIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+ ((STATE) == TIM_OCNIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling))
+#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \
+ ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+ ((SELECTION) == TIM_ICSelection_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_COM ((uint16_t)0x0020)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define TIM_IT_Break ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_Trigger) || \
+ ((IT) == TIM_IT_Break))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_RCR ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+ ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+ ((ACTION) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+ ((MODE) == TIM_EncoderMode_TI2) || \
+ ((MODE) == TIM_EncoderMode_TI12))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_COM ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define TIM_EventSource_Break ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+ ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+ ((STATE) == TIM_OCPreload_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+ ((STATE) == TIM_OCFast_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+ ((STATE) == TIM_OCClear_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+ ((SOURCE) == TIM_TRGOSource_Enable) || \
+ ((SOURCE) == TIM_TRGOSource_Update) || \
+ ((SOURCE) == TIM_TRGOSource_OC1) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+ ((MODE) == TIM_SlaveMode_Gated) || \
+ ((MODE) == TIM_SlaveMode_Trigger) || \
+ ((MODE) == TIM_SlaveMode_External1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_Update ((uint16_t)0x0001)
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)
+#define TIM_FLAG_COM ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)
+#define TIM_FLAG_Break ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_Trigger) || \
+ ((FLAG) == TIM_FLAG_Break) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Legacy
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_TIM_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_usart.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_usart.h"
new file mode 100644
index 0000000..162fa87
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_usart.h"
@@ -0,0 +1,412 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the USART
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @defgroup USART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t USART_Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_Clock */
+
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4) || \
+ ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4))
+/** @defgroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WordLength_8b ((uint16_t)0x0000)
+#define USART_WordLength_9b ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+ ((LENGTH) == USART_WordLength_9b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_StopBits_1 ((uint16_t)0x0000)
+#define USART_StopBits_0_5 ((uint16_t)0x1000)
+#define USART_StopBits_2 ((uint16_t)0x2000)
+#define USART_StopBits_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+ ((STOPBITS) == USART_StopBits_0_5) || \
+ ((STOPBITS) == USART_StopBits_2) || \
+ ((STOPBITS) == USART_StopBits_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+
+#define USART_Parity_No ((uint16_t)0x0000)
+#define USART_Parity_Even ((uint16_t)0x0400)
+#define USART_Parity_Odd ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+ ((PARITY) == USART_Parity_Even) || \
+ ((PARITY) == USART_Parity_Odd))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+
+#define USART_Mode_Rx ((uint16_t)0x0004)
+#define USART_Mode_Tx ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == USART_HardwareFlowControl_None) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+#define USART_Clock_Disable ((uint16_t)0x0000)
+#define USART_Clock_Enable ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+ ((CLOCK) == USART_Clock_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CPOL_Low ((uint16_t)0x0000)
+#define USART_CPOL_High ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CPHA_1Edge ((uint16_t)0x0000)
+#define USART_CPHA_2Edge ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_LastBit_Disable ((uint16_t)0x0000)
+#define USART_LastBit_Enable ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+ ((LASTBIT) == USART_LastBit_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028)
+#define USART_IT_TXE ((uint16_t)0x0727)
+#define USART_IT_TC ((uint16_t)0x0626)
+#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_IDLE ((uint16_t)0x0424)
+#define USART_IT_LBD ((uint16_t)0x0846)
+#define USART_IT_CTS ((uint16_t)0x096A)
+#define USART_IT_ERR ((uint16_t)0x0060)
+#define USART_IT_ORE ((uint16_t)0x0360)
+#define USART_IT_NE ((uint16_t)0x0260)
+#define USART_IT_FE ((uint16_t)0x0160)
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAReq_Tx ((uint16_t)0x0080)
+#define USART_DMAReq_Rx ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+ ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+ * @}
+ */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+ ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+ ((MODE) == USART_IrDAMode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTS ((uint16_t)0x0200)
+#define USART_FLAG_LBD ((uint16_t)0x0100)
+#define USART_FLAG_TXE ((uint16_t)0x0080)
+#define USART_FLAG_TC ((uint16_t)0x0040)
+#define USART_FLAG_RXNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLE ((uint16_t)0x0010)
+#define USART_FLAG_ORE ((uint16_t)0x0008)
+#define USART_FLAG_NE ((uint16_t)0x0004)
+#define USART_FLAG_FE ((uint16_t)0x0002)
+#define USART_FLAG_PE ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
+ ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTS))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_USART_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_wwdg.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_wwdg.h"
new file mode 100644
index 0000000..bdfa177
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/inc/stm32f10x_wwdg.h"
@@ -0,0 +1,115 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file contains all the functions prototypes for the WWDG firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+ ((PRESCALER) == WWDG_Prescaler_2) || \
+ ((PRESCALER) == WWDG_Prescaler_4) || \
+ ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/misc.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/misc.c"
new file mode 100644
index 0000000..c0a5e11
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/misc.c"
@@ -0,0 +1,225 @@
+/**
+ ******************************************************************************
+ * @file misc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the miscellaneous firmware functions (add-on
+ * to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @defgroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset: Vector Table base offset field. This value must be a multiple
+ * of 0x200.
+ * @retval None
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_adc.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_adc.c"
new file mode 100644
index 0000000..8155dc9
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_adc.c"
@@ -0,0 +1,1307 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the ADC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @defgroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set ((uint32_t)0x00000800)
+#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set ((uint32_t)0x00001000)
+#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CR2_ADON_Set ((uint32_t)0x00000001)
+#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set ((uint32_t)0x00000100)
+#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CR2_SWSTART_Set ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CR2_JSWSTART_Set ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_Set ((uint32_t)0x00800000)
+#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set ((uint32_t)0x0000001F)
+#define SQR2_SQ_Set ((uint32_t)0x0000001F)
+#define SQR1_SQ_Set ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_Set ((uint32_t)0x00300000)
+#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set ((uint32_t)0x00000007)
+#define SMPR2_SMP_Set ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DR_ADDRESS ((uint32_t)0x4001244C)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ if (ADCx == ADC1)
+ {
+ /* Enable ADC1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+ }
+ else if (ADCx == ADC2)
+ {
+ /* Enable ADC2 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+ /* Release ADC2 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+ }
+ else
+ {
+ if (ADCx == ADC3)
+ {
+ /* Enable ADC3 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+ /* Release ADC3 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+ * the configuration information for the specified ADC peripheral.
+ * @retval None
+ */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+ /*---------------------------- ADCx CR1 Configuration -----------------*/
+ /* Get the ADCx CR1 value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CR1_CLEAR_Mask;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to ADC_Mode value */
+ /* Set SCAN bit according to ADC_ScanConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+ /* Write to ADCx CR1 */
+ ADCx->CR1 = tmpreg1;
+
+ /*---------------------------- ADCx CR2 Configuration -----------------*/
+ /* Get the ADCx CR2 value */
+ tmpreg1 = ADCx->CR2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CR2_CLEAR_Mask;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to ADC_DataAlign value */
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+ /* Set CONT bit according to ADC_ContinuousConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+ /* Write to ADCx CR2 */
+ ADCx->CR2 = tmpreg1;
+
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/
+ /* Get the ADCx SQR1 value */
+ tmpreg1 = ADCx->SQR1;
+ /* Clear L bits */
+ tmpreg1 &= SQR1_CLEAR_Mask;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ADC_NbrOfChannel value */
+ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx SQR1 */
+ ADCx->SQR1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* Initialize the ADC_Mode member */
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+ /* initialize the ADC_ScanConvMode member */
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+ /* Initialize the ADC_ContinuousConvMode member */
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+ /* Initialize the ADC_ExternalTrigConv member */
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+ /* Initialize the ADC_DataAlign member */
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+ /* Initialize the ADC_NbrOfChannel member */
+ ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ADON bit to wake up the ADC from power down mode */
+ ADCx->CR2 |= CR2_ADON_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CR2 &= CR2_ADON_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.
+ * Note: ADC2 hasn't a DMA capability.
+ * @param NewState: new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CR2 |= CR2_DMA_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CR2 &= CR2_DMA_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @param NewState: new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CR1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CR1 &= (~(uint32_t)itmask);
+ }
+}
+
+/**
+ * @brief Resets the selected ADC calibration registers.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Resets the selected ADC calibration registers */
+ ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC reset calibration registers status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC reset calibration registers (SET or RESET).
+ */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of RSTCAL bit */
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
+ {
+ /* RSTCAL bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* RSTCAL bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the RSTCAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Enable the selected ADC calibration process */
+ ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of SWSTART bit */
+ if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
+ {
+ /* SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Number: specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ * @retval None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CR1 |= CR1_DISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CR1 &= CR1_DISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_REGULAR_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CR2 |= CR2_EXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t) ADCx->DR;
+}
+
+/**
+ * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ * @retval The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+ /* Return the dual mode conversion value */
+ return (*(__IO uint32_t *) DR_ADDRESS);
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CR1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CR1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CR1 |= CR1_JDISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CR1 &= CR1_JDISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+ * by external trigger (for ADC1, ADC2 and ADC3)
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpreg = ADCx->CR2;
+ /* Clear the old external event selection for injected group */
+ tmpreg &= CR2_JEXTSEL_Reset;
+ /* Set the external event selection for injected group */
+ tmpreg |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of JSWSTART bit */
+ if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
+ {
+ /* JSWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* JSWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the JSWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_INJECTED_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Get JL value: Number = JL+1 */
+ tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Length: The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ * @retval None
+ */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Clear the old injected sequnence lenght JL bits */
+ tmpreg1 &= JSQR_JL_Reset;
+ /* Set the injected sequnence lenght JL bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @param Offset: the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDR_Offset;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+ * @retval None
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpreg &= CR1_AWDMode_Reset;
+ /* Set the analog watchdog enable mode */
+ tmpreg |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+ uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->HTR = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->LTR = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= CR1_AWDCH_Reset;
+ /* Set the Analog watchdog channel */
+ tmpreg |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param NewState: new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 |= CR2_TSVREFE_Set;
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 &= CR2_TSVREFE_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval None
+ */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval The new state of ADC_IT (SET or RESET).
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's interrupt pending bits.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval None
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_bkp.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_bkp.c"
new file mode 100644
index 0000000..997eecc
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_bkp.c"
@@ -0,0 +1,308 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the BKP firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup BKP
+ * @brief BKP driver modules
+ * @{
+ */
+
+/** @defgroup BKP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Defines
+ * @{
+ */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
+
+/* --- CR Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CR_OFFSET (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber 0x01
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber 0x00
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber 0x02
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber 0x09
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber 0x08
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCR_CAL_MASK ((uint16_t)0xFF80)
+#define RTCCR_MASK ((uint16_t)0xFC7F)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup BKP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the BKP peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void BKP_DeInit(void)
+{
+ RCC_BackupResetCmd(ENABLE);
+ RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+ * @brief Configures the Tamper Pin active level.
+ * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ * This parameter can be one of the following values:
+ * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
+ * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
+ * @retval None
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+ /* Check the parameters */
+ assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+ *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin activation.
+ * @param NewState: new state of the Tamper Pin activation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin Interrupt.
+ * @param NewState: new state of the Tamper Pin Interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Select the RTC output source to output on the Tamper pin.
+ * @param BKP_RTCOutputSource: specifies the RTC output source.
+ * This parameter can be one of the following values:
+ * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+ * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+ * divided by 64 on the Tamper pin.
+ * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+ * the Tamper pin.
+ * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+ * the Tamper pin.
+ * @retval None
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
+ tmpreg = BKP->RTCCR;
+ /* Clear CCO, ASOE and ASOS bits */
+ tmpreg &= RTCCR_MASK;
+
+ /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+ tmpreg |= BKP_RTCOutputSource;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Sets RTC Clock Calibration value.
+ * @param CalibrationValue: specifies the RTC Clock Calibration value.
+ * This parameter must be a number between 0 and 0x7F.
+ * @retval None
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+ tmpreg = BKP->RTCCR;
+ /* Clear CAL[6:0] bits */
+ tmpreg &= RTCCR_CAL_MASK;
+ /* Set CAL[6:0] bits according to CalibrationValue value */
+ tmpreg |= CalibrationValue;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Writes user data to the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @param Data: data to write
+ * @retval None
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Reads data from the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @retval The content of the specified Data Backup Register
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Event flag is set or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Event flag (SET or RESET).
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+ return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Event pending flag.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearFlag(void)
+{
+ /* Set CTE bit to clear Tamper Pin Event flag */
+ BKP->CSR |= BKP_CSR_CTE;
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
+ */
+ITStatus BKP_GetITStatus(void)
+{
+ return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Interrupt pending bit.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearITPendingBit(void)
+{
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+ BKP->CSR |= BKP_CSR_CTI;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_can.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_can.c"
new file mode 100644
index 0000000..ec8e049
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_can.c"
@@ -0,0 +1,1415 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the CAN firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_can.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @defgroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
+
+
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
+/* Flags in MSR register */
+#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
+/* Flags in ESR register */
+#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+
+
+
+#define CAN_MODE_MASK ((uint32_t) 0x00000003)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @retval None.
+ */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (CANx == CAN1)
+ {
+ /* Enable CAN1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+ /* Release CAN1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+ }
+ else
+ {
+ /* Enable CAN2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+ /* Release CAN2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param CANx: where x can be 1 or 2 to to select the CAN
+ * peripheral.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+ * contains the configuration information for the
+ * CAN peripheral.
+ * @retval Constant indicates initialization succeed which will be
+ * CAN_InitStatus_Failed or CAN_InitStatus_Success.
+ */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+ uint8_t InitStatus = CAN_InitStatus_Failed;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+ /* Exit from sleep mode */
+ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ CANx->MCR |= CAN_MCR_INRQ ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* Check acknowledge */
+ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ InitStatus = CAN_InitStatus_Failed;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitStruct->CAN_NART == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)
+ {
+ CANx->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+ ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+ ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0;
+
+ while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ InitStatus = CAN_InitStatus_Failed;
+ }
+ else
+ {
+ InitStatus = CAN_InitStatus_Success ;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+ * structure that contains the configuration
+ * information.
+ * @retval None.
+ */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+ /* Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Filter Deactivation */
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+ {
+ /* 16-bit scale for the filter */
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+ {
+ /* 32-bit scale for the filter */
+ CAN1->FS1R |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter FIFO assignment */
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+ {
+ CAN1->FA1R |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Fills each CAN_InitStruct member with its default value.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
+ * will be initialized.
+ * @retval None.
+ */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+ /* Reset CAN init structure parameters values */
+
+ /* Initialize the time triggered communication mode */
+ CAN_InitStruct->CAN_TTCM = DISABLE;
+
+ /* Initialize the automatic bus-off management */
+ CAN_InitStruct->CAN_ABOM = DISABLE;
+
+ /* Initialize the automatic wake-up mode */
+ CAN_InitStruct->CAN_AWUM = DISABLE;
+
+ /* Initialize the no automatic retransmission */
+ CAN_InitStruct->CAN_NART = DISABLE;
+
+ /* Initialize the receive FIFO locked mode */
+ CAN_InitStruct->CAN_RFLM = DISABLE;
+
+ /* Initialize the transmit FIFO priority */
+ CAN_InitStruct->CAN_TXFP = DISABLE;
+
+ /* Initialize the CAN_Mode member */
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+
+ /* Initialize the CAN_SJW member */
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+
+ /* Initialize the CAN_BS1 member */
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+
+ /* Initialize the CAN_BS2 member */
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+
+ /* Initialize the CAN_Prescaler member */
+ CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+ * @brief Select the start bank filter for slave CAN.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
+ * @retval None.
+ */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+
+ /* Enter Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Select the start slave bank */
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+
+ /* Leave Initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState: new state of the CAN peripheral. This parameter can
+ * be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCR |= MCR_DBF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCR &= ~MCR_DBF;
+ }
+}
+
+
+/**
+ * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState : Mode new state , can be one of @ref FunctionalState.
+ * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
+ * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
+ * and TIME[15:8] in data byte 7
+ * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
+ * sent over the CAN bus.
+ * @retval None
+ */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TTCM mode */
+ CANx->MCR |= CAN_MCR_TTCM;
+
+ /* Set TGT bits */
+ CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+ }
+ else
+ {
+ /* Disable the TTCM mode */
+ CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+ /* Reset TGT bits */
+ CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+ CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+ CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+ }
+}
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN data.
+ * @retval The number of the mailbox that is used for transmission
+ * or CAN_TxStatus_NoMailBox if there is no empty mailbox.
+ */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+ assert_param(IS_CAN_RTR(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_TxStatus_NoMailBox;
+ }
+
+ if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_Id_Standard)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+ TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+ TxMessage->IDE | \
+ TxMessage->RTR);
+ }
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
+ ((uint32_t)TxMessage->Data[2] << 16) |
+ ((uint32_t)TxMessage->Data[1] << 8) |
+ ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
+ ((uint32_t)TxMessage->Data[6] << 16) |
+ ((uint32_t)TxMessage->Data[5] << 8) |
+ ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the
+ * CAN peripheral.
+ * @param TransmitMailbox: the number of the mailbox that is used for
+ * transmission.
+ * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed
+ * in an other case.
+ */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+ uint32_t state = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+
+ switch (TransmitMailbox)
+ {
+ case (CAN_TXMAILBOX_0):
+ state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
+ break;
+ case (CAN_TXMAILBOX_1):
+ state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
+ break;
+ case (CAN_TXMAILBOX_2):
+ state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
+ break;
+ default:
+ state = CAN_TxStatus_Failed;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0): state = CAN_TxStatus_Pending;
+ break;
+ /* transmit failed */
+ case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
+ break;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
+ break;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+ break;
+ /* transmit succeeded */
+ case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+ break;
+ case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+ break;
+ default: state = CAN_TxStatus_Failed;
+ break;
+ }
+ return (uint8_t) state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Mailbox: Mailbox number.
+ * @retval None.
+ */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
+ break;
+ case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
+ break;
+ case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
+ break;
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @brief Receives a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage: pointer to a structure receive message which contains
+ * CAN Id, CAN DLC, CAN datas and FMI number.
+ * @retval None.
+ */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ if (RxMessage->IDE == CAN_Id_Standard)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R |= CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R |= CAN_RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Releases the specified FIFO.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None.
+ */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R |= CAN_RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R |= CAN_RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval NbMessage : which is the number of pending message.
+ */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ uint8_t message_pending=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ if (FIFONumber == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+ }
+ else if (FIFONumber == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+
+/**
+ * @brief Select the CAN Operation mode.
+ * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one
+ * of @ref CAN_OperatingMode_TypeDef enumeration.
+ * @retval status of the requested mode which can be
+ * - CAN_ModeStatus_Failed CAN failed entering the specific mode
+ * - CAN_ModeStatus_Success CAN Succeed entering the specific mode
+
+ */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+ uint8_t status = CAN_ModeStatus_Failed;
+
+ /* Timeout for INAK or also for SLAK bits*/
+ uint32_t timeout = INAK_TIMEOUT;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+ if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+ {
+ /* Request initialisation */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+ {
+ /* Request leave initialisation and sleep mode and enter Normal mode */
+ CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != 0)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+ {
+ /* Request Sleep mode */
+ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+ {
+ timeout--;
+ }
+ if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+ else
+ {
+ status = CAN_ModeStatus_Success;
+ }
+ }
+ else
+ {
+ status = CAN_ModeStatus_Failed;
+ }
+
+ return (uint8_t) status;
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an
+ * other case.
+ */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+ uint8_t sleepstatus = CAN_Sleep_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CAN_Sleep_Ok;
+ }
+ /* return sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an
+ * other case.
+ */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+ uint32_t wait_slak = SLAK_TIMEOUT;
+ uint8_t wakeupstatus = CAN_WakeUp_Failed;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Sleep mode status */
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+ {
+ wait_slak--;
+ }
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+ {
+ /* wake up done : Sleep mode exited */
+ wakeupstatus = CAN_WakeUp_Ok;
+ }
+ /* return wakeup status */
+ return (uint8_t)wakeupstatus;
+}
+
+
+/**
+ * @brief Returns the CANx's last error code (LEC).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CAN_ErrorCode: specifies the Error code :
+ * - CAN_ERRORCODE_NoErr No Error
+ * - CAN_ERRORCODE_StuffErr Stuff Error
+ * - CAN_ERRORCODE_FormErr Form Error
+ * - CAN_ERRORCODE_ACKErr Acknowledgment Error
+ * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
+ * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
+ * - CAN_ERRORCODE_CRCErr CRC Error
+ * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
+ */
+
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+ uint8_t errorcode=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the error code*/
+ errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+
+ /* Return the error code*/
+ return errorcode;
+}
+/**
+ * @brief Returns the CANx Receive Error Counter (REC).
+ * @note In case of an error during reception, this counter is incremented
+ * by 1 or by 8 depending on the error condition as defined by the CAN
+ * standard. After every successful reception, the counter is
+ * decremented by 1 or reset to 120 if its value was higher than 128.
+ * When the counter value exceeds 127, the CAN controller enters the
+ * error passive state.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CAN Receive Error Counter.
+ */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the Receive Error Counter*/
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+
+ /* Return the Receive Error Counter*/
+ return counter;
+}
+
+
+/**
+ * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval LSB of the 9-bit CAN Transmit Error Counter.
+ */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+ uint8_t counter=0;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+
+ /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+ return counter;
+}
+
+
+/**
+ * @brief Enables or disables the specified CANx interrupts.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * - CAN_IT_TME,
+ * - CAN_IT_FMP0,
+ * - CAN_IT_FF0,
+ * - CAN_IT_FOV0,
+ * - CAN_IT_FMP1,
+ * - CAN_IT_FF1,
+ * - CAN_IT_FOV1,
+ * - CAN_IT_EWG,
+ * - CAN_IT_EPV,
+ * - CAN_IT_LEC,
+ * - CAN_IT_ERR,
+ * - CAN_IT_WKU or
+ * - CAN_IT_SLK.
+ * @param NewState: new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IT(CAN_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected CANx interrupt */
+ CANx->IER |= CAN_IT;
+ }
+ else
+ {
+ /* Disable the selected CANx interrupt */
+ CANx->IER &= ~CAN_IT;
+ }
+}
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to check.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_EWG
+ * - CAN_FLAG_EPV
+ * - CAN_FLAG_BOF
+ * - CAN_FLAG_RQCP0
+ * - CAN_FLAG_RQCP1
+ * - CAN_FLAG_RQCP2
+ * - CAN_FLAG_FMP1
+ * - CAN_FLAG_FF1
+ * - CAN_FLAG_FOV1
+ * - CAN_FLAG_FMP0
+ * - CAN_FLAG_FF0
+ * - CAN_FLAG_FOV0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @retval The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+
+ if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
+ {
+ /* Check the status of the specified CAN flag */
+ if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
+ {
+ /* Check the status of the specified CAN flag */
+ if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following flags:
+ * - CAN_FLAG_RQCP0
+ * - CAN_FLAG_RQCP1
+ * - CAN_FLAG_RQCP2
+ * - CAN_FLAG_FF1
+ * - CAN_FLAG_FOV1
+ * - CAN_FLAG_FF0
+ * - CAN_FLAG_FOV0
+ * - CAN_FLAG_WKU
+ * - CAN_FLAG_SLAK
+ * - CAN_FLAG_LEC
+ * @retval None.
+ */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ uint32_t flagtmp=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
+ {
+ /* Clear the selected CAN flags */
+ CANx->ESR = (uint32_t)RESET;
+ }
+ else /* MSR or TSR or RF0R or RF1R */
+ {
+ flagtmp = CAN_FLAG & 0x000FFFFF;
+
+ if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RF0R = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
+ {
+ /* Receive Flags */
+ CANx->RF1R = (uint32_t)(flagtmp);
+ }
+ else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
+ {
+ /* Transmit Flags */
+ CANx->TSR = (uint32_t)(flagtmp);
+ }
+ else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
+ {
+ /* Operating mode Flags */
+ CANx->MSR = (uint32_t)(flagtmp);
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified CANx interrupt has occurred or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt source to check.
+ * This parameter can be one of the following flags:
+ * - CAN_IT_TME
+ * - CAN_IT_FMP0
+ * - CAN_IT_FF0
+ * - CAN_IT_FOV0
+ * - CAN_IT_FMP1
+ * - CAN_IT_FF1
+ * - CAN_IT_FOV1
+ * - CAN_IT_WKU
+ * - CAN_IT_SLK
+ * - CAN_IT_EWG
+ * - CAN_IT_EPV
+ * - CAN_IT_BOF
+ * - CAN_IT_LEC
+ * - CAN_IT_ERR
+ * @retval The current state of CAN_IT (SET or RESET).
+ */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ ITStatus itstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IT(CAN_IT));
+
+ /* check the enable interrupt bit */
+ if((CANx->IER & CAN_IT) != RESET)
+ {
+ /* in case the Interrupt is enabled, .... */
+ switch (CAN_IT)
+ {
+ case CAN_IT_TME:
+ /* Check CAN_TSR_RQCPx bits */
+ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
+ break;
+ case CAN_IT_FMP0:
+ /* Check CAN_RF0R_FMP0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
+ break;
+ case CAN_IT_FF0:
+ /* Check CAN_RF0R_FULL0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
+ break;
+ case CAN_IT_FOV0:
+ /* Check CAN_RF0R_FOVR0 bit */
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
+ break;
+ case CAN_IT_FMP1:
+ /* Check CAN_RF1R_FMP1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
+ break;
+ case CAN_IT_FF1:
+ /* Check CAN_RF1R_FULL1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
+ break;
+ case CAN_IT_FOV1:
+ /* Check CAN_RF1R_FOVR1 bit */
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
+ break;
+ case CAN_IT_WKU:
+ /* Check CAN_MSR_WKUI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
+ break;
+ case CAN_IT_SLK:
+ /* Check CAN_MSR_SLAKI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
+ break;
+ case CAN_IT_EWG:
+ /* Check CAN_ESR_EWGF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
+ break;
+ case CAN_IT_EPV:
+ /* Check CAN_ESR_EPVF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
+ break;
+ case CAN_IT_BOF:
+ /* Check CAN_ESR_BOFF bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
+ break;
+ case CAN_IT_LEC:
+ /* Check CAN_ESR_LEC bit */
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
+ break;
+ case CAN_IT_ERR:
+ /* Check CAN_MSR_ERRI bit */
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
+ break;
+ default :
+ /* in case of error, return RESET */
+ itstatus = RESET;
+ break;
+ }
+ }
+ else
+ {
+ /* in case the Interrupt is not enabled, return RESET */
+ itstatus = RESET;
+ }
+
+ /* Return the CAN_IT status */
+ return itstatus;
+}
+
+/**
+ * @brief Clears the CANx's interrupt pending bits.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the interrupt pending bit to clear.
+ * - CAN_IT_TME
+ * - CAN_IT_FF0
+ * - CAN_IT_FOV0
+ * - CAN_IT_FF1
+ * - CAN_IT_FOV1
+ * - CAN_IT_WKU
+ * - CAN_IT_SLK
+ * - CAN_IT_EWG
+ * - CAN_IT_EPV
+ * - CAN_IT_BOF
+ * - CAN_IT_LEC
+ * - CAN_IT_ERR
+ * @retval None.
+ */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_CLEAR_IT(CAN_IT));
+
+ switch (CAN_IT)
+ {
+ case CAN_IT_TME:
+ /* Clear CAN_TSR_RQCPx (rc_w1)*/
+ CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
+ break;
+ case CAN_IT_FF0:
+ /* Clear CAN_RF0R_FULL0 (rc_w1)*/
+ CANx->RF0R = CAN_RF0R_FULL0;
+ break;
+ case CAN_IT_FOV0:
+ /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
+ CANx->RF0R = CAN_RF0R_FOVR0;
+ break;
+ case CAN_IT_FF1:
+ /* Clear CAN_RF1R_FULL1 (rc_w1)*/
+ CANx->RF1R = CAN_RF1R_FULL1;
+ break;
+ case CAN_IT_FOV1:
+ /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
+ CANx->RF1R = CAN_RF1R_FOVR1;
+ break;
+ case CAN_IT_WKU:
+ /* Clear CAN_MSR_WKUI (rc_w1)*/
+ CANx->MSR = CAN_MSR_WKUI;
+ break;
+ case CAN_IT_SLK:
+ /* Clear CAN_MSR_SLAKI (rc_w1)*/
+ CANx->MSR = CAN_MSR_SLAKI;
+ break;
+ case CAN_IT_EWG:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_IT_EPV:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_IT_BOF:
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : the corresponding Flag is cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ case CAN_IT_LEC:
+ /* Clear LEC bits */
+ CANx->ESR = RESET;
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ break;
+ case CAN_IT_ERR:
+ /*Clear LEC bits */
+ CANx->ESR = RESET;
+ /* Clear CAN_MSR_ERRI (rc_w1) */
+ CANx->MSR = CAN_MSR_ERRI;
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
+ of the CAN Bus status*/
+ break;
+ default :
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg: specifies the CAN interrupt register to check.
+ * @param It_Bit: specifies the interrupt source bit to check.
+ * @retval The new state of the CAN Interrupt (SET or RESET).
+ */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+ ITStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_IT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_IT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_cec.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_cec.c"
new file mode 100644
index 0000000..4dc615f
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_cec.c"
@@ -0,0 +1,433 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_cec.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the CEC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_cec.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CEC
+ * @brief CEC driver modules
+ * @{
+ */
+
+/** @defgroup CEC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Defines
+ * @{
+ */
+
+/* ------------ CEC registers bit address in the alias region ----------- */
+#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of PE bit */
+#define CFGR_OFFSET (CEC_OFFSET + 0x00)
+#define PE_BitNumber 0x00
+#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))
+
+/* Alias word address of IE bit */
+#define IE_BitNumber 0x01
+#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TSOM bit */
+#define CSR_OFFSET (CEC_OFFSET + 0x10)
+#define TSOM_BitNumber 0x00
+#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))
+
+/* Alias word address of TEOM bit */
+#define TEOM_BitNumber 0x01
+#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))
+
+#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */
+#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup CEC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CEC peripheral registers to their default reset
+ * values.
+ * @param None
+ * @retval None
+ */
+void CEC_DeInit(void)
+{
+ /* Enable CEC reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
+ /* Release CEC from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
+}
+
+
+/**
+ * @brief Initializes the CEC peripheral according to the specified
+ * parameters in the CEC_InitStruct.
+ * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that
+ * contains the configuration information for the specified
+ * CEC peripheral.
+ * @retval None
+ */
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode));
+ assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));
+
+ /*---------------------------- CEC CFGR Configuration -----------------*/
+ /* Get the CEC CFGR value */
+ tmpreg = CEC->CFGR;
+
+ /* Clear BTEM and BPEM bits */
+ tmpreg &= CFGR_CLEAR_Mask;
+
+ /* Configure CEC: Bit Timing Error and Bit Period Error */
+ tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);
+
+ /* Write to CEC CFGR register*/
+ CEC->CFGR = tmpreg;
+
+}
+
+/**
+ * @brief Enables or disables the specified CEC peripheral.
+ * @param NewState: new state of the CEC peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CEC_Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;
+
+ if(NewState == DISABLE)
+ {
+ /* Wait until the PE bit is cleared by hardware (Idle Line detected) */
+ while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)
+ {
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the CEC interrupt.
+ * @param NewState: new state of the CEC interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CEC_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Defines the Own Address of the CEC device.
+ * @param CEC_OwnAddress: The CEC own address
+ * @retval None
+ */
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
+
+ /* Set the CEC own address */
+ CEC->OAR = CEC_OwnAddress;
+}
+
+/**
+ * @brief Sets the CEC prescaler value.
+ * @param CEC_Prescaler: CEC prescaler new value
+ * @retval None
+ */
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_PRESCALER(CEC_Prescaler));
+
+ /* Set the Prescaler value*/
+ CEC->PRES = CEC_Prescaler;
+}
+
+/**
+ * @brief Transmits single data through the CEC peripheral.
+ * @param Data: the data to transmit.
+ * @retval None
+ */
+void CEC_SendDataByte(uint8_t Data)
+{
+ /* Transmit Data */
+ CEC->TXD = Data ;
+}
+
+
+/**
+ * @brief Returns the most recent received data by the CEC peripheral.
+ * @param None
+ * @retval The received data.
+ */
+uint8_t CEC_ReceiveDataByte(void)
+{
+ /* Receive Data */
+ return (uint8_t)(CEC->RXD);
+}
+
+/**
+ * @brief Starts a new message.
+ * @param None
+ * @retval None
+ */
+void CEC_StartOfMessage(void)
+{
+ /* Starts of new message */
+ *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;
+}
+
+/**
+ * @brief Transmits message with or without an EOM bit.
+ * @param NewState: new state of the CEC Tx End Of Message.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void CEC_EndOfMessageCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* The data byte will be transmitted with or without an EOM bit*/
+ *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Gets the CEC flag status
+ * @param CEC_FLAG: specifies the CEC flag to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_FLAG_BTE: Bit Timing Error
+ * @arg CEC_FLAG_BPE: Bit Period Error
+ * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error
+ * @arg CEC_FLAG_SBE: Start Bit Error
+ * @arg CEC_FLAG_ACKE: Block Acknowledge Error
+ * @arg CEC_FLAG_LINE: Line Error
+ * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error
+ * @arg CEC_FLAG_TEOM: Tx End Of Message
+ * @arg CEC_FLAG_TERR: Tx Error
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message
+ * @arg CEC_FLAG_REOM: Rx End Of Message
+ * @arg CEC_FLAG_RERR: Rx Error
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+ * @retval The new state of CEC_FLAG (SET or RESET)
+ */
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t cecreg = 0, cecbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
+
+ /* Get the CEC peripheral base address */
+ cecbase = (uint32_t)(CEC_BASE);
+
+ /* Read flag register index */
+ cecreg = CEC_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ CEC_FLAG &= FLAG_Mask;
+
+ if(cecreg != 0)
+ {
+ /* Flag in CEC ESR Register */
+ CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);
+
+ /* Get the CEC ESR register address */
+ cecbase += 0xC;
+ }
+ else
+ {
+ /* Get the CEC CSR register address */
+ cecbase += 0x10;
+ }
+
+ if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)
+ {
+ /* CEC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CEC_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the CEC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CEC's pending flags.
+ * @param CEC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg CEC_FLAG_TERR: Tx Error
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message
+ * @arg CEC_FLAG_REOM: Rx End Of Message
+ * @arg CEC_FLAG_RERR: Rx Error
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished
+ * @retval None
+ */
+void CEC_ClearFlag(uint32_t CEC_FLAG)
+{
+ uint32_t tmp = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
+
+ tmp = CEC->CSR & 0x2;
+
+ /* Clear the selected CEC flags */
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+ * @brief Checks whether the specified CEC interrupt has occurred or not.
+ * @param CEC_IT: specifies the CEC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CEC_IT_TERR: Tx Error
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished
+ * @arg CEC_IT_RERR: Rx Error
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished
+ * @retval The new state of CEC_IT (SET or RESET).
+ */
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_GET_IT(CEC_IT));
+
+ /* Get the CEC IT enable bit status */
+ enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;
+
+ /* Check the status of the specified CEC interrupt */
+ if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* CEC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CEC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the CEC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CEC's interrupt pending bits.
+ * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg CEC_IT_TERR: Tx Error
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished
+ * @arg CEC_IT_RERR: Rx Error
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished
+ * @retval None
+ */
+void CEC_ClearITPendingBit(uint16_t CEC_IT)
+{
+ uint32_t tmp = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_CEC_GET_IT(CEC_IT));
+
+ tmp = CEC->CSR & 0x2;
+
+ /* Clear the selected CEC interrupt pending bits */
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_crc.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_crc.c"
new file mode 100644
index 0000000..6501728
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_crc.c"
@@ -0,0 +1,160 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the CRC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @defgroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DR).
+ * @param None
+ * @retval None
+ */
+void CRC_ResetDR(void)
+{
+ /* Reset CRC generator */
+ CRC->CR = CRC_CR_RESET;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data: data word(32-bit) to compute its CRC
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+ CRC->DR = Data;
+
+ return (CRC->DR);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer: pointer to the buffer containing the data to be computed
+ * @param BufferLength: length of the buffer to be computed
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for(index = 0; index < BufferLength; index++)
+ {
+ CRC->DR = pBuffer[index];
+ }
+ return (CRC->DR);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @param None
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_GetCRC(void)
+{
+ return (CRC->DR);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+ CRC->IDR = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @param None
+ * @retval 8-bit value of the ID register
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+ return (CRC->IDR);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dac.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dac.c"
new file mode 100644
index 0000000..1cfc71d
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dac.c"
@@ -0,0 +1,571 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the DAC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dac.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @defgroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Defines
+ * @{
+ */
+
+/* CR register Mask */
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+ * contains the configuration information for the specified DAC channel.
+ * @retval None
+ */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+/*---------------------------- DAC CR Configuration --------------------------*/
+ /* Get the DAC CR value */
+ tmpreg1 = DAC->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set WAVEx bits according to DAC_WaveGeneration value */
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << DAC_Channel;
+ /* Write to DAC CR */
+ DAC->CR = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the DAC_Trigger member */
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+ /* Initialize the DAC_WaveGeneration member */
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+ /* Initialize the DAC_OutputBuffer member */
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);
+ }
+}
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+ * @brief Enables or disables the specified DAC interrupts.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @param NewState: new state of the specified DAC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC interrupts */
+ DAC->CR |= (DAC_IT << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC interrupts */
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+ }
+}
+#endif
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param NewState: new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SWTRIGR |= DUAL_SWTRIG_SET ;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_Wave: Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_Wave_Noise: noise wave generation
+ * @arg DAC_Wave_Triangle: triangle wave generation
+ * @param NewState: new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ DAC->CR |= DAC_Wave << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R1_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel2.
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R2_OFFSET + DAC_Align;
+
+ /* Set the DAC channel2 selected data holding register */
+ *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual channel
+ * DAC.
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data
+ * holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data
+ * holding register.
+ * @retval None
+ */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (DAC_Align == DAC_Align_8b_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12RD_OFFSET + DAC_Align;
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+ tmp = (uint32_t) DAC_BASE ;
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/**
+ * @brief Checks whether the specified DAC flag is set or not.
+ * @param DAC_Channel: thee selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to check.
+ * This parameter can be only of the following value:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @retval The new state of DAC_FLAG (SET or RESET).
+ */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Check the status of the specified DAC flag */
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+ {
+ /* DAC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channelx's pending flags.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to clear.
+ * This parameter can be of the following value:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @retval None
+ */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Clear the selected DAC flags */
+ DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+ * @brief Checks whether the specified DAC interrupt has occurred or not.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt source to check.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @retval The new state of DAC_IT (SET or RESET).
+ */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Get the DAC_IT enable bit status */
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+
+ /* Check the status of the specified DAC interrupt */
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+ {
+ /* DAC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channelx's interrupt pending bits.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @retval None
+ */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Clear the selected DAC interrupt pending bits */
+ DAC->SR = (DAC_IT << DAC_Channel);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c"
new file mode 100644
index 0000000..96a8fde
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dbgmcu.c"
@@ -0,0 +1,162 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the DBGMCU firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dbgmcu.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DBGMCU
+ * @brief DBGMCU driver modules
+ * @{
+ */
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Returns the device revision identifier.
+ * @param None
+ * @retval Device revision identifier
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+ return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @param None
+ * @retval Device identifier
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBGMCU_Periph: specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+ * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
+ * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
+ * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
+ * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
+ * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
+ * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
+ * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
+ * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
+ * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
+ * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
+ * @param NewState: new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->CR |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->CR &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dma.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dma.c"
new file mode 100644
index 0000000..bf072df
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_dma.c"
@@ -0,0 +1,714 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the DMA firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dma.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @defgroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Defines
+ * @{
+ */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval None
+ */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
+
+ /* Reset DMAy Channelx control register */
+ DMAy_Channelx->CCR = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAy_Channelx->CNDTR = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAy_Channelx->CPAR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAy_Channelx->CMAR = 0;
+
+ if (DMAy_Channelx == DMA1_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA1->IFCR |= DMA1_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA1->IFCR |= DMA1_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA1->IFCR |= DMA1_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA1->IFCR |= DMA1_Channel4_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA1->IFCR |= DMA1_Channel5_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA1->IFCR |= DMA1_Channel6_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA1->IFCR |= DMA1_Channel7_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel1 */
+ DMA2->IFCR |= DMA2_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel2 */
+ DMA2->IFCR |= DMA2_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel3 */
+ DMA2->IFCR |= DMA2_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel4 */
+ DMA2->IFCR |= DMA2_Channel4_IT_Mask;
+ }
+ else
+ {
+ if (DMAy_Channelx == DMA2_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel5 */
+ DMA2->IFCR |= DMA2_Channel5_IT_Mask;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitStruct.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+ * contains the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+ /* Get the DMAy_Channelx CCR value */
+ tmpreg = DMAy_Channelx->CCR;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpreg &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to DMA_DIR value */
+ /* Set CIRC bit according to DMA_Mode value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set the MEM2MEM bit according to DMA_M2M value */
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+ /* Write to DMAy Channelx CCR */
+ DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+ /* Write to DMAy Channelx CPAR */
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+ /* Write to DMAy Channelx CMAR */
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+ /* Initialize the DMA_MemoryBaseAddr member */
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+ /* Initialize the DMA_M2M member */
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param NewState: new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAy_Channelx->CCR |= DMA_CCR1_EN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @param NewState: new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAy_Channelx->CCR |= DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAy_Channelx->CCR &= ~DMA_IT;
+ }
+}
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DataNumber: The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAy_Channelx is disabled.
+ * @retval None.
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval The number of remaining data units in the current DMAy Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.
+ * @param DMAy_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+ {
+ /* DMAy_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAy_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's pending flags.
+ * @param DMAy_FLAG: specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval None
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy flags */
+ DMA2->IFCR = DMAy_FLAG;
+ }
+ else
+ {
+ /* Clear the selected DMAy flags */
+ DMA1->IFCR = DMAy_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
+ * @param DMAy_IT: specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+ /* Calculate the used DMA */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR;
+ }
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMA_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's interrupt pending bits.
+ * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval None
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA2->IFCR = DMAy_IT;
+ }
+ else
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA1->IFCR = DMAy_IT;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_exti.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_exti.c"
new file mode 100644
index 0000000..b6290d5
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_exti.c"
@@ -0,0 +1,269 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the EXTI firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_exti.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @defgroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMR = 0x00000000;
+ EXTI->EMR = 0x00000000;
+ EXTI->RTSR = 0x00000000;
+ EXTI->FTSR = 0x00000000;
+ EXTI->PR = 0x000FFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ * that contains the configuration information for the EXTI peripheral.
+ * @retval None
+ */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line: specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line: specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMR & EXTI_Line;
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line: specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_flash.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_flash.c"
new file mode 100644
index 0000000..cdff9e9
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_flash.c"
@@ -0,0 +1,1684 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the FLASH firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_flash.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @defgroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
+
+/* Flash Control Register bits */
+#define CR_PG_Set ((uint32_t)0x00000001)
+#define CR_PG_Reset ((uint32_t)0x00001FFE)
+#define CR_PER_Set ((uint32_t)0x00000002)
+#define CR_PER_Reset ((uint32_t)0x00001FFD)
+#define CR_MER_Set ((uint32_t)0x00000004)
+#define CR_MER_Reset ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set ((uint32_t)0x00000020)
+#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
+#define CR_STRT_Set ((uint32_t)0x00000040)
+#define CR_LOCK_Set ((uint32_t)0x00000080)
+
+/* FLASH Mask */
+#define RDPRT_Mask ((uint32_t)0x00000002)
+#define WRP0_Mask ((uint32_t)0x000000FF)
+#define WRP1_Mask ((uint32_t)0x0000FF00)
+#define WRP2_Mask ((uint32_t)0x00FF0000)
+#define WRP3_Mask ((uint32_t)0xFF000000)
+#define OB_USER_BFB2 ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+@code
+
+ This driver provides functions to configure and program the Flash memory of all STM32F10x devices,
+ including the latest STM32F10x_XL density devices.
+
+ STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
+ - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)
+ - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)
+ While other STM32F10x devices features only one bank with memory up to 512 Kbytes.
+
+ In version V3.3.0, some functions were updated and new ones were added to support
+ STM32F10x_XL devices. Thus some functions manages all devices, while other are
+ dedicated for XL devices only.
+
+ The table below presents the list of available functions depending on the used STM32F10x devices.
+
+ ***************************************************
+ * Legacy functions used for all STM32F10x devices *
+ ***************************************************
+ +----------------------------------------------------------------------------------------------------------------------------------+
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
+ | | devices | devices | |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_SetLatency | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_PrefetchBufferCmd | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |
+ | | | | - For other devices: unlock Bank1 and it is equivalent |
+ | | | | to FLASH_UnlockBank1 function. |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |
+ | | | | - For other devices: lock Bank1 and it is equivalent |
+ | | | | to FLASH_LockBank1 function. |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |
+ | | | | - For other devices: erase a page in Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |
+ | | | | - For other devices: erase all pages in Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_EraseOptionBytes | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ProgramOptionByteData | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_EnableWriteProtection | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ReadOutProtection | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_UserOptionByteConfig | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetUserOptionByte | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|
+ | | | | - For other devices: enable Bank1's interrupts |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|
+ | | | | - For other devices: return Bank1's flag status |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |
+ | | | | - For other devices: clear Bank1's flag |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |
+ | | | | equivalent to FLASH_GetBank1Status function |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |
+ | | | | equivalent to: FLASH_WaitForLastBank1Operation function |
+ +----------------------------------------------------------------------------------------------------------------------------------+
+
+ ************************************************************************************************************************
+ * New functions used for all STM32F10x devices to manage Bank1: *
+ * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *
+ * - For other devices, these functions are optional (covered by functions listed above) *
+ ************************************************************************************************************************
+ +----------------------------------------------------------------------------------------------------------------------------------+
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
+ | | devices | devices | |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |
+ +----------------------------------------------------------------------------------------------------------------------------------+
+
+ *****************************************************************************
+ * New Functions used only with STM32F10x_XL density devices to manage Bank2 *
+ *****************************************************************************
+ +----------------------------------------------------------------------------------------------------------------------------------+
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |
+ | | devices | devices | |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ |FLASH_LockBank2 | Yes | No | - Lock Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |
+ |----------------------------------------------------------------------------------------------------------------------------------|
+ | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |
+ +----------------------------------------------------------------------------------------------------------------------------------+
+@endcode
+*/
+
+
+/**
+ * @brief Sets the code latency value.
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_Latency: specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle
+ * @arg FLASH_Latency_1: FLASH One Latency cycle
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles
+ * @retval None
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpreg = FLASH->ACR;
+
+ /* Sets the Latency value */
+ tmpreg &= ACR_LATENCY_Mask;
+ tmpreg |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->ACR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Half cycle flash access.
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+ * This parameter can be one of the following values:
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+ * @retval None
+ */
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
+
+ /* Enable or disable the Half cycle access */
+ FLASH->ACR &= ACR_HLFCYA_Mask;
+ FLASH->ACR |= FLASH_HalfCycleAccess;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+ * @retval None
+ */
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->ACR &= ACR_PRFTBE_Mask;
+ FLASH->ACR |= FLASH_PrefetchBuffer;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.
+ * - For all other devices it unlocks Bank1 and it is equivalent
+ * to FLASH_UnlockBank1 function..
+ * @param None
+ * @retval None
+ */
+void FLASH_Unlock(void)
+{
+ /* Authorize the FPEC of Bank1 Access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+
+#ifdef STM32F10X_XL
+ /* Authorize the FPEC of Bank2 Access */
+ FLASH->KEYR2 = FLASH_KEY1;
+ FLASH->KEYR2 = FLASH_KEY2;
+#endif /* STM32F10X_XL */
+}
+/**
+ * @brief Unlocks the FLASH Bank1 Program Erase Controller.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function unlocks Bank1.
+ * - For all other devices it unlocks Bank1 and it is
+ * equivalent to FLASH_Unlock function.
+ * @param None
+ * @retval None
+ */
+void FLASH_UnlockBank1(void)
+{
+ /* Authorize the FPEC of Bank1 Access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Unlocks the FLASH Bank2 Program Erase Controller.
+ * @note This function can be used only for STM32F10X_XL density devices.
+ * @param None
+ * @retval None
+ */
+void FLASH_UnlockBank2(void)
+{
+ /* Authorize the FPEC of Bank2 Access */
+ FLASH->KEYR2 = FLASH_KEY1;
+ FLASH->KEYR2 = FLASH_KEY2;
+
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.
+ * - For all other devices it Locks Bank1 and it is equivalent
+ * to FLASH_LockBank1 function.
+ * @param None
+ * @retval None
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
+ FLASH->CR |= CR_LOCK_Set;
+
+#ifdef STM32F10X_XL
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
+ FLASH->CR2 |= CR_LOCK_Set;
+#endif /* STM32F10X_XL */
+}
+
+/**
+ * @brief Locks the FLASH Bank1 Program Erase Controller.
+ * @note this function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function Locks Bank1.
+ * - For all other devices it Locks Bank1 and it is equivalent
+ * to FLASH_Lock function.
+ * @param None
+ * @retval None
+ */
+void FLASH_LockBank1(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */
+ FLASH->CR |= CR_LOCK_Set;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Locks the FLASH Bank2 Program Erase Controller.
+ * @note This function can be used only for STM32F10X_XL density devices.
+ * @param None
+ * @retval None
+ */
+void FLASH_LockBank2(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */
+ FLASH->CR2 |= CR_LOCK_Set;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Page_Address: The page address to be erased.
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+#ifdef STM32F10X_XL
+ if(Page_Address < FLASH_BANK1_END_ADDRESS)
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR|= CR_PER_Set;
+ FLASH->AR = Page_Address;
+ FLASH->CR|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CR &= CR_PER_Reset;
+ }
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR2|= CR_PER_Set;
+ FLASH->AR2 = Page_Address;
+ FLASH->CR2|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CR2 &= CR_PER_Reset;
+ }
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR|= CR_PER_Set;
+ FLASH->AR = Page_Address;
+ FLASH->CR|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ /* Disable the PER Bit */
+ FLASH->CR &= CR_PER_Reset;
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+#ifdef STM32F10X_XL
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR2 |= CR_MER_Set;
+ FLASH->CR2 |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR2 &= CR_MER_Reset;
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all Bank1 FLASH pages.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices this function erases all Bank1 pages.
+ * - For all other devices it erases all Bank1 pages and it is equivalent
+ * to FLASH_EraseAllPages function.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank1Pages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Erases all Bank2 FLASH pages.
+ * @note This function can be used only for STM32F10x_XL density devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank2Pages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR2 |= CR_MER_Set;
+ FLASH->CR2 |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);
+
+ /* Disable the MER Bit */
+ FLASH->CR2 &= CR_MER_Reset;
+ }
+ /* Return the Erase Status */
+ return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+ uint16_t rdptmp = RDP_Key;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Get the actual read protection Option Byte value */
+ if(FLASH_GetReadOutProtectionStatus() != RESET)
+ {
+ rdptmp = 0x00;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ /* Restore the last read protection Option Byte value */
+ OB->RDP = (uint16_t)rdptmp;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+#ifdef STM32F10X_XL
+ if(Address < FLASH_BANK1_END_ADDRESS - 2)
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ }
+ else if(Address == (FLASH_BANK1_END_ADDRESS - 1))
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ FLASH->CR2 |= CR_PG_Set;
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ }
+ else
+ {
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR2 |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ }
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified address.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+
+#ifdef STM32F10X_XL
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(Address < FLASH_BANK1_END_ADDRESS)
+ {
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ else
+ {
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR2 |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR2 &= CR_PG_Reset;
+ }
+ }
+#else
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note This function can be used for all STM32F10x devices.
+ * @param FLASH_Pages: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
+ * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
+ * and FLASH_WRProt_Pages124to127
+ * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
+ * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
+ * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511
+ * @arg FLASH_WRProt_AllPages
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTPG_Set;
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 = WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 = WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 = WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 = WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @note This function can be used for all STM32F10x devices.
+ * @param Newstate: new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ if(NewState != DISABLE)
+ {
+ OB->RDP = 0x00;
+ }
+ else
+ {
+ OB->RDP = RDP_Key;
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @note This function can be used for all STM32F10x devices.
+ * @param OB_IWDG: Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param OB_STOP: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param OB_STDBY: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+
+ OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Configures to boot from Bank1 or Bank2.
+ * @note This function can be used only for STM32F10x_XL density devices.
+ * @param FLASH_BOOT: select the FLASH Bank to boot from.
+ * This parameter can be one of the following values:
+ * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash
+ * position and this parameter is selected the device will boot from Bank1(Default).
+ * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash
+ * position and this parameter is selected the device will boot from Bank2 or Bank1,
+ * depending on the activation of the bank. The active banks are checked in
+ * the following order: Bank2, followed by Bank1.
+ * The active bank is recognized by the value programmed at the base address
+ * of the respective bank (corresponding to the initial stack pointer value
+ * in the interrupt vector table).
+ * For more information, please refer to AN2606 from www.st.com.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ assert_param(IS_FLASH_BOOT(FLASH_BOOT));
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+
+ if(FLASH_BOOT == FLASH_BOOT_Bank1)
+ {
+ OB->USER |= OB_USER_BFB2;
+ }
+ else
+ {
+ OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+ /* Return the Flash write protection Register value */
+ return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @note This function can be used for all STM32F10x devices.
+ * @param None
+ * @retval FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts
+ for Bank1 and Bank2.
+ * - For other devices it enables or disables the specified FLASH interrupts for Bank1.
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR: FLASH Error Interrupt
+ * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+ * @param NewState: new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+#ifdef STM32F10X_XL
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if((FLASH_IT & 0x80000000) != 0x0)
+ {
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
+ }
+ }
+ else
+ {
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+ }
+#else
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+#endif /* STM32F10X_XL */
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices, this function checks whether the specified
+ * Bank1 or Bank2 flag is set or not.
+ * - For other devices, it checks whether the specified Bank1 flag is
+ * set or not.
+ * @param FLASH_FLAG: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+#ifdef STM32F10X_XL
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+ {
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH_FLAG & 0x80000000) != 0x0)
+ {
+ if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ }
+#else
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+ {
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+#endif /* STM32F10X_XL */
+
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @note This function can be used for all STM32F10x devices.
+ * - For STM32F10X_XL devices, this function clears Bank1 or Bank2抯 pending flags
+ * - For other devices, it clears Bank1抯 pending flags.
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @retval None
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+#ifdef STM32F10X_XL
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+ if((FLASH_FLAG & 0x80000000) != 0x0)
+ {
+ /* Clear the flags */
+ FLASH->SR2 = FLASH_FLAG;
+ }
+ else
+ {
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+ }
+
+#else
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+#endif /* STM32F10X_XL */
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @note This function can be used for all STM32F10x devices, it is equivalent
+ * to FLASH_GetBank1Status function.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Returns the FLASH Bank1 Status.
+ * @note This function can be used for all STM32F10x devices, it is equivalent
+ * to FLASH_GetStatus function.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Returns the FLASH Bank2 Status.
+ * @note This function can be used for STM32F10x_XL density devices.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetBank2Status(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+#endif /* STM32F10X_XL */
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @note This function can be used for all STM32F10x devices,
+ * it is equivalent to FLASH_WaitForLastBank1Operation.
+ * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation
+ * to complete or a TIMEOUT to occur.
+ * - For all other devices it waits for a Flash operation to complete
+ * or a TIMEOUT to occur.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetBank1Status();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetBank1Status();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+ * @note This function can be used for all STM32F10x devices,
+ * it is equivalent to FLASH_WaitForLastOperation.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetBank1Status();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetBank1Status();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+#ifdef STM32F10X_XL
+/**
+ * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.
+ * @note This function can be used only for STM32F10x_XL density devices.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetBank2Status();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
+ {
+ status = FLASH_GetBank2Status();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+#endif /* STM32F10X_XL */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_fsmc.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_fsmc.c"
new file mode 100644
index 0000000..51669ee
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_fsmc.c"
@@ -0,0 +1,866 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the FSMC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FSMC
+ * @brief FSMC driver modules
+ * @{
+ */
+
+/** @defgroup FSMC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Defines
+ * @{
+ */
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
+ * reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @retval None
+ */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+
+ /* FSMC_Bank1_NORSRAM1 */
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
+ }
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+ else
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
+ }
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval None
+ */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Set the FSMC_Bank2 registers to their reset values */
+ FSMC_Bank2->PCR2 = 0x00000018;
+ FSMC_Bank2->SR2 = 0x00000040;
+ FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+ FSMC_Bank2->PATT2 = 0xFCFCFCFC;
+ }
+ /* FSMC_Bank3_NAND */
+ else
+ {
+ /* Set the FSMC_Bank3 registers to their reset values */
+ FSMC_Bank3->PCR3 = 0x00000018;
+ FSMC_Bank3->SR3 = 0x00000040;
+ FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+ FSMC_Bank3->PATT3 = 0xFCFCFCFC;
+ }
+}
+
+/**
+ * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void FSMC_PCCARDDeInit(void)
+{
+ /* Set the FSMC_Bank4 registers to their reset values */
+ FSMC_Bank4->PCR4 = 0x00000018;
+ FSMC_Bank4->SR4 = 0x00000000;
+ FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+ FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+ FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
+ * parameters in the FSMC_NORSRAMInitStruct.
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+ * structure that contains the configuration information for
+ * the FSMC NOR/SRAM specified Banks.
+ * @retval None
+ */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+ assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
+
+ /* Bank1 NOR/SRAM control register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+ {
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+ }
+
+ /* Bank1 NOR/SRAM timing register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+
+
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+ {
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+ }
+ else
+ {
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC NAND Banks according to the specified
+ * parameters in the FSMC_NANDInitStruct.
+ * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
+ * structure that contains the configuration information for the FSMC
+ * NAND specified Banks.
+ * @retval None
+ */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+ /* Check the parameters */
+ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+ assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+ assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+ assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+ assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+ assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+ assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+ PCR_MemoryType_NAND |
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NANDInitStruct->FSMC_ECC |
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* FSMC_Bank2_NAND registers configuration */
+ FSMC_Bank2->PCR2 = tmppcr;
+ FSMC_Bank2->PMEM2 = tmppmem;
+ FSMC_Bank2->PATT2 = tmppatt;
+ }
+ else
+ {
+ /* FSMC_Bank3_NAND registers configuration */
+ FSMC_Bank3->PCR3 = tmppcr;
+ FSMC_Bank3->PMEM3 = tmppmem;
+ FSMC_Bank3->PATT3 = tmppatt;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC PCCARD Bank according to the specified
+ * parameters in the FSMC_PCCARDInitStruct.
+ * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
+ * structure that contains the configuration information for the FSMC
+ * PCCARD Bank.
+ * @retval None
+ */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+ assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+ assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+ FSMC_MemoryDataWidth_16b |
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+}
+
+/**
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Reset NOR/SRAM Init structure parameters values */
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+ * @brief Fills each FSMC_NANDInitStruct member with its default value.
+ * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ /* Reset NAND Init structure parameters values */
+ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+ FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+ FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+ FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
+ * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Reset PCCARD Init structure parameters values */
+ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+ }
+ else
+ {
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified NAND Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the PCCARD Memory Bank.
+ * @param NewState: new state of the PCCARD Memory Bank.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the FSMC NAND ECC feature.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC NAND ECC feature.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Returns the error correction code register value.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval The Error Correction Code (ECC) value.
+ */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+ uint32_t eccval = 0x00000000;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Get the ECCR2 register value */
+ eccval = FSMC_Bank2->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ eccval = FSMC_Bank3->ECCR3;
+ }
+ /* Return the error correction code value */
+ return(eccval);
+}
+
+/**
+ * @brief Enables or disables the specified FSMC interrupts.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @param NewState: new state of the specified FSMC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 |= FSMC_IT;
+ }
+ }
+ else
+ {
+ /* Disable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+
+ FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC flag is set or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
+ * @retval The new state of FSMC_FLAG (SET or RESET).
+ */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ /* Get the flag status */
+ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC's pending flags.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @retval None
+ */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~FSMC_FLAG;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC interrupt has occurred or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval The new state of FSMC_IT (SET or RESET).
+ */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ itstatus = tmpsr & FSMC_IT;
+
+ itenable = tmpsr & (FSMC_IT >> 3);
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC's interrupt pending bits.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval None
+ */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_gpio.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_gpio.c"
new file mode 100644
index 0000000..457ff11
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_gpio.c"
@@ -0,0 +1,650 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the GPIO firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @defgroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* --- MAPR Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber ((u8)0x17)
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
+#define LSB_MASK ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval None
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+ }
+ else if (GPIOx == GPIOE)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+ }
+ else if (GPIOx == GPIOF)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
+ }
+ else
+ {
+ if (GPIOx == GPIOG)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void GPIO_AFIODeInit(void)
+{
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+ uint32_t tmpreg = 0x00, pinmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+ /* Output mode */
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+ }
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+ /* Configure the eight low port pins */
+ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+ {
+ tmpreg = GPIOx->CRL;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding low control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << pinpos);
+ }
+ else
+ {
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
+ }
+ }
+ }
+ }
+ GPIOx->CRL = tmpreg;
+ }
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+ /* Configure the eight high port pins */
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+ {
+ tmpreg = GPIOx->CRH;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));
+ /* Get the port pins position */
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding high control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ }
+ }
+ GPIOx->CRH = tmpreg;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enum values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param PortVal: specifies the value to be written to the port output data register.
+ * @retval None
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ * @param GPIO_PinSource: specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmpreg = AFIO->EVCR;
+ /* Clear the PORT[6:4] and PIN[3:0] bits */
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;
+ tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+ tmpreg |= GPIO_PinSource;
+ AFIO->EVCR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param NewState: new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param GPIO_Remap: selects the pin to remap.
+ * This parameter can be one of the following values:
+ * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
+ * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
+ * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
+ * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
+ * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
+ * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
+ * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
+ * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
+ * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
+ * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
+ * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
+ * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
+ * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
+ * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
+ * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
+ * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
+ * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
+ * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
+ * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
+ * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
+ * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
+ * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
+ * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
+ * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
+ * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
+ * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
+ * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
+ * When the SPI3/I2S3 is remapped using this function, the SWJ is configured
+ * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
+ * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
+ * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
+ * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
+ * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
+ * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
+ * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
+ * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
+ * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
+ * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
+ * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
+ * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
+ * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
+ * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
+ * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
+ * only for High density Value line devices)
+ * @param NewState: new state of the port pin remapping.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if((GPIO_Remap & 0x80000000) == 0x80000000)
+ {
+ tmpreg = AFIO->MAPR2;
+ }
+ else
+ {
+ tmpreg = AFIO->MAPR;
+ }
+
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+ tmp = GPIO_Remap & LSB_MASK;
+
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+ {
+ tmpreg &= DBGAFR_SWJCFG_MASK;
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
+ }
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+ {
+ tmp1 = ((uint32_t)0x03) << tmpmask;
+ tmpreg &= ~tmp1;
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+ else
+ {
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+
+ if (NewState != DISABLE)
+ {
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
+ }
+
+ if((GPIO_Remap & 0x80000000) == 0x80000000)
+ {
+ AFIO->MAPR2 = tmpreg;
+ }
+ else
+ {
+ AFIO->MAPR = tmpreg;
+ }
+}
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ * @param GPIO_PinSource: specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+ * @brief Selects the Ethernet media interface.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
+ * This parameter can be one of the following values:
+ * @arg GPIO_ETH_MediaInterface_MII: MII mode
+ * @arg GPIO_ETH_MediaInterface_RMII: RMII mode
+ * @retval None
+ */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
+{
+ assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
+
+ /* Configure MII_RMII selection bit */
+ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_i2c.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_i2c.c"
new file mode 100644
index 0000000..4ea321c
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_i2c.c"
@@ -0,0 +1,1331 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the I2C firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @defgroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CR1_PE_Set ((uint16_t)0x0001)
+#define CR1_PE_Reset ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CR1_START_Set ((uint16_t)0x0100)
+#define CR1_START_Reset ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set ((uint16_t)0x0200)
+#define CR1_STOP_Reset ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set ((uint16_t)0x0400)
+#define CR1_ACK_Reset ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set ((uint16_t)0x0040)
+#define CR1_ENGC_Reset ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set ((uint16_t)0x8000)
+#define CR1_SWRST_Reset ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set ((uint16_t)0x1000)
+#define CR1_PEC_Reset ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set ((uint16_t)0x0020)
+#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set ((uint16_t)0x0010)
+#define CR1_ENARP_Reset ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
+#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set ((uint16_t)0x0800)
+#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set ((uint16_t)0x1000)
+#define CR2_LAST_Reset ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set ((uint16_t)0x0001)
+#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set ((uint16_t)0x0001)
+#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CCR_FS_Set ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+ * contains the configuration information for the specified I2C peripheral.
+ * @retval None
+ */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+ uint16_t tmpreg = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk1 = 8000000;
+ RCC_ClocksTypeDef rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+ /* Get the I2Cx CR2 value */
+ tmpreg = I2Cx->CR2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpreg &= CR2_FREQ_Reset;
+ /* Get pclk1 frequency value */
+ RCC_GetClocksFreq(&rcc_clocks);
+ pclk1 = rcc_clocks.PCLK1_Frequency;
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk1 / 1000000);
+ tmpreg |= freqrange;
+ /* Write to I2Cx CR2 */
+ I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TRISE */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ /* Reset tmpreg value */
+ /* Clear F/S, DUTY and CCR[11:0] bits */
+ tmpreg = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+ /* Test if CCR value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpreg |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+ {
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+ }
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_DutyCycle_16_9;
+ }
+
+ /* Test if CCR value is under 0x1*/
+ if ((result & CCR_CCR_Set) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpreg |= (uint16_t)(result | CCR_FS_Set);
+ /* Set Maximum Rise Time for fast mode */
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+
+ /* Write to I2Cx CCR */
+ I2Cx->CCR = tmpreg;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+ /* Get the I2Cx CR1 value */
+ tmpreg = I2Cx->CR1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+ /* Set ACK bit according to I2C_Ack value */
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the I2C_ClockSpeed member */
+ I2C_InitStruct->I2C_ClockSpeed = 5000;
+ /* Initialize the I2C_Mode member */
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+ /* Initialize the I2C_DutyCycle member */
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+ /* Initialize the I2C_OwnAddress1 member */
+ I2C_InitStruct->I2C_OwnAddress1 = 0;
+ /* Initialize the I2C_Ack member */
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+ /* Initialize the I2C_AcknowledgedAddress member */
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CR2 |= CR2_DMAEN_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CR2 &= CR2_DMAEN_Reset;
+ }
+}
+
+/**
+ * @brief Specifies if the next DMA transfer will be the last one.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CR2 |= CR2_LAST_Set;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CR2 &= CR2_LAST_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CR1 |= CR1_START_Set;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CR1 &= CR1_START_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CR1 |= CR1_STOP_Set;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CR1 &= CR1_STOP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CR1 |= CR1_ACK_Set;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CR1 &= CR1_ACK_Reset;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the 7bit I2C own address2.
+ * @retval None.
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->OAR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpreg &= OAR2_ADD2_Reset;
+
+ /* Set I2Cx Own address2 */
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OAR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CR1 |= CR1_ENGC_Set;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CR1 &= CR1_ENGC_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt mask
+ * @arg I2C_IT_EVT: Event interrupt mask
+ * @arg I2C_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CR2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data: Byte to be transmitted..
+ * @retval None
+ */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Write in the DR register the data to be sent */
+ I2Cx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the data in the DR register */
+ return (uint8_t)I2Cx->DR;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address which will be transmitted
+ * @param I2C_Direction: specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_Direction_Transmitter: Transmitter mode
+ * @arg I2C_Direction_Receiver: Receiver mode
+ * @retval None.
+ */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_Direction_Transmitter)
+ {
+ /* Set the address bit0 for read */
+ Address |= OAR1_ADD0_Set;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OAR1_ADD0_Reset;
+ }
+ /* Send the address */
+ I2Cx->DR = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2C_Register: specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_Register_CR1: CR1 register.
+ * @arg I2C_Register_CR2: CR2 register.
+ * @arg I2C_Register_OAR1: OAR1 register.
+ * @arg I2C_Register_OAR2: OAR2 register.
+ * @arg I2C_Register_DR: DR register.
+ * @arg I2C_Register_SR1: SR1 register.
+ * @arg I2C_Register_SR2: SR2 register.
+ * @arg I2C_Register_CCR: CCR register.
+ * @arg I2C_Register_TRISE: TRISE register.
+ * @retval The value of the read register.
+ */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_REGISTER(I2C_Register));
+
+ tmp = (uint32_t) I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CR1 |= CR1_SWRST_Set;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CR1 &= CR1_SWRST_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C NACK position in master receiver mode.
+ * This function is useful in I2C Master Receiver mode when the number
+ * of data to be received is equal to 2. In this case, this function
+ * should be called (with parameter I2C_NACKPosition_Next) before data
+ * reception starts,as described in the 2-byte reception procedure
+ * recommended in Reference Manual in Section: Master receiver.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_NACKPosition: specifies the NACK position.
+ * This parameter can be one of the following values:
+ * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+ * received byte.
+ * @arg I2C_NACKPosition_Current: indicates that current byte is the last
+ * received byte.
+ *
+ * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
+ * but is intended to be used in I2C mode while I2C_PECPositionConfig()
+ * is intended to used in SMBUS mode.
+ *
+ * @retval None
+ */
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+
+ /* Check the input parameter */
+ if (I2C_NACKPosition == I2C_NACKPosition_Next)
+ {
+ /* Next byte in shift register is the last received byte */
+ I2Cx->CR1 |= I2C_NACKPosition_Next;
+ }
+ else
+ {
+ /* Current byte in shift register is the last received byte */
+ I2Cx->CR1 &= I2C_NACKPosition_Current;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+ * @retval None
+ */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CR1 &= I2C_SMBusAlert_High;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CR1 |= CR1_PEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CR1 &= CR1_PEC_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition: specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC
+ *
+ * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
+ * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
+ * is intended to used in I2C mode.
+ *
+ * @retval None
+ */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PECPosition_Next)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CR1 |= I2C_PECPosition_Next;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CR1 &= I2C_PECPosition_Current;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transferred bytes.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CR1 |= CR1_ENPEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CR1 &= CR1_ENPEC_Reset;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The PEC value.
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->SR2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CR1 |= CR1_ENARP_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CR1 &= CR1_ENARP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+ * @retval None
+ */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CCR &= I2C_DutyCycle_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CCR |= I2C_DutyCycle_16_9;
+ }
+}
+
+
+
+/**
+ * @brief
+ ****************************************************************************************
+ *
+ * I2C State Monitoring Functions
+ *
+ ****************************************************************************************
+ * This I2C driver provides three different ways for I2C state monitoring
+ * depending on the application requirements and constraints:
+ *
+ *
+ * 1) Basic state monitoring:
+ * Using I2C_CheckEvent() function:
+ * It compares the status registers (SR1 and SR2) content to a given event
+ * (can be the combination of one or more flags).
+ * It returns SUCCESS if the current status includes the given flags
+ * and returns ERROR if one or more flags are missing in the current status.
+ * - When to use:
+ * - This function is suitable for most applications as well as for startup
+ * activity since the events are fully described in the product reference manual
+ * (RM0008).
+ * - It is also suitable for users who need to define their own events.
+ * - Limitations:
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication
+ * hold or corrupted real state.
+ * In this case, it is advised to use error interrupts to monitor the error
+ * events and handle them in the interrupt IRQ handler.
+ *
+ * @note
+ * For error management, it is advised to use the following functions:
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+ * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+ * Where x is the peripheral instance (I2C1, I2C2 ...)
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
+ * in order to determine which error occured.
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,
+ * and return to correct communication status.
+ *
+ *
+ * 2) Advanced state monitoring:
+ * Using the function I2C_GetLastEvent() which returns the image of both status
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left
+ * by 16 bits and concatenated to Status Register 1).
+ * - When to use:
+ * - This function is suitable for the same applications above but it allows to
+ * overcome the mentioned limitation of I2C_GetFlagStatus() function.
+ * The returned value could be compared to events already defined in the
+ * library (stm32f10x_i2c.h) or to custom values defined by user.
+ * - This function is suitable when multiple flags are monitored at the same time.
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to
+ * choose when an event is accepted (when all events flags are set and no
+ * other flags are set or just when the needed flags are set like
+ * I2C_CheckEvent() function).
+ * - Limitations:
+ * - User may need to define his own events.
+ * - Same remark concerning the error management is applicable for this
+ * function if user decides to check only regular communication flags (and
+ * ignores error flags).
+ *
+ *
+ * 3) Flag-based state monitoring:
+ * Using the function I2C_GetFlagStatus() which simply returns the status of
+ * one single flag (ie. I2C_FLAG_RXNE ...).
+ * - When to use:
+ * - This function could be used for specific applications or in debug phase.
+ * - It is suitable when only one flag checking is needed (most I2C events
+ * are monitored through multiple flags).
+ * - Limitations:
+ * - When calling this function, the Status register is accessed. Some flags are
+ * cleared when the status register is accessed. So checking the status
+ * of one Flag, may clear other ones.
+ * - Function may need to be called twice or more in order to monitor one
+ * single event.
+ *
+ * For detailed description of Events, please refer to section I2C_Events in
+ * stm32f10x_i2c.h file.
+ *
+ */
+
+/**
+ *
+ * 1) Basic state monitoring
+ *******************************************************************************
+ */
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT: specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in stm32f10x_i2c.h file.
+ *
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+
+ /* Check whether the last event contains the I2C_EVENT */
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ *
+ * 2) Advanced state monitoring
+ *******************************************************************************
+ */
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @note: For detailed description of Events, please refer to section
+ * I2C_Events in stm32f10x_i2c.h file.
+ *
+ * @retval The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ *
+ * 3) Flag-based state monitoring
+ *******************************************************************************
+ */
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDA"
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_Mask;
+
+ if(i2creg != 0)
+ {
+ /* Get the I2Cx SR1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx SR2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx SR2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
+ * second byte of the address in DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+ * register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_IT_PECERR: PEC error in reception flag
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure flag
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_IT_BERR: Bus error flag
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_IT_BTF: Byte transfer finished flag
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
+ * Address matched flag (Slave mode)"ENDAD"
+ * @arg I2C_IT_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_IT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
+
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_Mask;
+
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx抯 interrupt pending bits.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure interrupt
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+ * @arg I2C_IT_BERR: Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
+ * byte of the address in I2C_DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_DR register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_iwdg.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_iwdg.c"
new file mode 100644
index 0000000..c7cbf7e
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_iwdg.c"
@@ -0,0 +1,190 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the IWDG firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @defgroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload ((uint16_t)0xAAAA)
+#define KR_KEY_Enable ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+ * @retval None
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+ IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+ * @retval None
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+ IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload: specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ * @retval None
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RLR = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_KEY_Reload;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_KEY_Enable;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going
+ * @retval The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_pwr.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_pwr.c"
new file mode 100644
index 0000000..a5a5c57
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_pwr.c"
@@ -0,0 +1,307 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the PWR firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @defgroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber 0x08
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void PWR_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param NewState: new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param NewState: new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+ * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+ * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+ * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+ * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+ * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+ * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+ * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpreg = PWR->CR;
+ /* Clear PLS[7:5] bits */
+ tmpreg &= CR_PLS_MASK;
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+ tmpreg |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param NewState: new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= CR_DS_MASK;
+ /* Set LPDS bit according to PWR_Regulator value */
+ tmpreg |= PWR_Regulator;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @param None
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+ /* Clear Wake-up flag */
+ PWR->CR |= PWR_CR_CWUF;
+ /* Select STANDBY mode */
+ PWR->CR |= PWR_CR_PDDS;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM )
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @arg PWR_FLAG_PVDO: PVD Output
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @retval None
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->CR |= PWR_FLAG << 2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_rcc.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_rcc.c"
new file mode 100644
index 0000000..a29034b
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_rcc.c"
@@ -0,0 +1,1470 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the RCC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @defgroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+ /* Alias word address of PLL2ON bit */
+ #define PLL2ON_BitNumber 0x1A
+ #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
+
+ /* Alias word address of PLL3ON bit */
+ #define PLL3ON_BitNumber 0x1C
+ #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)
+
+#ifndef STM32F10X_CL
+ #define USBPRE_BitNumber 0x16
+ #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+#else
+ #define OTGFSPRE_BitNumber 0x16
+ #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x24)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+/* --- CFGR2 Register ---*/
+
+ /* Alias word address of I2S2SRC bit */
+ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
+ #define I2S2SRC_BitNumber 0x11
+ #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
+
+ /* Alias word address of I2S3SRC bit */
+ #define I2S3SRC_BitNumber 0x12
+ #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
+#define CR_HSEBYP_Set ((uint32_t)0x00040000)
+#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
+#define CR_HSEON_Set ((uint32_t)0x00010000)
+#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
+#else
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
+#endif /* STM32F10X_CL */
+
+#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
+#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
+#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
+#define CFGR_SWS_Mask ((uint32_t)0x0000000C)
+#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
+#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RMVF_Set ((uint32_t)0x01000000)
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+/* CFGR2 register bit mask */
+ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
+ #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
+#endif
+#ifdef STM32F10X_CL
+ #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
+ #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
+ #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
+#endif /* STM32F10X_CL */
+
+/* RCC Flag Mask */
+#define FLAG_Mask ((uint8_t)0x1F)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
+
+/* CFGR register byte 4 (Bits[31:24]) base address */
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
+
+/* BDCR register base address */
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Variables
+ * @{
+ */
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @param None
+ * @retval None
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: HSE oscillator OFF
+ * @arg RCC_HSE_ON: HSE oscillator ON
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CR &= CR_HSEON_Reset;
+ /* Reset HSEBYP bit */
+ RCC->CR &= CR_HSEBYP_Reset;
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+ switch(RCC_HSE)
+ {
+ case RCC_HSE_ON:
+ /* Set HSEON bit */
+ RCC->CR |= CR_HSEON_Set;
+ break;
+
+ case RCC_HSE_Bypass:
+ /* Set HSEBYP and HSEON bits */
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @param None
+ * @retval An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ StartUpCounter++;
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ * @retval None
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+ tmpreg = RCC->CR;
+ /* Clear HSITRIM[4:0] bits */
+ tmpreg &= CR_HSITRIM_Mask;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices,
+ * this parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul: specifies the PLL multiplication factor.
+ * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
+ * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ tmpreg &= CFGR_PLL_Mask;
+ /* Set the PLL configuration bits */
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
+/**
+ * @brief Configures the PREDIV1 division factor.
+ * @note
+ * - This function must be used only when the PLL is disabled.
+ * - This function applies only to STM32 Connectivity line and Value line
+ * devices.
+ * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
+ * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
+ * @note
+ * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
+ tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
+ /* Set the PREDIV1 clock source and division factor */
+ tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+#endif
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the PREDIV2 division factor.
+ * @note
+ * - This function must be used only when both PLL2 and PLL3 are disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
+ * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV2[3:0] bits */
+ tmpreg &= ~CFGR2_PREDIV2;
+ /* Set the PREDIV2 division factor */
+ tmpreg |= RCC_PREDIV2_Div;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the PLL2 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL2 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
+ * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL2Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL2MUL;
+ /* Set the PLL2 configuration bits */
+ tmpreg |= RCC_PLL2Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL2.
+ * @note
+ * - The PLL2 can not be disabled if it is used indirectly as system clock
+ * (i.e. it is used as PLL clock entry that is used as System clock).
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL2Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
+}
+
+
+/**
+ * @brief Configures the PLL3 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL3 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
+ * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL3Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL3MUL;
+ /* Set the PLL3 configuration bits */
+ tmpreg |= RCC_PLL3Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL3.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL3Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+ * @retval None
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+ tmpreg = RCC->CFGR;
+ /* Clear SW[1:0] bits */
+ tmpreg &= CFGR_SW_Mask;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @param None
+ * @retval The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+ return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+ * @retval None
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear HPRE[3:0] bits */
+ tmpreg &= CFGR_HPRE_Reset_Mask;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpreg |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE1[2:0] bits */
+ tmpreg &= CFGR_PPRE1_Reset_Mask;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE2[2:0] bits */
+ tmpreg &= CFGR_PPRE2_Reset_Mask;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @param NewState: new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_IT(RCC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+ }
+}
+
+#ifndef STM32F10X_CL
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ * clock source
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+ * @retval None
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+#else
+/**
+ * @brief Configures the USB OTG FS clock (OTGFSCLK).
+ * This function applies only to STM32 Connectivity line devices.
+ * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
+ * This clock is derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @retval None
+ */
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
+
+ *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the ADC clock (ADCCLK).
+ * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
+ * the APB2 clock (PCLK2).
+ * This parameter can be one of the following values:
+ * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
+ * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
+ * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
+ * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
+ * @retval None
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
+ tmpreg = RCC->CFGR;
+ /* Clear ADCPRE[1:0] bits */
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
+ tmpreg |= RCC_PCLK2;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the I2S2 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S2 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
+ * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
+ * @retval None
+ */
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
+}
+
+/**
+ * @brief Configures the I2S3 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S3 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
+ * @retval None
+ */
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: LSE oscillator OFF
+ * @arg RCC_LSE_ON: LSE oscillator ON
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Reset LSEBYP bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+ switch(RCC_LSE)
+ {
+ case RCC_LSE_ON:
+ /* Set LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
+ break;
+
+ case RCC_LSE_Bypass:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
+ * @retval None
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+ /* Select the RTC clock source */
+ RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+ * the clocks frequencies.
+ * @note The result of this function could be not correct when using
+ * fractional value for HSE crystal.
+ * @retval None
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ uint32_t prediv1factor = 0;
+#endif
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & CFGR_SWS_Mask;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ { /* HSE oscillator clock selected as PREDIV1 clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+ tmp = tmp >> 4;
+ presc = APBAHBPrescTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+ tmp = tmp >> 8;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+ tmp = tmp >> 11;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get ADCCLK prescaler */
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+ tmp = tmp >> 14;
+ presc = ADCPrescTable[tmp];
+ /* ADCCLK clock frequency */
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @arg RCC_AHBPeriph_ETH_MAC_Tx
+ * @arg RCC_AHBPeriph_ETH_MAC_Rx
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_FSMC
+ * @arg RCC_AHBPeriph_SDIO
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBENR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBENR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBRSTR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;
+ }
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @param NewState: new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param NewState: new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO: specifies the clock source to output.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
+ * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
+ * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
+ * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ *
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+
+ /* Perform Byte access to MCO bits to select the MCO source */
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG: specifies the flag to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * @retval The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_Mask;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ * @param None
+ * @retval None
+ */
+void RCC_ClearFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CSR |= CSR_RMVF_Set;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RCC_IT: specifies the RCC interrupt source to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * @retval The new state of RCC_IT (SET or RESET).
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC's interrupt pending bits.
+ * @param RCC_IT: specifies the interrupt pending bit to clear.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval None
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_rtc.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_rtc.c"
new file mode 100644
index 0000000..f05aef5
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_rtc.c"
@@ -0,0 +1,339 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the RTC firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rtc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/** @defgroup RTC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Defines
+ * @{
+ */
+#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
+#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @param NewState: new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RTC->CRH |= RTC_IT;
+ }
+ else
+ {
+ RTC->CRH &= (uint16_t)~RTC_IT;
+ }
+}
+
+/**
+ * @brief Enters the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_EnterConfigMode(void)
+{
+ /* Set the CNF flag to enter in the Configuration Mode */
+ RTC->CRL |= RTC_CRL_CNF;
+}
+
+/**
+ * @brief Exits from the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_ExitConfigMode(void)
+{
+ /* Reset the CNF flag to exit from the Configuration Mode */
+ RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
+}
+
+/**
+ * @brief Gets the RTC counter value.
+ * @param None
+ * @retval RTC counter value.
+ */
+uint32_t RTC_GetCounter(void)
+{
+ uint16_t tmp = 0;
+ tmp = RTC->CNTL;
+ return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+ * @brief Sets the RTC counter value.
+ * @param CounterValue: RTC counter new value.
+ * @retval None
+ */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+ RTC_EnterConfigMode();
+ /* Set RTC COUNTER MSB word */
+ RTC->CNTH = CounterValue >> 16;
+ /* Set RTC COUNTER LSB word */
+ RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC prescaler value.
+ * @param PrescalerValue: RTC prescaler new value.
+ * @retval None
+ */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_PRESCALER(PrescalerValue));
+
+ RTC_EnterConfigMode();
+ /* Set RTC PRESCALER MSB word */
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
+ /* Set RTC PRESCALER LSB word */
+ RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC alarm value.
+ * @param AlarmValue: RTC alarm new value.
+ * @retval None
+ */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+ RTC_EnterConfigMode();
+ /* Set the ALARM MSB word */
+ RTC->ALRH = AlarmValue >> 16;
+ /* Set the ALARM LSB word */
+ RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Gets the RTC divider value.
+ * @param None
+ * @retval RTC Divider value.
+ */
+uint32_t RTC_GetDivider(void)
+{
+ uint32_t tmp = 0x00;
+ tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+ tmp |= RTC->DIVL;
+ return tmp;
+}
+
+/**
+ * @brief Waits until last write operation on RTC registers has finished.
+ * @note This function must be called before any write to RTC registers.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForLastTask(void)
+{
+ /* Loop until RTOFF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+ * are synchronized with RTC APB clock.
+ * @note This function must be called before any read operation after an APB reset
+ * or an APB clock stop.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForSynchro(void)
+{
+ /* Clear RSF flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
+ /* Loop until RSF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG: specifies the flag to check.
+ * This parameter can be one the following values:
+ * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's pending flags.
+ * @param RTC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
+ * an APB reset or an APB Clock stop.
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval None
+ */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the corresponding RTC flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occurred or not.
+ * @param RTC_IT: specifies the RTC interrupts sources to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval The new state of the RTC_IT (SET or RESET).
+ */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_IT(RTC_IT));
+
+ bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
+ if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC's interrupt pending bits.
+ * @param RTC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval None
+ */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+
+ /* Clear the corresponding RTC pending bit */
+ RTC->CRL &= (uint16_t)~RTC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_sdio.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_sdio.c"
new file mode 100644
index 0000000..bc1719d
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_sdio.c"
@@ -0,0 +1,799 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the SDIO firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SDIO
+ * @brief SDIO driver modules
+ * @{
+ */
+
+/** @defgroup SDIO_Private_TypesDefinitions
+ * @{
+ */
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void SDIO_DeInit(void)
+{
+ SDIO->POWER = 0x00000000;
+ SDIO->CLKCR = 0x00000000;
+ SDIO->ARG = 0x00000000;
+ SDIO->CMD = 0x00000000;
+ SDIO->DTIMER = 0x00000000;
+ SDIO->DLEN = 0x00000000;
+ SDIO->DCTRL = 0x00000000;
+ SDIO->ICR = 0x00C007FF;
+ SDIO->MASK = 0x00000000;
+}
+
+/**
+ * @brief Initializes the SDIO peripheral according to the specified
+ * parameters in the SDIO_InitStruct.
+ * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
+ * that contains the configuration information for the SDIO peripheral.
+ * @retval None
+ */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
+
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/
+ /* Get the SDIO CLKCR value */
+ tmpreg = SDIO->CLKCR;
+
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+ tmpreg &= CLKCR_CLEAR_MASK;
+
+ /* Set CLKDIV bits according to SDIO_ClockDiv value */
+ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+ /* Set BYPASS bit according to SDIO_ClockBypass value */
+ /* Set WIDBUS bits according to SDIO_BusWide value */
+ /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
+ SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+ SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
+
+ /* Write to SDIO CLKCR */
+ SDIO->CLKCR = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_InitStruct member with its default value.
+ * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ /* SDIO_InitStruct members default value */
+ SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+ SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+ SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+ SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+ SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+ SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+ * @brief Enables or disables the SDIO Clock.
+ * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Sets the power status of the controller.
+ * @param SDIO_PowerState: new state of the Power state.
+ * This parameter can be one of the following values:
+ * @arg SDIO_PowerState_OFF
+ * @arg SDIO_PowerState_ON
+ * @retval None
+ */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+
+ SDIO->POWER &= PWR_PWRCTRL_MASK;
+ SDIO->POWER |= SDIO_PowerState;
+}
+
+/**
+ * @brief Gets the power status of the controller.
+ * @param None
+ * @retval Power status of the controller. The returned value can
+ * be one of the following:
+ * - 0x00: Power OFF
+ * - 0x02: Power UP
+ * - 0x03: Power ON
+ */
+uint32_t SDIO_GetPowerState(void)
+{
+ return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+ * @brief Enables or disables the SDIO interrupts.
+ * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @param NewState: new state of the specified SDIO interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_IT(SDIO_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the SDIO interrupts */
+ SDIO->MASK |= SDIO_IT;
+ }
+ else
+ {
+ /* Disable the SDIO interrupts */
+ SDIO->MASK &= ~SDIO_IT;
+ }
+}
+
+/**
+ * @brief Enables or disables the SDIO DMA request.
+ * @param NewState: new state of the selected SDIO DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Initializes the SDIO Command according to the specified
+ * parameters in the SDIO_CmdInitStruct and send the command.
+ * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
+ * structure that contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+ assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+ /* Set the SDIO Argument value */
+ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+
+/*---------------------------- SDIO CMD Configuration ------------------------*/
+ /* Get the SDIO CMD value */
+ tmpreg = SDIO->CMD;
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+ tmpreg &= CMD_CLEAR_MASK;
+ /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+ /* Set WAITRESP bits according to SDIO_Response value */
+ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+ /* Set CPSMEN bits according to SDIO_CPSM value */
+ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+ | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+
+ /* Write to SDIO CMD */
+ SDIO->CMD = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.
+ * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+ /* SDIO_CmdInitStruct members default value */
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+ SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+ * @brief Returns command index of last command for which response received.
+ * @param None
+ * @retval Returns the command index of the last command response received.
+ */
+uint8_t SDIO_GetCommandResponse(void)
+{
+ return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+ * @brief Returns response received from the card for the last command.
+ * @param SDIO_RESP: Specifies the SDIO response register.
+ * This parameter can be one of the following values:
+ * @arg SDIO_RESP1: Response Register 1
+ * @arg SDIO_RESP2: Response Register 2
+ * @arg SDIO_RESP3: Response Register 3
+ * @arg SDIO_RESP4: Response Register 4
+ * @retval The Corresponding response register value.
+ */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+ tmp = SDIO_RESP_ADDR + SDIO_RESP;
+
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @brief Initializes the SDIO data path according to the specified
+ * parameters in the SDIO_DataInitStruct.
+ * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+ * contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+ assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+ assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+ assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+ /* Set the SDIO Data TimeOut value */
+ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+ /* Set the SDIO DataLength value */
+ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/
+ /* Get the SDIO DCTRL value */
+ tmpreg = SDIO->DCTRL;
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+ tmpreg &= DCTRL_CLEAR_MASK;
+ /* Set DEN bit according to SDIO_DPSM value */
+ /* Set DTMODE bit according to SDIO_TransferMode value */
+ /* Set DTDIR bit according to SDIO_TransferDir value */
+ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+ | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+ /* Write to SDIO DCTRL */
+ SDIO->DCTRL = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_DataInitStruct member with its default value.
+ * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ /* SDIO_DataInitStruct members default value */
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+ SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+ SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+ * @brief Returns number of remaining data bytes to be transferred.
+ * @param None
+ * @retval Number of remaining data bytes to be transferred
+ */
+uint32_t SDIO_GetDataCounter(void)
+{
+ return SDIO->DCOUNT;
+}
+
+/**
+ * @brief Read one data word from Rx FIFO.
+ * @param None
+ * @retval Data received
+ */
+uint32_t SDIO_ReadData(void)
+{
+ return SDIO->FIFO;
+}
+
+/**
+ * @brief Write one data word to Tx FIFO.
+ * @param Data: 32-bit data word to write.
+ * @retval None
+ */
+void SDIO_WriteData(uint32_t Data)
+{
+ SDIO->FIFO = Data;
+}
+
+/**
+ * @brief Returns the number of words left to be written to or read from FIFO.
+ * @param None
+ * @retval Remaining number of words.
+ */
+uint32_t SDIO_GetFIFOCount(void)
+{
+ return SDIO->FIFOCNT;
+}
+
+/**
+ * @brief Starts the SD I/O Read Wait operation.
+ * @param NewState: new state of the Start SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Stops the SD I/O Read Wait operation.
+ * @param NewState: new state of the Stop SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Sets one of the two options of inserting read wait interval.
+ * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+ * This parameter can be:
+ * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+ * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+ * @retval None
+ */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+ *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode Operation.
+ * @param NewState: new state of SDIO specific operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode suspend command sending.
+ * @param NewState: new state of the SD I/O Mode suspend command.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the command completion signal.
+ * @param NewState: new state of command completion signal.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the CE-ATA interrupt.
+ * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+ * @brief Sends CE-ATA command (CMD61).
+ * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param SDIO_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SDIO_FLAG (SET or RESET).
+ */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+
+ if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's pending flags.
+ * @param SDIO_FLAG: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+
+ SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param SDIO_IT: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SDIO_IT (SET or RESET).
+ */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_GET_IT(SDIO_IT));
+ if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's interrupt pending bits.
+ * @param SDIO_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+
+ SDIO->ICR = SDIO_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_spi.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_spi.c"
new file mode 100644
index 0000000..4ec65b2
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_spi.c"
@@ -0,0 +1,908 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the SPI firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_spi.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @defgroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPE mask */
+#define CR1_SPE_Set ((uint16_t)0x0040)
+#define CR1_SPE_Reset ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CR1_CRCNext_Set ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CR1_CRCEN_Set ((uint16_t)0x2000)
+#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CR2_SSOE_Set ((uint16_t)0x0004)
+#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select ((uint16_t)0xF7FF)
+#define I2S_Mode_Select ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+ }
+ else
+ {
+ if (SPIx == SPI3)
+ {
+ /* Enable SPI3 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+ /* Release SPI3 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral.
+ * @retval None
+ */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+ uint16_t tmpreg = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+ /* Set LSBFirst bit according to SPI_FirstBit value */
+ /* Set BR bits according to SPI_BaudRatePrescaler value */
+ /* Set CPOL bit according to SPI_CPOL value */
+ /* Set CPHA bit according to SPI_CPHA value */
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ SPIx->I2SCFGR &= SPI_Mode_Select;
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ * @retval None
+ */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksTypeDef RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+ SPIx->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = SPIx->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if(((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLOCK_SRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S3 */
+ tmp = I2S3_CLOCK_SRC;
+ }
+
+ /* Check the I2S clock source configuration depending on the Device:
+ Only Connectivity line devices have the PLL3 VCO clock */
+#ifdef STM32F10X_CL
+ if((RCC->CFGR2 & tmp) != 0)
+ {
+ /* Get the configuration bits of RCC PLL3 multiplier */
+ tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
+
+ /* Get the value of the PLL3 multiplier */
+ if((tmp > 5) && (tmp < 15))
+ {
+ /* Multiplier is between 8 and 14 (value 15 is forbidden) */
+ tmp += 2;
+ }
+ else
+ {
+ if (tmp == 15)
+ {
+ /* Multiplier is 20 */
+ tmp = 20;
+ }
+ }
+ /* Get the PREDIV2 value */
+ sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
+
+ /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
+ sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
+ }
+ else
+ {
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+ }
+#else /* STM32F10X_HD */
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+#endif /* STM32F10X_CL */
+
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the SPI_Direction member */
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ /* initialize the SPI_Mode member */
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+ /* initialize the SPI_DataSize member */
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+ /* Initialize the SPI_CPOL member */
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+ /* Initialize the SPI_CPHA member */
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+ /* Initialize the SPI_NSS member */
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+ /* Initialize the SPI_BaudRatePrescaler member */
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ /* Initialize the SPI_FirstBit member */
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+ /* Initialize the SPI_CRCPolynomial member */
+ SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2S_Mode member */
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+ /* Initialize the I2S_Standard member */
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+ /* Initialize the I2S_DataFormat member */
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+ /* Initialize the I2S_MCLKOutput member */
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+ /* Initialize the I2S_AudioFreq member */
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+ /* Initialize the I2S_CPOL member */
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CR1 |= CR1_SPE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CR1 &= CR1_SPE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+ uint16_t itpos = 0, itmask = 0 ;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CR2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CR2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+ * @param NewState: new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CR2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param Data : Data to be transmitted.
+ * @retval None
+ */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Write in the DR register the data to be sent */
+ SPIx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @retval The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the data in the DR register */
+ return SPIx->DR;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+ * @retval None
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CR2 |= CR2_SSOE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CR2 &= CR2_SSOE_Reset;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_DataSize: specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit
+ * @retval None
+ */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+ /* Clear DFF bit */
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+ /* Set new DFF bit value */
+ SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CR1 |= CR1_CRCNext_Set;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transferred bytes.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CR1 |= CR1_CRCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CR1 &= CR1_CRCEN_Reset;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_CRC: specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_Tx: Selects Tx CRC register
+ * @arg SPI_CRC_Rx: Selects Rx CRC register
+ * @retval The selected CRC register value..
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_Rx)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->TXCRCR;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->RXCRCR;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPR;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction
+ * @arg SPI_Direction_Rx: Selects Rx receive direction
+ * @retval None
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));
+ if (SPI_Direction == SPI_Direction_Tx)
+ {
+ /* Set the Tx only mode */
+ SPIx->CR1 |= SPI_Direction_Tx;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CR1 &= SPI_Direction_Rx;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.
+ * @arg SPI_FLAG_MODF: Mode Fault flag.
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.
+ * @arg I2S_FLAG_UDR: Underrun Error flag.
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.
+ * @arg SPI_IT_MODF: Mode Fault interrupt.
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.
+ * @arg I2S_IT_UDR: Underrun Error interrupt.
+ * @retval The new state of SPI_I2S_IT (SET or RESET).
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CR2 & itmask) ;
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR interrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
+ * the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->SR = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_tim.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_tim.c"
new file mode 100644
index 0000000..bfb4dd1
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_tim.c"
@@ -0,0 +1,2890 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the TIM firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @defgroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_Mask ((uint16_t)0x00FF)
+#define CCMR_Offset ((uint16_t)0x0018)
+#define CCER_CCE_Set ((uint16_t)0x0001)
+#define CCER_CCNE_Set ((uint16_t)0x0004)
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+ }
+ else if (TIMx == TIM8)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+ }
+ else if (TIMx == TIM9)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
+ }
+ else if (TIMx == TIM10)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
+ }
+ else if (TIMx == TIM11)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
+ }
+ else if (TIMx == TIM12)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
+ }
+ else if (TIMx == TIM13)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
+ }
+ else if (TIMx == TIM14)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
+ }
+ else if (TIMx == TIM15)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
+ }
+ else if (TIMx == TIM16)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
+ }
+ else
+ {
+ if (TIMx == TIM17)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+ * structure that contains the configuration information for the
+ * specified TIM peripheral.
+ * @retval None
+ */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ uint16_t tmpcr1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+ tmpcr1 = TIMx->CR1;
+
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
+ (TIMx == TIM4) || (TIMx == TIM5))
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+ }
+
+ if((TIMx != TIM6) && (TIMx != TIM7))
+ {
+ /* Set the clock division */
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+ if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler and the Repetition counter
+ values immediately */
+ TIMx->EGR = TIM_PSCReloadMode_Immediate;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare Mode Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
+ (TIMx == TIM16)|| (TIMx == TIM17))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+ * the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
+
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+ /* Reset the Output Compare and Output Compare N IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+ if((TIMx == TIM1) || (TIMx == TIM8))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Output Compare IDLE State */
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+ }
+ else
+ {
+ assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+ {
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+ {
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* TI3 Configuration */
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* TI4 Configuration */
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+ {
+ icoppositepolarity = TIM_ICPolarity_Falling;
+ }
+ else
+ {
+ icoppositepolarity = TIM_ICPolarity_Rising;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+ {
+ icoppositeselection = TIM_ICSelection_IndirectTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_ICSelection_DirectTI;
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI2 Configuration */
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI1 Configuration */
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx: where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval None
+ */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+ * @param NewState: new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= TIM_CR1_CEN;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BDTR |= TIM_BDTR_MOE;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+ * TIM_IT_CC2 or TIM_IT_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DIER |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DIER &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_EventSource: specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EventSource_Update: Timer update Event source
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EventSource_COM: Timer COM event source
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source
+ * @arg TIM_EventSource_Break: Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EGR = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx's DMA interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
+ * the TIM peripheral.
+ * @param TIM_DMABase: DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+ * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+ * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+ * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+ * TIM_DMABase_DCR.
+ * @param TIM_DMABurstLength: DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+ * @retval None
+ */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx's DMA Requests.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
+ * to select the TIM peripheral.
+ * @param TIM_DMASource: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_Update: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST9_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DIER |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx internal Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
+ * to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ITRSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @param TIM_TS_ITR0: Internal Trigger 0
+ * @param TIM_TS_ITR1: Internal Trigger 1
+ * @param TIM_TS_ITR2: Internal Trigger 2
+ * @param TIM_TS_ITR3: Internal Trigger 3
+ * @retval None
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+ * @param TIM_ICPolarity: specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param ICFilter : specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ * @retval None
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+ assert_param(IS_TIM_IC_FILTER(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+ {
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ else
+ {
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the SMS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SlaveMode_External1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+ tmpsmcr |= TIM_TS_ETRF;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCR |= TIM_SMCR_ECE;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCR_ETR_Mask;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param Prescaler: specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
+ * @retval None
+ */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_CounterMode: specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+ * @retval None
+ */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+ uint16_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+ tmpcr1 = TIMx->CR1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM_CounterMode;
+ /* Write to TIMx CR1 register */
+ TIMx->CR1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource: The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @retval None
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+ * @retval None
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+ * @retval None
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+ * @retval None
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+ * @retval None
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ARR Preload Bit */
+ TIMx->CR1 |= TIM_CR1_ARPE;
+ }
+ else
+ {
+ /* Reset the ARR Preload Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CR2 |= TIM_CR2_CCUS;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
+ * the TIM peripheral.
+ * @param NewState: new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CR2 |= TIM_CR2_CCDS;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
+ * to select the TIMx peripheral
+ * @param NewState: new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CR2 |= TIM_CR2_CCPC;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+ * the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
+ * the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC1 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
+ tmpccer |= TIM_OCPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
+ tmpccer |= TIM_OCNPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC2 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC3 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC4 Polarity
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCX(TIM_CCx));
+
+ tmp = CCER_CCE_Set << TIM_Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t)~ tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+ * @retval None
+ */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+ tmp = CCER_CCNE_Set << TIM_Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+ * @brief Selects the TIM Output Compare Mode.
+ * @note This function disables the selected channel before changing the Output
+ * Compare Mode.
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parameter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCMode_Timing
+ * @arg TIM_OCMode_Active
+ * @arg TIM_OCMode_Toggle
+ * @arg TIM_OCMode_PWM1
+ * @arg TIM_OCMode_PWM2
+ * @arg TIM_ForcedAction_Active
+ * @arg TIM_ForcedAction_InActive
+ * @retval None
+ */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_OCM(TIM_OCMode));
+
+ tmp = (uint32_t) TIMx;
+ tmp += CCMR_Offset;
+
+ tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp1;
+
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+ {
+ tmp += (TIM_Channel>>1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= TIM_OCMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CR1 |= TIM_CR1_UDIS;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_UpdateSource: specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+ * @retval None
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)
+ {
+ /* Set the URS Bit */
+ TIMx->CR1 |= TIM_CR1_URS;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx's Hall sensor interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CR2 |= TIM_CR2_TI1S;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
+ }
+}
+
+/**
+ * @brief Selects the TIMx's One Pulse Mode.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_OPMode: specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMode_Single
+ * @arg TIM_OPMode_Repetitive
+ * @retval None
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
+ /* Configure the OPM Mode */
+ TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_TRGOSource: specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+ *
+ * @retval None
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST7_PERIPH(TIMx));
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
+ /* Select the TRGO source */
+ TIMx->CR2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+ * @retval None
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
+ /* Select the Slave Mode */
+ TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MasterSlaveMode_Disable: No action
+ * @retval None
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param Counter: specifies the Counter register new value.
+ * @retval None
+ */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param Autoreload: specifies the Autoreload register new value.
+ * @retval None
+ */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->ARR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param Compare1: specifies the Capture Compare1 register new value.
+ * @retval None
+ */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCR1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param Compare2: specifies the Capture Compare2 register new value.
+ * @retval None
+ */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCR2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3: specifies the Capture Compare3 register new value.
+ * @retval None
+ */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCR3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4: specifies the Capture Compare4 register new value.
+ * @retval None
+ */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCR4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
+ /* Set the IC1PSC value */
+ TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
+ /* Set the IC2PSC value */
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
+ /* Set the IC3PSC value */
+ TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
+ /* Set the IC4PSC value */
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select
+ * the TIM peripheral.
+ * @param TIM_CKD: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+ * @retval None
+ */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
+ /* Set the CKD value */
+ TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @retval Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCR1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @retval Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCR2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCR3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCR4;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @retval Counter Register value.
+ */
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @retval Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval None
+ */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_IT: specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+ * TIM_IT_CC2 or TIM_IT_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval The new state of the TIM_IT(SET or RESET).
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_IT(TIM_IT));
+
+ itstatus = TIMx->SR & TIM_IT;
+
+ itenable = TIMx->DIER & TIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
+ * @param TIM_IT: specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM1 update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
+ * TIM_IT_CC2 or TIM_IT_Trigger.
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
+ * @retval None
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+ }
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
+ }
+
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
+ }
+
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI4 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 12);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
+ (TIMx == TIM4) ||(TIMx == TIM5))
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+ }
+ else
+ {
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
+ }
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_usart.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_usart.c"
new file mode 100644
index 0000000..e794eae
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_usart.c"
@@ -0,0 +1,1058 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the USART firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @defgroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Defines
+ * @{
+ */
+
+#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */
+#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */
+#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */
+
+#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */
+
+#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */
+#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */
+#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+ }
+ else
+ {
+ if (USARTx == UART5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART
+ * peripheral.
+ * @retval None
+ */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+ uint32_t tmpreg = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksTypeDef RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear STOP[13:12] bits */
+ tmpreg &= CR2_STOP_CLEAR_Mask;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to USART_StopBits value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = USARTx->CR1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to USART_WordLength value */
+ /* Set PCE and PS bits according to USART_Parity value */
+ /* Set TE and RE bits according to USART_Mode value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+ USART_InitStruct->USART_Mode;
+ /* Write to USART CR1 */
+ USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/
+ tmpreg = USARTx->CR3;
+ /* Clear CTSE and RTSE bits */
+ tmpreg &= CR3_CLEAR_Mask;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+ /* Write to USART CR3 */
+ USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreq(&RCC_ClocksStatus);
+ if (usartxbase == USART1_BASE)
+ {
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+ }
+
+ /* Determine the integer part */
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+ {
+ /* Integer part computing in case Oversampling mode is 8 Samples */
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
+ }
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+ {
+ /* Integer part computing in case Oversampling mode is 16 Samples */
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
+ }
+ tmpreg = (integerdivider / 100) << 4;
+
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+ /* Implement the fractional part in the register */
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)
+ {
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+ }
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
+ {
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+ }
+
+ /* Write to USART BRR */
+ USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->USART_BaudRate = 9600;
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;
+ USART_InitStruct->USART_Parity = USART_Parity_No ;
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card and Synchronous modes are not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= CR2_CLOCK_CLEAR_Mask;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to USART_Clock value */
+ /* Set CPOL bit according to USART_CPOL value */
+ /* Set CPHA bit according to USART_CPHA value */
+ /* Set LBCL bit according to USART_LastBit value */
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CR1 register */
+ USARTx->CR1 |= CR1_UE_Set;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */
+ USARTx->CR1 &= CR1_UE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Transmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CONFIG_IT(USART_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_IT & IT_Mask;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CR3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (NewState != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART抯 DMA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_DMAReq: specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAReq_Tx: USART DMA transmit request
+ * @arg USART_DMAReq_Rx: USART DMA receive request
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The DMA mode is not available for UART5 except in the STM32
+ * High density value line devices(STM32F10X_HD_VL).
+ * @retval None
+ */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Address: Indicates the address of the USART node.
+ * @retval None
+ */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Address));
+
+ /* Clear the USART address */
+ USARTx->CR2 &= CR2_Address_Mask;
+ /* Set the USART address node */
+ USARTx->CR2 |= USART_Address;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUp: specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+ * @retval None
+ */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));
+
+ USARTx->CR1 &= CR1_WAKE_Mask;
+ USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
+ USARTx->CR1 |= CR1_RWU_Set;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+ USARTx->CR1 &= CR1_RWU_Reset;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+ * @retval None
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CR2 &= CR2_LBDL_Mask;
+ USARTx->CR2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART抯 LIN mode.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ USARTx->CR2 |= CR2_LINEN_Set;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+ USARTx->CR2 &= CR2_LINEN_Reset;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Data: the data to transmit.
+ * @retval None
+ */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime: specifies the guard time.
+ * @note The guard time bits are not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTPR &= GTPR_LSB_Mask;
+ /* Set the USART guard time */
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler: specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ * @retval None
+ */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTPR &= GTPR_MSB_Mask;
+ /* Set the USART prescaler */
+ USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USART抯 Smart Card mode.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ USARTx->CR3 |= CR3_SCEN_Set;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+ USARTx->CR3 &= CR3_SCEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+ USARTx->CR3 |= CR3_NACK_Set;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+ USARTx->CR3 &= CR3_NACK_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART抯 Half Duplex communication.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ USARTx->CR3 |= CR3_HDSEL_Set;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+ USARTx->CR3 &= CR3_HDSEL_Reset;
+ }
+}
+
+
+/**
+ * @brief Enables or disables the USART's 8x oversampling mode.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART one bit sampling method.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * This function has to be called before calling USART_Init()
+ * function in order to have correct baudrate Divider value.
+ * @retval None
+ */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+ USARTx->CR1 |= CR1_OVER8_Set;
+ }
+ else
+ {
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+ USARTx->CR1 &= CR1_OVER8_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART's one bit sampling method.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART one bit sampling method.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+ USARTx->CR3 |= CR3_ONEBITE_Set;
+ }
+ else
+ {
+ /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */
+ USARTx->CR3 &= CR3_ONEBITE_Reset;
+ }
+}
+
+/**
+ * @brief Configures the USART's IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode: specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IrDAMode_LowPower
+ * @arg USART_IrDAMode_Normal
+ * @retval None
+ */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CR3 &= CR3_IRLP_Mask;
+ USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART's IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ USARTx->CR3 |= CR3_IREN_Set;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+ USARTx->CR3 &= CR3_IREN_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LBD: LIN Break detection flag
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if (USART_FLAG == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LBD: LIN Break detection flag.
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of USART_IT (SET or RESET).
+ */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_IT & IT_Mask;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ itmask &= USARTx->CR1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ itmask &= USARTx->CR2;
+ }
+ else /* The IT is in CR3 register */
+ {
+ itmask &= USARTx->CR3;
+ }
+
+ bitpos = USART_IT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->SR;
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's interrupt pending bits.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt.
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_IT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->SR = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_wwdg.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_wwdg.c"
new file mode 100644
index 0000000..4a901e4
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/STM32F10x_FWLib/src/stm32f10x_wwdg.c"
@@ -0,0 +1,224 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief This file provides all the WWDG firmware functions.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_wwdg.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @defgroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber 0x09
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_WDGA_Set ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
+#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
+#define BIT_Mask ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void WWDG_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+ * @retval None
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpreg |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue: specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ * @retval None
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpreg = WWDG->CFR & CFR_W_Mask;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpreg |= WindowValue & (uint32_t) BIT_Mask;
+
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ * @param None
+ * @retval None
+ */
+void WWDG_EnableIT(void)
+{
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CR = Counter & BIT_Mask;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @param None
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+ return (FlagStatus)(WWDG->SR);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ * @param None
+ * @retval None
+ */
+void WWDG_ClearFlag(void)
+{
+ WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/delay/delay.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/delay/delay.c"
new file mode 100644
index 0000000..230340b
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/delay/delay.c"
@@ -0,0 +1,87 @@
+#include "delay.h"
+//////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////
+static u8 fac_us=0;//us延时倍乘数
+static u16 fac_ms=0;//ms延时倍乘数
+//初始化延迟函数
+//SYSTICK的时钟固定为HCLK时钟的1/8
+//SYSCLK:系统时钟
+void delay_init(u8 SYSCLK)
+{
+// SysTick->CTRL&=0xfffffffb;//bit2清空,选择外部时钟 HCLK/8
+ SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8); //选择外部时钟 HCLK/8
+ fac_us=SYSCLK/8;
+ fac_ms=(u16)fac_us*1000;
+}
+//延时nms
+//注意nms的范围
+//SysTick->LOAD为24位寄存器,所以,最大延时为:
+//nms<=0xffffff*8*1000/SYSCLK
+//SYSCLK单位为Hz,nms单位为ms
+//对72M条件下,nms<=1864
+void delay_ms(u16 nms)
+{
+ u32 temp;
+ SysTick->LOAD=(u32)nms*fac_ms;//时间加载(SysTick->LOAD为24bit)
+ SysTick->VAL =0x00; //清空计数器
+ SysTick->CTRL=0x01 ; //开始倒数
+ do
+ {
+ temp=SysTick->CTRL;
+ }
+ while(temp&0x01&&!(temp&(1<<16)));//等待时间到达
+ SysTick->CTRL=0x00; //关闭计数器
+ SysTick->VAL =0X00; //清空计数器
+}
+//延时nus
+//nus为要延时的us数.
+void delay_us(u32 nus)
+{
+ u32 temp;
+ SysTick->LOAD=nus*fac_us; //时间加载
+ SysTick->VAL=0x00; //清空计数器
+ SysTick->CTRL=0x01 ; //开始倒数
+ do
+ {
+ temp=SysTick->CTRL;
+ }
+ while(temp&0x01&&!(temp&(1<<16)));//等待时间到达
+ SysTick->CTRL=0x00; //关闭计数器
+ SysTick->VAL =0X00; //清空计数器
+}
+
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diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/delay/delay.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/delay/delay.h"
new file mode 100644
index 0000000..46be1ab
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/delay/delay.h"
@@ -0,0 +1,47 @@
+#ifndef __DELAY_H
+#define __DELAY_H
+#include "stm32f10x.h"
+//////////////////////////////////////////////////////////////////////////////////
+//使用SysTick的普通计数模式对延迟进行管理
+//包括delay_us,delay_ms
+
+
+//********************************************************************************
+//V1.2修改说明
+//修正了中断中调用出现死循环的错误
+//防止延时不准确,采用do while结构!
+//////////////////////////////////////////////////////////////////////////////////
+void delay_init(u8 SYSCLK);
+void delay_ms(u16 nms);
+void delay_us(u32 nus);
+
+#endif
+
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diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/nvic/NVIC.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/nvic/NVIC.c"
new file mode 100644
index 0000000..d402848
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/nvic/NVIC.c"
@@ -0,0 +1,119 @@
+
+/*
+//杜洋工作室出品
+//洋桃系列开发板应用程序
+//关注微信公众号：洋桃电子
+//洋桃开发板资料下载 www.DoYoung.net/YT
+//即可免费看所有教学视频，下载技术资料，技术疑难提问
+//更多内容尽在 杜洋工作室主页 www.doyoung.net
+*/
+
+/*
+《修改日志》
+1-201708202312 创建。
+
+
+*/
+
+#include "NVIC.h"
+
+u8 INT_MARK;//中断标志位
+
+void KEYPAD4x4_INT_INIT (void){ //按键中断初始化
+ NVIC_InitTypeDef NVIC_InitStruct; //定义结构体变量
+ EXTI_InitTypeDef EXTI_InitStruct;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,ENABLE); //启动GPIO时钟 （需要与复用时钟一同启动）
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO , ENABLE);//配置端口中断需要启用复用时钟
+
+//第1个中断
+ GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource4); //定义 GPIO 中断
+
+ EXTI_InitStruct.EXTI_Line=EXTI_Line4; //定义中断线
+ EXTI_InitStruct.EXTI_LineCmd=ENABLE; //中断使能
+ EXTI_InitStruct.EXTI_Mode=EXTI_Mode_Interrupt; //中断模式为 中断
+ EXTI_InitStruct.EXTI_Trigger=EXTI_Trigger_Falling; //下降沿触发
+
+ EXTI_Init(& EXTI_InitStruct);
+
+ NVIC_InitStruct.NVIC_IRQChannel=EXTI4_IRQn; //中断线
+ NVIC_InitStruct.NVIC_IRQChannelCmd=ENABLE; //使能中断
+ NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority=2; //抢占优先级 2
+ NVIC_InitStruct.NVIC_IRQChannelSubPriority=2; //子优先级 2
+ NVIC_Init(& NVIC_InitStruct);
+
+//第2个中断
+ GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource5); //定义 GPIO 中断
+
+ EXTI_InitStruct.EXTI_Line=EXTI_Line5; //定义中断线
+ EXTI_InitStruct.EXTI_LineCmd=ENABLE; //中断使能
+ EXTI_InitStruct.EXTI_Mode=EXTI_Mode_Interrupt; //中断模式为 中断
+ EXTI_InitStruct.EXTI_Trigger=EXTI_Trigger_Falling; //下降沿触发
+
+ EXTI_Init(& EXTI_InitStruct);
+
+ NVIC_InitStruct.NVIC_IRQChannel=EXTI9_5_IRQn; //中断线
+ NVIC_InitStruct.NVIC_IRQChannelCmd=ENABLE; //使能中断
+ NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority=2; //抢占优先级 2
+ NVIC_InitStruct.NVIC_IRQChannelSubPriority=2; //子优先级 2
+ NVIC_Init(& NVIC_InitStruct);
+
+//第3个中断
+ GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource6); //定义 GPIO 中断
+
+ EXTI_InitStruct.EXTI_Line=EXTI_Line6; //定义中断线
+ EXTI_InitStruct.EXTI_LineCmd=ENABLE; //中断使能
+ EXTI_InitStruct.EXTI_Mode=EXTI_Mode_Interrupt; //中断模式为 中断
+ EXTI_InitStruct.EXTI_Trigger=EXTI_Trigger_Falling; //下降沿触发
+
+ EXTI_Init(& EXTI_InitStruct);
+
+ NVIC_InitStruct.NVIC_IRQChannel=EXTI9_5_IRQn; //中断线
+ NVIC_InitStruct.NVIC_IRQChannelCmd=ENABLE; //使能中断
+ NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority=2; //抢占优先级 2
+ NVIC_InitStruct.NVIC_IRQChannelSubPriority=2; //子优先级 2
+ NVIC_Init(& NVIC_InitStruct);
+
+//第4个中断
+ GPIO_EXTILineConfig(GPIO_PortSourceGPIOA, GPIO_PinSource7); //定义 GPIO 中断
+
+ EXTI_InitStruct.EXTI_Line=EXTI_Line7; //定义中断线
+ EXTI_InitStruct.EXTI_LineCmd=ENABLE; //中断使能
+ EXTI_InitStruct.EXTI_Mode=EXTI_Mode_Interrupt; //中断模式为 中断
+ EXTI_InitStruct.EXTI_Trigger=EXTI_Trigger_Falling; //下降沿触发
+
+ EXTI_Init(& EXTI_InitStruct);
+
+ NVIC_InitStruct.NVIC_IRQChannel=EXTI9_5_IRQn; //中断线
+ NVIC_InitStruct.NVIC_IRQChannelCmd=ENABLE; //使能中断
+ NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority=2; //抢占优先级 2
+ NVIC_InitStruct.NVIC_IRQChannelSubPriority=2; //子优先级 2
+ NVIC_Init(& NVIC_InitStruct);
+
+}
+
+void EXTI4_IRQHandler(void){
+ if(EXTI_GetITStatus(EXTI_Line4)!=RESET){//判断某个线上的中断是否发生
+ INT_MARK=1;//标志位置1，表示有按键中断
+ EXTI_ClearITPendingBit(EXTI_Line4); //清除 LINE 上的中断标志位
+ }
+}
+void EXTI9_5_IRQHandler(void){
+ if(EXTI_GetITStatus(EXTI_Line5)!=RESET){//判断某个线上的中断是否发生
+ INT_MARK=2;//标志位置1，表示有按键中断
+ EXTI_ClearITPendingBit(EXTI_Line5); //清除 LINE 上的中断标志位
+ }
+ if(EXTI_GetITStatus(EXTI_Line6)!=RESET){//判断某个线上的中断是否发生
+ INT_MARK=3;//标志位置1，表示有按键中断
+ EXTI_ClearITPendingBit(EXTI_Line6); //清除 LINE 上的中断标志位
+ }
+ if(EXTI_GetITStatus(EXTI_Line7)!=RESET){//判断某个线上的中断是否发生
+ INT_MARK=4;//标志位置1，表示有按键中断
+ EXTI_ClearITPendingBit(EXTI_Line7); //清除 LINE 上的中断标志位
+ }
+}
+
+
+
+
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/nvic/NVIC.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/nvic/NVIC.h"
new file mode 100644
index 0000000..6d0eb35
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/nvic/NVIC.h"
@@ -0,0 +1,11 @@
+#ifndef __NVIC_H
+#define __NVIC_H
+#include "sys.h"
+
+
+extern u8 INT_MARK;//中断标志位
+
+
+void KEYPAD4x4_INT_INIT (void);
+
+#endif
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/sys/sys.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/sys/sys.c"
new file mode 100644
index 0000000..632f569
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/sys/sys.c"
@@ -0,0 +1,180 @@
+#include "sys.h"
+
+//设置向量表偏移地址
+//NVIC_VectTab:基址
+//Offset:偏移量
+void MY_NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
+{
+ SCB->VTOR = NVIC_VectTab|(Offset & (u32)0x1FFFFF80);//设置NVIC的向量表偏移寄存器
+ //用于标识向量表是在CODE区还是在RAM区
+}
+//设置NVIC分组
+//NVIC_Group:NVIC分组 0~4 总共5组
+void MY_NVIC_PriorityGroupConfig(u8 NVIC_Group)
+{
+ u32 temp,temp1;
+ temp1=(~NVIC_Group)&0x07;//取后三位
+ temp1<<=8;
+ temp=SCB->AIRCR; //读取先前的设置
+ temp&=0X0000F8FF; //清空先前分组
+ temp|=0X05FA0000; //写入钥匙
+ temp|=temp1;
+ SCB->AIRCR=temp; //设置分组
+}
+//设置NVIC
+//NVIC_PreemptionPriority:抢占优先级
+//NVIC_SubPriority :响应优先级
+//NVIC_Channel :中断编号
+//NVIC_Group :中断分组 0~4
+//注意优先级不能超过设定的组的范围!否则会有意想不到的错误
+//组划分:
+//组0:0位抢占优先级,4位响应优先级
+//组1:1位抢占优先级,3位响应优先级
+//组2:2位抢占优先级,2位响应优先级
+//组3:3位抢占优先级,1位响应优先级
+//组4:4位抢占优先级,0位响应优先级
+//NVIC_SubPriority和NVIC_PreemptionPriority的原则是,数值越小,越优先
+void MY_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
+{
+ u32 temp;
+ u8 IPRADDR=NVIC_Channel/4; //每组只能存4个,得到组地址
+ u8 IPROFFSET=NVIC_Channel%4;//在组内的偏移
+ IPROFFSET=IPROFFSET*8+4; //得到偏移的确切位置
+ MY_NVIC_PriorityGroupConfig(NVIC_Group);//设置分组
+ temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
+ temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
+ temp&=0xf;//取低四位
+
+ if(NVIC_Channel<32)NVIC->ISER[0]|=1<ISER[1]|=1<<(NVIC_Channel-32);
+ NVIC->IP[IPRADDR]|=temp<APB2ENR|=0x01;//使能io复用时钟
+
+ AFIO->EXTICR[EXTADDR]&=~(0x000F<EXTICR[EXTADDR]|=GPIOx<IMR|=1<EMR|=1<FTSR|=1<RTSR|=1<APB1RSTR = 0x00000000;//复位结束
+ RCC->APB2RSTR = 0x00000000;
+
+ RCC->AHBENR = 0x00000014; //睡眠模式闪存和SRAM时钟使能.其他关闭.
+ RCC->APB2ENR = 0x00000000; //外设时钟关闭.
+ RCC->APB1ENR = 0x00000000;
+ RCC->CR |= 0x00000001; //使能内部高速时钟HSION
+ RCC->CFGR &= 0xF8FF0000; //复位SW[1:0],HPRE[3:0],PPRE1[2:0],PPRE2[2:0],ADCPRE[1:0],MCO[2:0]
+ RCC->CR &= 0xFEF6FFFF; //复位HSEON,CSSON,PLLON
+ RCC->CR &= 0xFFFBFFFF; //复位HSEBYP
+ RCC->CFGR &= 0xFF80FFFF; //复位PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE
+ RCC->CIR = 0x00000000; //关闭所有中断
+ //配置向量表
+#ifdef VECT_TAB_RAM
+ MY_NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else
+ MY_NVIC_SetVectorTable(NVIC_VectTab_FLASH,0x0);
+#endif
+}
+//THUMB指令不支持汇编内联
+//采用如下方法实现执行汇编指令WFI
+__asm void WFI_SET(void)
+{
+ WFI;
+}
+//关闭所有中断
+__asm void INTX_DISABLE(void)
+{
+ CPSID I;
+}
+//开启所有中断
+__asm void INTX_ENABLE(void)
+{
+ CPSIE I;
+}
+//设置栈顶地址
+//addr:栈顶地址
+__asm void MSR_MSP(u32 addr)
+{
+ MSR MSP, r0 //set Main Stack value
+ BX r14
+}
+
+//进入待机模式
+void Sys_Standby(void)
+{
+ SCB->SCR|=1<<2;//使能SLEEPDEEP位 (SYS->CTRL)
+ RCC->APB1ENR|=1<<28; //使能电源时钟
+ PWR->CSR|=1<<8; //设置WKUP用于唤醒
+ PWR->CR|=1<<2; //清除Wake-up 标志
+ PWR->CR|=1<<1; //PDDS置位
+ WFI_SET(); //执行WFI指令
+}
+//系统软复位
+void Sys_Soft_Reset(void)
+{
+ SCB->AIRCR =0X05FA0000|(u32)0x04;
+}
+//JTAG模式设置,用于设置JTAG的模式
+//mode:jtag,swd模式设置;00,全使能;01,使能SWD;10,全关闭;
+//#define JTAG_SWD_DISABLE 0X02
+//#define SWD_ENABLE 0X01
+//#define JTAG_SWD_ENABLE 0X00
+void JTAG_Set(u8 mode)
+{
+ u32 temp;
+ temp=mode;
+ temp<<=25;
+ RCC->APB2ENR|=1<<0; //开启辅助时钟
+ AFIO->MAPR&=0XF8FFFFFF; //清除MAPR的[26:24]
+ AFIO->MAPR|=temp; //设置jtag模式
+}
+//系统时钟初始化函数
+//pll:选择的倍频数，从2开始，最大值为16
+void Stm32_Clock_Init(u8 PLL)
+{
+ unsigned char temp=0;
+ MYRCC_DeInit(); //复位并配置向量表
+ RCC->CR|=0x00010000; //外部高速时钟使能HSEON
+ while(!(RCC->CR>>17));//等待外部时钟就绪
+ RCC->CFGR=0X00000400; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
+ PLL-=2;//抵消2个单位
+ RCC->CFGR|=PLL<<18; //设置PLL值 2~16
+ RCC->CFGR|=1<<16; //PLLSRC ON
+ FLASH->ACR|=0x32; //FLASH 2个延时周期
+
+ RCC->CR|=0x01000000; //PLLON
+ while(!(RCC->CR>>25));//等待PLL锁定
+ RCC->CFGR|=0x00000002;//PLL作为系统时钟
+ while(temp!=0x02) //等待PLL作为系统时钟设置成功
+ {
+ temp=RCC->CFGR>>2;
+ temp&=0x03;
+ }
+}
+void NVIC_Configuration(void){ //嵌套中断向量控制器 的设置
+ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); //设置NVIC中断分组2:2位抢占优先级，2位响应优先级
+}
\ No newline at end of file
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/sys/sys.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/sys/sys.h"
new file mode 100644
index 0000000..50dfeb3
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/sys/sys.h"
@@ -0,0 +1,63 @@
+#ifndef __SYS_H
+#define __SYS_H
+#include "stm32f10x.h"
+
+
+//0,不支持ucos
+//1,支持ucos
+#define SYSTEM_SUPPORT_UCOS 0 //定义系统文件夹是否支持UCOS
+
+
+//位带操作,实现51类似的GPIO控制功能
+//具体实现思想,参考<>第五章(87页~92页).
+//IO口操作宏定义
+#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
+#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
+#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
+//IO口地址映射
+#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
+#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
+#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
+#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
+#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
+#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
+#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
+
+#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
+#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
+#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
+#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
+#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
+#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
+#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
+
+//IO口操作,只对单一的IO口!
+//确保n的值小于16!
+#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //输出
+#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //输入
+
+#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出
+#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入
+
+#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出
+#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入
+
+#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //输出
+#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //输入
+
+#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出
+#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入
+
+#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //输出
+#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //输入
+
+#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //输出
+#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //输入
+
+
+
+void NVIC_Configuration(void);
+
+
+
+#endif
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/usart/usart.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/usart/usart.c"
new file mode 100644
index 0000000..1b64fa9
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/usart/usart.c"
@@ -0,0 +1,144 @@
+#include "sys.h"
+#include "usart.h"
+//////////////////////////////////////////////////////////////////////////////////
+//本程序只供学习使用，未经作者许可，不得用于其它任何用途
+//ALIENTEK Mini STM32开发板
+//串口1初始化
+//正点原子@ALIENTEK
+//技术论坛:www.openedv.com
+//修改日期:2010/5/27
+//版本：V1.3
+//版权所有，盗版必究。
+//Copyright(C) 正点原子 2009-2019
+//All rights reserved
+//********************************************************************************
+//V1.3修改说明
+//支持适应不同频率下的串口波特率设置.
+//加入了对printf的支持
+//增加了串口接收命令功能.
+//修正了printf第一个字符丢失的bug
+//////////////////////////////////////////////////////////////////////////////////
+
+
+//加入以下代码,支持printf函数,而不需要选择use MicroLIB
+#if 1
+#pragma import(__use_no_semihosting)
+//标准库需要的支持函数
+struct __FILE
+{
+ int handle;
+
+};
+
+FILE __stdout;
+//定义_sys_exit()以避免使用半主机模式
+_sys_exit(int x)
+{
+ x = x;
+}
+//重定义fputc函数
+int fputc(int ch, FILE *f)
+{
+ while((USART1->SR&0X40)==0);//循环发送,直到发送完毕
+ USART1->DR = (u8) ch;
+ return ch;
+}
+#endif
+
+/*使用microLib的方法*/
+ /*
+int fputc(int ch, FILE *f)
+{
+ USART_SendData(USART1, (uint8_t) ch);
+
+ while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET) {}
+
+ return ch;
+}
+int GetKey (void) {
+
+ while (!(USART1->SR & USART_FLAG_RXNE));
+
+ return ((int)(USART1->DR & 0x1FF));
+}
+*/
+
+u8 USART_RX_BUF[64]; //接收缓冲,最大64个字节.
+//接收状态
+//bit7，接收完成标志
+//bit6，接收到0x0d
+//bit5~0，接收到的有效字节数目
+u8 USART_RX_STA=0; //接收状态标记
+
+void uart_init(u32 bound){
+ //GPIO端口设置
+ GPIO_InitTypeDef GPIO_InitStructure;
+ USART_InitTypeDef USART_InitStructure;
+ NVIC_InitTypeDef NVIC_InitStructure;
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1|RCC_APB2Periph_GPIOA|RCC_APB2Periph_AFIO, ENABLE);
+ //USART1_TX PA.9
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ //USART1_RX PA.10
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ //Usart1 NVIC 配置
+
+ NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=3 ;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; //
+
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //IRQ通道使能
+ NVIC_Init(&NVIC_InitStructure); //根据NVIC_InitStruct中指定的参数初始化外设NVIC寄存器USART1
+
+ //USART 初始化设置
+
+ USART_InitStructure.USART_BaudRate = bound;//一般设置为9600;
+ USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+ USART_InitStructure.USART_StopBits = USART_StopBits_1;
+ USART_InitStructure.USART_Parity = USART_Parity_No;
+ USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+ USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+ USART_Init(USART1, &USART_InitStructure);
+
+
+ USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);//开启中断
+
+ USART_Cmd(USART1, ENABLE); //使能串口
+
+}
+
+void USART1_IRQHandler(void) //串口1中断服务程序
+ {
+ u8 Res;
+ if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET) //接收中断(接收到的数据必须是0x0d 0x0a结尾)
+ {
+ Res =USART_ReceiveData(USART1);//(USART1->DR); //读取接收到的数据
+
+ if((USART_RX_STA&0x80)==0)//接收未完成
+ {
+ if(USART_RX_STA&0x40)//接收到了0x0d
+ {
+ if(Res!=0x0a)USART_RX_STA=0;//接收错误,重新开始
+ else USART_RX_STA|=0x80; //接收完成了
+ }
+ else //还没收到0X0D
+ {
+ if(Res==0x0d)USART_RX_STA|=0x40;
+ else
+ {
+ USART_RX_BUF[USART_RX_STA&0X3F]=Res ;
+ USART_RX_STA++;
+ if(USART_RX_STA>63)USART_RX_STA=0;//接收数据错误,重新开始接收
+ }
+ }
+ }
+ }
+}
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/usart/usart.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/usart/usart.h"
new file mode 100644
index 0000000..ba99252
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/SYSTEM/usart/usart.h"
@@ -0,0 +1,27 @@
+#ifndef __USART_H
+#define __USART_H
+#include "stdio.h"
+//////////////////////////////////////////////////////////////////////////////////
+//本程序只供学习使用，未经作者许可，不得用于其它任何用途
+//Mini STM32开发板
+//串口1初始化
+//正点原子@ALIENTEK
+//技术论坛:www.openedv.com
+//修改日期:2010/5/27
+//版本：V1.3
+//版权所有，盗版必究。
+//Copyright(C) 正点原子 2009-2019
+//All rights reserved
+//********************************************************************************
+//V1.3修改说明
+//支持适应不同频率下的串口波特率设置.
+//加入了对printf的支持
+//增加了串口接收命令功能.
+//修正了printf第一个字符丢失的bug
+//////////////////////////////////////////////////////////////////////////////////
+extern u8 USART_RX_BUF[64]; //接收缓冲,最大63个字节.末字节为换行符
+extern u8 USART_RX_STA; //接收状态标记
+
+void uart_init(u32 bound);
+
+#endif
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/GUI.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/GUI.c"
new file mode 100644
index 0000000..b415e86
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/GUI.c"
@@ -0,0 +1,658 @@
+#include "lcd.h"
+#include "string.h"
+#include "font.h"
+#include "delay.h"
+#include "gui.h"
+
+//******************************************************************
+//函数名： GUI_DrawPoint
+//功能： GUI描绘一个点
+//输入参数：x:光标位置x坐标
+// y:光标位置y坐标
+// color:要填充的颜色
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void GUI_DrawPoint(u16 x,u16 y,u16 color)
+{
+ LCD_SetCursor(x,y);//设置光标位置
+ LCD_WR_DATA_16Bit(color);
+}
+
+//******************************************************************
+//函数名： LCD_Fill
+//功能： 在指定区域内填充颜色
+//输入参数：sx:指定区域开始点x坐标
+// sy:指定区域开始点y坐标
+// ex:指定区域结束点x坐标
+// ey:指定区域结束点y坐标
+// color:要填充的颜色
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void LCD_Fill(u16 sx,u16 sy,u16 ex,u16 ey,u16 color)
+{
+
+ u16 i,j;
+ u16 width=ex-sx+1; //得到填充的宽度
+ u16 height=ey-sy+1; //高度
+ LCD_SetWindows(sx,sy,ex-1,ey-1);//设置显示窗口
+ for(i=0;i0)incx=1; //设置单步方向
+ else if(delta_x==0)incx=0;//垂直线
+ else {incx=-1;delta_x=-delta_x;}
+ if(delta_y>0)incy=1;
+ else if(delta_y==0)incy=0;//水平线
+ else{incy=-1;delta_y=-delta_y;}
+ if( delta_x>delta_y)distance=delta_x; //选取基本增量坐标轴
+ else distance=delta_y;
+ for(t=0;t<=distance+1;t++ )//画线输出
+ {
+ LCD_DrawPoint(uRow,uCol);//画点
+ xerr+=delta_x ;
+ yerr+=delta_y ;
+ if(xerr>distance)
+ {
+ xerr-=distance;
+ uRow+=incx;
+ }
+ if(yerr>distance)
+ {
+ yerr-=distance;
+ uCol+=incy;
+ }
+ }
+}
+
+//******************************************************************
+//函数名： LCD_DrawRectangle
+//功能： GUI画矩形(非填充)
+//输入参数：(x1,y1),(x2,y2):矩形的对角坐标
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void LCD_DrawRectangle(u16 x1, u16 y1, u16 x2, u16 y2)
+{
+ LCD_DrawLine(x1,y1,x2,y1);
+ LCD_DrawLine(x1,y1,x1,y2);
+ LCD_DrawLine(x1,y2,x2,y2);
+ LCD_DrawLine(x2,y1,x2,y2);
+}
+
+//******************************************************************
+//函数名： LCD_DrawFillRectangle
+//功能： GUI画矩形(填充)
+//输入参数：(x1,y1),(x2,y2):矩形的对角坐标
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void LCD_DrawFillRectangle(u16 x1, u16 y1, u16 x2, u16 y2)
+{
+ LCD_Fill(x1,y1,x2,y2,POINT_COLOR);
+
+}
+
+//******************************************************************
+//函数名： _draw_circle_8
+//功能： 对称性画圆算法(内部调用)
+//输入参数：(xc,yc) :圆中心坐标
+// (x,y):光标相对于圆心的坐标
+// c:填充的颜色
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void _draw_circle_8(int xc, int yc, int x, int y, u16 c)
+{
+ GUI_DrawPoint(xc + x, yc + y, c);
+
+ GUI_DrawPoint(xc - x, yc + y, c);
+
+ GUI_DrawPoint(xc + x, yc - y, c);
+
+ GUI_DrawPoint(xc - x, yc - y, c);
+
+ GUI_DrawPoint(xc + y, yc + x, c);
+
+ GUI_DrawPoint(xc - y, yc + x, c);
+
+ GUI_DrawPoint(xc + y, yc - x, c);
+
+ GUI_DrawPoint(xc - y, yc - x, c);
+}
+
+//******************************************************************
+//函数名： gui_circle
+//功能： 在指定位置画一个指定大小的圆(填充)
+//输入参数：(xc,yc) :圆中心坐标
+// c:填充的颜色
+// r:圆半径
+// fill:填充判断标志，1-填充，0-不填充
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void gui_circle(int xc, int yc,u16 c,int r, int fill)
+{
+ int x = 0, y = r, yi, d;
+
+ d = 3 - 2 * r;
+
+
+ if (fill)
+ {
+ // 如果填充（画实心圆）
+ while (x <= y) {
+ for (yi = x; yi <= y; yi++)
+ _draw_circle_8(xc, yc, x, yi, c);
+
+ if (d < 0) {
+ d = d + 4 * x + 6;
+ } else {
+ d = d + 4 * (x - y) + 10;
+ y--;
+ }
+ x++;
+ }
+ } else
+ {
+ // 如果不填充（画空心圆）
+ while (x <= y) {
+ _draw_circle_8(xc, yc, x, y, c);
+ if (d < 0) {
+ d = d + 4 * x + 6;
+ } else {
+ d = d + 4 * (x - y) + 10;
+ y--;
+ }
+ x++;
+ }
+ }
+}
+
+//******************************************************************
+//函数名： LCD_ShowChar
+//功能： 显示单个英文字符
+//输入参数：(x,y):字符显示位置起始坐标
+// fc:前置画笔颜色
+// bc:背景颜色
+// num:数值（0-94）
+// size:字体大小
+// mode:模式 0,填充模式;1,叠加模式
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void LCD_ShowChar(u16 x,u16 y,u16 fc, u16 bc, u8 num,u8 size,u8 mode)
+{
+ u8 temp;
+ u8 pos,t;
+ u16 colortemp=POINT_COLOR;
+
+ num=num-' ';//得到偏移后的值
+ LCD_SetWindows(x,y,x+size/2-1,y+size-1);//设置单个文字显示窗口
+ if(!mode) //非叠加方式
+ {
+
+ for(pos=0;pos>=1;
+
+ }
+
+ }
+ }else//叠加方式
+ {
+ for(pos=0;pos>=1;
+ }
+ }
+ }
+ POINT_COLOR=colortemp;
+ LCD_SetWindows(0,0,lcddev.width-1,lcddev.height-1);//恢复窗口为全屏
+}
+
+//******************************************************************
+//函数名： LCD_ShowChar
+//功能： 显示单个英文字符
+//输入参数：(x,y):字符显示位置起始坐标
+// fc:前置画笔颜色
+// bc:背景颜色
+// num:数值（0-94）
+// size:字体大小
+// mode:模式 0,填充模式;1,叠加模式
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void LCD_ShowNum2412(u16 x,u16 y,u16 fc, u16 bc,u8 *p ,u8 size,u8 mode)
+{
+ u16 temp;
+ u8 pos,t;
+ u16 colortemp=POINT_COLOR;
+ u16 x0=x;
+ u16 y0=y;
+ u8 num=0;
+
+
+ while((*p<='~')&&(*p>=' '))//判断是不是非法字符!
+ {
+
+ if(x>(lcddev.width-1)||y>(lcddev.height-1))
+ return;
+ num=*p;
+ if(':'==num) //特殊字符":"
+ num=10;
+ else if('.'==num)//特殊字符"."
+ num=11;
+ else //纯数字
+// num=num-'0';
+ num=num;
+ x0=x;
+
+ for(pos=0;pos<48;pos++)
+ {
+ temp=asc2_2412[num][pos];
+ for(t=0;t<8;t++)
+ {
+ POINT_COLOR=fc;
+ if(temp&0x80)LCD_DrawPoint(x,y);//画一个点
+ //else LCD_WR_DATA_16Bit(bc);
+ temp<<=1;
+ x++;
+ if((x-x0)==12)
+ {
+ x=x0;
+ y++;
+ break;
+ }
+ }
+ }
+ if(num<10)
+ x+=16; //人为控制字距，使得排版更好看，原值为12
+ else
+ x+=8; //人为控制字距，使得排版更好看，原值为12
+
+ y=y0;
+ p++;
+ }
+ POINT_COLOR=colortemp;
+}
+
+
+//******************************************************************
+//函数名： LCD_ShowString
+//功能： 显示英文字符串
+//输入参数：x,y :起点坐标
+// size:字体大小
+// *p:字符串起始地址
+// mode:模式 0,填充模式;1,叠加模式
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void LCD_ShowString(u16 x,u16 y,u8 size,u8 *p,u8 mode)
+{
+ while((*p<='~')&&(*p>=' '))//判断是不是非法字符!
+ {
+ if(x>(lcddev.width-1)||y>(lcddev.height-1))
+ return;
+ LCD_ShowChar(x,y,POINT_COLOR,BACK_COLOR,*p,size,mode);
+ x+=size/2;
+ p++;
+ }
+}
+
+//******************************************************************
+//函数名： mypow
+//功能： 求m的n次方(gui内部调用)
+//输入参数：m:乘数
+// n:幂
+//返回值： m的n次方
+//修改记录：无
+//******************************************************************
+u32 mypow(u8 m,u8 n)
+{
+ u32 result=1;
+ while(n--)result*=m;
+ return result;
+}
+
+//******************************************************************
+//函数名： LCD_ShowNum
+//功能： 显示单个数字变量值
+//输入参数：x,y :起点坐标
+// len :指定显示数字的位数
+// size:字体大小(12,16)
+// color:颜色
+// num:数值(0~4294967295)
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void LCD_ShowNum(u16 x,u16 y,u32 num,u8 len,u8 size)
+{
+ u8 t,temp;
+ u8 enshow=0;
+ for(t=0;t>j)) LCD_WR_DATA_16Bit(fc);
+ else LCD_WR_DATA_16Bit(bc);
+ }
+ else
+ {
+ POINT_COLOR=fc;
+ if(tfont16[k].Msk[i]&(0x80>>j)) LCD_DrawPoint(x,y);//画一个点
+ x++;
+ if((x-x0)==16)
+ {
+ x=x0;
+ y++;
+ break;
+ }
+ }
+
+ }
+
+ }
+
+
+ }
+ continue; //查找到对应点阵字库立即退出，防止多个汉字重复取模带来影响
+ }
+
+ LCD_SetWindows(0,0,lcddev.width-1,lcddev.height-1);//恢复窗口为全屏
+}
+
+//******************************************************************
+//函数名： GUI_DrawFont24
+//功能： 显示单个24X24中文字体
+//输入参数：x,y :起点坐标
+// fc:前置画笔颜色
+// bc:背景颜色
+// s:字符串地址
+// mode:模式 0,填充模式;1,叠加模式
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void GUI_DrawFont24(u16 x, u16 y, u16 fc, u16 bc, u8 *s,u8 mode)
+{
+ u8 i,j;
+ u16 k;
+ u16 HZnum;
+ u16 x0=x;
+ HZnum=sizeof(tfont24)/sizeof(typFNT_GB24); //自动统计汉字数目
+
+ for (k=0;k>j)) LCD_WR_DATA_16Bit(fc);
+ else LCD_WR_DATA_16Bit(bc);
+ }
+ else
+ {
+ POINT_COLOR=fc;
+ if(tfont24[k].Msk[i]&(0x80>>j)) LCD_DrawPoint(x,y);//画一个点
+ x++;
+ if((x-x0)==24)
+ {
+ x=x0;
+ y++;
+ break;
+ }
+ }
+ }
+ }
+
+
+ }
+ continue; //查找到对应点阵字库立即退出，防止多个汉字重复取模带来影响
+ }
+
+ LCD_SetWindows(0,0,lcddev.width-1,lcddev.height-1);//恢复窗口为全屏
+}
+
+//******************************************************************
+//函数名： GUI_DrawFont32
+//功能： 显示单个32X32中文字体
+//输入参数：x,y :起点坐标
+// fc:前置画笔颜色
+// bc:背景颜色
+// s:字符串地址
+// mode:模式 0,填充模式;1,叠加模式
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void GUI_DrawFont32(u16 x, u16 y, u16 fc, u16 bc, u8 *s,u8 mode)
+{
+ u8 i,j;
+ u16 k;
+ u16 HZnum;
+ u16 x0=x;
+ HZnum=sizeof(tfont32)/sizeof(typFNT_GB32); //自动统计汉字数目
+ for (k=0;k>j)) LCD_WR_DATA_16Bit(fc);
+ else LCD_WR_DATA_16Bit(bc);
+ }
+ else
+ {
+ POINT_COLOR=fc;
+ if(tfont32[k].Msk[i]&(0x80>>j)) LCD_DrawPoint(x,y);//画一个点
+ x++;
+ if((x-x0)==32)
+ {
+ x=x0;
+ y++;
+ break;
+ }
+ }
+ }
+ }
+
+
+ }
+ continue; //查找到对应点阵字库立即退出，防止多个汉字重复取模带来影响
+ }
+
+ LCD_SetWindows(0,0,lcddev.width-1,lcddev.height-1);//恢复窗口为全屏
+}
+
+//******************************************************************
+//函数名： Show_Str
+//功能： 显示一个字符串,包含中英文显示
+//输入参数：x,y :起点坐标
+// fc:前置画笔颜色
+// bc:背景颜色
+// str :字符串
+// size:字体大小
+// mode:模式 0,填充模式;1,叠加模式
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void Show_Str(u16 x, u16 y, u16 fc, u16 bc, u8 *str,u8 size,u8 mode)
+{
+ u16 x0=x;
+ u8 bHz=0; //字符或者中文
+ while(*str!=0)//数据未结束
+ {
+ if(!bHz)
+ {
+ if(x>(lcddev.width-size/2)||y>(lcddev.height-size))
+ return;
+ if(*str>0x80)bHz=1;//中文
+ else //字符
+ {
+ if(*str==0x0D)//换行符号
+ {
+ y+=size;
+ x=x0;
+ str++;
+ }
+ else
+ {
+ if(size==12||size==16)
+ {
+ LCD_ShowChar(x,y,fc,bc,*str,size,mode);
+ x+=size/2; //字符,为全字的一半
+ }
+ else//字库中没有集成16X32的英文字体,用8X16代替
+ {
+ LCD_ShowChar(x,y,fc,bc,*str,16,mode);
+ x+=8; //字符,为全字的一半
+ }
+ }
+ str++;
+
+ }
+ }else//中文
+ {
+ if(x>(lcddev.width-size)||y>(lcddev.height-size))
+ return;
+ bHz=0;//有汉字库
+ if(size==32)
+ GUI_DrawFont32(x,y,fc,bc,str,mode);
+ else if(size==24)
+ GUI_DrawFont24(x,y,fc,bc,str,mode);
+ else
+ GUI_DrawFont16(x,y,fc,bc,str,mode);
+
+ str+=2;
+ x+=size;//下一个汉字偏移
+ }
+ }
+}
+
+//******************************************************************
+//函数名： Gui_StrCenter
+//功能： 居中显示一个字符串,包含中英文显示
+//输入参数：x,y :起点坐标
+// fc:前置画笔颜色
+// bc:背景颜色
+// str :字符串
+// size:字体大小
+// mode:模式 0,填充模式;1,叠加模式
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void Gui_StrCenter(u16 x, u16 y, u16 fc, u16 bc, u8 *str,u8 size,u8 mode)
+{
+ u16 len=strlen((const char *)str);
+ u16 x1=(lcddev.width-len*8)/2;
+ Show_Str(x+x1,y,fc,bc,str,size,mode);
+}
+
+//******************************************************************
+//函数名： Gui_Drawbmp16
+//功能： 显示一副16位BMP图像
+//输入参数：x,y :起点坐标
+// *p :图像数组起始地址
+//返回值： 无
+//修改记录：无
+//******************************************************************
+void Gui_Drawbmp16(u16 x,u16 y,const unsigned char *p) //显示40*40 QQ图片
+{
+ int i;
+ unsigned char picH,picL;
+ LCD_SetWindows(x,y,x+40-1,y+40-1);//窗口设置
+ for(i=0;i<40*40;i++)
+ {
+ picL=*(p+i*2); //数据低位在前
+ picH=*(p+i*2+1);
+ LCD_WR_DATA_16Bit(picH<<8|picL);
+ }
+ LCD_SetWindows(0,0,lcddev.width-1,lcddev.height-1);//恢复显示窗口为全屏
+
+}
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/GUI.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/GUI.h"
new file mode 100644
index 0000000..c1e19ca
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/GUI.h"
@@ -0,0 +1,23 @@
+#ifndef __GUI_H__
+#define __GUI_H__
+
+void GUI_DrawPoint(u16 x,u16 y,u16 color);
+void LCD_Fill(u16 sx,u16 sy,u16 ex,u16 ey,u16 color);
+void LCD_DrawLine(u16 x1, u16 y1, u16 x2, u16 y2);
+void LCD_DrawRectangle(u16 x1, u16 y1, u16 x2, u16 y2);
+void Draw_Circle(u16 x0,u16 y0,u16 fc,u8 r);
+void LCD_ShowChar(u16 x,u16 y,u16 fc, u16 bc, u8 num,u8 size,u8 mode);
+void LCD_ShowNum(u16 x,u16 y,u32 num,u8 len,u8 size);
+void LCD_Show2Num(u16 x,u16 y,u16 num,u8 len,u8 size,u8 mode);
+void LCD_ShowString(u16 x,u16 y,u8 size,u8 *p,u8 mode);
+void GUI_DrawFont16(u16 x, u16 y, u16 fc, u16 bc, u8 *s,u8 mode);
+void GUI_DrawFont24(u16 x, u16 y, u16 fc, u16 bc, u8 *s,u8 mode);
+void GUI_DrawFont32(u16 x, u16 y, u16 fc, u16 bc, u8 *s,u8 mode);
+void Show_Str(u16 x, u16 y, u16 fc, u16 bc, u8 *str,u8 size,u8 mode);
+void Gui_Drawbmp16(u16 x,u16 y,const unsigned char *p); //显示40*40 QQ图片
+void gui_circle(int xc, int yc,u16 c,int r, int fill);
+void Gui_StrCenter(u16 x, u16 y, u16 fc, u16 bc, u8 *str,u8 size,u8 mode);
+void LCD_DrawFillRectangle(u16 x1, u16 y1, u16 x2, u16 y2);
+void LCD_ShowNum2412(u16 x,u16 y,u16 fc, u16 bc,u8 *p ,u8 size,u8 mode);
+#endif
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLink Regs CM3.txt" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLink Regs CM3.txt"
new file mode 100644
index 0000000..08327ff
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLink Regs CM3.txt"
@@ -0,0 +1,32 @@
+0: R0: 0x00
+1: R1: 0x01
+2: R2: 0x02
+3: R3: 0x03
+4: R4: 0x04
+5: R5: 0x05
+6: R6: 0x06
+7: R7: 0x07
+8: R8: 0x08
+9: R9: 0x09
+10: R10: 0x0a
+11: R11: 0x0b
+12: R12: 0x0c
+13: R13: 0x0d
+14: R14: 0x0e
+15: R15: 0x0f
+16: XPSR: 0x10
+17: MSP: 0x11
+18: PSP: 0x12
+19: RAZ: 0x13
+20: CFBP: 0x14
+21: APSR: 0x15
+22: EPSR: 0x16
+23: IPSR: 0x17
+24: PRIMASK: 0x18
+25: BASEPRI: 0x19
+26: FAULTMASK: 0x1a
+27: CONTROL: 0x1b
+28: BASEPRI_MAX: 0x1c
+29: IAPSR: 0x1d
+30: EAPSR: 0x1e
+31: IEPSR: 0x1f
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLinkLog.txt" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLinkLog.txt"
new file mode 100644
index 0000000..2e8844e
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLinkLog.txt"
@@ -0,0 +1,1785 @@
+
+T0964 000:113 SEGGER J-Link V6.30d Log File (0001ms, 0054ms total)
+T0964 000:113 DLL Compiled: Feb 16 2018 13:30:32 (0001ms, 0054ms total)
+T0964 000:113 Logging started @ 2019-01-18 11:12 (0001ms, 0054ms total)
+T0964 000:114 JLINK_SetWarnOutHandler(...) (0000ms, 0054ms total)
+T0964 000:114 JLINK_OpenEx(...)
+Firmware: J-Link V9 compiled Feb 16 2018 13:04:36
+Hardware: V9.40
+S/N: 59400616
+Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
+TELNET listener socket opened on port 19021WEBSRV
+Starting webserver (0074ms, 0128ms total)
+T0964 000:114 WEBSRV Webserver running on local port 19080 (0074ms, 0128ms total)
+T0964 000:114 returns O.K. (0074ms, 0128ms total)
+T0964 000:189 JLINK_SetErrorOutHandler(...) (0000ms, 0128ms total)
+T0964 000:189 JLINK_ExecCommand("ProjectFile = "F:\项目\compile\KEY\矩阵键盘显示\USER\JLinkSettings.ini"", ...). returns 0x00 (0246ms, 0374ms total)
+T0964 000:439 JLINK_ExecCommand("Device = STM32F103RB", ...). Device "STM32F103RB" selected. returns 0x00 (0008ms, 0382ms total)
+T0964 000:447 JLINK_ExecCommand("DisableConnectionTimeout", ...). returns 0x01 (0000ms, 0382ms total)
+T0964 000:447 JLINK_GetHardwareVersion() returns 0x16F30 (0000ms, 0382ms total)
+T0964 000:447 JLINK_GetDLLVersion() returns 63004 (0000ms, 0382ms total)
+T0964 000:447 JLINK_GetFirmwareString(...) (0000ms, 0382ms total)
+T0964 000:463 JLINK_GetDLLVersion() returns 63004 (0000ms, 0382ms total)
+T0964 000:463 JLINK_GetCompileDateTime() (0000ms, 0382ms total)
+T0964 000:467 JLINK_GetFirmwareString(...) (0000ms, 0382ms total)
+T0964 000:475 JLINK_GetHardwareVersion() returns 0x16F30 (0000ms, 0382ms total)
+T0964 000:494 JLINK_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0002ms, 0384ms total)
+T0964 000:496 JLINK_SetSpeed(10000) (0000ms, 0384ms total)
+T0964 000:496 JLINK_GetId() >0x10B TIF>Found SW-DP with ID 0x1BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF>
+ >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x10B TIF>Found SW-DP with ID 0x1BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF>Scanning AP map to find all available APs >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF>
+ >0x0D TIF> >0x21 TIF>AP[1]: Stopped AP scan as end of AP map has been reachedAP[0]: AHB-AP (IDR: 0x14770011)Iterating through AP map to find AHB-AP to use >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>AP[0]: Core foundAP[0]: AHB-AP ROM base: 0xE00FF000 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF>
+ >0x21 TIF>CPUID register: 0x411FC231. Implementer code: 0x41 (ARM)Found Cortex-M3 r1p1, Little endian. -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)
+ -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl[0] @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 001BB000 SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 001BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)
+ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 001BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl[0][4]: E0040000, CID: B105900D, PID: 001BB923 TPIU-Lite >0x0D TIF> >0x21 TIF> returns 0x1BA01477 (0279ms, 0663ms total)
+T0964 000:776 JLINK_GetDLLVersion() returns 63004 (0000ms, 0663ms total)
+T0964 000:776 JLINK_CORE_GetFound() returns 0x30000FF (0000ms, 0663ms total)
+T0964 000:776 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 0663ms total)
+T0964 000:781 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 0663ms total)
+T0964 000:781 JLINK_GetDebugInfo(0x101 = JLINKARM_DEBUG_INFO_ETM_ADDR_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 0663ms total)
+T0964 000:781 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 returns 0x00 (0001ms, 0664ms total)
+T0964 000:782 JLINK_GetDebugInfo(0x102 = JLINKARM_DEBUG_INFO_MTB_ADDR_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 0664ms total)
+T0964 000:782 JLINK_GetDebugInfo(0x103 = JLINKARM_DEBUG_INFO_TPIU_ADDR_INDEX) -- Value=0xE0040000 returns 0x00 (0000ms, 0664ms total)
+T0964 000:782 JLINK_GetDebugInfo(0x104 = JLINKARM_DEBUG_INFO_ITM_ADDR_INDEX) -- Value=0xE0000000 returns 0x00 (0000ms, 0664ms total)
+T0964 000:782 JLINK_GetDebugInfo(0x105 = JLINKARM_DEBUG_INFO_DWT_ADDR_INDEX) -- Value=0xE0001000 returns 0x00 (0000ms, 0664ms total)
+T0964 000:782 JLINK_GetDebugInfo(0x106 = JLINKARM_DEBUG_INFO_FPB_ADDR_INDEX) -- Value=0xE0002000 returns 0x00 (0000ms, 0664ms total)
+T0964 000:783 JLINK_GetDebugInfo(0x107 = JLINKARM_DEBUG_INFO_NVIC_ADDR_INDEX) -- Value=0xE000E000 returns 0x00 (0000ms, 0664ms total)
+T0964 000:783 JLINK_GetDebugInfo(0x10C = JLINKARM_DEBUG_INFO_DBG_ADDR_INDEX) -- Value=0xE000EDF0 returns 0x00 (0000ms, 0664ms total)
+T0964 000:783 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41 returns 0x01 (0000ms, 0664ms total)
+T0964 000:783 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) returns JLINKARM_CM3_RESET_TYPE_NORMAL (0000ms, 0664ms total)
+T0964 000:783 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.SYSRESETREQ. -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) >0x0D TIF> >0x28 TIF> -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0078ms, 0742ms total)
+T0964 000:861 JLINK_Halt() returns 0x00 (0000ms, 0742ms total)
+T0964 000:861 JLINK_IsHalted() returns TRUE (0000ms, 0742ms total)
+T0964 000:861 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 0743ms total)
+T0964 000:862 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 0743ms total)
+T0964 000:862 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 0744ms total)
+T0964 000:881 JLINK_GetHWStatus(...) returns 0x00 (0001ms, 0745ms total)
+T0964 000:895 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 0745ms total)
+T0964 000:895 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 0745ms total)
+T0964 000:895 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 0745ms total)
+T0964 000:913 JLINK_GetSpeed() returns 0x1770 (0000ms, 0745ms total)
+T0964 000:922 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0001ms, 0746ms total)
+T0964 000:923 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0000ms, 0746ms total)
+T0964 000:923 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0002ms, 0748ms total)
+T0964 000:925 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 0749ms total)
+T0964 000:926 JLINK_Halt() returns 0x00 (0000ms, 0749ms total)
+T0964 000:926 JLINK_IsHalted() returns TRUE (0000ms, 0749ms total)
+T0964 000:932 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0002ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R1, 0x007A1200) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0751ms total)
+T0964 000:935 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0001ms, 0752ms total)
+T0964 000:936 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0752ms total)
+T0964 000:936 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000001 (0001ms, 0753ms total)
+T0964 000:937 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0005ms, 0758ms total)
+T0964 000:942 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0761ms total)
+T0964 000:945 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0758ms total)
+T0964 000:945 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 0758ms total)
+T0964 000:945 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0758ms total)
+T0964 000:946 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0758ms total)
+T0964 000:947 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0758ms total)
+T0964 000:947 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 0758ms total)
+T0964 000:947 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0760ms total)
+T0964 000:949 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0762ms total)
+T0964 000:951 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0760ms total)
+T0964 000:951 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 0760ms total)
+T0964 000:952 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0761ms total)
+T0964 000:952 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 0761ms total)
+T0964 000:952 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0763ms total)
+T0964 000:954 JLINK_IsHalted() returns FALSE (0001ms, 0764ms total)
+T0964 001:072 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0766ms total)
+T0964 001:075 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0763ms total)
+T0964 001:075 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 0763ms total)
+T0964 001:075 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0763ms total)
+T0964 001:076 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000004 (0000ms, 0763ms total)
+T0964 001:076 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0765ms total)
+T0964 001:078 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0768ms total)
+T0964 001:081 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0765ms total)
+T0964 001:081 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 0765ms total)
+T0964 001:081 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0765ms total)
+T0964 001:081 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 0765ms total)
+T0964 001:081 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0765ms total)
+T0964 001:081 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0765ms total)
+T0964 001:081 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0765ms total)
+T0964 001:081 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0766ms total)
+T0964 001:082 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 0766ms total)
+T0964 001:082 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0768ms total)
+T0964 001:084 JLINK_IsHalted() returns FALSE (0001ms, 0769ms total)
+T0964 001:088 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:090 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:092 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:094 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:096 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:098 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:100 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:102 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:104 JLINK_IsHalted() returns FALSE (0000ms, 0768ms total)
+T0964 001:106 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0770ms total)
+T0964 001:108 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0768ms total)
+T0964 001:108 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 0768ms total)
+T0964 001:108 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0768ms total)
+T0964 001:109 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0769ms total)
+T0964 001:109 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0769ms total)
+T0964 001:109 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0769ms total)
+T0964 001:109 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0769ms total)
+T0964 001:109 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0769ms total)
+T0964 001:109 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0770ms total)
+T0964 001:110 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 0770ms total)
+T0964 001:110 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0772ms total)
+T0964 001:112 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0775ms total)
+T0964 001:115 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0772ms total)
+T0964 001:115 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0772ms total)
+T0964 001:115 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0001ms, 0773ms total)
+T0964 001:116 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0773ms total)
+T0964 001:116 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0773ms total)
+T0964 001:116 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 0773ms total)
+T0964 001:116 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0774ms total)
+T0964 001:118 JLINK_IsHalted() returns FALSE (0000ms, 0775ms total)
+T0964 001:123 JLINK_IsHalted() returns FALSE (0000ms, 0775ms total)
+T0964 001:125 JLINK_IsHalted() returns FALSE (0000ms, 0775ms total)
+T0964 001:145 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0777ms total)
+T0964 001:147 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0775ms total)
+T0964 001:147 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0000ms, 0775ms total)
+T0964 001:147 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0775ms total)
+T0964 001:148 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0776ms total)
+T0964 001:149 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 0776ms total)
+T0964 001:149 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0778ms total)
+T0964 001:151 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0781ms total)
+T0964 001:154 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0778ms total)
+T0964 001:154 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0778ms total)
+T0964 001:154 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0001ms, 0779ms total)
+T0964 001:155 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0779ms total)
+T0964 001:155 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 0779ms total)
+T0964 001:155 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0781ms total)
+T0964 001:157 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:159 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:161 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:163 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:165 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:167 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:169 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:171 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:175 JLINK_IsHalted() returns FALSE (0000ms, 0781ms total)
+T0964 001:177 JLINK_IsHalted() returns FALSE (0004ms, 0785ms total)
+T0964 001:183 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0783ms total)
+T0964 001:185 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0781ms total)
+T0964 001:185 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 0781ms total)
+T0964 001:185 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0781ms total)
+T0964 001:186 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 0781ms total)
+T0964 001:186 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0781ms total)
+T0964 001:186 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0781ms total)
+T0964 001:186 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0781ms total)
+T0964 001:186 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0781ms total)
+T0964 001:186 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0781ms total)
+T0964 001:186 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0781ms total)
+T0964 001:187 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0782ms total)
+T0964 001:187 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 0782ms total)
+T0964 001:187 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0784ms total)
+T0964 001:189 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0787ms total)
+T0964 001:192 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0784ms total)
+T0964 001:192 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:192 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0784ms total)
+T0964 001:193 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0785ms total)
+T0964 001:193 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 0785ms total)
+T0964 001:193 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0787ms total)
+T0964 001:195 JLINK_IsHalted() returns FALSE (0001ms, 0788ms total)
+T0964 001:198 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:200 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:202 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:204 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:206 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:208 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:210 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:212 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:214 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:216 JLINK_IsHalted() returns FALSE (0000ms, 0787ms total)
+T0964 001:218 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0789ms total)
+T0964 001:220 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0788ms total)
+T0964 001:221 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0000ms, 0788ms total)
+T0964 001:221 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0788ms total)
+T0964 001:221 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 0788ms total)
+T0964 001:221 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0788ms total)
+T0964 001:222 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0789ms total)
+T0964 001:222 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 0789ms total)
+T0964 001:222 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0791ms total)
+T0964 001:224 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0794ms total)
+T0964 001:227 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0791ms total)
+T0964 001:227 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0791ms total)
+T0964 001:227 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 0792ms total)
+T0964 001:228 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0792ms total)
+T0964 001:228 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0792ms total)
+T0964 001:228 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0792ms total)
+T0964 001:228 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0792ms total)
+T0964 001:228 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0792ms total)
+T0964 001:228 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0792ms total)
+T0964 001:228 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0792ms total)
+T0964 001:228 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 0792ms total)
+T0964 001:228 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0794ms total)
+T0964 001:230 JLINK_IsHalted() returns FALSE (0000ms, 0794ms total)
+T0964 001:232 JLINK_IsHalted() returns FALSE (0000ms, 0794ms total)
+T0964 001:234 JLINK_IsHalted() returns FALSE (0000ms, 0794ms total)
+T0964 001:252 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0797ms total)
+T0964 001:255 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0794ms total)
+T0964 001:255 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 0794ms total)
+T0964 001:255 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0794ms total)
+T0964 001:256 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 0794ms total)
+T0964 001:256 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0796ms total)
+T0964 001:259 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0798ms total)
+T0964 001:261 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0797ms total)
+T0964 001:262 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0797ms total)
+T0964 001:262 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000F (0000ms, 0797ms total)
+T0964 001:262 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0799ms total)
+T0964 001:264 JLINK_IsHalted() returns FALSE (0001ms, 0800ms total)
+T0964 001:267 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:269 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:271 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:273 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:275 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:277 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:279 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:283 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:285 JLINK_IsHalted() returns FALSE (0000ms, 0799ms total)
+T0964 001:287 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0802ms total)
+T0964 001:290 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0799ms total)
+T0964 001:290 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 0799ms total)
+T0964 001:290 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R0, 0x08001C00) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0799ms total)
+T0964 001:291 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 0799ms total)
+T0964 001:291 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0801ms total)
+T0964 001:293 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0804ms total)
+T0964 001:296 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0801ms total)
+T0964 001:296 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 0801ms total)
+T0964 001:296 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0801ms total)
+T0964 001:296 JLINK_WriteReg(R0, 0x08001C00) returns 0x00 (0000ms, 0801ms total)
+T0964 001:296 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0801ms total)
+T0964 001:296 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0801ms total)
+T0964 001:296 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0802ms total)
+T0964 001:297 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000011 (0000ms, 0802ms total)
+T0964 001:297 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0804ms total)
+T0964 001:299 JLINK_IsHalted() returns FALSE (0001ms, 0805ms total)
+T0964 001:302 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:304 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:306 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:308 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:310 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:312 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:314 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:316 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:318 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:320 JLINK_IsHalted() returns FALSE (0000ms, 0804ms total)
+T0964 001:322 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0806ms total)
+T0964 001:324 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0804ms total)
+T0964 001:324 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 0804ms total)
+T0964 001:324 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0804ms total)
+T0964 001:325 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0805ms total)
+T0964 001:326 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 0805ms total)
+T0964 001:326 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0806ms total)
+T0964 001:328 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0809ms total)
+T0964 001:330 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0807ms total)
+T0964 001:330 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 0807ms total)
+T0964 001:330 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0807ms total)
+T0964 001:330 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0807ms total)
+T0964 001:330 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0807ms total)
+T0964 001:330 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0807ms total)
+T0964 001:330 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0808ms total)
+T0964 001:331 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 0808ms total)
+T0964 001:331 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0810ms total)
+T0964 001:333 JLINK_IsHalted() returns FALSE (0001ms, 0811ms total)
+T0964 001:336 JLINK_IsHalted() returns FALSE (0000ms, 0810ms total)
+T0964 001:338 JLINK_IsHalted() returns FALSE (0000ms, 0810ms total)
+T0964 001:340 JLINK_IsHalted() returns FALSE (0000ms, 0810ms total)
+T0964 001:342 JLINK_IsHalted() returns FALSE (0000ms, 0810ms total)
+T0964 001:358 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0813ms total)
+T0964 001:361 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0810ms total)
+T0964 001:361 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 0810ms total)
+T0964 001:361 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R0, 0x08002400) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0810ms total)
+T0964 001:362 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0810ms total)
+T0964 001:363 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000014 (0000ms, 0811ms total)
+T0964 001:363 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0813ms total)
+T0964 001:365 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0816ms total)
+T0964 001:368 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0813ms total)
+T0964 001:368 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R0, 0x08002400) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0813ms total)
+T0964 001:368 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0813ms total)
+T0964 001:369 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0814ms total)
+T0964 001:369 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 0814ms total)
+T0964 001:369 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0816ms total)
+T0964 001:371 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:376 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:378 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:380 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:382 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:384 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:386 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:388 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:390 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:392 JLINK_IsHalted() returns FALSE (0000ms, 0816ms total)
+T0964 001:396 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0819ms total)
+T0964 001:399 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0816ms total)
+T0964 001:399 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 0816ms total)
+T0964 001:399 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0816ms total)
+T0964 001:399 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0001ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0817ms total)
+T0964 001:400 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 0817ms total)
+T0964 001:400 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0819ms total)
+T0964 001:402 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0822ms total)
+T0964 001:405 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0819ms total)
+T0964 001:405 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0819ms total)
+T0964 001:405 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0820ms total)
+T0964 001:406 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000017 (0000ms, 0820ms total)
+T0964 001:406 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0822ms total)
+T0964 001:408 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:410 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:412 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:414 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:416 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:418 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:420 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:422 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:424 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:426 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:428 JLINK_IsHalted() returns FALSE (0000ms, 0822ms total)
+T0964 001:430 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0824ms total)
+T0964 001:432 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0822ms total)
+T0964 001:432 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 0822ms total)
+T0964 001:432 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R0, 0x08002C00) returns 0x00 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0822ms total)
+T0964 001:433 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0823ms total)
+T0964 001:434 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 0823ms total)
+T0964 001:434 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0825ms total)
+T0964 001:436 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0827ms total)
+T0964 001:438 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0826ms total)
+T0964 001:439 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R0, 0x08002C00) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0826ms total)
+T0964 001:439 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 0826ms total)
+T0964 001:439 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0828ms total)
+T0964 001:442 JLINK_IsHalted() returns FALSE (0000ms, 0828ms total)
+T0964 001:444 JLINK_IsHalted() returns FALSE (0000ms, 0828ms total)
+T0964 001:446 JLINK_IsHalted() returns FALSE (0000ms, 0828ms total)
+T0964 001:448 JLINK_IsHalted() returns FALSE (0000ms, 0828ms total)
+T0964 001:450 JLINK_IsHalted() returns FALSE (0000ms, 0828ms total)
+T0964 001:467 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0831ms total)
+T0964 001:470 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0828ms total)
+T0964 001:470 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 0828ms total)
+T0964 001:470 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0828ms total)
+T0964 001:471 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001A (0000ms, 0828ms total)
+T0964 001:471 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0831ms total)
+T0964 001:474 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0834ms total)
+T0964 001:477 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0831ms total)
+T0964 001:477 JLINK_ClrBPEx(BPHandle = 0x0000001A) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0831ms total)
+T0964 001:477 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0832ms total)
+T0964 001:478 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0832ms total)
+T0964 001:478 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0832ms total)
+T0964 001:478 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0832ms total)
+T0964 001:478 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001B (0000ms, 0832ms total)
+T0964 001:478 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0834ms total)
+T0964 001:480 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:484 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:486 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:488 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:490 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:492 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:494 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:496 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:498 JLINK_IsHalted() returns FALSE (0000ms, 0834ms total)
+T0964 001:502 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0837ms total)
+T0964 001:505 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0834ms total)
+T0964 001:505 JLINK_ClrBPEx(BPHandle = 0x0000001B) returns 0x00 (0000ms, 0834ms total)
+T0964 001:505 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0834ms total)
+T0964 001:505 JLINK_WriteReg(R0, 0x08003400) returns 0x00 (0000ms, 0834ms total)
+T0964 001:505 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0835ms total)
+T0964 001:506 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001C (0000ms, 0835ms total)
+T0964 001:506 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0837ms total)
+T0964 001:508 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0840ms total)
+T0964 001:511 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0837ms total)
+T0964 001:511 JLINK_ClrBPEx(BPHandle = 0x0000001C) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R0, 0x08003400) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0837ms total)
+T0964 001:511 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0001ms, 0838ms total)
+T0964 001:512 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0838ms total)
+T0964 001:512 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0838ms total)
+T0964 001:512 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0838ms total)
+T0964 001:512 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0838ms total)
+T0964 001:512 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0838ms total)
+T0964 001:512 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0838ms total)
+T0964 001:512 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001D (0000ms, 0838ms total)
+T0964 001:512 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0840ms total)
+T0964 001:514 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:516 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:518 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:520 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:522 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:524 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:526 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:528 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:530 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:532 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:534 JLINK_IsHalted() returns FALSE (0000ms, 0840ms total)
+T0964 001:536 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0842ms total)
+T0964 001:538 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0840ms total)
+T0964 001:538 JLINK_ClrBPEx(BPHandle = 0x0000001D) returns 0x00 (0000ms, 0840ms total)
+T0964 001:539 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0841ms total)
+T0964 001:539 JLINK_WriteReg(R0, 0x08003800) returns 0x00 (0000ms, 0841ms total)
+T0964 001:539 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0841ms total)
+T0964 001:539 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0841ms total)
+T0964 001:539 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0842ms total)
+T0964 001:540 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001E (0000ms, 0842ms total)
+T0964 001:540 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0844ms total)
+T0964 001:542 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0847ms total)
+T0964 001:545 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0844ms total)
+T0964 001:545 JLINK_ClrBPEx(BPHandle = 0x0000001E) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R0, 0x08003800) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0844ms total)
+T0964 001:545 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0001ms, 0845ms total)
+T0964 001:546 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0845ms total)
+T0964 001:546 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0845ms total)
+T0964 001:546 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0845ms total)
+T0964 001:546 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0845ms total)
+T0964 001:546 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0845ms total)
+T0964 001:546 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0845ms total)
+T0964 001:546 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001F (0000ms, 0845ms total)
+T0964 001:546 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0847ms total)
+T0964 001:548 JLINK_IsHalted() returns FALSE (0001ms, 0848ms total)
+T0964 001:552 JLINK_IsHalted() returns FALSE (0000ms, 0847ms total)
+T0964 001:554 JLINK_IsHalted() returns FALSE (0000ms, 0847ms total)
+T0964 001:556 JLINK_IsHalted() returns FALSE (0000ms, 0847ms total)
+T0964 001:558 JLINK_IsHalted() returns FALSE (0000ms, 0847ms total)
+T0964 001:560 JLINK_IsHalted() returns FALSE (0000ms, 0847ms total)
+T0964 001:562 JLINK_IsHalted() returns FALSE (0000ms, 0847ms total)
+T0964 001:564 JLINK_IsHalted() returns FALSE (0000ms, 0847ms total)
+T0964 001:580 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0850ms total)
+T0964 001:583 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0847ms total)
+T0964 001:583 JLINK_ClrBPEx(BPHandle = 0x0000001F) returns 0x00 (0000ms, 0847ms total)
+T0964 001:583 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0847ms total)
+T0964 001:583 JLINK_WriteReg(R0, 0x00000001) returns 0x00 (0000ms, 0847ms total)
+T0964 001:583 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0847ms total)
+T0964 001:583 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0847ms total)
+T0964 001:583 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:583 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0847ms total)
+T0964 001:584 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000020 (0000ms, 0847ms total)
+T0964 001:584 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0850ms total)
+T0964 001:587 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0852ms total)
+T0964 001:589 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0850ms total)
+T0964 001:589 JLINK_ClrBPEx(BPHandle = 0x00000020) returns 0x00 (0000ms, 0850ms total)
+T0964 001:589 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 0851ms total)
+T0964 001:651 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0002ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R1, 0x007A1200) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R2, 0x00000002) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0853ms total)
+T0964 001:653 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0853ms total)
+T0964 001:654 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0854ms total)
+T0964 001:654 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000021 (0000ms, 0854ms total)
+T0964 001:654 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0857ms total)
+T0964 001:657 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0860ms total)
+T0964 001:660 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0857ms total)
+T0964 001:660 JLINK_ClrBPEx(BPHandle = 0x00000021) returns 0x00 (0000ms, 0857ms total)
+T0964 001:660 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0857ms total)
+T0964 001:661 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: A8 06 00 20 01 1D 00 08 09 1D 00 08 0B 1D 00 08 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0861ms total)
+T0964 001:665 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000022 (0000ms, 0861ms total)
+T0964 001:665 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0864ms total)
+T0964 001:668 JLINK_IsHalted() returns FALSE (0000ms, 0864ms total)
+T0964 001:676 JLINK_IsHalted() returns FALSE (0000ms, 0864ms total)
+T0964 001:696 JLINK_IsHalted() returns FALSE (0000ms, 0864ms total)
+T0964 001:699 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0867ms total)
+T0964 001:702 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0864ms total)
+T0964 001:702 JLINK_ClrBPEx(BPHandle = 0x00000022) returns 0x00 (0000ms, 0864ms total)
+T0964 001:702 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0864ms total)
+T0964 001:703 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 00 F0 67 F9 F0 1B C6 B2 15 E7 00 00 18 00 00 20 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0868ms total)
+T0964 001:707 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000023 (0001ms, 0869ms total)
+T0964 001:708 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0871ms total)
+T0964 001:710 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:712 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:714 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:716 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:718 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:720 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:726 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:728 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:730 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:732 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:734 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:736 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:738 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:740 JLINK_IsHalted() returns FALSE (0000ms, 0871ms total)
+T0964 001:742 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0874ms total)
+T0964 001:745 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0871ms total)
+T0964 001:745 JLINK_ClrBPEx(BPHandle = 0x00000023) returns 0x00 (0000ms, 0871ms total)
+T0964 001:745 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0871ms total)
+T0964 001:746 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 00 25 5F E0 1D 48 00 88 40 1E A0 42 04 DB 1B 48 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0875ms total)
+T0964 001:750 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000024 (0000ms, 0875ms total)
+T0964 001:750 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0878ms total)
+T0964 001:753 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:755 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:757 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:759 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:761 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:763 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:768 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:770 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:772 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:774 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:776 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:778 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:780 JLINK_IsHalted() returns FALSE (0000ms, 0878ms total)
+T0964 001:796 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0881ms total)
+T0964 001:799 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0878ms total)
+T0964 001:799 JLINK_ClrBPEx(BPHandle = 0x00000024) returns 0x00 (0000ms, 0878ms total)
+T0964 001:799 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0878ms total)
+T0964 001:800 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: FC 5F 05 46 88 46 91 46 9A 46 DD F8 30 B0 00 95 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0882ms total)
+T0964 001:804 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000025 (0000ms, 0882ms total)
+T0964 001:804 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0885ms total)
+T0964 001:807 JLINK_IsHalted() returns FALSE (0001ms, 0886ms total)
+T0964 001:810 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:812 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:814 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:816 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:818 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:820 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:822 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:824 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:826 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:828 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:830 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:832 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:836 JLINK_IsHalted() returns FALSE (0000ms, 0885ms total)
+T0964 001:838 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0887ms total)
+T0964 001:840 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0886ms total)
+T0964 001:841 JLINK_ClrBPEx(BPHandle = 0x00000025) returns 0x00 (0000ms, 0886ms total)
+T0964 001:841 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0886ms total)
+T0964 001:841 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: E8 10 48 60 08 46 00 68 40 F0 80 70 08 60 00 BF ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0890ms total)
+T0964 001:845 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0001ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0891ms total)
+T0964 001:846 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000026 (0001ms, 0892ms total)
+T0964 001:847 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0894ms total)
+T0964 001:849 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:851 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:853 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:855 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:857 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:859 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:863 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:865 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:867 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:869 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:871 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:873 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:875 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:877 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:879 JLINK_IsHalted() returns FALSE (0000ms, 0894ms total)
+T0964 001:881 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0896ms total)
+T0964 001:884 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0894ms total)
+T0964 001:884 JLINK_ClrBPEx(BPHandle = 0x00000026) returns 0x00 (0000ms, 0894ms total)
+T0964 001:884 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0894ms total)
+T0964 001:885 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 00 F0 9E FC 10 BD 00 00 80 FF FF 1F 08 ED 00 E0 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0898ms total)
+T0964 001:889 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000027 (0000ms, 0898ms total)
+T0964 001:889 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0900ms total)
+T0964 001:891 JLINK_IsHalted() returns FALSE (0001ms, 0901ms total)
+T0964 001:894 JLINK_IsHalted() returns FALSE (0000ms, 0900ms total)
+T0964 001:910 JLINK_IsHalted() returns FALSE (0000ms, 0900ms total)
+T0964 001:912 JLINK_IsHalted() returns FALSE (0000ms, 0900ms total)
+T0964 001:914 JLINK_IsHalted() returns FALSE (0000ms, 0900ms total)
+T0964 001:916 JLINK_IsHalted() returns FALSE (0000ms, 0900ms total)
+T0964 001:918 JLINK_IsHalted() returns FALSE (0000ms, 0900ms total)
+T0964 001:920 JLINK_IsHalted() returns FALSE (0000ms, 0900ms total)
+T0964 001:922 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0904ms total)
+T0964 001:926 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0900ms total)
+T0964 001:926 JLINK_ClrBPEx(BPHandle = 0x00000027) returns 0x00 (0000ms, 0900ms total)
+T0964 001:926 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0900ms total)
+T0964 001:927 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: DA FE 8A 20 FF F7 EA FE EE 20 FF F7 E7 FE C5 20 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0904ms total)
+T0964 001:931 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0905ms total)
+T0964 001:932 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0905ms total)
+T0964 001:932 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0905ms total)
+T0964 001:932 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0905ms total)
+T0964 001:932 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000028 (0000ms, 0905ms total)
+T0964 001:932 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0907ms total)
+T0964 001:934 JLINK_IsHalted() returns FALSE (0001ms, 0908ms total)
+T0964 001:937 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:941 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:943 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:945 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:947 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:949 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:951 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:953 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:955 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:957 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:959 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:961 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:963 JLINK_IsHalted() returns FALSE (0000ms, 0907ms total)
+T0964 001:965 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0910ms total)
+T0964 001:968 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0907ms total)
+T0964 001:968 JLINK_ClrBPEx(BPHandle = 0x00000028) returns 0x00 (0000ms, 0907ms total)
+T0964 001:968 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0907ms total)
+T0964 001:969 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 68 46 00 F0 1F FE 17 20 8D F8 08 00 01 20 8D F8 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R0, 0x08001C00) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0911ms total)
+T0964 001:973 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000029 (0000ms, 0911ms total)
+T0964 001:973 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0914ms total)
+T0964 001:976 JLINK_IsHalted() returns FALSE (0001ms, 0915ms total)
+T0964 001:980 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:982 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:984 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:986 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:988 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:990 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:992 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:994 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:996 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 001:998 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 002:000 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 002:002 JLINK_IsHalted() returns FALSE (0000ms, 0914ms total)
+T0964 002:018 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0917ms total)
+T0964 002:021 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0914ms total)
+T0964 002:021 JLINK_ClrBPEx(BPHandle = 0x00000029) returns 0x00 (0000ms, 0914ms total)
+T0964 002:021 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0914ms total)
+T0964 002:022 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 70 47 02 46 00 20 93 68 0B 40 0B B1 01 20 00 E0 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0918ms total)
+T0964 002:026 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0918ms total)
+T0964 002:027 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0919ms total)
+T0964 002:027 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0919ms total)
+T0964 002:027 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0919ms total)
+T0964 002:027 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002A (0000ms, 0919ms total)
+T0964 002:027 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0921ms total)
+T0964 002:029 JLINK_IsHalted() returns FALSE (0001ms, 0922ms total)
+T0964 002:032 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:034 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:036 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:038 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:040 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:042 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:044 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:046 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:048 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:050 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:055 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:057 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:059 JLINK_IsHalted() returns FALSE (0000ms, 0921ms total)
+T0964 002:061 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0924ms total)
+T0964 002:064 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0921ms total)
+T0964 002:064 JLINK_ClrBPEx(BPHandle = 0x0000002A) returns 0x00 (0000ms, 0921ms total)
+T0964 002:064 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0921ms total)
+T0964 002:064 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: E0 61 09 0A 43 4D 6B 5C 45 68 DD 40 85 60 3A 4D ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0005ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R0, 0x08002400) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0926ms total)
+T0964 002:069 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002B (0000ms, 0926ms total)
+T0964 002:069 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0929ms total)
+T0964 002:072 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:076 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:078 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:080 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:082 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:083 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:085 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:087 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:089 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:091 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:093 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:095 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:097 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:099 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:101 JLINK_IsHalted() returns FALSE (0000ms, 0929ms total)
+T0964 002:103 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0932ms total)
+T0964 002:106 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0929ms total)
+T0964 002:106 JLINK_ClrBPEx(BPHandle = 0x0000002B) returns 0x00 (0000ms, 0929ms total)
+T0964 002:106 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0929ms total)
+T0964 002:107 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 00 E0 00 20 F0 BD 10 B5 00 22 01 F0 0F 04 01 23 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0933ms total)
+T0964 002:111 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0001ms, 0934ms total)
+T0964 002:112 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0934ms total)
+T0964 002:112 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002C (0000ms, 0934ms total)
+T0964 002:112 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0936ms total)
+T0964 002:114 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:130 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:133 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:135 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:137 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:139 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:141 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:144 JLINK_IsHalted() returns FALSE (0000ms, 0936ms total)
+T0964 002:146 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0939ms total)
+T0964 002:149 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0936ms total)
+T0964 002:149 JLINK_ClrBPEx(BPHandle = 0x0000002C) returns 0x00 (0000ms, 0936ms total)
+T0964 002:149 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0936ms total)
+T0964 002:150 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 37 12 0A 06 0A 0A 12 37 00 00 00 00 07 02 02 02 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0005ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R0, 0x08002C00) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0941ms total)
+T0964 002:155 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002D (0000ms, 0941ms total)
+T0964 002:155 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0943ms total)
+T0964 002:157 JLINK_IsHalted() returns FALSE (0001ms, 0944ms total)
+T0964 002:162 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:163 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:165 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:167 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:169 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:171 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:173 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:175 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:177 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:179 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:181 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:183 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:185 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:187 JLINK_IsHalted() returns FALSE (0000ms, 0943ms total)
+T0964 002:189 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0945ms total)
+T0964 002:191 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0943ms total)
+T0964 002:192 JLINK_ClrBPEx(BPHandle = 0x0000002D) returns 0x00 (0000ms, 0944ms total)
+T0964 002:192 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0944ms total)
+T0964 002:193 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 00 18 24 42 42 42 64 58 40 40 24 1C 00 00 00 00 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0948ms total)
+T0964 002:197 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002E (0000ms, 0948ms total)
+T0964 002:197 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0950ms total)
+T0964 002:199 JLINK_IsHalted() returns FALSE (0001ms, 0951ms total)
+T0964 002:202 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:204 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:206 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:208 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:210 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:212 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:214 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:216 JLINK_IsHalted() returns FALSE (0000ms, 0950ms total)
+T0964 002:237 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0953ms total)
+T0964 002:240 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0950ms total)
+T0964 002:240 JLINK_ClrBPEx(BPHandle = 0x0000002E) returns 0x00 (0000ms, 0950ms total)
+T0964 002:240 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0950ms total)
+T0964 002:241 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: 00 00 00 00 00 E7 42 24 24 14 18 08 08 07 00 00 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R0, 0x08003400) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0954ms total)
+T0964 002:246 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0955ms total)
+T0964 002:247 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0955ms total)
+T0964 002:247 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0955ms total)
+T0964 002:247 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0955ms total)
+T0964 002:247 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002F (0000ms, 0955ms total)
+T0964 002:247 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0957ms total)
+T0964 002:249 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:251 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:253 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:255 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:257 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:259 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:261 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:264 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:266 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:270 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:272 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:275 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:277 JLINK_IsHalted() returns FALSE (0000ms, 0957ms total)
+T0964 002:280 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0959ms total)
+T0964 002:282 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0957ms total)
+T0964 002:283 JLINK_ClrBPEx(BPHandle = 0x0000002F) returns 0x00 (0000ms, 0958ms total)
+T0964 002:283 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0958ms total)
+T0964 002:284 JLINK_WriteMem(0x20000164, 0x0400 Bytes, ...) - Data: F0 08 10 20 08 10 20 08 10 20 08 10 20 0F FF E0 ... -- CPU_WriteMem(1024 bytes @ 0x20000164) returns 0x400 (0004ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R0, 0x08003800) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R1, 0x0000035C) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0962ms total)
+T0964 002:288 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0001ms, 0963ms total)
+T0964 002:289 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0963ms total)
+T0964 002:289 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0963ms total)
+T0964 002:289 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000030 (0000ms, 0963ms total)
+T0964 002:289 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0965ms total)
+T0964 002:291 JLINK_IsHalted() returns FALSE (0001ms, 0966ms total)
+T0964 002:294 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:296 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:298 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:300 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:302 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:304 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:306 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:308 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:310 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:312 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:314 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:316 JLINK_IsHalted() returns FALSE (0000ms, 0965ms total)
+T0964 002:318 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0967ms total)
+T0964 002:320 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0966ms total)
+T0964 002:321 JLINK_ClrBPEx(BPHandle = 0x00000030) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R0, 0x00000002) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R1, 0x0000035C) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0966ms total)
+T0964 002:321 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000031 (0000ms, 0966ms total)
+T0964 002:321 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0968ms total)
+T0964 002:323 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0971ms total)
+T0964 002:326 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0968ms total)
+T0964 002:326 JLINK_ClrBPEx(BPHandle = 0x00000031) returns 0x00 (0000ms, 0968ms total)
+T0964 002:327 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0969ms total)
+T0964 002:388 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0002ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R1, 0x007A1200) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R2, 0x00000003) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0971ms total)
+T0964 002:390 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0972ms total)
+T0964 002:391 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0972ms total)
+T0964 002:391 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0972ms total)
+T0964 002:391 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0972ms total)
+T0964 002:391 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000032 (0000ms, 0972ms total)
+T0964 002:392 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0976ms total)
+T0964 002:395 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0979ms total)
+T0964 002:398 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0976ms total)
+T0964 002:398 JLINK_ClrBPEx(BPHandle = 0x00000032) returns 0x00 (0001ms, 0977ms total)
+T0964 002:399 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R0, 0xFFFFFFFF) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R2, 0x00003B5C) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:399 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0977ms total)
+T0964 002:400 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0978ms total)
+T0964 002:400 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0978ms total)
+T0964 002:400 JLINK_WriteReg(R15 (PC), 0x20000002) returns 0x00 (0000ms, 0978ms total)
+T0964 002:400 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0978ms total)
+T0964 002:400 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0978ms total)
+T0964 002:400 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0978ms total)
+T0964 002:400 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0978ms total)
+T0964 002:400 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000033 (0000ms, 0978ms total)
+T0964 002:400 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0981ms total)
+T0964 002:403 JLINK_IsHalted() returns FALSE (0001ms, 0982ms total)
+T0964 002:438 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:459 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:461 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:463 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:465 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:467 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:469 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:471 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:475 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:477 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:479 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:481 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:483 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:485 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:489 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:491 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:493 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:495 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:497 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:499 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:501 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:503 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:505 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:507 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:509 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:511 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:513 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:515 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:520 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:522 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:524 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:526 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:528 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:530 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:532 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:534 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:536 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:538 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:540 JLINK_IsHalted() returns FALSE (0004ms, 0985ms total)
+T0964 002:546 JLINK_IsHalted() returns FALSE (0000ms, 0981ms total)
+T0964 002:572 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0984ms total)
+T0964 002:575 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0981ms total)
+T0964 002:575 JLINK_ClrBPEx(BPHandle = 0x00000033) returns 0x00 (0000ms, 0981ms total)
+T0964 002:575 JLINK_ReadReg(R0) returns 0x40CF7682 (0000ms, 0981ms total)
+T0964 002:576 JLINK_WriteReg(R0, 0x00000003) returns 0x00 (0000ms, 0981ms total)
+T0964 002:576 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 0981ms total)
+T0964 002:576 JLINK_WriteReg(R2, 0x00003B5C) returns 0x00 (0000ms, 0981ms total)
+T0964 002:576 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0001ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0982ms total)
+T0964 002:577 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000034 (0000ms, 0982ms total)
+T0964 002:577 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0984ms total)
+T0964 002:579 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0987ms total)
+T0964 002:582 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0984ms total)
+T0964 002:582 JLINK_ClrBPEx(BPHandle = 0x00000034) returns 0x00 (0000ms, 0984ms total)
+T0964 002:582 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0984ms total)
+T0964 002:645 JLINK_WriteMem(0x20000000, 0x0002 Bytes, ...) - Data: FE E7 -- CPU_WriteMem(2 bytes @ 0x20000000) returns 0x02 (0001ms, 0985ms total)
+T0964 002:647 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) returns JLINKARM_CM3_RESET_TYPE_NORMAL (0000ms, 0986ms total)
+T0964 002:647 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.SYSRESETREQ. -- CPU_WriteMem(4 bytes @ 0xE000ED0C) >0x0D TIF> >0x28 TIF> -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000)
+ -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0101ms, 1087ms total)
+T0964 002:748 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0004ms, 1091ms total)
+T0964 002:796 JLINK_Close() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000201C) >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF>
+ >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> (0022ms, 1113ms total)
+T0964 002:796 (0022ms, 1113ms total)
+T0964 002:796 Closed (0022ms, 1113ms total)
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLinkSettings.ini" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLinkSettings.ini"
new file mode 100644
index 0000000..5516360
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/JLinkSettings.ini"
@@ -0,0 +1,17 @@
+[FLASH]
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="ADUC7020X62"
+[BREAKPOINTS]
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[SWO]
+SWOLogFile=""
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui.Administrator" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui.Administrator"
new file mode 100644
index 0000000..eb4a9f7
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui.Administrator"
@@ -0,0 +1,1405 @@
+
+
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+ -5.1
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diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui.Ping" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui.Ping"
new file mode 100644
index 0000000..10ea885
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui.Ping"
@@ -0,0 +1,2657 @@
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diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui_Ping.bak" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvgui_Ping.bak"
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diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvopt" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvopt"
new file mode 100644
index 0000000..9b1bf2c
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvopt"
@@ -0,0 +1,442 @@
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+ ### uVision Project, (C) Keil Software
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+ HARDWARE
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+ lcd.c
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+ KEYPAD4x4.c
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+ NVIC.c
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+ stm32f10x_spi.c
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+
+ 4
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+ ..\STM32F10x_FWLib\src\stm32f10x_usart.c
+ stm32f10x_usart.c
+ 0
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+
+
+ 4
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+ 1
+ 0
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+ ..\STM32F10x_FWLib\src\stm32f10x_exti.c
+ stm32f10x_exti.c
+ 0
+ 0
+
+
+
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvproj" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvproj"
new file mode 100644
index 0000000..9ea03fd
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo.uvproj"
@@ -0,0 +1,492 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ Target 1
+ 0x4
+ ARM-ADS
+ 5060061::V5.06 update 1 (build 61)::ARMCC
+
+
+ STM32F103RB
+ STMicroelectronics
+ IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")
+
+ "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")
+ UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000)
+ 4231
+ stm32f10x_lib.h
+
+
+
+
+
+
+
+
+
+
+ 0
+ 0
+
+
+
+ ST\STM32F10x\
+ ST\STM32F10x\
+
+ 0
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+ 0
+ 0
+ 1
+
+ ..\OBJ\
+ TOUCH
+ 1
+ 0
+ 1
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+ 1
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+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+
+ DARMSTM.DLL
+ -pSTM32F103RB
+ SARMCM3.DLL
+
+ TARMSTM.DLL
+ -pSTM32F103RB
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+
+
+ 1
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+ 4099
+
+ 1
+ Segger\JL2CM3.dll
+ "" ()
+
+
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+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+
+
+ STM32F10X_MD,USE_STDPERIPH_DRIVER
+
+ ..\HARDWARE\LED;..\SYSTEM\delay;..\SYSTEM\sys;..\SYSTEM\usart;..\USER;..\STM32F10x_FWLib\inc;..\CORE;..\HARDWARE\KEY;..\HARDWARE\EXTI;..\HARDWARE\WDG;..\HARDWARE\TIMER;..\HARDWARE\PWM;..\HARDWARE\LCD;..\HARDWARE\WKUP;..\HARDWARE\ADC;..\HARDWARE\TSensor;..\HARDWARE\IIC;..\HARDWARE\24CXX;..\HARDWARE\SPI;..\HARDWARE\FLASH;..\HARDWARE\TOUCH;..\HARDWARE\KEYPAD4x4;..\SYSTEM\nvic
+
+
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+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ USER
+
+
+ main.c
+ 1
+ .\main.c
+
+
+ GUI.c
+ 1
+ .\GUI.c
+
+
+ delay.c
+ 1
+ ..\SYSTEM\delay\delay.c
+
+
+ system_stm32f10x.c
+ 1
+ .\system_stm32f10x.c
+
+
+ sys.c
+ 1
+ ..\SYSTEM\sys\sys.c
+
+
+
+
+ HARDWARE
+
+
+ key.c
+ 1
+ ..\HARDWARE\KEY\key.c
+
+
+ lcd.c
+ 1
+ ..\HARDWARE\LCD\lcd.c
+
+
+ myiic.c
+ 1
+ ..\HARDWARE\IIC\myiic.c
+
+
+ 24cxx.c
+ 1
+ ..\HARDWARE\24CXX\24cxx.c
+
+
+ KEYPAD4x4.c
+ 1
+ ..\HARDWARE\KEYPAD4x4\KEYPAD4x4.c
+
+
+ NVIC.c
+ 1
+ ..\SYSTEM\nvic\NVIC.c
+
+
+
+
+ CORE
+
+
+ core_cm3.c
+ 1
+ ..\CORE\core_cm3.c
+
+
+ startup_stm32f10x_md.s
+ 2
+ ..\CORE\startup_stm32f10x_md.s
+
+
+
+
+ FWLib
+
+
+ misc.c
+ 1
+ ..\STM32F10x_FWLib\src\misc.c
+
+
+ stm32f10x_gpio.c
+ 1
+ ..\STM32F10x_FWLib\src\stm32f10x_gpio.c
+
+
+ stm32f10x_rcc.c
+ 1
+ ..\STM32F10x_FWLib\src\stm32f10x_rcc.c
+
+
+ stm32f10x_spi.c
+ 1
+ ..\STM32F10x_FWLib\src\stm32f10x_spi.c
+
+
+ stm32f10x_usart.c
+ 1
+ ..\STM32F10x_FWLib\src\stm32f10x_usart.c
+
+
+ stm32f10x_exti.c
+ 1
+ ..\STM32F10x_FWLib\src\stm32f10x_exti.c
+
+
+
+
+
+
+
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo_Target 1.dep" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo_Target 1.dep"
new file mode 100644
index 0000000..75d7170
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TFT_Demo_Target 1.dep"
@@ -0,0 +1,412 @@
+Dependencies for Project 'TFT_Demo', Target 'Target 1': (DO NOT MODIFY !)
+F (.\main.c)(0x55C08BFF)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\EXTI -I..\HARDWARE\WDG -I..\HARDWARE\TIMER -I..\HARDWARE\PWM -I..\HARDWARE\LCD -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\TSensor -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\TOUCH
-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o main.o --omf_browse main.crf --depend main.d)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\SYSTEM\delay\delay.h)(0x5462DF52)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\USER\stm32f10x.h)(0x5462DF55)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\CORE\core_cm3.h)(0x5462DF2F)
+I (C:\Keil\ARM\ARMCC\include\stdint.h)(0x51C7B744)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\USER\system_stm32f10x.h)(0x5462DF55)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\USER\stm32f10x_conf.h)(0x5462DF55)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_adc.h)(0x5462DF48)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_bkp.h)(0x5462DF48)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x5462DF48)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_cec.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_crc.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_dac.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_dma.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_exti.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_flash.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_fsmc.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_i2c.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_rtc.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_sdio.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_spi.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_tim.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_usart.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_wwdg.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\misc.h)(0x5462DF48)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\SYSTEM\sys\sys.h)(0x5462DF53)
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+I (C:\Keil\ARM\ARMCC\include\stdlib.h)(0x51C7B744)
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-I C:\Keil\ARM\Inc\ST\STM32F10x
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-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o ..\obj\key.o --omf_browse ..\obj\key.crf --depend ..\obj\key.d)
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-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o ..\obj\core_cm3.o --omf_browse ..\obj\core_cm3.crf --depend ..\obj\core_cm3.d)
+I (C:\Keil\ARM\ARMCC\include\stdint.h)(0x51C7B744)
+F (..\CORE\startup_stm32f10x_md.s)(0x5462DF2F)(--cpu Cortex-M3 -g --apcs=interwork
-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
--list .\startup_stm32f10x_md.lst --xref -o ..\obj\startup_stm32f10x_md.o --depend ..\obj\startup_stm32f10x_md.d)
+F (..\STM32F10x_FWLib\src\misc.c)(0x5462DF4D)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\EXTI -I..\HARDWARE\WDG -I..\HARDWARE\TIMER -I..\HARDWARE\PWM -I..\HARDWARE\LCD -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\TSensor -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\TOUCH
-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o ..\obj\misc.o --omf_browse ..\obj\misc.crf --depend ..\obj\misc.d)
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+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_rtc.h)(0x5462DF4B)
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+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_spi.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_tim.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_usart.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_wwdg.h)(0x5462DF4D)
+F (..\STM32F10x_FWLib\src\stm32f10x_gpio.c)(0x5462DF50)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\EXTI -I..\HARDWARE\WDG -I..\HARDWARE\TIMER -I..\HARDWARE\PWM -I..\HARDWARE\LCD -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\TSensor -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\TOUCH
-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o ..\obj\stm32f10x_gpio.o --omf_browse ..\obj\stm32f10x_gpio.crf --depend ..\obj\stm32f10x_gpio.d)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x5462DF4A)
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+I (C:\Keil\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o ..\obj\stm32f10x_rcc.o --omf_browse ..\obj\stm32f10x_rcc.crf --depend ..\obj\stm32f10x_rcc.d)
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+I (C:\Keil\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o ..\obj\stm32f10x_spi.o --omf_browse ..\obj\stm32f10x_spi.crf --depend ..\obj\stm32f10x_spi.d)
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+I (C:\Keil\ARM\ARMCC\include\stdint.h)(0x51C7B744)
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+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_dma.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_exti.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_flash.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_fsmc.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_i2c.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_rtc.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_sdio.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_tim.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_usart.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_wwdg.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\misc.h)(0x5462DF48)
+F (..\STM32F10x_FWLib\src\stm32f10x_usart.c)(0x5462DF52)(-c --cpu Cortex-M3 -g -O0 --apcs=interwork -I..\HARDWARE\LED -I..\SYSTEM\delay -I..\SYSTEM\sys -I..\SYSTEM\usart -I..\USER -I..\STM32F10x_FWLib\inc -I..\CORE -I..\HARDWARE\KEY -I..\HARDWARE\EXTI -I..\HARDWARE\WDG -I..\HARDWARE\TIMER -I..\HARDWARE\PWM -I..\HARDWARE\LCD -I..\HARDWARE\WKUP -I..\HARDWARE\ADC -I..\HARDWARE\TSensor -I..\HARDWARE\IIC -I..\HARDWARE\24CXX -I..\HARDWARE\SPI -I..\HARDWARE\FLASH -I..\HARDWARE\TOUCH
-I C:\Keil\ARM\RV31\INC
-I C:\Keil\ARM\CMSIS\Include
-I C:\Keil\ARM\Inc\ST\STM32F10x
-DSTM32F10X_MD -DUSE_STDPERIPH_DRIVER -o ..\obj\stm32f10x_usart.o --omf_browse ..\obj\stm32f10x_usart.crf --depend ..\obj\stm32f10x_usart.d)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_usart.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\USER\stm32f10x.h)(0x5462DF55)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\CORE\core_cm3.h)(0x5462DF2F)
+I (C:\Keil\ARM\ARMCC\include\stdint.h)(0x51C7B744)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\USER\system_stm32f10x.h)(0x5462DF55)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\USER\stm32f10x_conf.h)(0x5462DF55)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_adc.h)(0x5462DF48)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_bkp.h)(0x5462DF48)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_can.h)(0x5462DF48)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_cec.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_crc.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_dac.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_dma.h)(0x5462DF49)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_exti.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_flash.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_fsmc.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_gpio.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_i2c.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_iwdg.h)(0x5462DF4A)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_pwr.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_rcc.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_rtc.h)(0x5462DF4B)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_sdio.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_spi.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_tim.h)(0x5462DF4C)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\stm32f10x_wwdg.h)(0x5462DF4D)
+I (E:\完成设计的产品\(MCUDEV)-STM32开发板系列\MCUDEV_TFT_144液晶\MCUDEV_TFT_1.44液晶--客户资料\STM32 硬件SPI_中文显示测试源码\STM32F10x_FWLib\inc\misc.h)(0x5462DF48)
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TOUCH.map" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TOUCH.map"
new file mode 100644
index 0000000..8393d02
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/TOUCH.map"
@@ -0,0 +1,849 @@
+Component: ARM Compiler 5.06 update 1 (build 61) Tool: armlink [4d35a8]
+
+==============================================================================
+
+Section Cross References
+
+ main.o(.text) refers to system_stm32f10x.o(.text) for SystemInit
+ main.o(.text) refers to delay.o(.text) for delay_init
+ main.o(.text) refers to lcd.o(.text) for LCD_Init
+ main.o(.text) refers to sys.o(.text) for NVIC_Configuration
+ main.o(.text) refers to keypad4x4.o(.text) for KEYPAD4x4_Init
+ main.o(.text) refers to nvic.o(.text) for KEYPAD4x4_INT_INIT
+ main.o(.text) refers to gui.o(.text) for LCD_DrawRectangle
+ main.o(.text) refers to lcd.o(.data) for POINT_COLOR
+ main.o(.text) refers to nvic.o(.data) for INT_MARK
+ gui.o(.text) refers to lcd.o(.text) for LCD_SetCursor
+ gui.o(.text) refers to lcd.o(.bss) for lcddev
+ gui.o(.text) refers to lcd.o(.data) for POINT_COLOR
+ gui.o(.text) refers to gui.o(.constdata) for asc2_1206
+ gui.o(.text) refers to strlen.o(.text) for strlen
+ delay.o(.text) refers to misc.o(.text) for SysTick_CLKSourceConfig
+ delay.o(.text) refers to delay.o(.data) for fac_us
+ system_stm32f10x.o(.text) refers to system_stm32f10x.o(.data) for SystemCoreClock
+ sys.o(.text) refers to sys.o(.emb_text) for WFI_SET
+ sys.o(.text) refers to misc.o(.text) for NVIC_PriorityGroupConfig
+ key.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
+ key.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_PinRemapConfig
+ key.o(.text) refers to delay.o(.text) for delay_ms
+ lcd.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
+ lcd.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
+ lcd.o(.text) refers to stm32f10x_spi.o(.text) for SPI_Init
+ lcd.o(.text) refers to delay.o(.text) for delay_ms
+ lcd.o(.text) refers to lcd.o(.bss) for lcddev
+ lcd.o(.text) refers to lcd.o(.data) for POINT_COLOR
+ myiic.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
+ myiic.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
+ myiic.o(.text) refers to delay.o(.text) for delay_us
+ 24cxx.o(.text) refers to myiic.o(.text) for IIC_Init
+ 24cxx.o(.text) refers to delay.o(.text) for delay_ms
+ keypad4x4.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_Init
+ keypad4x4.o(.text) refers to delay.o(.text) for delay_ms
+ nvic.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphClockCmd
+ nvic.o(.text) refers to stm32f10x_gpio.o(.text) for GPIO_EXTILineConfig
+ nvic.o(.text) refers to stm32f10x_exti.o(.text) for EXTI_Init
+ nvic.o(.text) refers to misc.o(.text) for NVIC_Init
+ nvic.o(.text) refers to nvic.o(.data) for INT_MARK
+ startup_stm32f10x_md.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_md.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_md.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(STACK) for __initial_sp
+ startup_stm32f10x_md.o(RESET) refers to startup_stm32f10x_md.o(.text) for Reset_Handler
+ startup_stm32f10x_md.o(RESET) refers to nvic.o(.text) for EXTI4_IRQHandler
+ startup_stm32f10x_md.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_md.o(.text) refers to system_stm32f10x.o(.text) for SystemInit
+ startup_stm32f10x_md.o(.text) refers to __main.o(!!!main) for __main
+ startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(HEAP) for Heap_Mem
+ startup_stm32f10x_md.o(.text) refers to startup_stm32f10x_md.o(STACK) for Stack_Mem
+ stm32f10x_gpio.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
+ stm32f10x_rcc.o(.text) refers to stm32f10x_rcc.o(.data) for APBAHBPrescTable
+ stm32f10x_spi.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
+ stm32f10x_usart.o(.text) refers to stm32f10x_rcc.o(.text) for RCC_APB2PeriphResetCmd
+ __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh
+ __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text) for main
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D
+ __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap
+ __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004
+ sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace
+ sys_stackheap_outer.o(.text) refers to startup_stm32f10x_md.o(.text) for __user_initial_stackheap
+ exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1
+ libspace.o(.text) refers to libspace.o(.bss) for __libspace_start
+ rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+ rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+ rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+ rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+ rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+ rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+ rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000
+ libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+ libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+ rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown
+ rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit
+ rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001
+ rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003
+ rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004
+ argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv
+ sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+ sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+ _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard
+ _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM
+ _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1
+ sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+ sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+ defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+ defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
+ defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
+ rt_raise.o(.text) refers to __raise.o(.text) for __raise
+ rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit
+ defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit
+ defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler
+ defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch
+ sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+ sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+ defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+ defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+
+
+==============================================================================
+
+Removing Unused input sections from the image.
+
+ Removing key.o(.text), (188 bytes).
+ Removing myiic.o(.text), (600 bytes).
+ Removing 24cxx.o(.text), (378 bytes).
+ Removing core_cm3.o(.emb_text), (32 bytes).
+ Removing stm32f10x_usart.o(.text), (1032 bytes).
+
+5 unused section(s) (total 2230 bytes) removed from the image.
+
+==============================================================================
+
+Image Symbol Table
+
+ Local Symbols
+
+ Symbol Name Value Ov Type Size Object(Section)
+
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE
+ ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE
+ ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE
+ ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE
+ ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE
+ ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE
+ ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE
+ ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE
+ ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE
+ ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE
+ ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE
+ ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE
+ ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE
+ ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE
+ ../clib/string.c 0x00000000 Number 0 strlen.o ABSOLUTE
+ ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE
+ ..\CORE\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE
+ ..\CORE\startup_stm32f10x_md.s 0x00000000 Number 0 startup_stm32f10x_md.o ABSOLUTE
+ ..\HARDWARE\24CXX\24cxx.c 0x00000000 Number 0 24cxx.o ABSOLUTE
+ ..\HARDWARE\IIC\myiic.c 0x00000000 Number 0 myiic.o ABSOLUTE
+ ..\HARDWARE\KEYPAD4x4\KEYPAD4x4.c 0x00000000 Number 0 keypad4x4.o ABSOLUTE
+ ..\HARDWARE\KEY\key.c 0x00000000 Number 0 key.o ABSOLUTE
+ ..\HARDWARE\LCD\lcd.c 0x00000000 Number 0 lcd.o ABSOLUTE
+ ..\STM32F10x_FWLib\src\misc.c 0x00000000 Number 0 misc.o ABSOLUTE
+ ..\STM32F10x_FWLib\src\stm32f10x_exti.c 0x00000000 Number 0 stm32f10x_exti.o ABSOLUTE
+ ..\STM32F10x_FWLib\src\stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE
+ ..\STM32F10x_FWLib\src\stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE
+ ..\STM32F10x_FWLib\src\stm32f10x_spi.c 0x00000000 Number 0 stm32f10x_spi.o ABSOLUTE
+ ..\STM32F10x_FWLib\src\stm32f10x_usart.c 0x00000000 Number 0 stm32f10x_usart.o ABSOLUTE
+ ..\SYSTEM\delay\delay.c 0x00000000 Number 0 delay.o ABSOLUTE
+ ..\SYSTEM\nvic\NVIC.c 0x00000000 Number 0 nvic.o ABSOLUTE
+ ..\SYSTEM\sys\sys.c 0x00000000 Number 0 sys.o ABSOLUTE
+ ..\\CORE\\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE
+ ..\\SYSTEM\\sys\\sys.c 0x00000000 Number 0 sys.o ABSOLUTE
+ GUI.c 0x00000000 Number 0 gui.o ABSOLUTE
+ dc.s 0x00000000 Number 0 dc.o ABSOLUTE
+ main.c 0x00000000 Number 0 main.o ABSOLUTE
+ system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE
+ RESET 0x08000000 Section 236 startup_stm32f10x_md.o(RESET)
+ !!!main 0x080000ec Section 8 __main.o(!!!main)
+ !!!scatter 0x080000f4 Section 52 __scatter.o(!!!scatter)
+ !!handler_copy 0x08000128 Section 26 __scatter_copy.o(!!handler_copy)
+ !!handler_zi 0x08000144 Section 28 __scatter_zi.o(!!handler_zi)
+ .ARM.Collect$$libinit$$00000000 0x08000160 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000)
+ .ARM.Collect$$libinit$$00000002 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000002)
+ .ARM.Collect$$libinit$$00000004 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004)
+ .ARM.Collect$$libinit$$0000000A 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A)
+ .ARM.Collect$$libinit$$0000000C 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C)
+ .ARM.Collect$$libinit$$0000000E 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E)
+ .ARM.Collect$$libinit$$00000011 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011)
+ .ARM.Collect$$libinit$$00000013 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013)
+ .ARM.Collect$$libinit$$00000015 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015)
+ .ARM.Collect$$libinit$$00000017 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017)
+ .ARM.Collect$$libinit$$00000019 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019)
+ .ARM.Collect$$libinit$$0000001B 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B)
+ .ARM.Collect$$libinit$$0000001D 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D)
+ .ARM.Collect$$libinit$$0000001F 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F)
+ .ARM.Collect$$libinit$$00000021 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021)
+ .ARM.Collect$$libinit$$00000023 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023)
+ .ARM.Collect$$libinit$$00000025 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025)
+ .ARM.Collect$$libinit$$0000002C 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C)
+ .ARM.Collect$$libinit$$0000002E 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E)
+ .ARM.Collect$$libinit$$00000030 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030)
+ .ARM.Collect$$libinit$$00000032 0x08000162 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032)
+ .ARM.Collect$$libinit$$00000033 0x08000162 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033)
+ .ARM.Collect$$libshutdown$$00000000 0x08000164 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
+ .ARM.Collect$$libshutdown$$00000002 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
+ .ARM.Collect$$libshutdown$$00000004 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
+ .ARM.Collect$$libshutdown$$00000007 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
+ .ARM.Collect$$libshutdown$$0000000A 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
+ .ARM.Collect$$libshutdown$$0000000C 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
+ .ARM.Collect$$libshutdown$$0000000F 0x08000166 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
+ .ARM.Collect$$libshutdown$$00000010 0x08000166 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
+ .ARM.Collect$$rtentry$$00000000 0x08000168 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000)
+ .ARM.Collect$$rtentry$$00000002 0x08000168 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
+ .ARM.Collect$$rtentry$$00000004 0x08000168 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
+ .ARM.Collect$$rtentry$$00000009 0x0800016e Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
+ .ARM.Collect$$rtentry$$0000000A 0x0800016e Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
+ .ARM.Collect$$rtentry$$0000000C 0x08000172 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
+ .ARM.Collect$$rtentry$$0000000D 0x08000172 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
+ .ARM.Collect$$rtexit$$00000000 0x0800017a Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000)
+ .ARM.Collect$$rtexit$$00000002 0x0800017c Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002)
+ .ARM.Collect$$rtexit$$00000003 0x0800017c Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003)
+ .ARM.Collect$$rtexit$$00000004 0x08000180 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004)
+ .emb_text 0x08000188 Section 12 sys.o(.emb_text)
+ .text 0x08000194 Section 0 main.o(.text)
+ .text 0x0800041c Section 0 gui.o(.text)
+ .text 0x08000ec0 Section 0 delay.o(.text)
+ .text 0x08000f6c Section 0 system_stm32f10x.o(.text)
+ SetSysClockTo72 0x08000f6d Thumb Code 214 system_stm32f10x.o(.text)
+ SetSysClock 0x08001043 Thumb Code 8 system_stm32f10x.o(.text)
+ .text 0x0800114c Section 0 sys.o(.text)
+ .text 0x08001438 Section 0 lcd.o(.text)
+ .text 0x080019bc Section 0 keypad4x4.o(.text)
+ .text 0x08001b90 Section 0 nvic.o(.text)
+ .text 0x08001d00 Section 64 startup_stm32f10x_md.o(.text)
+ .text 0x08001d40 Section 0 misc.o(.text)
+ .text 0x08001e1c Section 0 stm32f10x_gpio.o(.text)
+ .text 0x08002178 Section 0 stm32f10x_rcc.o(.text)
+ .text 0x0800251c Section 0 stm32f10x_spi.o(.text)
+ .text 0x08002828 Section 0 stm32f10x_exti.o(.text)
+ .text 0x08002944 Section 0 strlen.o(.text)
+ .text 0x08002982 Section 0 heapauxi.o(.text)
+ .text 0x08002988 Section 74 sys_stackheap_outer.o(.text)
+ .text 0x080029d2 Section 0 exit.o(.text)
+ .text 0x080029e4 Section 8 libspace.o(.text)
+ .text 0x080029ec Section 0 sys_exit.o(.text)
+ .text 0x080029f8 Section 2 use_no_semi.o(.text)
+ .constdata 0x080029fa Section 4364 gui.o(.constdata)
+ .text 0x080029fa Section 0 indicate_semi.o(.text)
+ .data 0x20000000 Section 4 delay.o(.data)
+ fac_us 0x20000000 Data 1 delay.o(.data)
+ fac_ms 0x20000002 Data 2 delay.o(.data)
+ .data 0x20000004 Section 20 system_stm32f10x.o(.data)
+ .data 0x20000018 Section 6 lcd.o(.data)
+ .data 0x2000001e Section 1 nvic.o(.data)
+ .data 0x2000001f Section 20 stm32f10x_rcc.o(.data)
+ APBAHBPrescTable 0x2000001f Data 16 stm32f10x_rcc.o(.data)
+ ADCPrescTable 0x2000002f Data 4 stm32f10x_rcc.o(.data)
+ .bss 0x20000034 Section 14 lcd.o(.bss)
+ .bss 0x20000044 Section 96 libspace.o(.bss)
+ HEAP 0x200000a8 Section 512 startup_stm32f10x_md.o(HEAP)
+ Heap_Mem 0x200000a8 Data 512 startup_stm32f10x_md.o(HEAP)
+ STACK 0x200002a8 Section 1024 startup_stm32f10x_md.o(STACK)
+ Stack_Mem 0x200002a8 Data 1024 startup_stm32f10x_md.o(STACK)
+ __initial_sp 0x200006a8 Data 0 startup_stm32f10x_md.o(STACK)
+
+ Global Symbols
+
+ Symbol Name Value Ov Type Size Object(Section)
+
+ BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
+ __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE
+ __ARM_exceptions_init - Undefined Weak Reference
+ __alloca_initialize - Undefined Weak Reference
+ __arm_preinit_ - Undefined Weak Reference
+ __cpp_initialize__aeabi_ - Undefined Weak Reference
+ __cxa_finalize - Undefined Weak Reference
+ __rt_locale - Undefined Weak Reference
+ __sigvec_lookup - Undefined Weak Reference
+ _atexit_init - Undefined Weak Reference
+ _call_atexit_fns - Undefined Weak Reference
+ _clock_init - Undefined Weak Reference
+ _fp_trap_init - Undefined Weak Reference
+ _fp_trap_shutdown - Undefined Weak Reference
+ _get_lc_collate - Undefined Weak Reference
+ _get_lc_ctype - Undefined Weak Reference
+ _get_lc_monetary - Undefined Weak Reference
+ _get_lc_numeric - Undefined Weak Reference
+ _get_lc_time - Undefined Weak Reference
+ _getenv_init - Undefined Weak Reference
+ _handle_redirection - Undefined Weak Reference
+ _init_alloc - Undefined Weak Reference
+ _init_user_alloc - Undefined Weak Reference
+ _initio - Undefined Weak Reference
+ _rand_init - Undefined Weak Reference
+ _signal_finish - Undefined Weak Reference
+ _signal_init - Undefined Weak Reference
+ _terminate_alloc - Undefined Weak Reference
+ _terminate_user_alloc - Undefined Weak Reference
+ _terminateio - Undefined Weak Reference
+ __Vectors_Size 0x000000ec Number 0 startup_stm32f10x_md.o ABSOLUTE
+ __Vectors 0x08000000 Data 4 startup_stm32f10x_md.o(RESET)
+ __Vectors_End 0x080000ec Data 0 startup_stm32f10x_md.o(RESET)
+ __main 0x080000ed Thumb Code 8 __main.o(!!!main)
+ __scatterload 0x080000f5 Thumb Code 0 __scatter.o(!!!scatter)
+ __scatterload_rt2 0x080000f5 Thumb Code 44 __scatter.o(!!!scatter)
+ __scatterload_rt2_thumb_only 0x080000f5 Thumb Code 0 __scatter.o(!!!scatter)
+ __scatterload_null 0x08000103 Thumb Code 0 __scatter.o(!!!scatter)
+ __scatterload_copy 0x08000129 Thumb Code 26 __scatter_copy.o(!!handler_copy)
+ __scatterload_zeroinit 0x08000145 Thumb Code 28 __scatter_zi.o(!!handler_zi)
+ __rt_lib_init 0x08000161 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000)
+ __rt_lib_init_alloca_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E)
+ __rt_lib_init_argv_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C)
+ __rt_lib_init_atexit_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B)
+ __rt_lib_init_clock_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021)
+ __rt_lib_init_cpp_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032)
+ __rt_lib_init_exceptions_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030)
+ __rt_lib_init_fp_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002)
+ __rt_lib_init_fp_trap_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F)
+ __rt_lib_init_getenv_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023)
+ __rt_lib_init_heap_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A)
+ __rt_lib_init_lc_collate_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011)
+ __rt_lib_init_lc_ctype_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013)
+ __rt_lib_init_lc_monetary_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015)
+ __rt_lib_init_lc_numeric_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017)
+ __rt_lib_init_lc_time_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019)
+ __rt_lib_init_preinit_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004)
+ __rt_lib_init_rand_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E)
+ __rt_lib_init_return 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033)
+ __rt_lib_init_signal_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D)
+ __rt_lib_init_stdio_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025)
+ __rt_lib_init_user_alloc_1 0x08000163 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C)
+ __rt_lib_shutdown 0x08000165 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
+ __rt_lib_shutdown_cpp_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
+ __rt_lib_shutdown_fp_trap_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
+ __rt_lib_shutdown_heap_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
+ __rt_lib_shutdown_return 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
+ __rt_lib_shutdown_signal_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
+ __rt_lib_shutdown_stdio_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
+ __rt_lib_shutdown_user_alloc_1 0x08000167 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
+ __rt_entry 0x08000169 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000)
+ __rt_entry_presh_1 0x08000169 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
+ __rt_entry_sh 0x08000169 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
+ __rt_entry_li 0x0800016f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
+ __rt_entry_postsh_1 0x0800016f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
+ __rt_entry_main 0x08000173 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
+ __rt_entry_postli_1 0x08000173 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
+ __rt_exit 0x0800017b Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000)
+ __rt_exit_ls 0x0800017d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003)
+ __rt_exit_prels_1 0x0800017d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002)
+ __rt_exit_exit 0x08000181 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004)
+ WFI_SET 0x08000189 Thumb Code 2 sys.o(.emb_text)
+ INTX_DISABLE 0x0800018b Thumb Code 2 sys.o(.emb_text)
+ INTX_ENABLE 0x0800018d Thumb Code 2 sys.o(.emb_text)
+ MSR_MSP 0x0800018f Thumb Code 6 sys.o(.emb_text)
+ main 0x08000195 Thumb Code 630 main.o(.text)
+ GUI_DrawPoint 0x0800041d Thumb Code 24 gui.o(.text)
+ LCD_Fill 0x08000435 Thumb Code 114 gui.o(.text)
+ LCD_DrawLine 0x080004a7 Thumb Code 176 gui.o(.text)
+ LCD_DrawRectangle 0x08000557 Thumb Code 64 gui.o(.text)
+ LCD_DrawFillRectangle 0x08000597 Thumb Code 30 gui.o(.text)
+ _draw_circle_8 0x080005b5 Thumb Code 132 gui.o(.text)
+ gui_circle 0x08000639 Thumb Code 154 gui.o(.text)
+ LCD_ShowChar 0x080006d3 Thumb Code 280 gui.o(.text)
+ LCD_ShowNum2412 0x080007eb Thumb Code 240 gui.o(.text)
+ LCD_ShowString 0x080008db Thumb Code 94 gui.o(.text)
+ mypow 0x08000939 Thumb Code 22 gui.o(.text)
+ LCD_ShowNum 0x0800094f Thumb Code 168 gui.o(.text)
+ GUI_DrawFont16 0x080009f7 Thumb Code 252 gui.o(.text)
+ GUI_DrawFont24 0x08000af3 Thumb Code 268 gui.o(.text)
+ GUI_DrawFont32 0x08000bff Thumb Code 276 gui.o(.text)
+ Show_Str 0x08000d13 Thumb Code 268 gui.o(.text)
+ Gui_StrCenter 0x08000e1f Thumb Code 68 gui.o(.text)
+ Gui_Drawbmp16 0x08000e63 Thumb Code 90 gui.o(.text)
+ delay_init 0x08000ec1 Thumb Code 52 delay.o(.text)
+ delay_ms 0x08000ef5 Thumb Code 56 delay.o(.text)
+ delay_us 0x08000f2d Thumb Code 56 delay.o(.text)
+ SystemInit 0x0800104b Thumb Code 78 system_stm32f10x.o(.text)
+ SystemCoreClockUpdate 0x08001099 Thumb Code 142 system_stm32f10x.o(.text)
+ MY_NVIC_SetVectorTable 0x0800114d Thumb Code 12 sys.o(.text)
+ MY_NVIC_PriorityGroupConfig 0x08001159 Thumb Code 36 sys.o(.text)
+ MY_NVIC_Init 0x0800117d Thumb Code 146 sys.o(.text)
+ Ex_NVIC_Config 0x0800120f Thumb Code 146 sys.o(.text)
+ MYRCC_DeInit 0x080012a1 Thumb Code 90 sys.o(.text)
+ Sys_Standby 0x080012fb Thumb Code 68 sys.o(.text)
+ Sys_Soft_Reset 0x0800133f Thumb Code 12 sys.o(.text)
+ JTAG_Set 0x0800134b Thumb Code 42 sys.o(.text)
+ Stm32_Clock_Init 0x08001375 Thumb Code 134 sys.o(.text)
+ NVIC_Configuration 0x080013fb Thumb Code 12 sys.o(.text)
+ SPIv_WriteData 0x08001439 Thumb Code 60 lcd.o(.text)
+ SPI_WriteByte 0x08001475 Thumb Code 76 lcd.o(.text)
+ SPI_SetSpeed 0x080014c1 Thumb Code 38 lcd.o(.text)
+ SPI2_Init 0x080014e7 Thumb Code 208 lcd.o(.text)
+ LCD_WR_REG 0x080015b7 Thumb Code 38 lcd.o(.text)
+ LCD_WR_DATA 0x080015dd Thumb Code 40 lcd.o(.text)
+ LCD_WR_DATA_16Bit 0x08001605 Thumb Code 50 lcd.o(.text)
+ LCD_WriteReg 0x08001637 Thumb Code 20 lcd.o(.text)
+ LCD_WriteRAM_Prepare 0x0800164b Thumb Code 12 lcd.o(.text)
+ LCD_SetWindows 0x08001657 Thumb Code 88 lcd.o(.text)
+ LCD_SetCursor 0x080016af Thumb Code 20 lcd.o(.text)
+ LCD_DrawPoint 0x080016c3 Thumb Code 24 lcd.o(.text)
+ LCD_GPIOInit 0x080016db Thumb Code 42 lcd.o(.text)
+ LCD_RESET 0x08001705 Thumb Code 16 lcd.o(.text)
+ LCD_SetParam 0x08001715 Thumb Code 36 lcd.o(.text)
+ LCD_Init 0x08001739 Thumb Code 570 lcd.o(.text)
+ LCD_Clear 0x08001973 Thumb Code 68 lcd.o(.text)
+ KEYPAD4x4_Init 0x080019bd Thumb Code 66 keypad4x4.o(.text)
+ KEYPAD4x4_Init2 0x080019ff Thumb Code 66 keypad4x4.o(.text)
+ KEYPAD4x4_Read 0x08001a41 Thumb Code 330 keypad4x4.o(.text)
+ KEYPAD4x4_INT_INIT 0x08001b91 Thumb Code 276 nvic.o(.text)
+ EXTI4_IRQHandler 0x08001ca5 Thumb Code 24 nvic.o(.text)
+ EXTI9_5_IRQHandler 0x08001cbd Thumb Code 64 nvic.o(.text)
+ Reset_Handler 0x08001d01 Thumb Code 8 startup_stm32f10x_md.o(.text)
+ NMI_Handler 0x08001d09 Thumb Code 2 startup_stm32f10x_md.o(.text)
+ HardFault_Handler 0x08001d0b Thumb Code 2 startup_stm32f10x_md.o(.text)
+ MemManage_Handler 0x08001d0d Thumb Code 2 startup_stm32f10x_md.o(.text)
+ BusFault_Handler 0x08001d0f Thumb Code 2 startup_stm32f10x_md.o(.text)
+ UsageFault_Handler 0x08001d11 Thumb Code 2 startup_stm32f10x_md.o(.text)
+ SVC_Handler 0x08001d13 Thumb Code 2 startup_stm32f10x_md.o(.text)
+ DebugMon_Handler 0x08001d15 Thumb Code 2 startup_stm32f10x_md.o(.text)
+ PendSV_Handler 0x08001d17 Thumb Code 2 startup_stm32f10x_md.o(.text)
+ SysTick_Handler 0x08001d19 Thumb Code 2 startup_stm32f10x_md.o(.text)
+ ADC1_2_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ CAN1_RX1_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ CAN1_SCE_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ DMA1_Channel1_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ DMA1_Channel2_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ DMA1_Channel3_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ DMA1_Channel4_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ DMA1_Channel5_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ DMA1_Channel6_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ DMA1_Channel7_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ EXTI0_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ EXTI15_10_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ EXTI1_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ EXTI2_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ EXTI3_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ FLASH_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ I2C1_ER_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ I2C1_EV_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ I2C2_ER_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ I2C2_EV_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ PVD_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ RCC_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ RTCAlarm_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ RTC_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ SPI1_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ SPI2_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TAMPER_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TIM1_BRK_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TIM1_CC_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TIM1_TRG_COM_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TIM1_UP_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TIM2_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TIM3_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ TIM4_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ USART1_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ USART2_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ USART3_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ USBWakeUp_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ USB_HP_CAN1_TX_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ USB_LP_CAN1_RX0_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ WWDG_IRQHandler 0x08001d1b Thumb Code 0 startup_stm32f10x_md.o(.text)
+ __user_initial_stackheap 0x08001d1d Thumb Code 0 startup_stm32f10x_md.o(.text)
+ NVIC_PriorityGroupConfig 0x08001d41 Thumb Code 10 misc.o(.text)
+ NVIC_Init 0x08001d4b Thumb Code 100 misc.o(.text)
+ NVIC_SetVectorTable 0x08001daf Thumb Code 14 misc.o(.text)
+ NVIC_SystemLPConfig 0x08001dbd Thumb Code 34 misc.o(.text)
+ SysTick_CLKSourceConfig 0x08001ddf Thumb Code 40 misc.o(.text)
+ GPIO_DeInit 0x08001e1d Thumb Code 172 stm32f10x_gpio.o(.text)
+ GPIO_AFIODeInit 0x08001ec9 Thumb Code 20 stm32f10x_gpio.o(.text)
+ GPIO_Init 0x08001edd Thumb Code 278 stm32f10x_gpio.o(.text)
+ GPIO_StructInit 0x08001ff3 Thumb Code 16 stm32f10x_gpio.o(.text)
+ GPIO_ReadInputDataBit 0x08002003 Thumb Code 18 stm32f10x_gpio.o(.text)
+ GPIO_ReadInputData 0x08002015 Thumb Code 8 stm32f10x_gpio.o(.text)
+ GPIO_ReadOutputDataBit 0x0800201d Thumb Code 18 stm32f10x_gpio.o(.text)
+ GPIO_ReadOutputData 0x0800202f Thumb Code 8 stm32f10x_gpio.o(.text)
+ GPIO_SetBits 0x08002037 Thumb Code 4 stm32f10x_gpio.o(.text)
+ GPIO_ResetBits 0x0800203b Thumb Code 4 stm32f10x_gpio.o(.text)
+ GPIO_WriteBit 0x0800203f Thumb Code 10 stm32f10x_gpio.o(.text)
+ GPIO_Write 0x08002049 Thumb Code 4 stm32f10x_gpio.o(.text)
+ GPIO_PinLockConfig 0x0800204d Thumb Code 18 stm32f10x_gpio.o(.text)
+ GPIO_EventOutputConfig 0x0800205f Thumb Code 26 stm32f10x_gpio.o(.text)
+ GPIO_EventOutputCmd 0x08002079 Thumb Code 6 stm32f10x_gpio.o(.text)
+ GPIO_PinRemapConfig 0x0800207f Thumb Code 138 stm32f10x_gpio.o(.text)
+ GPIO_EXTILineConfig 0x08002109 Thumb Code 66 stm32f10x_gpio.o(.text)
+ GPIO_ETH_MediaInterfaceConfig 0x0800214b Thumb Code 8 stm32f10x_gpio.o(.text)
+ RCC_DeInit 0x08002179 Thumb Code 64 stm32f10x_rcc.o(.text)
+ RCC_HSEConfig 0x080021b9 Thumb Code 70 stm32f10x_rcc.o(.text)
+ RCC_GetFlagStatus 0x080021ff Thumb Code 56 stm32f10x_rcc.o(.text)
+ RCC_WaitForHSEStartUp 0x08002237 Thumb Code 56 stm32f10x_rcc.o(.text)
+ RCC_AdjustHSICalibrationValue 0x0800226f Thumb Code 20 stm32f10x_rcc.o(.text)
+ RCC_HSICmd 0x08002283 Thumb Code 6 stm32f10x_rcc.o(.text)
+ RCC_PLLConfig 0x08002289 Thumb Code 24 stm32f10x_rcc.o(.text)
+ RCC_PLLCmd 0x080022a1 Thumb Code 6 stm32f10x_rcc.o(.text)
+ RCC_SYSCLKConfig 0x080022a7 Thumb Code 18 stm32f10x_rcc.o(.text)
+ RCC_GetSYSCLKSource 0x080022b9 Thumb Code 10 stm32f10x_rcc.o(.text)
+ RCC_HCLKConfig 0x080022c3 Thumb Code 18 stm32f10x_rcc.o(.text)
+ RCC_PCLK1Config 0x080022d5 Thumb Code 18 stm32f10x_rcc.o(.text)
+ RCC_PCLK2Config 0x080022e7 Thumb Code 20 stm32f10x_rcc.o(.text)
+ RCC_ITConfig 0x080022fb Thumb Code 26 stm32f10x_rcc.o(.text)
+ RCC_USBCLKConfig 0x08002315 Thumb Code 8 stm32f10x_rcc.o(.text)
+ RCC_ADCCLKConfig 0x0800231d Thumb Code 18 stm32f10x_rcc.o(.text)
+ RCC_LSEConfig 0x0800232f Thumb Code 50 stm32f10x_rcc.o(.text)
+ RCC_LSICmd 0x08002361 Thumb Code 6 stm32f10x_rcc.o(.text)
+ RCC_RTCCLKConfig 0x08002367 Thumb Code 12 stm32f10x_rcc.o(.text)
+ RCC_RTCCLKCmd 0x08002373 Thumb Code 8 stm32f10x_rcc.o(.text)
+ RCC_GetClocksFreq 0x0800237b Thumb Code 192 stm32f10x_rcc.o(.text)
+ RCC_AHBPeriphClockCmd 0x0800243b Thumb Code 26 stm32f10x_rcc.o(.text)
+ RCC_APB2PeriphClockCmd 0x08002455 Thumb Code 26 stm32f10x_rcc.o(.text)
+ RCC_APB1PeriphClockCmd 0x0800246f Thumb Code 26 stm32f10x_rcc.o(.text)
+ RCC_APB2PeriphResetCmd 0x08002489 Thumb Code 26 stm32f10x_rcc.o(.text)
+ RCC_APB1PeriphResetCmd 0x080024a3 Thumb Code 26 stm32f10x_rcc.o(.text)
+ RCC_BackupResetCmd 0x080024bd Thumb Code 8 stm32f10x_rcc.o(.text)
+ RCC_ClockSecuritySystemCmd 0x080024c5 Thumb Code 6 stm32f10x_rcc.o(.text)
+ RCC_MCOConfig 0x080024cb Thumb Code 6 stm32f10x_rcc.o(.text)
+ RCC_ClearFlag 0x080024d1 Thumb Code 14 stm32f10x_rcc.o(.text)
+ RCC_GetITStatus 0x080024df Thumb Code 20 stm32f10x_rcc.o(.text)
+ RCC_ClearITPendingBit 0x080024f3 Thumb Code 6 stm32f10x_rcc.o(.text)
+ SPI_I2S_DeInit 0x0800251d Thumb Code 76 stm32f10x_spi.o(.text)
+ SPI_Init 0x08002569 Thumb Code 60 stm32f10x_spi.o(.text)
+ I2S_Init 0x080025a5 Thumb Code 226 stm32f10x_spi.o(.text)
+ SPI_StructInit 0x08002687 Thumb Code 24 stm32f10x_spi.o(.text)
+ I2S_StructInit 0x0800269f Thumb Code 20 stm32f10x_spi.o(.text)
+ SPI_Cmd 0x080026b3 Thumb Code 24 stm32f10x_spi.o(.text)
+ I2S_Cmd 0x080026cb Thumb Code 24 stm32f10x_spi.o(.text)
+ SPI_I2S_ITConfig 0x080026e3 Thumb Code 32 stm32f10x_spi.o(.text)
+ SPI_I2S_DMACmd 0x08002703 Thumb Code 18 stm32f10x_spi.o(.text)
+ SPI_I2S_SendData 0x08002715 Thumb Code 4 stm32f10x_spi.o(.text)
+ SPI_I2S_ReceiveData 0x08002719 Thumb Code 6 stm32f10x_spi.o(.text)
+ SPI_NSSInternalSoftwareConfig 0x0800271f Thumb Code 30 stm32f10x_spi.o(.text)
+ SPI_SSOutputCmd 0x0800273d Thumb Code 24 stm32f10x_spi.o(.text)
+ SPI_DataSizeConfig 0x08002755 Thumb Code 18 stm32f10x_spi.o(.text)
+ SPI_TransmitCRC 0x08002767 Thumb Code 10 stm32f10x_spi.o(.text)
+ SPI_CalculateCRC 0x08002771 Thumb Code 24 stm32f10x_spi.o(.text)
+ SPI_GetCRC 0x08002789 Thumb Code 16 stm32f10x_spi.o(.text)
+ SPI_GetCRCPolynomial 0x08002799 Thumb Code 6 stm32f10x_spi.o(.text)
+ SPI_BiDirectionalLineConfig 0x0800279f Thumb Code 28 stm32f10x_spi.o(.text)
+ SPI_I2S_GetFlagStatus 0x080027bb Thumb Code 18 stm32f10x_spi.o(.text)
+ SPI_I2S_ClearFlag 0x080027cd Thumb Code 6 stm32f10x_spi.o(.text)
+ SPI_I2S_GetITStatus 0x080027d3 Thumb Code 52 stm32f10x_spi.o(.text)
+ SPI_I2S_ClearITPendingBit 0x08002807 Thumb Code 20 stm32f10x_spi.o(.text)
+ EXTI_DeInit 0x08002829 Thumb Code 28 stm32f10x_exti.o(.text)
+ EXTI_Init 0x08002845 Thumb Code 142 stm32f10x_exti.o(.text)
+ EXTI_StructInit 0x080028d3 Thumb Code 16 stm32f10x_exti.o(.text)
+ EXTI_GenerateSWInterrupt 0x080028e3 Thumb Code 16 stm32f10x_exti.o(.text)
+ EXTI_GetFlagStatus 0x080028f3 Thumb Code 22 stm32f10x_exti.o(.text)
+ EXTI_ClearFlag 0x08002909 Thumb Code 8 stm32f10x_exti.o(.text)
+ EXTI_GetITStatus 0x08002911 Thumb Code 34 stm32f10x_exti.o(.text)
+ EXTI_ClearITPendingBit 0x08002933 Thumb Code 8 stm32f10x_exti.o(.text)
+ strlen 0x08002945 Thumb Code 62 strlen.o(.text)
+ __use_two_region_memory 0x08002983 Thumb Code 2 heapauxi.o(.text)
+ __rt_heap_escrow$2region 0x08002985 Thumb Code 2 heapauxi.o(.text)
+ __rt_heap_expand$2region 0x08002987 Thumb Code 2 heapauxi.o(.text)
+ __user_setup_stackheap 0x08002989 Thumb Code 74 sys_stackheap_outer.o(.text)
+ exit 0x080029d3 Thumb Code 18 exit.o(.text)
+ __user_libspace 0x080029e5 Thumb Code 8 libspace.o(.text)
+ __user_perproc_libspace 0x080029e5 Thumb Code 0 libspace.o(.text)
+ __user_perthread_libspace 0x080029e5 Thumb Code 0 libspace.o(.text)
+ _sys_exit 0x080029ed Thumb Code 8 sys_exit.o(.text)
+ __I$use$semihosting 0x080029f9 Thumb Code 0 use_no_semi.o(.text)
+ __use_no_semihosting_swi 0x080029f9 Thumb Code 2 use_no_semi.o(.text)
+ __semihosting_library_function 0x080029fb Thumb Code 0 indicate_semi.o(.text)
+ asc2_1206 0x080029fa Data 1140 gui.o(.constdata)
+ asc2_1608 0x08002e6e Data 1520 gui.o(.constdata)
+ asc2_2412 0x0800345e Data 624 gui.o(.constdata)
+ tfont16 0x080036ce Data 136 gui.o(.constdata)
+ tfont24 0x08003756 Data 814 gui.o(.constdata)
+ tfont32 0x08003a84 Data 130 gui.o(.constdata)
+ Region$$Table$$Base 0x08003b08 Number 0 anon$$obj.o(Region$$Table)
+ Region$$Table$$Limit 0x08003b28 Number 0 anon$$obj.o(Region$$Table)
+ SystemCoreClock 0x20000004 Data 4 system_stm32f10x.o(.data)
+ AHBPrescTable 0x20000008 Data 16 system_stm32f10x.o(.data)
+ POINT_COLOR 0x20000018 Data 2 lcd.o(.data)
+ BACK_COLOR 0x2000001a Data 2 lcd.o(.data)
+ DeviceCode 0x2000001c Data 2 lcd.o(.data)
+ INT_MARK 0x2000001e Data 1 nvic.o(.data)
+ lcddev 0x20000034 Data 14 lcd.o(.bss)
+ __libspace_start 0x20000044 Data 96 libspace.o(.bss)
+ __temporary_stack_top$libspace 0x200000a4 Data 0 libspace.o(.bss)
+
+
+
+==============================================================================
+
+Memory Map of the image
+
+ Image Entry point : 0x080000ed
+
+ Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00003b5c, Max: 0x00020000, ABSOLUTE)
+
+ Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x00003b28, Max: 0x00020000, ABSOLUTE)
+
+ Base Addr Size Type Attr Idx E Section Name Object
+
+ 0x08000000 0x000000ec Data RO 337 RESET startup_stm32f10x_md.o
+ 0x080000ec 0x00000008 Code RO 422 * !!!main c_w.l(__main.o)
+ 0x080000f4 0x00000034 Code RO 579 !!!scatter c_w.l(__scatter.o)
+ 0x08000128 0x0000001a Code RO 581 !!handler_copy c_w.l(__scatter_copy.o)
+ 0x08000142 0x00000002 PAD
+ 0x08000144 0x0000001c Code RO 583 !!handler_zi c_w.l(__scatter_zi.o)
+ 0x08000160 0x00000002 Code RO 449 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o)
+ 0x08000162 0x00000000 Code RO 456 .ARM.Collect$$libinit$$00000002 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 458 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 461 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 463 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 465 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 468 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 470 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 472 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 474 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 476 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 478 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 480 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 482 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 484 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 486 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 488 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 492 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 494 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 496 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o)
+ 0x08000162 0x00000000 Code RO 498 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o)
+ 0x08000162 0x00000002 Code RO 499 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o)
+ 0x08000164 0x00000002 Code RO 519 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o)
+ 0x08000166 0x00000000 Code RO 532 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o)
+ 0x08000166 0x00000000 Code RO 534 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o)
+ 0x08000166 0x00000000 Code RO 537 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o)
+ 0x08000166 0x00000000 Code RO 540 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o)
+ 0x08000166 0x00000000 Code RO 542 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o)
+ 0x08000166 0x00000000 Code RO 545 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o)
+ 0x08000166 0x00000002 Code RO 546 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o)
+ 0x08000168 0x00000000 Code RO 424 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o)
+ 0x08000168 0x00000000 Code RO 426 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o)
+ 0x08000168 0x00000006 Code RO 438 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o)
+ 0x0800016e 0x00000000 Code RO 428 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o)
+ 0x0800016e 0x00000004 Code RO 429 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o)
+ 0x08000172 0x00000000 Code RO 431 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o)
+ 0x08000172 0x00000008 Code RO 432 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o)
+ 0x0800017a 0x00000002 Code RO 453 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o)
+ 0x0800017c 0x00000000 Code RO 501 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o)
+ 0x0800017c 0x00000004 Code RO 502 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o)
+ 0x08000180 0x00000006 Code RO 503 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o)
+ 0x08000186 0x00000002 PAD
+ 0x08000188 0x0000000c Code RO 206 .emb_text sys.o
+ 0x08000194 0x00000288 Code RO 1 .text main.o
+ 0x0800041c 0x00000aa4 Code RO 131 .text gui.o
+ 0x08000ec0 0x000000ac Code RO 152 .text delay.o
+ 0x08000f6c 0x000001e0 Code RO 166 .text system_stm32f10x.o
+ 0x0800114c 0x000002ec Code RO 207 .text sys.o
+ 0x08001438 0x00000584 Code RO 238 .text lcd.o
+ 0x080019bc 0x000001d4 Code RO 295 .text keypad4x4.o
+ 0x08001b90 0x00000170 Code RO 307 .text nvic.o
+ 0x08001d00 0x00000040 Code RO 338 .text startup_stm32f10x_md.o
+ 0x08001d40 0x000000dc Code RO 342 .text misc.o
+ 0x08001e1c 0x0000035c Code RO 354 .text stm32f10x_gpio.o
+ 0x08002178 0x000003a4 Code RO 366 .text stm32f10x_rcc.o
+ 0x0800251c 0x0000030c Code RO 380 .text stm32f10x_spi.o
+ 0x08002828 0x0000011c Code RO 404 .text stm32f10x_exti.o
+ 0x08002944 0x0000003e Code RO 418 .text c_w.l(strlen.o)
+ 0x08002982 0x00000006 Code RO 420 .text c_w.l(heapauxi.o)
+ 0x08002988 0x0000004a Code RO 440 .text c_w.l(sys_stackheap_outer.o)
+ 0x080029d2 0x00000012 Code RO 442 .text c_w.l(exit.o)
+ 0x080029e4 0x00000008 Code RO 450 .text c_w.l(libspace.o)
+ 0x080029ec 0x0000000c Code RO 511 .text c_w.l(sys_exit.o)
+ 0x080029f8 0x00000002 Code RO 522 .text c_w.l(use_no_semi.o)
+ 0x080029fa 0x00000000 Code RO 524 .text c_w.l(indicate_semi.o)
+ 0x080029fa 0x0000110c Data RO 132 .constdata gui.o
+ 0x08003b06 0x00000002 PAD
+ 0x08003b08 0x00000020 Data RO 577 Region$$Table anon$$obj.o
+
+
+ Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x000006a8, Max: 0x00005000, ABSOLUTE)
+
+ Base Addr Size Type Attr Idx E Section Name Object
+
+ 0x20000000 0x00000004 Data RW 153 .data delay.o
+ 0x20000004 0x00000014 Data RW 167 .data system_stm32f10x.o
+ 0x20000018 0x00000006 Data RW 240 .data lcd.o
+ 0x2000001e 0x00000001 Data RW 308 .data nvic.o
+ 0x2000001f 0x00000014 Data RW 367 .data stm32f10x_rcc.o
+ 0x20000033 0x00000001 PAD
+ 0x20000034 0x0000000e Zero RW 239 .bss lcd.o
+ 0x20000042 0x00000002 PAD
+ 0x20000044 0x00000060 Zero RW 451 .bss c_w.l(libspace.o)
+ 0x200000a4 0x00000004 PAD
+ 0x200000a8 0x00000200 Zero RW 336 HEAP startup_stm32f10x_md.o
+ 0x200002a8 0x00000400 Zero RW 335 STACK startup_stm32f10x_md.o
+
+
+==============================================================================
+
+Image component sizes
+
+
+ Code (inc. data) RO Data RW Data ZI Data Debug Object Name
+
+ 172 8 0 4 0 1047 delay.o
+ 2724 48 4364 0 0 10532 gui.o
+ 468 6 0 0 0 1088 keypad4x4.o
+ 1412 24 0 6 14 6254 lcd.o
+ 648 18 0 0 0 234775 main.o
+ 220 22 0 0 0 1765 misc.o
+ 368 4 0 1 0 1184 nvic.o
+ 64 26 236 0 1536 776 startup_stm32f10x_md.o
+ 284 10 0 0 0 2223 stm32f10x_exti.o
+ 860 38 0 0 0 5697 stm32f10x_gpio.o
+ 932 36 0 20 0 8860 stm32f10x_rcc.o
+ 780 14 0 0 0 6582 stm32f10x_spi.o
+ 760 50 0 0 0 3022 sys.o
+ 480 38 0 20 0 1683 system_stm32f10x.o
+
+ ----------------------------------------------------------------------
+ 10172 342 4634 52 1552 285488 Object Totals
+ 0 0 32 0 0 0 (incl. Generated)
+ 0 0 2 1 2 0 (incl. Padding)
+
+ ----------------------------------------------------------------------
+
+ Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
+
+ 8 0 0 0 0 68 __main.o
+ 0 0 0 0 0 0 __rtentry.o
+ 12 0 0 0 0 0 __rtentry2.o
+ 6 0 0 0 0 0 __rtentry4.o
+ 52 8 0 0 0 0 __scatter.o
+ 26 0 0 0 0 0 __scatter_copy.o
+ 28 0 0 0 0 0 __scatter_zi.o
+ 18 0 0 0 0 80 exit.o
+ 6 0 0 0 0 152 heapauxi.o
+ 0 0 0 0 0 0 indicate_semi.o
+ 2 0 0 0 0 0 libinit.o
+ 2 0 0 0 0 0 libinit2.o
+ 2 0 0 0 0 0 libshutdown.o
+ 2 0 0 0 0 0 libshutdown2.o
+ 8 4 0 0 96 68 libspace.o
+ 2 0 0 0 0 0 rtexit.o
+ 10 0 0 0 0 0 rtexit2.o
+ 62 0 0 0 0 76 strlen.o
+ 12 4 0 0 0 68 sys_exit.o
+ 74 0 0 0 0 80 sys_stackheap_outer.o
+ 2 0 0 0 0 68 use_no_semi.o
+
+ ----------------------------------------------------------------------
+ 338 16 0 0 100 660 Library Totals
+ 4 0 0 0 4 0 (incl. Padding)
+
+ ----------------------------------------------------------------------
+
+ Code (inc. data) RO Data RW Data ZI Data Debug Library Name
+
+ 334 16 0 0 96 660 c_w.l
+
+ ----------------------------------------------------------------------
+ 338 16 0 0 100 660 Library Totals
+
+ ----------------------------------------------------------------------
+
+==============================================================================
+
+
+ Code (inc. data) RO Data RW Data ZI Data Debug
+
+ 10510 358 4634 52 1652 284844 Grand Totals
+ 10510 358 4634 52 1652 284844 ELF Image Totals
+ 10510 358 4634 52 0 0 ROM Totals
+
+==============================================================================
+
+ Total RO Size (Code + RO Data) 15144 ( 14.79kB)
+ Total RW Size (RW Data + ZI Data) 1704 ( 1.66kB)
+ Total ROM Size (Code + RO Data + RW Data) 15196 ( 14.84kB)
+
+==============================================================================
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.crf"
new file mode 100644
index 0000000..1454010
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.d"
new file mode 100644
index 0000000..9fb4148
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.d"
@@ -0,0 +1,37 @@
+gui.o: GUI.c
+gui.o: ..\HARDWARE\LCD\lcd.h
+gui.o: ..\SYSTEM\sys\sys.h
+gui.o: ..\USER\stm32f10x.h
+gui.o: ..\CORE\core_cm3.h
+gui.o: C:\Keil\ARM\ARMCC\bin\..\include\stdint.h
+gui.o: ..\USER\system_stm32f10x.h
+gui.o: ..\USER\stm32f10x_conf.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+gui.o: ..\USER\stm32f10x.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+gui.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+gui.o: ..\STM32F10x_FWLib\inc\misc.h
+gui.o: C:\Keil\ARM\ARMCC\bin\..\include\stdlib.h
+gui.o: C:\Keil\ARM\ARMCC\bin\..\include\string.h
+gui.o: ..\HARDWARE\LCD\font.h
+gui.o: ..\SYSTEM\delay\delay.h
+gui.o: gui.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.o"
new file mode 100644
index 0000000..0eb3579
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/gui.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.c"
new file mode 100644
index 0000000..0839d6a
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.c"
@@ -0,0 +1,86 @@
+#include "delay.h"
+#include "sys.h"
+#include "lcd.h"
+#include "touch.h"
+#include "gui.h"
+#include "test.h"
+#include "KEYPAD4x4.h"
+#include "NVIC.h"
+//////////////////////////////////////////////////////////////////////////////////
+//本程序只供学习使用，未经作者许可，不得用于其它任何用途
+//测试硬件：单片机STM32F103RBT6,正点原子MiniSTM32开发板,主频72MHZ
+//All rights reserved
+//////////////////////////////////////////////////////////////////////////////////
+/****************************************************************************************************
+//=======================================液晶屏数据线接线==========================================//
+//CS 接PB12 //片选信号
+//CLK 接PB13 //SPI时钟信号
+//SDI(DIN) 接PB15 //SPI总线数据信号
+//=======================================液晶屏控制线接线==========================================//
+//RS(D/C) 接PB1 //寄存器/数据选择信号(RS=0数据总线发送的是指令；RS=1数据总线发送的是像素数据)
+/////////////////////////////////////////////////////////////////////////////////////////////////
+//==================================如何精简到只需要3个IO=======================================//
+//1.CS信号可以精简，不作SPI复用片选可将CS接地常低，节省1个IO
+//2.LED背光控制信号可以接高电平3.3V背光常亮，节省1个IO
+//3.RST复位信号可以接到单片机的复位端，利用系统上电复位，节省1个IO
+//==================================如何切换横竖屏显示=======================================//
+//打开lcd.h头文件，修改宏#define USE_HORIZONTAL 值为0使用竖屏模式.1,使用横屏模式
+//===========================如何切换模拟SPI总线驱动和硬件SPI总线驱动=========================//
+//打开lcd.h头文件，修改宏#define USE_HARDWARE_SPI 值为0使用模拟SPI总线.1,使用硬件SPI总线
+**************************************************************************************************/
+int main(void)
+{
+ u8 s,a=6,b,S;
+ SystemInit();//初始化RCC 设置系统主频为72MHZ
+ delay_init(72); //延时初始化
+ LCD_Init(); //液晶屏初始化
+ LCD_Clear(BLACK); //清屏
+
+ POINT_COLOR=WHITE;
+
+ INT_MARK=0;//标志位清0
+
+ NVIC_Configuration();//设置中断优先级
+ KEYPAD4x4_Init();//阵列键盘初始化
+ KEYPAD4x4_INT_INIT();//阵列键盘的中断初始化
+ LCD_DrawRectangle(0,0,128-1,128-1); //画矩形
+ Show_Str(36,5,BLUE,YELLOW,"取件码",16,0);
+
+// Show_Str(5,25,RED,YELLOW,"温度 ℃",24,1);
+// LCD_ShowNum2412(5+48,25,RED,YELLOW,":32",24,1);
+
+ LCD_DrawLine(5,80,20,80);
+ LCD_DrawLine(25,80,40,80);
+ LCD_DrawLine(45,80,60,80);
+ LCD_DrawLine(65,80,80,80);
+ LCD_DrawLine(85,80,100,80);
+ LCD_DrawLine(105,80,120,80);
+
+ while(1)
+ {
+ if(INT_MARK){ //中断标志位为1表示有按键中断
+ INT_MARK=0;//标志位清0
+ s=KEYPAD4x4_Read();//读出按键值
+ if((s!=0)&&(s<=10)&&(s!=36)&&(a>=0)){ //如按键值不是0，也就是说有按键操作，则判断为真
+ a--;
+ if(s==10)s-=10;//因为没按键按下时s就是等于零，所以要输出0必须使用这种方法
+ S=s;
+ if(a==5){LCD_ShowNum(9,65,s,1,18);b+=s*100000;}
+ if(a==4){LCD_ShowNum(29,65,s,1,18);b+=s*10000;}
+ if(a==3){LCD_ShowNum(49,65,s,1,18);b+=s*1000;}
+ if(a==2){LCD_ShowNum(69,65,s,1,18);b+=s*100;}
+ if(a==1){LCD_ShowNum(89,65,s,1,18);b+=s*10;}
+ if(a==0){LCD_ShowNum(109,65,s,1,18);b+=s;}
+ }
+ if(s!=0&&s==36&&a<=5){
+ a++;
+ if(a==6){LCD_ShowChar(7,67,BLACK,BLACK,0,25,0);b-=S*100000;}
+ if(a==5){LCD_ShowChar(27,67,BLACK,BLACK,0,25,0);b-=S*10000;}
+ if(a==4){LCD_ShowChar(47,67,BLACK,BLACK,0,25,0);b-=S*1000;}
+ if(a==3){LCD_ShowChar(67,67,BLACK,BLACK,0,25,0);b-=S*100;}
+ if(a==2){LCD_ShowChar(87,67,BLACK,BLACK,0,25,0);b-=S*10;}
+ if(a==1){LCD_ShowChar(107,67,BLACK,BLACK,0,25,0);b-=S;}
+ }
+ }
+}
+}
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.crf"
new file mode 100644
index 0000000..1b70295
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.d"
new file mode 100644
index 0000000..e12d319
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.d"
@@ -0,0 +1,37 @@
+main.o: main.c
+main.o: ..\SYSTEM\delay\delay.h
+main.o: ..\USER\stm32f10x.h
+main.o: ..\CORE\core_cm3.h
+main.o: C:\Keil\ARM\ARMCC\bin\..\include\stdint.h
+main.o: ..\USER\system_stm32f10x.h
+main.o: ..\USER\stm32f10x_conf.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+main.o: ..\USER\stm32f10x.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+main.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+main.o: ..\STM32F10x_FWLib\inc\misc.h
+main.o: ..\SYSTEM\sys\sys.h
+main.o: ..\HARDWARE\LCD\lcd.h
+main.o: C:\Keil\ARM\ARMCC\bin\..\include\stdlib.h
+main.o: ..\HARDWARE\TOUCH\touch.h
+main.o: gui.h
+main.o: test.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.o"
new file mode 100644
index 0000000..6cc3cf6
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/main.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/pic.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/pic.h"
new file mode 100644
index 0000000..ba1f9ed
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/pic.h"
@@ -0,0 +1,234 @@
+#ifndef __PIC_H
+#define __PIC_H
+//////////////////////////////////////////////////////////////////////////////////
+//本程序只供学习使用，未经作者许可，不得用于其它任何用途
+//测试硬件：单片机STM32F103RBT6,主频72M 单片机工作电压3.3V
+//QDtech-TFT液晶驱动 for STM32 IO模拟
+//xiao冯@ShenZhen QDtech co.,LTD
+//公司网站:www.qdtech.net
+//淘宝网站：http://qdtech.taobao.com
+//我司提供技术支持，任何技术问题欢迎随时交流学习
+//固话(传真) :+86 0755-23594567
+//手机:15989313508（冯工）
+//邮箱:QDtech2008@gmail.com
+//Skype:QDtech2008
+//技术交流QQ群:324828016
+//创建日期:2013/5/13
+//版本：V1.1
+//版权所有，盗版必究。
+//Copyright(C) 深圳市全动电子技术有限公司 2009-2019
+//All rights reserved
+//////////////////////////////////////////////////////////////////////////////////
+
+//16位BMP 40X40 QQ图像取模数据
+//Image2LCD取模选项设置
+//水平扫描
+//16位
+//40X40
+//不包含图像头数据
+//自左至右
+//自顶至底
+//低位在前
+const unsigned char gImage_qq[3200] = { /* 0X00,0X10,0X28,0X00,0X28,0X00,0X01,0X1B, */
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+0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+0X59,0XDE,0X0D,0XC4,0X06,0XCB,0XE4,0XD2,0X03,0XDB,0X03,0XDB,0XE3,0XDA,0XC3,0XD2,
+0XA4,0XC2,0X09,0XB3,0XD2,0XBC,0X9E,0XF7,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFB,0XE6,
+0X0E,0XB4,0XA6,0XBA,0X83,0XD2,0XE3,0XE2,0X02,0XEB,0X22,0XEB,0X22,0XE3,0X03,0XDB,
+0XE4,0XD2,0X6A,0XC3,0XB6,0XD5,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,0XFF,
+};
+#endif
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/startup_stm32f10x_md.lst" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/startup_stm32f10x_md.lst"
new file mode 100644
index 0000000..c03a0de
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/startup_stm32f10x_md.lst"
@@ -0,0 +1,1208 @@
+
+
+
+ARM Macro Assembler Page 1
+
+
+ 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron
+ ics ********************
+ 2 00000000 ;* File Name : startup_stm32f10x_md.s
+ 3 00000000 ;* Author : MCD Application Team
+ 4 00000000 ;* Version : V3.5.0
+ 5 00000000 ;* Date : 11-March-2011
+ 6 00000000 ;* Description : STM32F10x Medium Density Devices
+ vector table for MDK-ARM
+ 7 00000000 ;* toolchain.
+ 8 00000000 ;* This module performs:
+ 9 00000000 ;* - Set the initial SP
+ 10 00000000 ;* - Set the initial PC == Reset_Ha
+ ndler
+ 11 00000000 ;* - Set the vector table entries w
+ ith the exceptions ISR address
+ 12 00000000 ;* - Configure the clock system
+ 13 00000000 ;* - Branches to __main in the C li
+ brary (which eventually
+ 14 00000000 ;* calls main()).
+ 15 00000000 ;* After Reset the CortexM3 process
+ or is in Thread mode,
+ 16 00000000 ;* priority is Privileged, and the
+ Stack is set to Main.
+ 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
+ 18 00000000 ;*******************************************************
+ ************************
+ 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
+ T PROVIDING CUSTOMERS
+ 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
+ DER FOR THEM TO SAVE TIME.
+ 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB
+ LE FOR ANY DIRECT,
+ 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
+ CLAIMS ARISING FROM THE
+ 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
+ ERS OF THE CODING
+ 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR
+ PRODUCTS.
+ 25 00000000 ;*******************************************************
+ ************************
+ 26 00000000
+ 27 00000000 ; Amount of memory (in bytes) allocated for Stack
+ 28 00000000 ; Tailor this value to your application needs
+ 29 00000000 ; Stack Configuration
+ 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ 31 00000000 ;
+ 32 00000000
+ 33 00000000 00000400
+ Stack_Size
+ EQU 0x00000400
+ 34 00000000
+ 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
+=3
+ 36 00000000 Stack_Mem
+ SPACE Stack_Size
+ 37 00000400 __initial_sp
+ 38 00000400
+ 39 00000400
+ 40 00000400 ; Heap Configuration
+
+
+
+ARM Macro Assembler Page 2
+
+
+ 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ 42 00000400 ;
+ 43 00000400
+ 44 00000400 00000200
+ Heap_Size
+ EQU 0x00000200
+ 45 00000400
+ 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
+3
+ 47 00000000 __heap_base
+ 48 00000000 Heap_Mem
+ SPACE Heap_Size
+ 49 00000200 __heap_limit
+ 50 00000200
+ 51 00000200 PRESERVE8
+ 52 00000200 THUMB
+ 53 00000200
+ 54 00000200
+ 55 00000200 ; Vector Table Mapped to Address 0 at Reset
+ 56 00000200 AREA RESET, DATA, READONLY
+ 57 00000000 EXPORT __Vectors
+ 58 00000000 EXPORT __Vectors_End
+ 59 00000000 EXPORT __Vectors_Size
+ 60 00000000
+ 61 00000000 00000000
+ __Vectors
+ DCD __initial_sp ; Top of Stack
+ 62 00000004 00000000 DCD Reset_Handler ; Reset Handler
+ 63 00000008 00000000 DCD NMI_Handler ; NMI Handler
+ 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
+ Handler
+ 65 00000010 00000000 DCD MemManage_Handler
+ ; MPU Fault Handler
+
+ 66 00000014 00000000 DCD BusFault_Handler
+ ; Bus Fault Handler
+
+ 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
+ t Handler
+ 68 0000001C 00000000 DCD 0 ; Reserved
+ 69 00000020 00000000 DCD 0 ; Reserved
+ 70 00000024 00000000 DCD 0 ; Reserved
+ 71 00000028 00000000 DCD 0 ; Reserved
+ 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
+ 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
+ r Handler
+ 74 00000034 00000000 DCD 0 ; Reserved
+ 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
+
+ 76 0000003C 00000000 DCD SysTick_Handler
+ ; SysTick Handler
+ 77 00000040
+ 78 00000040 ; External Interrupts
+ 79 00000040 00000000 DCD WWDG_IRQHandler
+ ; Window Watchdog
+ 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
+ TI Line detect
+ 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper
+ 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC
+
+
+
+ARM Macro Assembler Page 3
+
+
+ 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash
+ 84 00000054 00000000 DCD RCC_IRQHandler ; RCC
+ 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0
+ 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1
+ 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2
+ 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3
+ 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4
+ 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler
+ ; DMA1 Channel 1
+ 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler
+ ; DMA1 Channel 2
+ 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler
+ ; DMA1 Channel 3
+ 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler
+ ; DMA1 Channel 4
+ 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler
+ ; DMA1 Channel 5
+ 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler
+ ; DMA1 Channel 6
+ 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler
+ ; DMA1 Channel 7
+ 97 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1_2
+ 98 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB
+ High Priority or C
+ AN1 TX
+ 99 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US
+ B Low Priority or
+ CAN1 RX0
+ 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ 102 0000009C 00000000 DCD EXTI9_5_IRQHandler
+ ; EXTI Line 9..5
+ 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler
+ ; TIM1 Break
+ 104 000000A4 00000000 DCD TIM1_UP_IRQHandler
+ ; TIM1 Update
+ 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1
+ Trigger and Commuta
+ tion
+ 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
+ re Compare
+ 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
+ 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
+ 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
+ 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
+
+ 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
+
+ 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
+
+ 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error
+
+ 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
+ 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
+ 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1
+ 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2
+ 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3
+ 119 000000E0 00000000 DCD EXTI15_10_IRQHandler
+ ; EXTI Line 15..10
+
+
+
+ARM Macro Assembler Page 4
+
+
+ 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm
+ through EXTI Line
+ 121 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake
+ up from suspend
+ 122 000000EC __Vectors_End
+ 123 000000EC
+ 124 000000EC 000000EC
+ __Vectors_Size
+ EQU __Vectors_End - __Vectors
+ 125 000000EC
+ 126 000000EC AREA |.text|, CODE, READONLY
+ 127 00000000
+ 128 00000000 ; Reset handler
+ 129 00000000 Reset_Handler
+ PROC
+ 130 00000000 EXPORT Reset_Handler [WEAK
+]
+ 131 00000000 IMPORT __main
+ 132 00000000 IMPORT SystemInit
+ 133 00000000 4809 LDR R0, =SystemInit
+ 134 00000002 4780 BLX R0
+ 135 00000004 4809 LDR R0, =__main
+ 136 00000006 4700 BX R0
+ 137 00000008 ENDP
+ 138 00000008
+ 139 00000008 ; Dummy Exception Handlers (infinite loops which can be
+ modified)
+ 140 00000008
+ 141 00000008 NMI_Handler
+ PROC
+ 142 00000008 EXPORT NMI_Handler [WEA
+K]
+ 143 00000008 E7FE B .
+ 144 0000000A ENDP
+ 146 0000000A HardFault_Handler
+ PROC
+ 147 0000000A EXPORT HardFault_Handler [WEA
+K]
+ 148 0000000A E7FE B .
+ 149 0000000C ENDP
+ 151 0000000C MemManage_Handler
+ PROC
+ 152 0000000C EXPORT MemManage_Handler [WEA
+K]
+ 153 0000000C E7FE B .
+ 154 0000000E ENDP
+ 156 0000000E BusFault_Handler
+ PROC
+ 157 0000000E EXPORT BusFault_Handler [WEA
+K]
+ 158 0000000E E7FE B .
+ 159 00000010 ENDP
+ 161 00000010 UsageFault_Handler
+ PROC
+ 162 00000010 EXPORT UsageFault_Handler [WEA
+K]
+ 163 00000010 E7FE B .
+ 164 00000012 ENDP
+ 165 00000012 SVC_Handler
+
+
+
+ARM Macro Assembler Page 5
+
+
+ PROC
+ 166 00000012 EXPORT SVC_Handler [WEA
+K]
+ 167 00000012 E7FE B .
+ 168 00000014 ENDP
+ 170 00000014 DebugMon_Handler
+ PROC
+ 171 00000014 EXPORT DebugMon_Handler [WEA
+K]
+ 172 00000014 E7FE B .
+ 173 00000016 ENDP
+ 174 00000016 PendSV_Handler
+ PROC
+ 175 00000016 EXPORT PendSV_Handler [WEA
+K]
+ 176 00000016 E7FE B .
+ 177 00000018 ENDP
+ 178 00000018 SysTick_Handler
+ PROC
+ 179 00000018 EXPORT SysTick_Handler [WEA
+K]
+ 180 00000018 E7FE B .
+ 181 0000001A ENDP
+ 182 0000001A
+ 183 0000001A Default_Handler
+ PROC
+ 184 0000001A
+ 185 0000001A EXPORT WWDG_IRQHandler [WEA
+K]
+ 186 0000001A EXPORT PVD_IRQHandler [WEA
+K]
+ 187 0000001A EXPORT TAMPER_IRQHandler [WEA
+K]
+ 188 0000001A EXPORT RTC_IRQHandler [WEA
+K]
+ 189 0000001A EXPORT FLASH_IRQHandler [WEA
+K]
+ 190 0000001A EXPORT RCC_IRQHandler [WEA
+K]
+ 191 0000001A EXPORT EXTI0_IRQHandler [WEA
+K]
+ 192 0000001A EXPORT EXTI1_IRQHandler [WEA
+K]
+ 193 0000001A EXPORT EXTI2_IRQHandler [WEA
+K]
+ 194 0000001A EXPORT EXTI3_IRQHandler [WEA
+K]
+ 195 0000001A EXPORT EXTI4_IRQHandler [WEA
+K]
+ 196 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA
+K]
+ 197 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA
+K]
+ 198 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA
+K]
+ 199 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA
+K]
+ 200 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA
+K]
+
+
+
+ARM Macro Assembler Page 6
+
+
+ 201 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA
+K]
+ 202 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA
+K]
+ 203 0000001A EXPORT ADC1_2_IRQHandler [WEA
+K]
+ 204 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA
+K]
+ 205 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA
+K]
+ 206 0000001A EXPORT CAN1_RX1_IRQHandler [WEA
+K]
+ 207 0000001A EXPORT CAN1_SCE_IRQHandler [WEA
+K]
+ 208 0000001A EXPORT EXTI9_5_IRQHandler [WEA
+K]
+ 209 0000001A EXPORT TIM1_BRK_IRQHandler [WEA
+K]
+ 210 0000001A EXPORT TIM1_UP_IRQHandler [WEA
+K]
+ 211 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA
+K]
+ 212 0000001A EXPORT TIM1_CC_IRQHandler [WEA
+K]
+ 213 0000001A EXPORT TIM2_IRQHandler [WEA
+K]
+ 214 0000001A EXPORT TIM3_IRQHandler [WEA
+K]
+ 215 0000001A EXPORT TIM4_IRQHandler [WEA
+K]
+ 216 0000001A EXPORT I2C1_EV_IRQHandler [WEA
+K]
+ 217 0000001A EXPORT I2C1_ER_IRQHandler [WEA
+K]
+ 218 0000001A EXPORT I2C2_EV_IRQHandler [WEA
+K]
+ 219 0000001A EXPORT I2C2_ER_IRQHandler [WEA
+K]
+ 220 0000001A EXPORT SPI1_IRQHandler [WEA
+K]
+ 221 0000001A EXPORT SPI2_IRQHandler [WEA
+K]
+ 222 0000001A EXPORT USART1_IRQHandler [WEA
+K]
+ 223 0000001A EXPORT USART2_IRQHandler [WEA
+K]
+ 224 0000001A EXPORT USART3_IRQHandler [WEA
+K]
+ 225 0000001A EXPORT EXTI15_10_IRQHandler [WEA
+K]
+ 226 0000001A EXPORT RTCAlarm_IRQHandler [WEA
+K]
+ 227 0000001A EXPORT USBWakeUp_IRQHandler [WEA
+K]
+ 228 0000001A
+ 229 0000001A WWDG_IRQHandler
+ 230 0000001A PVD_IRQHandler
+ 231 0000001A TAMPER_IRQHandler
+ 232 0000001A RTC_IRQHandler
+
+
+
+ARM Macro Assembler Page 7
+
+
+ 233 0000001A FLASH_IRQHandler
+ 234 0000001A RCC_IRQHandler
+ 235 0000001A EXTI0_IRQHandler
+ 236 0000001A EXTI1_IRQHandler
+ 237 0000001A EXTI2_IRQHandler
+ 238 0000001A EXTI3_IRQHandler
+ 239 0000001A EXTI4_IRQHandler
+ 240 0000001A DMA1_Channel1_IRQHandler
+ 241 0000001A DMA1_Channel2_IRQHandler
+ 242 0000001A DMA1_Channel3_IRQHandler
+ 243 0000001A DMA1_Channel4_IRQHandler
+ 244 0000001A DMA1_Channel5_IRQHandler
+ 245 0000001A DMA1_Channel6_IRQHandler
+ 246 0000001A DMA1_Channel7_IRQHandler
+ 247 0000001A ADC1_2_IRQHandler
+ 248 0000001A USB_HP_CAN1_TX_IRQHandler
+ 249 0000001A USB_LP_CAN1_RX0_IRQHandler
+ 250 0000001A CAN1_RX1_IRQHandler
+ 251 0000001A CAN1_SCE_IRQHandler
+ 252 0000001A EXTI9_5_IRQHandler
+ 253 0000001A TIM1_BRK_IRQHandler
+ 254 0000001A TIM1_UP_IRQHandler
+ 255 0000001A TIM1_TRG_COM_IRQHandler
+ 256 0000001A TIM1_CC_IRQHandler
+ 257 0000001A TIM2_IRQHandler
+ 258 0000001A TIM3_IRQHandler
+ 259 0000001A TIM4_IRQHandler
+ 260 0000001A I2C1_EV_IRQHandler
+ 261 0000001A I2C1_ER_IRQHandler
+ 262 0000001A I2C2_EV_IRQHandler
+ 263 0000001A I2C2_ER_IRQHandler
+ 264 0000001A SPI1_IRQHandler
+ 265 0000001A SPI2_IRQHandler
+ 266 0000001A USART1_IRQHandler
+ 267 0000001A USART2_IRQHandler
+ 268 0000001A USART3_IRQHandler
+ 269 0000001A EXTI15_10_IRQHandler
+ 270 0000001A RTCAlarm_IRQHandler
+ 271 0000001A USBWakeUp_IRQHandler
+ 272 0000001A
+ 273 0000001A E7FE B .
+ 274 0000001C
+ 275 0000001C ENDP
+ 276 0000001C
+ 277 0000001C ALIGN
+ 278 0000001C
+ 279 0000001C ;*******************************************************
+ ************************
+ 280 0000001C ; User Stack and Heap initialization
+ 281 0000001C ;*******************************************************
+ ************************
+ 282 0000001C IF :DEF:__MICROLIB
+ 289 0000001C
+ 290 0000001C IMPORT __use_two_region_memory
+ 291 0000001C EXPORT __user_initial_stackheap
+ 292 0000001C
+ 293 0000001C __user_initial_stackheap
+ 294 0000001C
+ 295 0000001C 4804 LDR R0, = Heap_Mem
+
+
+
+ARM Macro Assembler Page 8
+
+
+ 296 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size)
+ 297 00000020 4A05 LDR R2, = (Heap_Mem + Heap_Size)
+ 298 00000022 4B06 LDR R3, = Stack_Mem
+ 299 00000024 4770 BX LR
+ 300 00000026
+ 301 00000026 00 00 ALIGN
+ 302 00000028
+ 303 00000028 ENDIF
+ 304 00000028
+ 305 00000028 END
+ 00000000
+ 00000000
+ 00000000
+ 00000400
+ 00000200
+ 00000000
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
+ork --depend=..\obj\startup_stm32f10x_md.d -o..\obj\startup_stm32f10x_md.o -ID:
+\Keil_v5\ARM\RV31\INC -ID:\Keil_v5\ARM\CMSIS\Include -ID:\Keil_v5\ARM\Inc\ST\ST
+M32F10x --predefine="__UVISION_VERSION SETA 518" --list=.\startup_stm32f10x_md.
+lst ..\CORE\startup_stm32f10x_md.s
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+STACK 00000000
+
+Symbol: STACK
+ Definitions
+ At line 35 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: STACK unused
+Stack_Mem 00000000
+
+Symbol: Stack_Mem
+ Definitions
+ At line 36 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 296 in file ..\CORE\startup_stm32f10x_md.s
+ At line 298 in file ..\CORE\startup_stm32f10x_md.s
+
+__initial_sp 00000400
+
+Symbol: __initial_sp
+ Definitions
+ At line 37 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 61 in file ..\CORE\startup_stm32f10x_md.s
+Comment: __initial_sp used once
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+HEAP 00000000
+
+Symbol: HEAP
+ Definitions
+ At line 46 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: HEAP unused
+Heap_Mem 00000000
+
+Symbol: Heap_Mem
+ Definitions
+ At line 48 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 295 in file ..\CORE\startup_stm32f10x_md.s
+ At line 297 in file ..\CORE\startup_stm32f10x_md.s
+
+__heap_base 00000000
+
+Symbol: __heap_base
+ Definitions
+ At line 47 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: __heap_base unused
+__heap_limit 00000200
+
+Symbol: __heap_limit
+ Definitions
+ At line 49 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: __heap_limit unused
+4 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+RESET 00000000
+
+Symbol: RESET
+ Definitions
+ At line 56 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: RESET unused
+__Vectors 00000000
+
+Symbol: __Vectors
+ Definitions
+ At line 61 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 57 in file ..\CORE\startup_stm32f10x_md.s
+ At line 124 in file ..\CORE\startup_stm32f10x_md.s
+
+__Vectors_End 000000EC
+
+Symbol: __Vectors_End
+ Definitions
+ At line 122 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 58 in file ..\CORE\startup_stm32f10x_md.s
+ At line 124 in file ..\CORE\startup_stm32f10x_md.s
+
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.text 00000000
+
+Symbol: .text
+ Definitions
+ At line 126 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: .text unused
+ADC1_2_IRQHandler 0000001A
+
+Symbol: ADC1_2_IRQHandler
+ Definitions
+ At line 247 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 97 in file ..\CORE\startup_stm32f10x_md.s
+ At line 203 in file ..\CORE\startup_stm32f10x_md.s
+
+BusFault_Handler 0000000E
+
+Symbol: BusFault_Handler
+ Definitions
+ At line 156 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 66 in file ..\CORE\startup_stm32f10x_md.s
+ At line 157 in file ..\CORE\startup_stm32f10x_md.s
+
+CAN1_RX1_IRQHandler 0000001A
+
+Symbol: CAN1_RX1_IRQHandler
+ Definitions
+ At line 250 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 100 in file ..\CORE\startup_stm32f10x_md.s
+ At line 206 in file ..\CORE\startup_stm32f10x_md.s
+
+CAN1_SCE_IRQHandler 0000001A
+
+Symbol: CAN1_SCE_IRQHandler
+ Definitions
+ At line 251 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 101 in file ..\CORE\startup_stm32f10x_md.s
+ At line 207 in file ..\CORE\startup_stm32f10x_md.s
+
+DMA1_Channel1_IRQHandler 0000001A
+
+Symbol: DMA1_Channel1_IRQHandler
+ Definitions
+ At line 240 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 90 in file ..\CORE\startup_stm32f10x_md.s
+ At line 196 in file ..\CORE\startup_stm32f10x_md.s
+
+DMA1_Channel2_IRQHandler 0000001A
+
+Symbol: DMA1_Channel2_IRQHandler
+ Definitions
+ At line 241 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+
+
+
+ARM Macro Assembler Page 2 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 91 in file ..\CORE\startup_stm32f10x_md.s
+ At line 197 in file ..\CORE\startup_stm32f10x_md.s
+
+DMA1_Channel3_IRQHandler 0000001A
+
+Symbol: DMA1_Channel3_IRQHandler
+ Definitions
+ At line 242 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 92 in file ..\CORE\startup_stm32f10x_md.s
+ At line 198 in file ..\CORE\startup_stm32f10x_md.s
+
+DMA1_Channel4_IRQHandler 0000001A
+
+Symbol: DMA1_Channel4_IRQHandler
+ Definitions
+ At line 243 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 93 in file ..\CORE\startup_stm32f10x_md.s
+ At line 199 in file ..\CORE\startup_stm32f10x_md.s
+
+DMA1_Channel5_IRQHandler 0000001A
+
+Symbol: DMA1_Channel5_IRQHandler
+ Definitions
+ At line 244 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 94 in file ..\CORE\startup_stm32f10x_md.s
+ At line 200 in file ..\CORE\startup_stm32f10x_md.s
+
+DMA1_Channel6_IRQHandler 0000001A
+
+Symbol: DMA1_Channel6_IRQHandler
+ Definitions
+ At line 245 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 95 in file ..\CORE\startup_stm32f10x_md.s
+ At line 201 in file ..\CORE\startup_stm32f10x_md.s
+
+DMA1_Channel7_IRQHandler 0000001A
+
+Symbol: DMA1_Channel7_IRQHandler
+ Definitions
+ At line 246 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 96 in file ..\CORE\startup_stm32f10x_md.s
+ At line 202 in file ..\CORE\startup_stm32f10x_md.s
+
+DebugMon_Handler 00000014
+
+Symbol: DebugMon_Handler
+ Definitions
+ At line 170 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 73 in file ..\CORE\startup_stm32f10x_md.s
+ At line 171 in file ..\CORE\startup_stm32f10x_md.s
+
+Default_Handler 0000001A
+
+
+
+
+ARM Macro Assembler Page 3 Alphabetic symbol ordering
+Relocatable symbols
+
+Symbol: Default_Handler
+ Definitions
+ At line 183 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: Default_Handler unused
+EXTI0_IRQHandler 0000001A
+
+Symbol: EXTI0_IRQHandler
+ Definitions
+ At line 235 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 85 in file ..\CORE\startup_stm32f10x_md.s
+ At line 191 in file ..\CORE\startup_stm32f10x_md.s
+
+EXTI15_10_IRQHandler 0000001A
+
+Symbol: EXTI15_10_IRQHandler
+ Definitions
+ At line 269 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 119 in file ..\CORE\startup_stm32f10x_md.s
+ At line 225 in file ..\CORE\startup_stm32f10x_md.s
+
+EXTI1_IRQHandler 0000001A
+
+Symbol: EXTI1_IRQHandler
+ Definitions
+ At line 236 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 86 in file ..\CORE\startup_stm32f10x_md.s
+ At line 192 in file ..\CORE\startup_stm32f10x_md.s
+
+EXTI2_IRQHandler 0000001A
+
+Symbol: EXTI2_IRQHandler
+ Definitions
+ At line 237 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 87 in file ..\CORE\startup_stm32f10x_md.s
+ At line 193 in file ..\CORE\startup_stm32f10x_md.s
+
+EXTI3_IRQHandler 0000001A
+
+Symbol: EXTI3_IRQHandler
+ Definitions
+ At line 238 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 88 in file ..\CORE\startup_stm32f10x_md.s
+ At line 194 in file ..\CORE\startup_stm32f10x_md.s
+
+EXTI4_IRQHandler 0000001A
+
+Symbol: EXTI4_IRQHandler
+ Definitions
+ At line 239 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 89 in file ..\CORE\startup_stm32f10x_md.s
+ At line 195 in file ..\CORE\startup_stm32f10x_md.s
+
+
+
+ARM Macro Assembler Page 4 Alphabetic symbol ordering
+Relocatable symbols
+
+
+EXTI9_5_IRQHandler 0000001A
+
+Symbol: EXTI9_5_IRQHandler
+ Definitions
+ At line 252 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 102 in file ..\CORE\startup_stm32f10x_md.s
+ At line 208 in file ..\CORE\startup_stm32f10x_md.s
+
+FLASH_IRQHandler 0000001A
+
+Symbol: FLASH_IRQHandler
+ Definitions
+ At line 233 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 83 in file ..\CORE\startup_stm32f10x_md.s
+ At line 189 in file ..\CORE\startup_stm32f10x_md.s
+
+HardFault_Handler 0000000A
+
+Symbol: HardFault_Handler
+ Definitions
+ At line 146 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 64 in file ..\CORE\startup_stm32f10x_md.s
+ At line 147 in file ..\CORE\startup_stm32f10x_md.s
+
+I2C1_ER_IRQHandler 0000001A
+
+Symbol: I2C1_ER_IRQHandler
+ Definitions
+ At line 261 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 111 in file ..\CORE\startup_stm32f10x_md.s
+ At line 217 in file ..\CORE\startup_stm32f10x_md.s
+
+I2C1_EV_IRQHandler 0000001A
+
+Symbol: I2C1_EV_IRQHandler
+ Definitions
+ At line 260 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 110 in file ..\CORE\startup_stm32f10x_md.s
+ At line 216 in file ..\CORE\startup_stm32f10x_md.s
+
+I2C2_ER_IRQHandler 0000001A
+
+Symbol: I2C2_ER_IRQHandler
+ Definitions
+ At line 263 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 113 in file ..\CORE\startup_stm32f10x_md.s
+ At line 219 in file ..\CORE\startup_stm32f10x_md.s
+
+I2C2_EV_IRQHandler 0000001A
+
+Symbol: I2C2_EV_IRQHandler
+ Definitions
+
+
+
+ARM Macro Assembler Page 5 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 262 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 112 in file ..\CORE\startup_stm32f10x_md.s
+ At line 218 in file ..\CORE\startup_stm32f10x_md.s
+
+MemManage_Handler 0000000C
+
+Symbol: MemManage_Handler
+ Definitions
+ At line 151 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 65 in file ..\CORE\startup_stm32f10x_md.s
+ At line 152 in file ..\CORE\startup_stm32f10x_md.s
+
+NMI_Handler 00000008
+
+Symbol: NMI_Handler
+ Definitions
+ At line 141 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 63 in file ..\CORE\startup_stm32f10x_md.s
+ At line 142 in file ..\CORE\startup_stm32f10x_md.s
+
+PVD_IRQHandler 0000001A
+
+Symbol: PVD_IRQHandler
+ Definitions
+ At line 230 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 80 in file ..\CORE\startup_stm32f10x_md.s
+ At line 186 in file ..\CORE\startup_stm32f10x_md.s
+
+PendSV_Handler 00000016
+
+Symbol: PendSV_Handler
+ Definitions
+ At line 174 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 75 in file ..\CORE\startup_stm32f10x_md.s
+ At line 175 in file ..\CORE\startup_stm32f10x_md.s
+
+RCC_IRQHandler 0000001A
+
+Symbol: RCC_IRQHandler
+ Definitions
+ At line 234 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 84 in file ..\CORE\startup_stm32f10x_md.s
+ At line 190 in file ..\CORE\startup_stm32f10x_md.s
+
+RTCAlarm_IRQHandler 0000001A
+
+Symbol: RTCAlarm_IRQHandler
+ Definitions
+ At line 270 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 120 in file ..\CORE\startup_stm32f10x_md.s
+ At line 226 in file ..\CORE\startup_stm32f10x_md.s
+
+
+
+
+ARM Macro Assembler Page 6 Alphabetic symbol ordering
+Relocatable symbols
+
+RTC_IRQHandler 0000001A
+
+Symbol: RTC_IRQHandler
+ Definitions
+ At line 232 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 82 in file ..\CORE\startup_stm32f10x_md.s
+ At line 188 in file ..\CORE\startup_stm32f10x_md.s
+
+Reset_Handler 00000000
+
+Symbol: Reset_Handler
+ Definitions
+ At line 129 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 62 in file ..\CORE\startup_stm32f10x_md.s
+ At line 130 in file ..\CORE\startup_stm32f10x_md.s
+
+SPI1_IRQHandler 0000001A
+
+Symbol: SPI1_IRQHandler
+ Definitions
+ At line 264 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 114 in file ..\CORE\startup_stm32f10x_md.s
+ At line 220 in file ..\CORE\startup_stm32f10x_md.s
+
+SPI2_IRQHandler 0000001A
+
+Symbol: SPI2_IRQHandler
+ Definitions
+ At line 265 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 115 in file ..\CORE\startup_stm32f10x_md.s
+ At line 221 in file ..\CORE\startup_stm32f10x_md.s
+
+SVC_Handler 00000012
+
+Symbol: SVC_Handler
+ Definitions
+ At line 165 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 72 in file ..\CORE\startup_stm32f10x_md.s
+ At line 166 in file ..\CORE\startup_stm32f10x_md.s
+
+SysTick_Handler 00000018
+
+Symbol: SysTick_Handler
+ Definitions
+ At line 178 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 76 in file ..\CORE\startup_stm32f10x_md.s
+ At line 179 in file ..\CORE\startup_stm32f10x_md.s
+
+TAMPER_IRQHandler 0000001A
+
+Symbol: TAMPER_IRQHandler
+ Definitions
+ At line 231 in file ..\CORE\startup_stm32f10x_md.s
+
+
+
+ARM Macro Assembler Page 7 Alphabetic symbol ordering
+Relocatable symbols
+
+ Uses
+ At line 81 in file ..\CORE\startup_stm32f10x_md.s
+ At line 187 in file ..\CORE\startup_stm32f10x_md.s
+
+TIM1_BRK_IRQHandler 0000001A
+
+Symbol: TIM1_BRK_IRQHandler
+ Definitions
+ At line 253 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 103 in file ..\CORE\startup_stm32f10x_md.s
+ At line 209 in file ..\CORE\startup_stm32f10x_md.s
+
+TIM1_CC_IRQHandler 0000001A
+
+Symbol: TIM1_CC_IRQHandler
+ Definitions
+ At line 256 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 106 in file ..\CORE\startup_stm32f10x_md.s
+ At line 212 in file ..\CORE\startup_stm32f10x_md.s
+
+TIM1_TRG_COM_IRQHandler 0000001A
+
+Symbol: TIM1_TRG_COM_IRQHandler
+ Definitions
+ At line 255 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 105 in file ..\CORE\startup_stm32f10x_md.s
+ At line 211 in file ..\CORE\startup_stm32f10x_md.s
+
+TIM1_UP_IRQHandler 0000001A
+
+Symbol: TIM1_UP_IRQHandler
+ Definitions
+ At line 254 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 104 in file ..\CORE\startup_stm32f10x_md.s
+ At line 210 in file ..\CORE\startup_stm32f10x_md.s
+
+TIM2_IRQHandler 0000001A
+
+Symbol: TIM2_IRQHandler
+ Definitions
+ At line 257 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 107 in file ..\CORE\startup_stm32f10x_md.s
+ At line 213 in file ..\CORE\startup_stm32f10x_md.s
+
+TIM3_IRQHandler 0000001A
+
+Symbol: TIM3_IRQHandler
+ Definitions
+ At line 258 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 108 in file ..\CORE\startup_stm32f10x_md.s
+ At line 214 in file ..\CORE\startup_stm32f10x_md.s
+
+TIM4_IRQHandler 0000001A
+
+
+
+ARM Macro Assembler Page 8 Alphabetic symbol ordering
+Relocatable symbols
+
+
+Symbol: TIM4_IRQHandler
+ Definitions
+ At line 259 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 109 in file ..\CORE\startup_stm32f10x_md.s
+ At line 215 in file ..\CORE\startup_stm32f10x_md.s
+
+USART1_IRQHandler 0000001A
+
+Symbol: USART1_IRQHandler
+ Definitions
+ At line 266 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 116 in file ..\CORE\startup_stm32f10x_md.s
+ At line 222 in file ..\CORE\startup_stm32f10x_md.s
+
+USART2_IRQHandler 0000001A
+
+Symbol: USART2_IRQHandler
+ Definitions
+ At line 267 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 117 in file ..\CORE\startup_stm32f10x_md.s
+ At line 223 in file ..\CORE\startup_stm32f10x_md.s
+
+USART3_IRQHandler 0000001A
+
+Symbol: USART3_IRQHandler
+ Definitions
+ At line 268 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 118 in file ..\CORE\startup_stm32f10x_md.s
+ At line 224 in file ..\CORE\startup_stm32f10x_md.s
+
+USBWakeUp_IRQHandler 0000001A
+
+Symbol: USBWakeUp_IRQHandler
+ Definitions
+ At line 271 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 121 in file ..\CORE\startup_stm32f10x_md.s
+ At line 227 in file ..\CORE\startup_stm32f10x_md.s
+
+USB_HP_CAN1_TX_IRQHandler 0000001A
+
+Symbol: USB_HP_CAN1_TX_IRQHandler
+ Definitions
+ At line 248 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 98 in file ..\CORE\startup_stm32f10x_md.s
+ At line 204 in file ..\CORE\startup_stm32f10x_md.s
+
+USB_LP_CAN1_RX0_IRQHandler 0000001A
+
+Symbol: USB_LP_CAN1_RX0_IRQHandler
+ Definitions
+ At line 249 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+
+
+
+ARM Macro Assembler Page 9 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 99 in file ..\CORE\startup_stm32f10x_md.s
+ At line 205 in file ..\CORE\startup_stm32f10x_md.s
+
+UsageFault_Handler 00000010
+
+Symbol: UsageFault_Handler
+ Definitions
+ At line 161 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 67 in file ..\CORE\startup_stm32f10x_md.s
+ At line 162 in file ..\CORE\startup_stm32f10x_md.s
+
+WWDG_IRQHandler 0000001A
+
+Symbol: WWDG_IRQHandler
+ Definitions
+ At line 229 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 79 in file ..\CORE\startup_stm32f10x_md.s
+ At line 185 in file ..\CORE\startup_stm32f10x_md.s
+
+__user_initial_stackheap 0000001C
+
+Symbol: __user_initial_stackheap
+ Definitions
+ At line 293 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 291 in file ..\CORE\startup_stm32f10x_md.s
+Comment: __user_initial_stackheap used once
+56 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+Heap_Size 00000200
+
+Symbol: Heap_Size
+ Definitions
+ At line 44 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 48 in file ..\CORE\startup_stm32f10x_md.s
+ At line 297 in file ..\CORE\startup_stm32f10x_md.s
+
+Stack_Size 00000400
+
+Symbol: Stack_Size
+ Definitions
+ At line 33 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 36 in file ..\CORE\startup_stm32f10x_md.s
+ At line 296 in file ..\CORE\startup_stm32f10x_md.s
+
+__Vectors_Size 000000EC
+
+Symbol: __Vectors_Size
+ Definitions
+ At line 124 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 59 in file ..\CORE\startup_stm32f10x_md.s
+Comment: __Vectors_Size used once
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+External symbols
+
+SystemInit 00000000
+
+Symbol: SystemInit
+ Definitions
+ At line 132 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 133 in file ..\CORE\startup_stm32f10x_md.s
+Comment: SystemInit used once
+__main 00000000
+
+Symbol: __main
+ Definitions
+ At line 131 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ At line 135 in file ..\CORE\startup_stm32f10x_md.s
+Comment: __main used once
+__use_two_region_memory 00000000
+
+Symbol: __use_two_region_memory
+ Definitions
+ At line 290 in file ..\CORE\startup_stm32f10x_md.s
+ Uses
+ None
+Comment: __use_two_region_memory unused
+3 symbols
+407 symbols in table
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x.h"
new file mode 100644
index 0000000..8bf7624
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x.h"
@@ -0,0 +1,8336 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F10x Connectivity line,
+ * High density, High density value line, Medium density,
+ * Medium density Value line, Low density, Low density Value line
+ * and XL-density devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripheral抯 drivers in application code(i.e.
+ * code will be based on direct access to peripheral抯 registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral抯 registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x
+ * @{
+ */
+
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
+ /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
+ /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
+ /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
+ /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
+ /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */
+ /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */
+ /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
+#endif
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash
+ memory density ranges between 16 and 32 Kbytes.
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Medium-density value line devices are STM32F100xx microcontrollers where the
+ Flash memory density ranges between 64 and 128 Kbytes.
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where
+ the Flash memory density ranges between 256 and 512 Kbytes.
+ - High-density value line devices are STM32F100xx microcontrollers where the
+ Flash memory density ranges between 256 and 512 Kbytes.
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
+ the Flash memory density ranges between 512 and 1024 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+ */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
+#endif
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_VALUE
+ #ifdef STM32F10X_CL
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #else
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_VALUE */
+
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+
+#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+
+/**
+ * @brief STM32F10x Standard Peripheral Library version number
+ */
+#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32F10X_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+#ifdef STM32F10X_XL
+ #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
+#else
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
+#endif /* STM32F10X_XL */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+
+#ifdef STM32F10X_LD
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_LD */
+
+#ifdef STM32F10X_LD_VL
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */
+#endif /* STM32F10X_LD_VL */
+
+#ifdef STM32F10X_MD
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_MD */
+
+#ifdef STM32F10X_MD_VL
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */
+#endif /* STM32F10X_MD_VL */
+
+#ifdef STM32F10X_HD
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_HD_VL
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
+ TIM12_IRQn = 43, /*!< TIM12 global Interrupt */
+ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */
+ TIM14_IRQn = 45, /*!< TIM14 global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+ DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
+ mapped at position 60 only if the MISC_REMAP bit in
+ the AFIO_MAPR2 register is set) */
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_XL
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+#endif /* STM32F10X_XL */
+
+#ifdef STM32F10X_CL
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
+#endif /* STM32F10X_CL */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f10x.h"
+#include
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
+#define HSE_Value HSE_VALUE
+#define HSI_Value HSI_VALUE
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint16_t DR1;
+ uint16_t RESERVED1;
+ __IO uint16_t DR2;
+ uint16_t RESERVED2;
+ __IO uint16_t DR3;
+ uint16_t RESERVED3;
+ __IO uint16_t DR4;
+ uint16_t RESERVED4;
+ __IO uint16_t DR5;
+ uint16_t RESERVED5;
+ __IO uint16_t DR6;
+ uint16_t RESERVED6;
+ __IO uint16_t DR7;
+ uint16_t RESERVED7;
+ __IO uint16_t DR8;
+ uint16_t RESERVED8;
+ __IO uint16_t DR9;
+ uint16_t RESERVED9;
+ __IO uint16_t DR10;
+ uint16_t RESERVED10;
+ __IO uint16_t RTCCR;
+ uint16_t RESERVED11;
+ __IO uint16_t CR;
+ uint16_t RESERVED12;
+ __IO uint16_t CSR;
+ uint16_t RESERVED13[5];
+ __IO uint16_t DR11;
+ uint16_t RESERVED14;
+ __IO uint16_t DR12;
+ uint16_t RESERVED15;
+ __IO uint16_t DR13;
+ uint16_t RESERVED16;
+ __IO uint16_t DR14;
+ uint16_t RESERVED17;
+ __IO uint16_t DR15;
+ uint16_t RESERVED18;
+ __IO uint16_t DR16;
+ uint16_t RESERVED19;
+ __IO uint16_t DR17;
+ uint16_t RESERVED20;
+ __IO uint16_t DR18;
+ uint16_t RESERVED21;
+ __IO uint16_t DR19;
+ uint16_t RESERVED22;
+ __IO uint16_t DR20;
+ uint16_t RESERVED23;
+ __IO uint16_t DR21;
+ uint16_t RESERVED24;
+ __IO uint16_t DR22;
+ uint16_t RESERVED25;
+ __IO uint16_t DR23;
+ uint16_t RESERVED26;
+ __IO uint16_t DR24;
+ uint16_t RESERVED27;
+ __IO uint16_t DR25;
+ uint16_t RESERVED28;
+ __IO uint16_t DR26;
+ uint16_t RESERVED29;
+ __IO uint16_t DR27;
+ uint16_t RESERVED30;
+ __IO uint16_t DR28;
+ uint16_t RESERVED31;
+ __IO uint16_t DR29;
+ uint16_t RESERVED32;
+ __IO uint16_t DR30;
+ uint16_t RESERVED33;
+ __IO uint16_t DR31;
+ uint16_t RESERVED34;
+ __IO uint16_t DR32;
+ uint16_t RESERVED35;
+ __IO uint16_t DR33;
+ uint16_t RESERVED36;
+ __IO uint16_t DR34;
+ uint16_t RESERVED37;
+ __IO uint16_t DR35;
+ uint16_t RESERVED38;
+ __IO uint16_t DR36;
+ uint16_t RESERVED39;
+ __IO uint16_t DR37;
+ uint16_t RESERVED40;
+ __IO uint16_t DR38;
+ uint16_t RESERVED41;
+ __IO uint16_t DR39;
+ uint16_t RESERVED42;
+ __IO uint16_t DR40;
+ uint16_t RESERVED43;
+ __IO uint16_t DR41;
+ uint16_t RESERVED44;
+ __IO uint16_t DR42;
+ uint16_t RESERVED45;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+#ifndef STM32F10X_CL
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+#else
+ CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */
+} CAN_TypeDef;
+
+/**
+ * @brief Consumer Electronics Control (CEC)
+ */
+typedef struct
+{
+ __IO uint32_t CFGR;
+ __IO uint32_t OAR;
+ __IO uint32_t PRES;
+ __IO uint32_t ESR;
+ __IO uint32_t CSR;
+ __IO uint32_t TXD;
+ __IO uint32_t RXD;
+} CEC_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR;
+ __IO uint8_t IDR;
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CR;
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ __IO uint32_t SR;
+#endif
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ uint32_t RESERVED8[567];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ uint32_t RESERVED9[9];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+#ifdef STM32F10X_XL
+ uint32_t RESERVED1[8];
+ __IO uint32_t KEYR2;
+ uint32_t RESERVED2;
+ __IO uint32_t SR2;
+ __IO uint32_t CR2;
+ __IO uint32_t AR2;
+#endif /* STM32F10X_XL */
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2;
+ __IO uint32_t SR2;
+ __IO uint32_t PMEM2;
+ __IO uint32_t PATT2;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR2;
+} FSMC_Bank2_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR3;
+ __IO uint32_t SR3;
+ __IO uint32_t PMEM3;
+ __IO uint32_t PATT3;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR3;
+} FSMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+ uint32_t RESERVED0;
+ __IO uint32_t MAPR2;
+} AFIO_TypeDef;
+/**
+ * @brief Inter Integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t OAR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OAR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DR;
+ uint16_t RESERVED4;
+ __IO uint16_t SR1;
+ uint16_t RESERVED5;
+ __IO uint16_t SR2;
+ uint16_t RESERVED6;
+ __IO uint16_t CCR;
+ uint16_t RESERVED7;
+ __IO uint16_t TRISE;
+ uint16_t RESERVED8;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR;
+ __IO uint32_t PR;
+ __IO uint32_t RLR;
+ __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+
+#ifdef STM32F10X_CL
+ __IO uint32_t AHBRSTR;
+ __IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ uint32_t RESERVED0;
+ __IO uint32_t CFGR2;
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint16_t CRH;
+ uint16_t RESERVED0;
+ __IO uint16_t CRL;
+ uint16_t RESERVED1;
+ __IO uint16_t PRLH;
+ uint16_t RESERVED2;
+ __IO uint16_t PRLL;
+ uint16_t RESERVED3;
+ __IO uint16_t DIVH;
+ uint16_t RESERVED4;
+ __IO uint16_t DIVL;
+ uint16_t RESERVED5;
+ __IO uint16_t CNTH;
+ uint16_t RESERVED6;
+ __IO uint16_t CNTL;
+ uint16_t RESERVED7;
+ __IO uint16_t ALRH;
+ uint16_t RESERVED8;
+ __IO uint16_t ALRL;
+ uint16_t RESERVED9;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SR;
+ uint16_t RESERVED2;
+ __IO uint16_t DR;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPR;
+ uint16_t RESERVED4;
+ __IO uint16_t RXCRCR;
+ uint16_t RESERVED5;
+ __IO uint16_t TXCRCR;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFGR;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPR;
+ uint16_t RESERVED8;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SMCR;
+ uint16_t RESERVED2;
+ __IO uint16_t DIER;
+ uint16_t RESERVED3;
+ __IO uint16_t SR;
+ uint16_t RESERVED4;
+ __IO uint16_t EGR;
+ uint16_t RESERVED5;
+ __IO uint16_t CCMR1;
+ uint16_t RESERVED6;
+ __IO uint16_t CCMR2;
+ uint16_t RESERVED7;
+ __IO uint16_t CCER;
+ uint16_t RESERVED8;
+ __IO uint16_t CNT;
+ uint16_t RESERVED9;
+ __IO uint16_t PSC;
+ uint16_t RESERVED10;
+ __IO uint16_t ARR;
+ uint16_t RESERVED11;
+ __IO uint16_t RCR;
+ uint16_t RESERVED12;
+ __IO uint16_t CCR1;
+ uint16_t RESERVED13;
+ __IO uint16_t CCR2;
+ uint16_t RESERVED14;
+ __IO uint16_t CCR3;
+ uint16_t RESERVED15;
+ __IO uint16_t CCR4;
+ uint16_t RESERVED16;
+ __IO uint16_t BDTR;
+ uint16_t RESERVED17;
+ __IO uint16_t DCR;
+ uint16_t RESERVED18;
+ __IO uint16_t DMAR;
+ uint16_t RESERVED19;
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t SR;
+ uint16_t RESERVED0;
+ __IO uint16_t DR;
+ uint16_t RESERVED1;
+ __IO uint16_t BRR;
+ uint16_t RESERVED2;
+ __IO uint16_t CR1;
+ uint16_t RESERVED3;
+ __IO uint16_t CR2;
+ uint16_t RESERVED4;
+ __IO uint16_t CR3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTPR;
+ uint16_t RESERVED6;
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFR;
+ __IO uint32_t SR;
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
+
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
+#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
+#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
+#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
+#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+#ifdef STM32F10X_CL
+ #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
+ #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
+ #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
+ #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#ifdef STM32F10X_CL
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
+ #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+
+ #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+ #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+ #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
+ #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
+ #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#else
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+ #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+#ifdef STM32F10X_CL
+ #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
+ #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
+ #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
+ #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
+ #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
+ #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
+#endif
+
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
+ #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
+ #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
+#endif
+
+#ifdef STM32F10X_XL
+ #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */
+ #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */
+ #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */
+#endif /* STM32F10X_XL */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
+#endif
+
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+ #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+ #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
+ #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+ #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
+#endif /* STM32F10X_XL */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)
+ #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
+ #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
+ #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
+ #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
+ #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
+#endif /* STM32F10X_CL */
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
+#endif
+
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
+#endif
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
+ #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
+ #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */
+#endif
+
+#if defined (STM32F10X_HD_VL)
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
+#endif
+
+#ifdef STM32F10X_XL
+ #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */
+ #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */
+ #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */
+#endif
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
+#endif
+
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
+ #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+ #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+ #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+ #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
+ #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#endif
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+ #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
+#endif
+
+#ifdef STM32F10X_HD_VL
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#endif /* STM32F10X_HD_VL */
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
+#endif /* STM32F10X_CL */
+
+#ifdef STM32F10X_XL
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
+#endif /* STM32F10X_XL */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+#ifdef STM32F10X_CL
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+ #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
+ #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+ #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
+ #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+ #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+ #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
+ #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
+ #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
+ #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
+ #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
+ #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
+ #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
+ #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
+ #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
+ #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+ #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
+ #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
+ #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
+ #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
+ #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
+ #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
+ #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
+ #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
+ #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
+ #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
+
+ #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
+ #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+#endif
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+#ifdef STM32F10X_CL
+/*!< ETH_REMAP configuration */
+ #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+ #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+ #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+ #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+ #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+ #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+#endif
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
+#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
+#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
+#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
+#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
+#endif
+
+#ifdef STM32F10X_HD_VL
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */
+#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */
+#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */
+#endif
+
+#ifdef STM32F10X_XL
+/****************** Bit definition for AFIO_MAPR2 register ******************/
+#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */
+#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */
+#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
+#endif
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR1 register *******************/
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR2 register *******************/
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR3 register *******************/
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CCR4 register *******************/
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CCR5 register *******************/
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CCR6 register *******************/
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR7 register *******************/
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/****************** Bit definition for DMA_CNDTR1 register ******************/
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR2 register ******************/
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR3 register ******************/
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR4 register ******************/
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR5 register ******************/
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR6 register ******************/
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR7 register ******************/
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR1 register *******************/
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR2 register *******************/
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR3 register *******************/
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR4 register *******************/
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR5 register *******************/
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR6 register *******************/
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR7 register *******************/
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR1 register *******************/
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR2 register *******************/
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR3 register *******************/
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+
+/****************** Bit definition for DMA_CMAR4 register *******************/
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR5 register *******************/
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR6 register *******************/
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR7 register *******************/
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */
+#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */
+#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */
+#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */
+#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* CEC */
+/* */
+/******************************************************************************/
+/******************** Bit definition for CEC_CFGR register ******************/
+#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
+#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
+#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
+
+/******************** Bit definition for CEC_OAR register ******************/
+#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
+#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
+
+/******************** Bit definition for CEC_PRES register ******************/
+#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
+
+/******************** Bit definition for CEC_ESR register ******************/
+#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
+#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
+#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
+#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
+#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
+#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
+#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */
+
+/******************** Bit definition for CEC_CSR register ******************/
+#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
+#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
+#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
+#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
+#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
+#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
+#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
+#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
+
+/******************** Bit definition for CEC_TXD register ******************/
+#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
+
+/******************** Bit definition for CEC_RXD register ******************/
+#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */
+
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */
+#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for RTC_CRH register ********************/
+#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */
+#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */
+#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */
+
+/******************* Bit definition for RTC_CRL register ********************/
+#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */
+#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */
+#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */
+#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */
+#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */
+#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */
+
+/******************* Bit definition for RTC_PRLH register *******************/
+#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */
+
+/******************* Bit definition for RTC_PRLL register *******************/
+#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */
+
+/******************* Bit definition for RTC_DIVH register *******************/
+#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */
+
+/******************* Bit definition for RTC_DIVL register *******************/
+#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */
+
+/******************* Bit definition for RTC_CNTH register *******************/
+#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */
+
+/******************* Bit definition for RTC_CNTL register *******************/
+#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */
+
+/******************* Bit definition for RTC_ALRH register *******************/
+#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */
+
+/******************* Bit definition for RTC_ALRL register *******************/
+#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_PCR2 register *******************/
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */
+
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/****************** Bit definition for FSMC_PCR3 register *******************/
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */
+
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/****************** Bit definition for FSMC_PCR4 register *******************/
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */
+
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */
+
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+
+/******************* Bit definition for FSMC_SR2 register *******************/
+#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
+
+/******************* Bit definition for FSMC_SR3 register *******************/
+#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
+
+/******************* Bit definition for FSMC_SR4 register *******************/
+#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */
+#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */
+#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */
+#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */
+#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */
+
+/****************** Bit definition for FSMC_PMEM2 register ******************/
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM3 register ******************/
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PMEM4 register ******************/
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PATT2 register ******************/
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PATT3 register ******************/
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PATT4 register ******************/
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_PIO4 register *******************/
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */
+
+/****************** Bit definition for FSMC_ECCR2 register ******************/
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/****************** Bit definition for FSMC_ECCR3 register ******************/
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* USB Device FS */
+/* */
+/******************************************************************************/
+
+/*!< Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */
+
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */
+
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */
+
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */
+
+/*!< Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+
+/*!< CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */
+
+/*!< Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */
+
+/*!< CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Debug MCU */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */
+#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */
+
+#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */
+#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */
+#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */
+#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */
+#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */
+
+#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */
+#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */
+#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */
+#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for FLASH_RDP register *******************/
+#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for FLASH_USER register ******************/
+#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_Data0 register *****************/
+#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */
+#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_Data1 register *****************/
+#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */
+#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+#ifdef STM32F10X_CL
+/******************************************************************************/
+/* Ethernet MAC Registers bits definitions */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
+ #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+ a transmission attempt during retries after a collision: 0 =< r <2^k */
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
+ RSVD - Filter1 Command - RSVD - Filter0 Command
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
+
+/******************************************************************************/
+/* Ethernet MMC Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Contol Register */
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/* Ethernet PTP Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
+
+/******************************************************************************/
+/* Ethernet DMA Registers bits definition */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
+ /* combination with EBS[2:0] for GetFlagStatus function */
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32f10x_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_conf.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_conf.h"
new file mode 100644
index 0000000..9fd706d
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_conf.h"
@@ -0,0 +1,77 @@
+/**
+ ******************************************************************************
+ * @file GPIO/IOToggle/stm32f10x_conf.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief Library configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "stm32f10x_adc.h"
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_can.h"
+#include "stm32f10x_cec.h"
+#include "stm32f10x_crc.h"
+#include "stm32f10x_dac.h"
+#include "stm32f10x_dbgmcu.h"
+#include "stm32f10x_dma.h"
+#include "stm32f10x_exti.h"
+#include "stm32f10x_flash.h"
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_iwdg.h"
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+#include "stm32f10x_rtc.h"
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_spi.h"
+#include "stm32f10x_tim.h"
+#include "stm32f10x_usart.h"
+#include "stm32f10x_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the
+ Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT 1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function which reports
+ * the name of the source file and the source line number of the call
+ * that failed. If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_it.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_it.c"
new file mode 100644
index 0000000..bca289e
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_it.c"
@@ -0,0 +1,87 @@
+/**
+ ******************************************************************************
+ * @file GPIO/IOToggle/stm32f10x_it.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief Main Interrupt Service Routines.
+ * This file provides template for all exceptions handler and peripherals
+ * interrupt service routine.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+
+
+
+void NMI_Handler(void)
+{
+}
+
+void HardFault_Handler(void)
+{
+ /* Go to infinite loop when Hard Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+void MemManage_Handler(void)
+{
+ /* Go to infinite loop when Memory Manage exception occurs */
+ while (1)
+ {
+ }
+}
+
+
+void BusFault_Handler(void)
+{
+ /* Go to infinite loop when Bus Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+void UsageFault_Handler(void)
+{
+ /* Go to infinite loop when Usage Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+void SVC_Handler(void)
+{
+}
+
+void DebugMon_Handler(void)
+{
+}
+
+void PendSV_Handler(void)
+{
+}
+
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/* STM32F10x Peripherals Interrupt Handlers */
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
+/* available peripheral interrupt handler's name please refer to the startup */
+/* file (startup_stm32f10x_xx.s). */
+/******************************************************************************/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_it.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_it.h"
new file mode 100644
index 0000000..900c7c1
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/stm32f10x_it.h"
@@ -0,0 +1,46 @@
+/**
+ ******************************************************************************
+ * @file GPIO/IOToggle/stm32f10x_it.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.c"
new file mode 100644
index 0000000..4242895
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.c"
@@ -0,0 +1,1094 @@
+/**
+ ******************************************************************************
+ * @file GPIO/IOToggle/system_stm32f10x.c
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 08-April-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * factors, AHB/APBx prescalers and Flash settings).
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f10x_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+ * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
+ * When HSE is used as system clock source, directly or through PLL, and you
+ * are using different crystal you have to adapt the HSE value to your own
+ * configuration.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/** @addtogroup STM32F10x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f10x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your device's
+ maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume that:
+ - For Low, Medium and High density Value line devices an external 8MHz
+ crystal is used to drive the System clock.
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to drive
+ the System clock.
+ If you are using different crystal you have to adapt those functions accordingly.
+ */
+
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+ #define SYSCLK_FREQ_24MHz 24000000
+#else
+/* #define SYSCLK_FREQ_HSE HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_36MHz 36000000 */
+/* #define SYSCLK_FREQ_48MHz 48000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
+#define SYSCLK_FREQ_72MHz 72000000
+#endif
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
+ STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+/* #define DATA_IN_ExtSRAM */
+#endif
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+ uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+ uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+ uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+ static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+ static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+ static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+ static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+ static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+ static void SetSysClockTo72(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifdef STM32F10X_CL
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#else
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
+ #ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+ #endif /* DATA_IN_ExtSRAM */
+#endif
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+ * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
+ * that HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ uint32_t prediv1factor = 0;
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ #else
+ /* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ SystemCoreClock = HSE_VALUE * pllmull;
+ }
+ #endif
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+ SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+ SetSysClockTo72();
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ source (default after reset) */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x44444B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+ if (HSE_VALUE <= 24000000)
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+ }
+ else
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+ }
+#endif /* STM32F10X_CL */
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo24(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#endif
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo36(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+#else
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo48(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo56(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL7);
+#else
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo72(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+#else
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.crf"
new file mode 100644
index 0000000..ae38235
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.d"
new file mode 100644
index 0000000..d25f3a5
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.d"
@@ -0,0 +1,30 @@
+system_stm32f10x.o: system_stm32f10x.c
+system_stm32f10x.o: stm32f10x.h
+system_stm32f10x.o: ..\CORE\core_cm3.h
+system_stm32f10x.o: C:\Keil\ARM\ARMCC\bin\..\include\stdint.h
+system_stm32f10x.o: system_stm32f10x.h
+system_stm32f10x.o: stm32f10x_conf.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+system_stm32f10x.o: ..\USER\stm32f10x.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+system_stm32f10x.o: ..\STM32F10x_FWLib\inc\misc.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.h"
new file mode 100644
index 0000000..54bc1ab
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.h"
@@ -0,0 +1,98 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.5.0
+ * @date 11-March-2011
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2011 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.o"
new file mode 100644
index 0000000..585f97e
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/system_stm32f10x.o" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.c" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.c"
new file mode 100644
index 0000000..76fd446
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.c"
@@ -0,0 +1,250 @@
+#include "lcd.h"
+#include "delay.h"
+#include "gui.h"
+#include "test.h"
+#include "touch.h"
+#include "key.h"
+#include "led.h"
+#include "pic.h"
+//////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////
+//========================variable==========================//
+u16 ColorTab[5]={BRED,YELLOW,RED,GREEN,BLUE};//定义颜色数组
+//=====================end of variable======================//
+
+//******************************************************************
+//函数名： DrawTestPage
+//功能： 绘制测试界面
+//输入参数：str :字符串指针
+//返回值： 无
+//修改记录：
+//******************************************************************
+void DrawTestPage(u8 *str)
+{
+//绘制固定栏up
+LCD_Fill(0,0,lcddev.width,20,BLUE);
+//绘制固定栏down
+LCD_Fill(0,lcddev.height-20,lcddev.width,lcddev.height,BLUE);
+POINT_COLOR=WHITE;
+Gui_StrCenter(0,2,WHITE,BLUE,str,16,1);//居中显示
+Gui_StrCenter(0,lcddev.height-18,WHITE,BLUE,"QDtech版权所有",16,1);//居中显示
+//绘制测试区域
+LCD_Fill(0,20,lcddev.width,lcddev.height-20,BLACK);
+}
+
+//******************************************************************
+//函数名： main_test
+//功能： 绘制全动电子综合测试程序主界面
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void main_test(void)
+{
+ DrawTestPage("全动电子综合测试程序");
+
+ Gui_StrCenter(0,30,RED,BLUE,"全动电子",16,1);//居中显示
+ Gui_StrCenter(0,60,RED,BLUE,"综合测试程序",16,1);//居中显示
+ Gui_StrCenter(0,90,YELLOW,BLUE,"3.2' ILI9341 240X320",16,1);//居中显示
+ Gui_StrCenter(0,120,BLUE,BLUE,"xiaoFeng@QDtech 2014-02-25",16,1);//居中显示
+ delay_ms(1500);
+ delay_ms(1500);
+}
+
+//******************************************************************
+//函数名： Test_Color
+//功能： 颜色填充测试，依次填充白色、黑色、红色、绿色、蓝色
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void Test_Color(void)
+{
+ DrawTestPage("测试1:纯色填充测试");
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,WHITE);
+ Show_Str(lcddev.width-50,30,BLUE,YELLOW,"White",16,1);delay_ms(500);
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,BLACK);
+ Show_Str(lcddev.width-50,30,BLUE,YELLOW,"Black",16,1);delay_ms(500);
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,RED);
+ Show_Str(lcddev.width-50,30,BLUE,YELLOW,"Red",16,1); delay_ms(500);
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,GREEN);
+ Show_Str(lcddev.width-50,30,BLUE,YELLOW,"Green",16,1);delay_ms(500);
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,BLUE);
+ Show_Str(lcddev.width-50,30,WHITE,YELLOW,"Blue",16,1);delay_ms(500);
+
+}
+
+//******************************************************************
+//函数名： Test_FillRec
+//功能： 矩形框显示和填充测试，依次显示粉红色、黄色、红色、绿色、蓝色矩形框，
+// 延时1500毫秒后，依次按照粉红色、黄色、红色、绿色、蓝色填充矩形框
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void Test_FillRec(void)
+{
+ u8 i=0;
+ DrawTestPage("测试2:GUI矩形填充测试");
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,WHITE);
+ for (i=0; i<5; i++)
+ {
+ LCD_DrawRectangle(lcddev.width/2-80+(i*15),lcddev.height/2-80+(i*15),lcddev.width/2-80+(i*15)+60,lcddev.height/2-80+(i*15)+60);
+ POINT_COLOR=ColorTab[i];
+ }
+ delay_ms(1500);
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,WHITE);
+ for (i=0; i<5; i++)
+ {
+ LCD_DrawFillRectangle(lcddev.width/2-80+(i*15),lcddev.height/2-80+(i*15),lcddev.width/2-80+(i*15)+60,lcddev.height/2-80+(i*15)+60);
+ POINT_COLOR=ColorTab[i];
+ }
+ delay_ms(1500);
+}
+
+//******************************************************************
+//函数名： Test_FillRec
+//功能： 圆形框显示和填充测试，依次显示粉红色、黄色、红色、绿色、蓝色圆形框，
+// 延时1500毫秒后，依次按照粉红色、黄色、红色、绿色、蓝色填充圆形框
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void Test_Circle(void)
+{
+ u8 i=0;
+ DrawTestPage("测试3:GUI画圆填充测试");
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,WHITE);
+ for (i=0; i<5; i++)
+ gui_circle(lcddev.width/2-80+(i*25),lcddev.height/2-50+(i*25),ColorTab[i],30,0);
+ delay_ms(1500);
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,WHITE);
+ for (i=0; i<5; i++)
+ gui_circle(lcddev.width/2-80+(i*25),lcddev.height/2-50+(i*25),ColorTab[i],30,1);
+ delay_ms(1500);
+}
+
+//******************************************************************
+//函数名： English_Font_test
+//功能： 英文显示测试
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void English_Font_test(void)
+{
+ DrawTestPage("测试4:英文显示测试");
+ POINT_COLOR=RED;
+ BACK_COLOR=BLUE;
+ LCD_ShowString(10,30,12,"6X12:abcdefghijklmnopqrstuvwxyz0123456789",0);
+ LCD_ShowString(10,45,12,"6X12:ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789",1);
+ LCD_ShowString(10,60,12,"6X12:~!@#$%^&*()_+{}:<>?/|-+.",0);
+ LCD_ShowString(10,80,16,"8X16:abcdefghijklmnopqrstuvwxyz0123456789",0);
+ LCD_ShowString(10,100,16,"8X16:ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789",1);
+ LCD_ShowString(10,120,16,"8X16:~!@#$%^&*()_+{}:<>?/|-+.",0);
+ delay_ms(1200);
+}
+
+//******************************************************************
+//函数名： Chinese_Font_test
+//功能： 中文显示测试
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void Chinese_Font_test(void)
+{
+ DrawTestPage("测试5:中文显示测试");
+ Show_Str(10,30,BLUE,YELLOW,"16X16:全动电子技术有限公司欢迎您",16,0);
+ Show_Str(10,50,BLUE,YELLOW,"16X16:Welcome全动电子",16,1);
+ Show_Str(10,70,BLUE,YELLOW,"24X24:深圳市中文测试",24,1);
+ Show_Str(10,100,BLUE,YELLOW,"32X32:字体测试",32,1);
+ delay_ms(1200);
+}
+
+//******************************************************************
+//函数名： Pic_test
+//功能： 图片显示测试，依次显示三幅40X40 QQ图像
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void Pic_test(void)
+{
+ DrawTestPage("测试6:图片显示测试");
+ LCD_Fill(0,20,lcddev.width,lcddev.height-20,WHITE);
+ Gui_Drawbmp16(30,30,gImage_qq);
+ Show_Str(30+12,75,BLUE,YELLOW,"QQ",16,1);
+ Gui_Drawbmp16(90,30,gImage_qq);
+ Show_Str(90+12,75,BLUE,YELLOW,"QQ",16,1);
+ Gui_Drawbmp16(150,30,gImage_qq);
+ Show_Str(150+12,75,BLUE,YELLOW,"QQ",16,1);
+ delay_ms(1200);
+}
+
+//******************************************************************
+//函数名： Touch_Test
+//功能： 触摸手写测试
+//输入参数：无
+//返回值： 无
+//修改记录：
+//******************************************************************
+void Touch_Test(void)
+{
+u8 key;
+ u8 i=0;
+ u16 j=0;
+ u16 colorTemp=0;
+ TP_Init();
+ KEY_Init();
+ TP_Adjust(); //强制执行一次屏幕校准 (适用于没有IIC存储触摸参数的用户)
+ DrawTestPage("测试7:Touch测试");
+ LCD_ShowString(lcddev.width-24,0,16,"RST",1);//显示清屏区域
+ LCD_Fill(lcddev.width-52,2,lcddev.width-50+20,18,RED);
+ POINT_COLOR=RED;
+ while(1)
+ {
+ key=KEY_Scan();
+ tp_dev.scan(0);
+ if(tp_dev.sta&TP_PRES_DOWN) //触摸屏被按下
+ {
+ if(tp_dev.x(lcddev.width-24)&&tp_dev.y<16)
+ {
+ DrawTestPage("测试7:Touch测试");//清除
+ LCD_ShowString(lcddev.width-24,0,16,"RST",1);//显示清屏区域
+ POINT_COLOR=colorTemp;
+ LCD_Fill(lcddev.width-52,2,lcddev.width-50+20,18,POINT_COLOR);
+ }
+ else if((tp_dev.x>(lcddev.width-60)&&tp_dev.x<(lcddev.width-50+20))&&tp_dev.y<20)
+ {
+ LCD_Fill(lcddev.width-52,2,lcddev.width-50+20,18,ColorTab[j%5]);
+ POINT_COLOR=ColorTab[(j++)%5];
+ colorTemp=POINT_COLOR;
+ delay_ms(10);
+ }
+
+ else TP_Draw_Big_Point(tp_dev.x,tp_dev.y,POINT_COLOR); //画图
+ }
+ }else delay_ms(10); //没有按键按下的时候
+ if(key==1) //KEY_RIGHT按下,则执行校准程序
+ {
+
+ LCD_Clear(WHITE);//清屏
+ TP_Adjust(); //屏幕校准
+ TP_Save_Adjdata();
+ DrawTestPage("测试7:Touch测试");
+ }
+ i++;
+ if(i==20)
+ {
+ i=0;
+ LED0=!LED0;
+ }
+ }
+}
+
+
+
+
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.crf" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.crf"
new file mode 100644
index 0000000..df4cd37
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.crf" differ
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.d" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.d"
new file mode 100644
index 0000000..3ae5aff
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.d"
@@ -0,0 +1,40 @@
+test.o: test.c
+test.o: ..\HARDWARE\LCD\lcd.h
+test.o: ..\SYSTEM\sys\sys.h
+test.o: ..\USER\stm32f10x.h
+test.o: ..\CORE\core_cm3.h
+test.o: C:\Keil\ARM\ARMCC\bin\..\include\stdint.h
+test.o: ..\USER\system_stm32f10x.h
+test.o: ..\USER\stm32f10x_conf.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_adc.h
+test.o: ..\USER\stm32f10x.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_bkp.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_can.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_cec.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_crc.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_dac.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_dbgmcu.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_dma.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_exti.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_flash.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_fsmc.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_gpio.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_i2c.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_iwdg.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_pwr.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_rcc.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_rtc.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_sdio.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_spi.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_tim.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_usart.h
+test.o: ..\STM32F10x_FWLib\inc\stm32f10x_wwdg.h
+test.o: ..\STM32F10x_FWLib\inc\misc.h
+test.o: C:\Keil\ARM\ARMCC\bin\..\include\stdlib.h
+test.o: ..\SYSTEM\delay\delay.h
+test.o: gui.h
+test.o: test.h
+test.o: ..\HARDWARE\TOUCH\touch.h
+test.o: ..\HARDWARE\KEY\key.h
+test.o: ..\HARDWARE\LED\led.h
+test.o: pic.h
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.h" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.h"
new file mode 100644
index 0000000..0345bc0
--- /dev/null
+++ "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.h"
@@ -0,0 +1,14 @@
+#ifndef __TEST_H__
+#define __TEST_H__
+
+void DrawTestPage(u8 *str);
+void Test_Color(void);
+void Test_FillRec(void);
+void Test_Circle(void);
+void English_Font_test(void);
+void Chinese_Font_test(void);
+void Pic_test(void);
+void Load_Drow_Dialog(void);
+void Touch_Test(void);
+void main_test(void);
+#endif
diff --git "a/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.o" "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.o"
new file mode 100644
index 0000000..3df39e8
Binary files /dev/null and "b/F107/Hardware/\347\237\251\351\230\265\351\224\256\347\233\230\346\230\276\347\244\272/USER/test.o" differ
diff --git a/F107/Libraries/CMSIS/Core/CM3/core_cm3.c b/F107/Libraries/CMSIS/Core/CM3/core_cm3.c
new file mode 100644
index 0000000..861fc8e
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/core_cm3.c
@@ -0,0 +1,829 @@
+/******************************************************************************
+ * @file: core_cm3.c
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version: V1.20
+ * @date: 22. May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+
+#include
+
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for armcc */
+ #define __INLINE __inline /*!< inline keyword for armcc */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for iarcc */
+ #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for gcc */
+ #define __INLINE inline /*!< inline keyword for gcc */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+ clrex
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ __ASM("rev16 r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, psp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, msp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+uint32_t __get_PRIMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int32_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ uint8_t result=0;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ uint16_t result=0;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/F107/Libraries/CMSIS/Core/CM3/core_cm3.h b/F107/Libraries/CMSIS/Core/CM3/core_cm3.h
new file mode 100644
index 0000000..1401587
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/core_cm3.h
@@ -0,0 +1,1367 @@
+/******************************************************************************
+ * @file: core_cm3.h
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version: V1.20
+ * @date: 22. May 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+/**
+ * Lint configuration \n
+ * ----------------------- \n
+ *
+ * The following Lint messages will be suppressed and not shown: \n
+ * \n
+ * --- Error 10: --- \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';' \n
+ * \n
+ * --- Error 530: --- \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
+ * \n
+ * --- Error 550: --- \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * } \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
+ * \n
+ * --- Error 754: --- \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 750: --- \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 528: --- \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 751: --- \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
+ * \n
+ * \n
+ * Note: To re-enable a Message, insert a space before 'lint' * \n
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+#include /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+#define __I volatile /*!< defines 'read only' permissions */
+#else
+#define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+
+
+/* System Reset */
+#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
+#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
+#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
+#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
+
+/* Core Debug */
+#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
+#define ITM_TCR_ITMENA 1 /*!< ITM enable */
+
+
+
+
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
+} NVIC_Type;
+
+
+/* memory mapping struct for System Control Block */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< System Control Register */
+ __IO uint32_t CCR; /*!< Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Processor Feature Register */
+ __I uint32_t DFR; /*!< Debug Feature Register */
+ __I uint32_t ADR; /*!< Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< ISA Feature Register */
+} SCB_Type;
+
+
+/* memory mapping struct for SysTick */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */
+} SysTick_Type;
+
+
+/* memory mapping structur for ITM */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< ITM Product ID Registers */
+ __I uint32_t PID5;
+ __I uint32_t PID6;
+ __I uint32_t PID7;
+ __I uint32_t PID0;
+ __I uint32_t PID1;
+ __I uint32_t PID2;
+ __I uint32_t PID3;
+ __I uint32_t CID0;
+ __I uint32_t CID1;
+ __I uint32_t CID2;
+ __I uint32_t CID3;
+} ITM_Type;
+
+
+/* memory mapped struct for Interrupt Type */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+
+/* Memory Protection Unit */
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+typedef struct
+{
+ __I uint32_t TYPE; /*!< MPU Type Register */
+ __IO uint32_t CTRL; /*!< MPU Control Register */
+ __IO uint32_t RNR; /*!< MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+#endif
+
+
+/* Core Debug Register */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+#define __WFI __wfi
+#define __WFE __wfe
+#define __SEV __sev
+#define __ISB() __isb(0)
+#define __DSB() __dsb(0)
+#define __DMB() __dmb(0)
+#define __REV __rev
+#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else /* (__ARMCC_VERSION >= 400000) */
+
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX __clrex
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0x1ff);
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
+
+#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
+static __INLINE void __WFI() { __ASM ("wfi"); }
+static __INLINE void __WFE() { __ASM ("wfe"); }
+static __INLINE void __SEV() { __ASM ("sev"); }
+static __INLINE void __CLREX() { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void) */
+/* intrinsic void __DSB(void) */
+/* intrinsic void __DMB(void) */
+/* intrinsic void __set_PRIMASK(); */
+/* intrinsic void __get_PRIMASK(); */
+/* intrinsic void __set_FAULTMASK(); */
+/* intrinsic void __get_FAULTMASK(); */
+/* intrinsic uint32_t __REV(uint32_t value); */
+/* intrinsic uint32_t __REVSH(uint32_t value); */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }
+static __INLINE void __SEV() { __ASM volatile ("sev"); }
+static __INLINE void __ISB() { __ASM volatile ("isb"); }
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+*
+* @param none
+* @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+
+/* ########################## NVIC functions #################################### */
+
+
+/**
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param uint32_t priority_grouping is priority grouping field
+ * @return none
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
+ reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+/**
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @param none
+ * @return uint32_t priority grouping field
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */
+}
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn_Type IRQn specifies the interrupt number
+ * @return none
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn_Type IRQn is the positive number of the external interrupt
+ * @return none
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param IRQn_Type IRQn is the number of the device specifc interrupt
+ * @return uint32_t 1 if pending interrupt else 0
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending,
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief Set the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief Clear the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief Read the active bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return uint32_t 1 if active else 0
+ *
+ * Read the active register in NVIC and returns 1 if its status is active,
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief Set the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @param priority is the priority for the interrupt
+ * @return none
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt. \n
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+/**
+ * @brief Read the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return uint32_t priority is the priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/**
+ * @brief Encode the priority for an interrupt
+ *
+ * @param uint32_t PriorityGroup is the used priority group
+ * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)
+ * @param uint32_t SubPriority is the sub priority value (starting from 0)
+ * @return uint32_t the priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/**
+ * @brief Decode the priority of an interrupt
+ *
+ * @param uint32_t Priority the priority for the interrupt
+ * @param uint32_t PrioGroup is the used priority group
+ * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
+ * @param uint32_t* pSubPrio is the sub priority value (starting from 0)
+ * @return none
+ *
+ * Decode an interrupt priority value with the given priority group to
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+
+/* ################################## SysTick function ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/* SysTick constants */
+#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
+#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
+#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
+#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
+
+/**
+ * @brief Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param uint32_t ticks is the number of ticks between two interrupts
+ * @return none
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 0)) )
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CM3_CORE_H__ */
+
+/*lint -restore */
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_cl.s b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..0cb477c
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_cl.s
@@ -0,0 +1,364 @@
+;******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_cl.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x Connectivity line devices vector table for RVMDK
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C1 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT ETH_WKUP_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX0_IRQHandler [WEAK]
+ EXPORT CAN2_RX1_IRQHandler [WEAK]
+ EXPORT CAN2_SCE_IRQHandler [WEAK]
+ EXPORT OTG_FS_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+OTG_FS_WKUP_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+ETH_IRQHandler
+ETH_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX0_IRQHandler
+CAN2_RX1_IRQHandler
+CAN2_SCE_IRQHandler
+OTG_FS_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE*****
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_hd.s b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..16b1dd4
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_hd.s
@@ -0,0 +1,370 @@
+;******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_hd.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x High Density Devices vector table for RVMDK
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Configure external SRAM mounted on STM3210E-EVAL board
+;* to be used as data memory (optional, to be enabled by user)
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+__initial_spTop EQU 0x20000400 ; stack used for SystemInit_ExtMemCtl
+ ; always internal RAM used
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_spTop ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Dummy SystemInit_ExtMemCtl function
+SystemInit_ExtMemCtl PROC
+ EXPORT SystemInit_ExtMemCtl [WEAK]
+ BX LR
+ ENDP
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+
+ LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
+ BLX R0
+
+ LDR R1, = __initial_sp ; restore original stack pointer
+ MSR MSP, R1
+
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_IRQHandler [WEAK]
+ EXPORT TIM8_UP_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT ADC3_IRQHandler [WEAK]
+ EXPORT FSMC_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+TIM8_BRK_IRQHandler
+TIM8_UP_IRQHandler
+TIM8_TRG_COM_IRQHandler
+TIM8_CC_IRQHandler
+ADC3_IRQHandler
+FSMC_IRQHandler
+SDIO_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_5_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE*****
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_ld.s b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..7742056
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_ld.s
@@ -0,0 +1,293 @@
+;******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_ld.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x Low Density Devices vector table for RVMDK
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1_2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD 0 ; Reserved
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+SPI1_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE*****
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_md.s b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_md.s
new file mode 100644
index 0000000..4380a01
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/arm/startup_stm32f10x_md.s
@@ -0,0 +1,303 @@
+;******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_md.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x Medium Density Devices vector table for RVMDK
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the CortexM3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1_2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
+ EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
+ EXPORT CAN1_RX1_IRQHandler [WEAK]
+ EXPORT CAN1_SCE_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTCAlarm_IRQHandler [WEAK]
+ EXPORT USBWakeUp_IRQHandler [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
+
+;******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE*****
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_cl.s b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..ee9b9eb
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_cl.s
@@ -0,0 +1,464 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_cl.s
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR
+ * address.
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ *******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN1_TX_IRQHandler
+ .word CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word OTG_FS_WKUP_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word ETH_IRQHandler
+ .word ETH_WKUP_IRQHandler
+ .word CAN2_TX_IRQHandler
+ .word CAN2_RX0_IRQHandler
+ .word CAN2_RX1_IRQHandler
+ .word CAN2_SCE_IRQHandler
+ .word OTG_FS_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x Connectivity line Devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+ .weak CAN2_SCE_IRQHandler
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler ,Default_Handler
+
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_hd.s b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..7abcbcd
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_hd.s
@@ -0,0 +1,483 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_hd.s
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure external SRAM mounted on STM3210E-EVAL board
+ * to be used as data memory (optional, to be enabled by user)
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global SystemInit_ExtMemCtl_Dummy
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+.equ Initial_spTop, 0x20000400
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+ bl SystemInit_ExtMemCtl
+/* restore original stack pointer */
+ LDR r0, =_estack
+ MSR msp, r0
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief Dummy SystemInit_ExtMemCtl function
+ * @param None
+ * @retval : None
+*/
+ .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits
+SystemInit_ExtMemCtl_Dummy:
+ bx lr
+ .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word Initial_spTop
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FSMC_IRQHandler
+ .word SDIO_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_5_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x High Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_5_IRQHandler
+ .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
+
+ .weak SystemInit_ExtMemCtl
+ .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy
+
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_ld.s b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..1ad1bb4
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_ld.s
@@ -0,0 +1,339 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_ld.s
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address.
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ 0
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ 0
+ 0
+ .word SPI1_IRQHandler
+ 0
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ 0
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32F10x Low Density devices.*/
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_md.s b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_md.s
new file mode 100644
index 0000000..65d5455
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/gcc/startup_stm32f10x_md.s
@@ -0,0 +1,355 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f10x_md.s
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M3 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ *******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+ .syntax unified
+ .cpu cortex-m3
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF108F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_IRQHandler
+ .word TAMPER_IRQHandler
+ .word RTC_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word USB_HP_CAN1_TX_IRQHandler
+ .word USB_LP_CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTCAlarm_IRQHandler
+ .word USBWakeUp_IRQHandler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word BootRAM /* @0x108. This is for boot in RAM mode for
+ STM32F10x Medium Density devices. */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMPER_IRQHandler
+ .thumb_set TAMPER_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak USB_HP_CAN1_TX_IRQHandler
+ .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
+
+ .weak USB_LP_CAN1_RX0_IRQHandler
+ .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTCAlarm_IRQHandler
+ .thumb_set RTCAlarm_IRQHandler,Default_Handler
+
+ .weak USBWakeUp_IRQHandler
+ .thumb_set USBWakeUp_IRQHandler,Default_Handler
+
+
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_cl.s b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_cl.s
new file mode 100644
index 0000000..4594ebc
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_cl.s
@@ -0,0 +1,498 @@
+;/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_cl.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x Connectivity line devices vector table for
+;* EWARM5.x toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD __iar_program_start
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 and ADC2
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C1 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
+ DCD ETH_IRQHandler ; Ethernet
+ DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX0_IRQHandler
+ B CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK OTG_FS_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+OTG_FS_WKUP_IRQHandler
+ B OTG_FS_WKUP_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK ETH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ETH_IRQHandler
+ B ETH_IRQHandler
+
+ PUBWEAK ETH_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ETH_WKUP_IRQHandler
+ B ETH_WKUP_IRQHandler
+
+ PUBWEAK CAN2_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_TX_IRQHandler
+ B CAN2_TX_IRQHandler
+
+ PUBWEAK CAN2_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_RX0_IRQHandler
+ B CAN2_RX0_IRQHandler
+
+ PUBWEAK CAN2_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_RX1_IRQHandler
+ B CAN2_RX1_IRQHandler
+
+ PUBWEAK CAN2_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN2_SCE_IRQHandler
+ B CAN2_SCE_IRQHandler
+
+ PUBWEAK OTG_FS_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+OTG_FS_IRQHandler
+ B OTG_FS_IRQHandler
+
+ END
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_hd.s b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_hd.s
new file mode 100644
index 0000000..92cf6fb
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_hd.s
@@ -0,0 +1,510 @@
+;/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_hd.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x High Density Devices vector table for EWARM5.x
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR address,
+;* - Configure external SRAM mounted on STM3210E-EVAL board
+;* to be used as data memory (optional, to be enabled by user)
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; ICODE is the same segment as cstartup. By placing __low_level_init
+ ;; in the same segment, we make sure it can be reached with BL. */
+
+ SECTION CSTACK:DATA:NOROOT(3)
+ SECTION .icode:CODE:NOROOT(2)
+ PUBLIC __low_level_init
+
+ PUBWEAK SystemInit_ExtMemCtl
+ SECTION .text:CODE:REORDER(2)
+ THUMB
+SystemInit_ExtMemCtl
+ BX LR
+
+__low_level_init:
+
+ ;; Initialize hardware.
+ LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
+ MOV R11, LR
+ BLX R0
+ LDR R1, =sfe(CSTACK) ; restore original stack pointer
+ MSR MSP, R1
+ MOV R0,#1
+ ;; Return with BX to be independent of mode of caller
+ BX R11
+
+ ;; Forward declaration of sections.
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+__intial_sp EQU 0x20000400
+__vector_table
+ DCD __intial_sp
+ DCD __iar_program_start
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+ DCD TIM8_BRK_IRQHandler ; TIM8 Break
+ DCD TIM8_UP_IRQHandler ; TIM8 Update
+ DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
+ DCD ADC3_IRQHandler ; ADC3
+ DCD FSMC_IRQHandler ; FSMC
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_IRQHandler ; TIM6
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
+ DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ PUBWEAK TIM8_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_BRK_IRQHandler
+ B TIM8_BRK_IRQHandler
+
+ PUBWEAK TIM8_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_UP_IRQHandler
+ B TIM8_UP_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_TRG_COM_IRQHandler
+ B TIM8_TRG_COM_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK ADC3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC3_IRQHandler
+ B ADC3_IRQHandler
+
+ PUBWEAK FSMC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FSMC_IRQHandler
+ B FSMC_IRQHandler
+
+ PUBWEAK SDIO_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler
+ B SDIO_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM6_IRQHandler
+ B TIM6_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA2_Channel4_5_IRQHandler
+ B DMA2_Channel4_5_IRQHandler
+
+
+ END
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_ld.s b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_ld.s
new file mode 100644
index 0000000..e3da4a7
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_ld.s
@@ -0,0 +1,357 @@
+;/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_ld.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x Low Density Devices vector table for EWARM5.x
+;* toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD __iar_program_start
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD 0 ; Reserved
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI1_IRQHandler ; SPI1
+ DCD 0 ; Reserved
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD 0 ; Reserved
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ END
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_md.s b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_md.s
new file mode 100644
index 0000000..32a28a1
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/startup/iar/startup_stm32f10x_md.s
@@ -0,0 +1,382 @@
+;/******************** (C) COPYRIGHT 2009 STMicroelectronics ********************
+;* File Name : startup_stm32f10x_md.s
+;* Author : MCD Application Team
+;* Version : V3.1.2
+;* Date : 09/28/2009
+;* Description : STM32F10x Medium Density Devices vector table for
+;* EWARM5.x toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == __iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* After Reset the Cortex-M3 processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD __iar_program_start
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+ DCD RTC_IRQHandler ; RTC
+ DCD FLASH_IRQHandler ; Flash
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line 0
+ DCD EXTI1_IRQHandler ; EXTI Line 1
+ DCD EXTI2_IRQHandler ; EXTI Line 2
+ DCD EXTI3_IRQHandler ; EXTI Line 3
+ DCD EXTI4_IRQHandler ; EXTI Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
+ DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
+ DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
+ DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
+ DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler
+ B PVD_IRQHandler
+
+ PUBWEAK TAMPER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TAMPER_IRQHandler
+ B TAMPER_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK USB_HP_CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+ B USB_HP_CAN1_TX_IRQHandler
+
+ PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+ B USB_LP_CAN1_RX0_IRQHandler
+
+ PUBWEAK CAN1_RX1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_RX1_IRQHandler
+ B CAN1_RX1_IRQHandler
+
+ PUBWEAK CAN1_SCE_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN1_SCE_IRQHandler
+ B CAN1_SCE_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTCAlarm_IRQHandler
+ B RTCAlarm_IRQHandler
+
+ PUBWEAK USBWakeUp_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBWakeUp_IRQHandler
+ B USBWakeUp_IRQHandler
+
+ END
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/CMSIS/Core/CM3/stm32f10x.h b/F107/Libraries/CMSIS/Core/CM3/stm32f10x.h
new file mode 100644
index 0000000..dc63684
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/stm32f10x.h
@@ -0,0 +1,7854 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32F10x Connectivity line, High
+ * density, Medium density and Low density devices.
+ ******************************************************************************
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x
+ * @{
+ */
+
+#ifndef __STM32F10x_H
+#define __STM32F10x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32 device used in your
+ application
+ */
+
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)
+ /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
+ /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
+ /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
+ #define STM32F10X_CL /*!< STM32F10X_CL: STM32 Connectivity line devices */
+#endif
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 16 and 32 Kbytes.
+ - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
+ where the Flash memory density ranges between 64 and 128 Kbytes.
+ - High density devices are STM32F101xx and STM32F103xx microcontrollers where
+ the Flash memory density ranges between 256 and 512 Kbytes.
+ - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
+ */
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined HSE_Value
+ #ifdef STM32F10X_CL
+ #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #else
+ #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* STM32F10X_CL */
+#endif /* HSE_Value */
+
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
+
+#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+
+/**
+ * @brief STM32F10x Standard Peripheral Library version number
+ */
+#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
+#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
+#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
+ | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
+ | __STM32F10X_STDPERIPH_VERSION_SUB2)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @brief STM32F10x Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+#define CLI() __set_PRIMASK(1) //关闭总中断
+#define SEI() __set_PRIMASK(0) //打开总中断
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */
+ RTC_IRQn = 3, /*!< RTC global Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+
+#ifdef STM32F10X_LD
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_LD */
+
+#ifdef STM32F10X_MD
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+#endif /* STM32F10X_MD */
+
+#ifdef STM32F10X_HD
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_CL
+ CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
+ CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
+#endif /* STM32F10X_CL */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32f10x.h"
+#include
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< Read Only */
+typedef const int16_t sc16; /*!< Read Only */
+typedef const int8_t sc8; /*!< Read Only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< Read Only */
+typedef __I int16_t vsc16; /*!< Read Only */
+typedef __I int8_t vsc8; /*!< Read Only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< Read Only */
+typedef const uint16_t uc16; /*!< Read Only */
+typedef const uint8_t uc8; /*!< Read Only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< Read Only */
+typedef __I uint16_t vuc16; /*!< Read Only */
+typedef __I uint8_t vuc8; /*!< Read Only */
+
+#ifndef __cplusplus
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+#endif
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR;
+ __IO uint32_t CR1;
+ __IO uint32_t CR2;
+ __IO uint32_t SMPR1;
+ __IO uint32_t SMPR2;
+ __IO uint32_t JOFR1;
+ __IO uint32_t JOFR2;
+ __IO uint32_t JOFR3;
+ __IO uint32_t JOFR4;
+ __IO uint32_t HTR;
+ __IO uint32_t LTR;
+ __IO uint32_t SQR1;
+ __IO uint32_t SQR2;
+ __IO uint32_t SQR3;
+ __IO uint32_t JSQR;
+ __IO uint32_t JDR1;
+ __IO uint32_t JDR2;
+ __IO uint32_t JDR3;
+ __IO uint32_t JDR4;
+ __IO uint32_t DR;
+} ADC_TypeDef;
+
+/**
+ * @brief Backup Registers
+ */
+
+typedef struct
+{
+ uint32_t RESERVED0;
+ __IO uint16_t DR1;
+ uint16_t RESERVED1;
+ __IO uint16_t DR2;
+ uint16_t RESERVED2;
+ __IO uint16_t DR3;
+ uint16_t RESERVED3;
+ __IO uint16_t DR4;
+ uint16_t RESERVED4;
+ __IO uint16_t DR5;
+ uint16_t RESERVED5;
+ __IO uint16_t DR6;
+ uint16_t RESERVED6;
+ __IO uint16_t DR7;
+ uint16_t RESERVED7;
+ __IO uint16_t DR8;
+ uint16_t RESERVED8;
+ __IO uint16_t DR9;
+ uint16_t RESERVED9;
+ __IO uint16_t DR10;
+ uint16_t RESERVED10;
+ __IO uint16_t RTCCR;
+ uint16_t RESERVED11;
+ __IO uint16_t CR;
+ uint16_t RESERVED12;
+ __IO uint16_t CSR;
+ uint16_t RESERVED13[5];
+ __IO uint16_t DR11;
+ uint16_t RESERVED14;
+ __IO uint16_t DR12;
+ uint16_t RESERVED15;
+ __IO uint16_t DR13;
+ uint16_t RESERVED16;
+ __IO uint16_t DR14;
+ uint16_t RESERVED17;
+ __IO uint16_t DR15;
+ uint16_t RESERVED18;
+ __IO uint16_t DR16;
+ uint16_t RESERVED19;
+ __IO uint16_t DR17;
+ uint16_t RESERVED20;
+ __IO uint16_t DR18;
+ uint16_t RESERVED21;
+ __IO uint16_t DR19;
+ uint16_t RESERVED22;
+ __IO uint16_t DR20;
+ uint16_t RESERVED23;
+ __IO uint16_t DR21;
+ uint16_t RESERVED24;
+ __IO uint16_t DR22;
+ uint16_t RESERVED25;
+ __IO uint16_t DR23;
+ uint16_t RESERVED26;
+ __IO uint16_t DR24;
+ uint16_t RESERVED27;
+ __IO uint16_t DR25;
+ uint16_t RESERVED28;
+ __IO uint16_t DR26;
+ uint16_t RESERVED29;
+ __IO uint16_t DR27;
+ uint16_t RESERVED30;
+ __IO uint16_t DR28;
+ uint16_t RESERVED31;
+ __IO uint16_t DR29;
+ uint16_t RESERVED32;
+ __IO uint16_t DR30;
+ uint16_t RESERVED33;
+ __IO uint16_t DR31;
+ uint16_t RESERVED34;
+ __IO uint16_t DR32;
+ uint16_t RESERVED35;
+ __IO uint16_t DR33;
+ uint16_t RESERVED36;
+ __IO uint16_t DR34;
+ uint16_t RESERVED37;
+ __IO uint16_t DR35;
+ uint16_t RESERVED38;
+ __IO uint16_t DR36;
+ uint16_t RESERVED39;
+ __IO uint16_t DR37;
+ uint16_t RESERVED40;
+ __IO uint16_t DR38;
+ uint16_t RESERVED41;
+ __IO uint16_t DR39;
+ uint16_t RESERVED42;
+ __IO uint16_t DR40;
+ uint16_t RESERVED43;
+ __IO uint16_t DR41;
+ uint16_t RESERVED44;
+ __IO uint16_t DR42;
+ uint16_t RESERVED45;
+} BKP_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR;
+ __IO uint32_t TDTR;
+ __IO uint32_t TDLR;
+ __IO uint32_t TDHR;
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR;
+ __IO uint32_t RDTR;
+ __IO uint32_t RDLR;
+ __IO uint32_t RDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1;
+ __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR;
+ __IO uint32_t MSR;
+ __IO uint32_t TSR;
+ __IO uint32_t RF0R;
+ __IO uint32_t RF1R;
+ __IO uint32_t IER;
+ __IO uint32_t ESR;
+ __IO uint32_t BTR;
+ uint32_t RESERVED0[88];
+ CAN_TxMailBox_TypeDef sTxMailBox[3];
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+ uint32_t RESERVED1[12];
+ __IO uint32_t FMR;
+ __IO uint32_t FM1R;
+ uint32_t RESERVED2;
+ __IO uint32_t FS1R;
+ uint32_t RESERVED3;
+ __IO uint32_t FFA1R;
+ uint32_t RESERVED4;
+ __IO uint32_t FA1R;
+ uint32_t RESERVED5[8];
+#ifndef STM32F10X_CL
+ CAN_FilterRegister_TypeDef sFilterRegister[14];
+#else
+ CAN_FilterRegister_TypeDef sFilterRegister[28];
+#endif /* STM32F10X_CL */
+} CAN_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR;
+ __IO uint8_t IDR;
+ uint8_t RESERVED0;
+ uint16_t RESERVED1;
+ __IO uint32_t CR;
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t SWTRIGR;
+ __IO uint32_t DHR12R1;
+ __IO uint32_t DHR12L1;
+ __IO uint32_t DHR8R1;
+ __IO uint32_t DHR12R2;
+ __IO uint32_t DHR12L2;
+ __IO uint32_t DHR8R2;
+ __IO uint32_t DHR12RD;
+ __IO uint32_t DHR12LD;
+ __IO uint32_t DHR8RD;
+ __IO uint32_t DOR1;
+ __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE;
+ __IO uint32_t CR;
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR;
+ __IO uint32_t CNDTR;
+ __IO uint32_t CPAR;
+ __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR;
+ __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/**
+ * @brief Ethernet MAC
+ */
+
+typedef struct
+{
+ __IO uint32_t MACCR;
+ __IO uint32_t MACFFR;
+ __IO uint32_t MACHTHR;
+ __IO uint32_t MACHTLR;
+ __IO uint32_t MACMIIAR;
+ __IO uint32_t MACMIIDR;
+ __IO uint32_t MACFCR;
+ __IO uint32_t MACVLANTR; /* 8 */
+ uint32_t RESERVED0[2];
+ __IO uint32_t MACRWUFFR; /* 11 */
+ __IO uint32_t MACPMTCSR;
+ uint32_t RESERVED1[2];
+ __IO uint32_t MACSR; /* 15 */
+ __IO uint32_t MACIMR;
+ __IO uint32_t MACA0HR;
+ __IO uint32_t MACA0LR;
+ __IO uint32_t MACA1HR;
+ __IO uint32_t MACA1LR;
+ __IO uint32_t MACA2HR;
+ __IO uint32_t MACA2LR;
+ __IO uint32_t MACA3HR;
+ __IO uint32_t MACA3LR; /* 24 */
+ uint32_t RESERVED2[40];
+ __IO uint32_t MMCCR; /* 65 */
+ __IO uint32_t MMCRIR;
+ __IO uint32_t MMCTIR;
+ __IO uint32_t MMCRIMR;
+ __IO uint32_t MMCTIMR; /* 69 */
+ uint32_t RESERVED3[14];
+ __IO uint32_t MMCTGFSCCR; /* 84 */
+ __IO uint32_t MMCTGFMSCCR;
+ uint32_t RESERVED4[5];
+ __IO uint32_t MMCTGFCR;
+ uint32_t RESERVED5[10];
+ __IO uint32_t MMCRFCECR;
+ __IO uint32_t MMCRFAECR;
+ uint32_t RESERVED6[10];
+ __IO uint32_t MMCRGUFCR;
+ uint32_t RESERVED7[334];
+ __IO uint32_t PTPTSCR;
+ __IO uint32_t PTPSSIR;
+ __IO uint32_t PTPTSHR;
+ __IO uint32_t PTPTSLR;
+ __IO uint32_t PTPTSHUR;
+ __IO uint32_t PTPTSLUR;
+ __IO uint32_t PTPTSAR;
+ __IO uint32_t PTPTTHR;
+ __IO uint32_t PTPTTLR;
+ uint32_t RESERVED8[567];
+ __IO uint32_t DMABMR;
+ __IO uint32_t DMATPDR;
+ __IO uint32_t DMARPDR;
+ __IO uint32_t DMARDLAR;
+ __IO uint32_t DMATDLAR;
+ __IO uint32_t DMASR;
+ __IO uint32_t DMAOMR;
+ __IO uint32_t DMAIER;
+ __IO uint32_t DMAMFBOCR;
+ uint32_t RESERVED9[9];
+ __IO uint32_t DMACHTDR;
+ __IO uint32_t DMACHRDR;
+ __IO uint32_t DMACHTBAR;
+ __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR;
+ __IO uint32_t EMR;
+ __IO uint32_t RTSR;
+ __IO uint32_t FTSR;
+ __IO uint32_t SWIER;
+ __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR;
+ __IO uint32_t KEYR;
+ __IO uint32_t OPTKEYR;
+ __IO uint32_t SR;
+ __IO uint32_t CR;
+ __IO uint32_t AR;
+ __IO uint32_t RESERVED;
+ __IO uint32_t OBR;
+ __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint16_t RDP;
+ __IO uint16_t USER;
+ __IO uint16_t Data0;
+ __IO uint16_t Data1;
+ __IO uint16_t WRP0;
+ __IO uint16_t WRP1;
+ __IO uint16_t WRP2;
+ __IO uint16_t WRP3;
+} OB_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2;
+ __IO uint32_t SR2;
+ __IO uint32_t PMEM2;
+ __IO uint32_t PATT2;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR2;
+} FSMC_Bank2_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank3
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR3;
+ __IO uint32_t SR3;
+ __IO uint32_t PMEM3;
+ __IO uint32_t PATT3;
+ uint32_t RESERVED0;
+ __IO uint32_t ECCR3;
+} FSMC_Bank3_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4;
+ __IO uint32_t SR4;
+ __IO uint32_t PMEM4;
+ __IO uint32_t PATT4;
+ __IO uint32_t PIO4;
+} FSMC_Bank4_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t CRL;
+ __IO uint32_t CRH;
+ __IO uint32_t IDR;
+ __IO uint32_t ODR;
+ __IO uint32_t BSRR;
+ __IO uint32_t BRR;
+ __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+ * @brief Alternate Function I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t EVCR;
+ __IO uint32_t MAPR;
+ __IO uint32_t EXTICR[4];
+} AFIO_TypeDef;
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t OAR1;
+ uint16_t RESERVED2;
+ __IO uint16_t OAR2;
+ uint16_t RESERVED3;
+ __IO uint16_t DR;
+ uint16_t RESERVED4;
+ __IO uint16_t SR1;
+ uint16_t RESERVED5;
+ __IO uint16_t SR2;
+ uint16_t RESERVED6;
+ __IO uint16_t CCR;
+ uint16_t RESERVED7;
+ __IO uint16_t TRISE;
+ uint16_t RESERVED8;
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR;
+ __IO uint32_t PR;
+ __IO uint32_t RLR;
+ __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFGR;
+ __IO uint32_t CIR;
+ __IO uint32_t APB2RSTR;
+ __IO uint32_t APB1RSTR;
+ __IO uint32_t AHBENR;
+ __IO uint32_t APB2ENR;
+ __IO uint32_t APB1ENR;
+ __IO uint32_t BDCR;
+ __IO uint32_t CSR;
+#ifdef STM32F10X_CL
+ __IO uint32_t AHBRSTR;
+ __IO uint32_t CFGR2;
+#endif /* STM32F10X_CL */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint16_t CRH;
+ uint16_t RESERVED0;
+ __IO uint16_t CRL;
+ uint16_t RESERVED1;
+ __IO uint16_t PRLH;
+ uint16_t RESERVED2;
+ __IO uint16_t PRLL;
+ uint16_t RESERVED3;
+ __IO uint16_t DIVH;
+ uint16_t RESERVED4;
+ __IO uint16_t DIVL;
+ uint16_t RESERVED5;
+ __IO uint16_t CNTH;
+ uint16_t RESERVED6;
+ __IO uint16_t CNTL;
+ uint16_t RESERVED7;
+ __IO uint16_t ALRH;
+ uint16_t RESERVED8;
+ __IO uint16_t ALRL;
+ uint16_t RESERVED9;
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER;
+ __IO uint32_t CLKCR;
+ __IO uint32_t ARG;
+ __IO uint32_t CMD;
+ __I uint32_t RESPCMD;
+ __I uint32_t RESP1;
+ __I uint32_t RESP2;
+ __I uint32_t RESP3;
+ __I uint32_t RESP4;
+ __IO uint32_t DTIMER;
+ __IO uint32_t DLEN;
+ __IO uint32_t DCTRL;
+ __I uint32_t DCOUNT;
+ __I uint32_t STA;
+ __IO uint32_t ICR;
+ __IO uint32_t MASK;
+ uint32_t RESERVED0[2];
+ __I uint32_t FIFOCNT;
+ uint32_t RESERVED1[13];
+ __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SR;
+ uint16_t RESERVED2;
+ __IO uint16_t DR;
+ uint16_t RESERVED3;
+ __IO uint16_t CRCPR;
+ uint16_t RESERVED4;
+ __IO uint16_t RXCRCR;
+ uint16_t RESERVED5;
+ __IO uint16_t TXCRCR;
+ uint16_t RESERVED6;
+ __IO uint16_t I2SCFGR;
+ uint16_t RESERVED7;
+ __IO uint16_t I2SPR;
+ uint16_t RESERVED8;
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1;
+ uint16_t RESERVED0;
+ __IO uint16_t CR2;
+ uint16_t RESERVED1;
+ __IO uint16_t SMCR;
+ uint16_t RESERVED2;
+ __IO uint16_t DIER;
+ uint16_t RESERVED3;
+ __IO uint16_t SR;
+ uint16_t RESERVED4;
+ __IO uint16_t EGR;
+ uint16_t RESERVED5;
+ __IO uint16_t CCMR1;
+ uint16_t RESERVED6;
+ __IO uint16_t CCMR2;
+ uint16_t RESERVED7;
+ __IO uint16_t CCER;
+ uint16_t RESERVED8;
+ __IO uint16_t CNT;
+ uint16_t RESERVED9;
+ __IO uint16_t PSC;
+ uint16_t RESERVED10;
+ __IO uint16_t ARR;
+ uint16_t RESERVED11;
+ __IO uint16_t RCR;
+ uint16_t RESERVED12;
+ __IO uint16_t CCR1;
+ uint16_t RESERVED13;
+ __IO uint16_t CCR2;
+ uint16_t RESERVED14;
+ __IO uint16_t CCR3;
+ uint16_t RESERVED15;
+ __IO uint16_t CCR4;
+ uint16_t RESERVED16;
+ __IO uint16_t BDTR;
+ uint16_t RESERVED17;
+ __IO uint16_t DCR;
+ uint16_t RESERVED18;
+ __IO uint16_t DMAR;
+ uint16_t RESERVED19;
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t SR;
+ uint16_t RESERVED0;
+ __IO uint16_t DR;
+ uint16_t RESERVED1;
+ __IO uint16_t BRR;
+ uint16_t RESERVED2;
+ __IO uint16_t CR1;
+ uint16_t RESERVED3;
+ __IO uint16_t CR2;
+ uint16_t RESERVED4;
+ __IO uint16_t CR3;
+ uint16_t RESERVED5;
+ __IO uint16_t GTPR;
+ uint16_t RESERVED6;
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR;
+ __IO uint32_t CFR;
+ __IO uint32_t SR;
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
+
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
+
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+
+#define SDIO_BASE (PERIPH_BASE + 0x18000)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+
+#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE (ETH_BASE)
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#define BKP ((BKP_TypeDef *) BKP_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define ETH ((ETH_TypeDef *) ETH_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */
+#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */
+#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */
+#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */
+#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */
+#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */
+#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */
+#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/* */
+/* Backup registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for BKP_DR1 register ********************/
+#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR2 register ********************/
+#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR3 register ********************/
+#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR4 register ********************/
+#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR5 register ********************/
+#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR6 register ********************/
+#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR7 register ********************/
+#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR8 register ********************/
+#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR9 register ********************/
+#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR10 register *******************/
+#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR11 register *******************/
+#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR12 register *******************/
+#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR13 register *******************/
+#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR14 register *******************/
+#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR15 register *******************/
+#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR16 register *******************/
+#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR17 register *******************/
+#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_DR18 register ********************/
+#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR19 register *******************/
+#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR20 register *******************/
+#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR21 register *******************/
+#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR22 register *******************/
+#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR23 register *******************/
+#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR24 register *******************/
+#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR25 register *******************/
+#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR26 register *******************/
+#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR27 register *******************/
+#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR28 register *******************/
+#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR29 register *******************/
+#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR30 register *******************/
+#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR31 register *******************/
+#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR32 register *******************/
+#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR33 register *******************/
+#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR34 register *******************/
+#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR35 register *******************/
+#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR36 register *******************/
+#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR37 register *******************/
+#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR38 register *******************/
+#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR39 register *******************/
+#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR40 register *******************/
+#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR41 register *******************/
+#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/******************* Bit definition for BKP_DR42 register *******************/
+#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */
+
+/****************** Bit definition for BKP_RTCCR register *******************/
+#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */
+#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */
+#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */
+#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */
+
+/******************** Bit definition for BKP_CR register ********************/
+#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */
+#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */
+
+/******************* Bit definition for BKP_CSR register ********************/
+#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */
+#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */
+#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */
+#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */
+#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+
+#ifdef STM32F10X_CL
+ #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */
+ #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */
+ #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */
+ #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */
+#endif /* STM32F10X_CL */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#ifdef STM32F10X_CL
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */
+ #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+
+ #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+ #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+ #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
+ #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
+ #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+#else
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+ #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
+
+ #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
+ #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+ #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */
+
+/*!< MCO configuration */
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#endif /* STM32F10X_CL */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+#ifdef STM32F10X_CL
+ #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */
+ #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */
+ #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */
+ #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */
+ #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */
+ #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */
+#endif /* STM32F10X_CL */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
+#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
+#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */
+#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */
+#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */
+#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
+#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
+#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
+#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_HD
+ #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */
+ #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */
+ #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
+ #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
+#endif /* STM32F10X_HD */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
+#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+ #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+ #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
+ #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#endif /* STM32F10X_HD */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
+ #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */
+#endif /* STM32F10X_CL */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */
+#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
+#endif
+
+#ifdef STM32F10X_HD
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
+ #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_CL
+ #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
+ #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */
+ #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */
+ #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */
+#endif /* STM32F10X_CL */
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
+#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
+#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
+#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
+#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
+#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
+#endif /* STM32F10X_HD */
+
+#ifdef STM32F10X_HD
+ #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
+ #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
+ #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
+ #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
+#endif /* STM32F10X_HD */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
+#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+
+#ifndef STM32F10X_LD
+ #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+ #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+ #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+ #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#endif /* STM32F10X_HD */
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
+ #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
+#endif
+
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#endif
+
+#ifdef STM32F10X_CL
+ #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */
+#endif /* STM32F10X_CL */
+
+/******************* Bit definition for RCC_BDCR register *******************/
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+#ifdef STM32F10X_CL
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+ #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */
+ #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV1 configuration */
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
+
+/*!< PREDIV2 configuration */
+ #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */
+ #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+ #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+ #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+ #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+ #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */
+ #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */
+ #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */
+ #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */
+ #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */
+ #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */
+ #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */
+ #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */
+ #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */
+ #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */
+ #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */
+ #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */
+ #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */
+ #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */
+ #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */
+
+/*!< PLL2MUL configuration */
+ #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */
+ #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */
+ #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */
+ #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */
+ #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */
+ #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */
+ #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */
+ #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */
+ #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */
+ #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */
+
+/*!< PLL3MUL configuration */
+ #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */
+ #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+ #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+ #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+ #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+
+ #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */
+ #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */
+ #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */
+ #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */
+ #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */
+ #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */
+ #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */
+ #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */
+ #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */
+
+ #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+ #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */
+ #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
+#endif /* STM32F10X_CL */
+
+/******************************************************************************/
+/* */
+/* General Purpose and Alternate Function I/O */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for GPIO_CRL register *******************/
+#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/******************* Bit definition for GPIO_CRH register *******************/
+#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */
+
+#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */
+
+#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+
+#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */
+#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */
+
+/*!<****************** Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */
+
+/******************* Bit definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */
+
+/****************** Bit definition for GPIO_BSRR register *******************/
+#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */
+
+/******************* Bit definition for GPIO_BRR register *******************/
+#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */
+
+/****************** Bit definition for GPIO_LCKR register *******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for AFIO_EVCR register *******************/
+#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */
+#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */
+#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */
+
+/*!< PIN configuration */
+#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */
+#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */
+#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */
+#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */
+#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */
+#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */
+#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */
+#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */
+#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */
+#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */
+#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */
+#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */
+#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */
+#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */
+#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */
+
+#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */
+#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */
+#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */
+#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */
+
+/*!< PORT configuration */
+#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */
+#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */
+#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */
+#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */
+
+#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */
+
+/****************** Bit definition for AFIO_MAPR register *******************/
+#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */
+#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */
+#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */
+
+#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+/* USART3_REMAP configuration */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+#ifdef STM32F10X_CL
+/*!< ETH_REMAP configuration */
+ #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */
+
+/*!< CAN2_REMAP configuration */
+ #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
+
+/*!< MII_RMII_SEL configuration */
+ #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */
+
+/*!< SPI3_REMAP configuration */
+ #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */
+
+/*!< TIM2ITR1_IREMAP configuration */
+ #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
+
+/*!< PTP_PPS_REMAP configuration */
+ #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */
+#endif
+
+/***************** Bit definition for AFIO_EXTICR1 register *****************/
+#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */
+
+/***************** Bit definition for AFIO_EXTICR2 register *****************/
+#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */
+
+/***************** Bit definition for AFIO_EXTICR3 register *****************/
+#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */
+
+/***************** Bit definition for AFIO_EXTICR4 register *****************/
+#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
+
+/******************************************************************************/
+/* */
+/* SystemTick */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+
+/******************************************************************************/
+/* */
+/* DMA Controller */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR1 register *******************/
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR2 register *******************/
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR3 register *******************/
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CCR4 register *******************/
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!© COPYRIGHT 2009 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/** @addtogroup STM32F10x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f10x.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+ frequency (after reset the HSI is used as SYSCLK source)
+
+ IMPORTANT NOTE:
+ ==============
+ 1. After each device reset the HSI is used as System clock source.
+
+ 2. Please make sure that the selected System clock doesn't exceed your device's
+ maximum frequency.
+
+ 3. If none of the define below is enabled, the HSI is used as System clock
+ source.
+
+ 4. The System clock configuration functions provided within this file assume that:
+ - For Low, Medium and High density devices an external 8MHz crystal is
+ used to drive the System clock.
+ - For Connectivity line devices an external 25MHz crystal is used to drive
+ the System clock.
+ If you are using different crystal you have to adapt those functions accordingly.
+ */
+
+/* #define SYSCLK_FREQ_HSE HSE_Value */
+/* #define SYSCLK_FREQ_24MHz 24000000 */
+/* #define SYSCLK_FREQ_36MHz 36000000 */
+/* #define SYSCLK_FREQ_48MHz 48000000 */
+/* #define SYSCLK_FREQ_56MHz 56000000 */
+#define SYSCLK_FREQ_72MHz 72000000
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM3210E-EVAL board (STM32 High density devices) as data memory */
+#ifdef STM32F10X_HD
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F10X_HD */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Variables
+ * @{
+ */
+
+/*******************************************************************************
+* Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+ const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_24MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_36MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_48MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_56MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */
+#elif defined SYSCLK_FREQ_72MHz
+ const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */
+#else /*!< HSI Selected as System Clock source */
+ const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */
+ const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */
+ const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */
+ const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */
+ const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+ static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+ static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+ static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+ static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+ static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+ static void SetSysClockTo72(void);
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifndef STM32F10X_CL
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#else
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#endif /* STM32F10X_CL */
+
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+ /* Configure the Flash Latency cycles and enable prefetch buffer */
+ SetSysClock();
+
+}
+
+/**
+ * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+ SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+ SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+ SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+ SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+ SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+ SetSysClockTo72();
+#endif
+
+ /* If none of the define above is enabled, the HSI is used as System clock
+ source (default after reset) */
+}
+
+/**
+ * @brief Setup the external memory controller. Called in startup_stm32f10x.s
+ * before jump to __main
+ * @param None
+ * @retval None
+ */
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f10x_xx.s/.c before jump to main.
+ * This function configures the external SRAM mounted on STM3210E-EVAL
+ * board (STM32 High density devices). This SRAM will be used as program
+ * data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
+ required, then adjust the Register Addresses */
+
+ /* Enable FSMC clock */
+ RCC->AHBENR = 0x00000114;
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+ RCC->APB2ENR = 0x000001E0;
+
+/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
+/*---------------- SRAM Address lines configuration -------------------------*/
+/*---------------- NOE and NWE configuration --------------------------------*/
+/*---------------- NE3 configuration ----------------------------------------*/
+/*---------------- NBL0, NBL1 configuration ---------------------------------*/
+
+ GPIOD->CRL = 0x44BB44BB;
+ GPIOD->CRH = 0xBBBBBBBB;
+
+ GPIOE->CRL = 0xB44444BB;
+ GPIOE->CRH = 0xBBBBBBBB;
+
+ GPIOF->CRL = 0x44BBBBBB;
+ GPIOF->CRH = 0xBBBB4444;
+
+ GPIOG->CRL = 0x44BBBBBB;
+ GPIOG->CRH = 0x44444B44;
+
+/*---------------- FSMC Configuration ---------------------------------------*/
+/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
+
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000200;
+}
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+ * @brief Selects HSE as System clock source and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockToHSE(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+
+#ifndef STM32F10X_CL
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+#else
+ if (HSE_Value <= 24000000)
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+ }
+ else
+ {
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+ }
+#endif /* STM32F10X_CL */
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* Select HSE as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+ /* Wait till HSE is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+ * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo24(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 0 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+#else
+ /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+ * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo36(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+
+ /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+#else
+ /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+ * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo48(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK/2 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL6);
+#else
+ /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+ * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo56(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK/2 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL7);
+#else
+ /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
+
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+ * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+ * and PCLK1 prescalers.
+ * @note This function should be used only after reset.
+ * @param None
+ * @retval None
+ */
+static void SetSysClockTo72(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+ /* HCLK = SYSCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK/2 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+ /* Configure PLLs ------------------------------------------------------*/
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+ /* Enable PLL2 */
+ RCC->CR |= RCC_CR_PLL2ON;
+ /* Wait till PLL2 is ready */
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+ {
+ }
+
+
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+ RCC_CFGR_PLLMULL9);
+#else
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+ RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+
+ /* Go to infinite loop */
+ while (1)
+ {
+ }
+ }
+}
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/CMSIS/Core/CM3/system_stm32f10x.h b/F107/Libraries/CMSIS/Core/CM3/system_stm32f10x.h
new file mode 100644
index 0000000..c619f86
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/CM3/system_stm32f10x.h
@@ -0,0 +1,100 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f10x.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f10x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F10X_H
+#define __SYSTEM_STM32F10X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F10x_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F10x_System_Exported_types
+ * @{
+ */
+
+extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
+extern const uint32_t SystemFrequency_SysClk; /*!< System clock */
+extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */
+extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */
+extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F10x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F10X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/CMSIS/Core/Documentation/CMSIS_Core.htm b/F107/Libraries/CMSIS/Core/Documentation/CMSIS_Core.htm
new file mode 100644
index 0000000..8214461
--- /dev/null
+++ b/F107/Libraries/CMSIS/Core/Documentation/CMSIS_Core.htm
@@ -0,0 +1,1231 @@
+
+
+
+ CMSIS: Cortex Microcontroller Software Interface Standard
+
+
+
+Cortex Microcontroller Software Interface Standard
+
+This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).
+Version: 1.20 - 22. May 2009
+
+Information in this file, the accompany manuals, and software is
+ Copyright ARM Ltd.
All rights reserved.
+
+
+
+
+Revision History
+
+ - Version 1.00: initial release.
+ - Version 1.01: added __LDREXx, __STREXx, and __CLREX.
+ - Version 1.02: added Cortex-M0.
+ - Version 1.10: second review.
+ - Version 1.20: third review.
+
+
+
+
+Contents
+
+
+ - About
+ - Coding Rules and Conventions
+ - CMSIS Files
+ - Core Peripheral Access Layer
+ - CMSIS Example
+
+
+About
+
+
+ The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges
+ that are faced when software components are deployed to physical microcontroller devices based on a
+ Cortex-M0 / Cortex-M1 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
+ processor cores (the term Cortex-Mx is used to indicate that). The CMSIS is defined in close co-operation
+ with various silicon and software vendors and provides a common approach to interface to peripherals,
+ real-time operating systems, and middleware components.
+
+
+ARM provides as part of the CMSIS the following software layers that are
+available for various compiler implementations:
+
+ - Core Peripheral Access Layer: contains name definitions,
+ address definitions and helper functions to
+ access core registers and peripherals. It defines also an device
+ independent interface for RTOS Kernels that includes debug channel
+ definitions.
+ - Middleware Access Layer: provides common methods to
+ access peripherals for the software industry. The Middleware Access Layer
+ is adapted by the Silicon Vendor for the device specific peripherals used
+ by middleware components. The middleware access layer is currently in
+ development and not yet part of this documentation
+
+
+These software layers are expanded by Silicon partners with:
+
+ - Device Peripheral Access Layer: provides definitions
+ for all device peripherals
+ - Access Functions for Peripherals (optional): provides
+ additional helper functions for peripherals
+
+
+CMSIS defines for a Cortex-Mx Microcontroller System:
+
+ - A common way to access peripheral registers
+ and a common way to define exception vectors.
+ - The register names of the Core
+ Peripherals and the names of the Core
+ Exception Vectors.
+ - An device independent interface for RTOS Kernels including a debug
+ channel.
+ - Interfaces for middleware components (TCP/IP
+ Stack, Flash File System).
+
+
+
+ By using CMSIS compliant software components, the user can easier re-use template code.
+ CMSIS is intended to enable the combination of software components from multiple middleware vendors.
+
+
+Coding Rules and Conventions
+
+
+ The following section describes the coding rules and conventions used in the CMSIS
+ implementation. It contains also information about data types and version number information.
+
+
+Essentials
+
+ - The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
+ there are disable and enable sequences for PC-LINT inserted.
+ - ANSI standard data types defined in the ANSI C header file
+ <stdint.h> are used.
+ - #define constants that include expressions must be enclosed by
+ parenthesis.
+ - Variables and parameters have a complete data type.
+ - All functions in the Core Peripheral Access Layer are
+ re-entrant.
+ - The Core Peripheral Access Layer has no blocking code
+ (which means that wait/query loops are done at other software layers such as
+ the Middleware Access Layer).
+ - For each exception/interrupt there is definition for:
+
+ - an exception/interrupt handler with the postfix _Handler
+ (for exceptions) or _IRQHandler (for interrupts).
+ - a default exception/interrupt handler (weak definition) that contains an endless loop.
+ - a #define of the interrupt number with the postfix _IRQn.
+
+
+
+Recommendations
+
+The CMSIS recommends the following conventions for identifiers.
+
+ - CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
+ - CamelCase names to identify peripherals access functions and interrupts.
+ - PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
+ - Doxygen comments for all functions are included as described under Function Comments below.
+
+
+Comments
+
+
+
+Data Types and IO Type Qualifiers
+
+
+ The Cortex-Mx HAL uses the standard types from the standard ANSI C header file
+ <stdint.h>. IO Type Qualifiers are used to specify the access
+ to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
+ debug information of peripheral registers.
+
+
+
+
+
+ | IO Type Qualifier |
+ #define |
+ Description |
+
+
+ | __I |
+ volatile const |
+ Read access only |
+
+
+ | __O |
+ volatile |
+ Write access only |
+
+
+ | __IO |
+ volatile |
+ Read and write access |
+
+
+
+
+CMSIS Version Number
+
+ File core_cm3.h contains the version number of the CMSIS with the following define:
+
+
+
+#define __CM3_CMSIS_VERSION_MAIN (0x00) /* [31:16] main version */
+#define __CM3_CMSIS_VERSION_SUB (0x03) /* [15:0] sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
+
+
+ File core_cm0.h contains the version number of the CMSIS with the following define:
+
+
+
+#define __CM0_CMSIS_VERSION_MAIN (0x00) /* [31:16] main version */
+#define __CM0_CMSIS_VERSION_SUB (0x00) /* [15:0] sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
+
+
+CMSIS Cortex Core
+
+ File core_cm3.h contains the type of the CMSIS Cortex-Mx with the following define:
+
+
+
+#define __CORTEX_M (0x03)
+
+
+ File core_cm0.h contains the type of the CMSIS Cortex-Mx with the following define:
+
+
+
+#define __CORTEX_M (0x00)
+
+
+CMSIS Files
+
+ This section describes the Files provided in context with the CMSIS to access the Cortex-Mx
+ hardware and peripherals.
+
+
+
+
+
+ | File |
+ Provider |
+ Description |
+
+
+ | device.h |
+ Device specific (provided by silicon partner) |
+ Defines the peripherals for the actual device. The file may use
+ several other include files to define the peripherals of the actual device. |
+
+
+ | core_cm0.h |
+ ARM (for RealView ARMCC, IAR, and GNU GCC) |
+ Defines the core peripherals for the Cortex-M0 CPU and core peripherals. |
+
+
+ | core_cm3.h |
+ ARM (for RealView ARMCC, IAR, and GNU GCC) |
+ Defines the core peripherals for the Cortex-M3 CPU and core peripherals. |
+
+
+ | core_cm0.c |
+ ARM (for RealView ARMCC, IAR, and GNU GCC) |
+ Provides helper functions that access core registers. |
+
+
+ | core_cm0.c |
+ ARM (for RealView ARMCC, IAR, and GNU GCC) |
+ Provides helper functions that access core registers. |
+
+
+ | startup_device |
+ ARM (adapted by compiler partner / silicon partner) |
+ Provides the Cortex-Mx startup code and the complete (device specific) Interrupt Vector Table |
+
+
+ | system_device |
+ ARM (adapted by silicon partner) |
+ Provides a device specific configuration file for the device. It configures the device initializes
+ typically the oscillator (PLL) that is part of the microcontroller device |
+
+
+
+
+device.h
+
+
+ The file device.h is provided by the silicon vendor and is the
+ central include file that the application programmer is using in
+ the C source code. This file contains:
+
+
+ -
+
Interrupt Number Definition: provides interrupt numbers
+ (IRQn) for all core and device specific exceptions and interrupts.
+
+ -
+
Configuration for core_cm0.h / core_cm3.h: reflects the
+ actual configuration of the Cortex-Mx processor that is part of the actual
+ device. As such the file core_cm0.h / core_cm3.h is included that
+ implements access to processor registers and core peripherals.
+
+ -
+
Device Peripheral Access Layer: provides definitions
+ for all device peripherals. It contains all data structures and the address
+ mapping for the device specific peripherals.
+
+ - Access Functions for Peripherals (optional): provides
+ additional helper functions for peripherals that are useful for programming
+ of these peripherals. Access Functions may be provided as inline functions
+ or can be extern references to a device specific library provided by the
+ silicon vendor.
+
+
+
+Interrupt Number Definition
+
+To access the device specific interrupts the device.h file defines IRQn
+numbers for the complete device using a enum typedef as shown below:
+
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers ****************************************************************/
+ WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ :
+ :
+ } IRQn_Type;
+
+
+Configuration for core_cm0.h / core_cm3.h
+
+ The Cortex-Mx core configuration options which are defined for each device implementation. Some
+ configuration options are reflected in the CMSIS layer using the #define settings described below.
+
+
+ To access core peripherals file device.h includes file core_cm0.h / core_cm3.h.
+ Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be
+ defined before #include <core_cm0.h> / #include <core_cm3.h>
+ preprocessor command.
+
+
+
+
+
+ | #define |
+ File |
+ Value |
+ Description |
+
+
+ | __NVIC_PRIO_BITS |
+ core_cm0.h |
+ (2) |
+ Number of priority bits implemented in the NVIC (device specific) |
+
+
+ | __NVIC_PRIO_BITS |
+ core_cm3.h |
+ (2 ... 8) |
+ Number of priority bits implemented in the NVIC (device specific) |
+
+
+ | __MPU_PRESENT |
+ core_cm0.h, core_cm3.h |
+ (0, 1) |
+ Defines if an MPU is present or not |
+
+
+ | __Vendor_SysTickConfig |
+ core_cm0.h, core_cm3.h |
+ (1) |
+ When this define is setup to 1, the SysTickConfig function
+ in core_cm3.h is excluded. In this case the device.h
+ file must contain a vendor specific implementation of this function. |
+
+
+
+
+
+Device Peripheral Access Layer
+
+ Each peripheral uses a PERIPHERAL_ prefix to identify peripheral registers
+ and functions that access this specific peripheral. If more than one peripheral of the same
+ type exists, identifiers have a postfix (digit or letter). For example:
+
+
+ - UART_Type: defines the generic register layout for all UART channels in a device.
+ - UART1: is a pointer to a register structure that refers to a specific UART.
+ For example UART1->DR is the data register of UART1.
+ - UART_SendChar(UART1, c): is a generic function that works with all UART's in the device.
+ To communicate the UART that it accesses the first parameter is a pointer to the actual
+ UART register structure.
+ - UART1_SendChar(c): is an UART1 specific implementation (in this case the send function).
+
+
+Minimal Requiements
+
+ To access the peripheral registers and related function in a device the files device.h
+ and core_cm0.h / core_cm3.h defines as a minimum:
+
+
+ - The Register Layout Typedef for each peripheral that defines all register names.
+ Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
+ the peripheral registers. For example:
+
+typedef struct {
+ __IO uint32_t CTRL; /* SysTick Control and Status Register */
+ __IO uint32_t LOAD; /* SysTick Reload Value Register */
+ __IO uint32_t VAL; /* SysTick Current Value Register */
+ __I uint32_t CALIB; /* SysTick Calibration Register */
+ } SysTick_Type;
+
+
+ - Base Address for each peripheral (in case of multiple peripherals
+ that use the same register layout typedef multiple base addresses are defined). For example:
+
+#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */
+
+
+ - Access Definition for each peripheral (in case of multiple peripherals that use
+ the same register layout typedef multiple access definitions exist, i.e. UART0,
+ UART1). For Example:
+
+#define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */
+
+
+
+
+ These definitions allow to access the peripheral registers from user code with simple assignments like:
+
+SysTick->CTRL = 0;
+
+Optional Features
+In addition the device.h file may define:
+
+ - #define constants that simplify access to the peripheral registers.
+ These constant define bit-positions or other specific patterns are that
+ required for the programming of the peripheral registers. The identifiers
+ used start with the name of the PERIPERHAL_. It is
+ recommended to use CAPITAL letters for such #define constants.
+ - Functions that perform more complex functions with the peripheral (i.e.
+ status query before a sending register is accessed). Again these function
+ start with the name of the PERIPHERAL_.
+
+
+core_cm0.h and core_cm0.c
+
+ File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does
+ the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
+ and core peripherals with efficient functions (defined as static inline).
+
+
+ File core_cm0.c defines several helper functions that access processor registers.
+
+Together these files implement the Core Peripheral Access Layer for a Cortex-M0.
+
+core_cm3.h and core_cm3.c
+
+ File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does
+ the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
+ and core peripherals with efficient functions (defined as static inline).
+
+
+ File core_cm3.c defines several helper functions that access processor registers.
+
+Together these files implement the Core Peripheral Access Layer for a Cortex-M3.
+
+startup_device
+
+ A template file for startup_device is provided by ARM for each supported
+ compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
+ interrupt handlers. Each interrupt handler is defined as weak function
+ to an dummy handler. Therefore the interrupt handler can be directly used in application software
+ without any requirements to adapt the startup_device file.
+
+
+ The following exception names are fixed and define the start of the vector table for a Cortex-M0:
+
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+
+ The following exception names are fixed and define the start of the vector table for a Cortex-M3:
+
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+
+ In the following examples for device specific interrupts are shown:
+
+
+; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper
+
+
+ Device specific interrupts must have a dummy function that can be overwritten in user code.
+ Below is an example for this dummy function.
+
+
+Default_Handler PROC
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ :
+ :
+ WWDG_IRQHandler
+ PVD_IRQHandler
+ TAMPER_IRQHandler
+ :
+ :
+ B .
+ ENDP
+
+
+ The user application may simply define an interrupt handler function by using the handler name
+ as shown below.
+
+
+void WWDG_IRQHandler(void)
+{
+ :
+ :
+}
+
+
+system_device.c
+
+ A template file for system_device.c is provided by ARM but adapted by
+ the silicon vendor to match their actual device. As a minimum requirement
+ this file must provide a device specific system configuration function and a global variable
+ that contains the system frequency. It configures the device and initializes typically the
+ oscillator (PLL) that is part of the microcontroller device.
+
+
+ The file system_device.c must provide
+ as a minimum requirement the SystemInit function as shown below.
+
+
+
+
+
+ | Function Definition |
+ Description |
+
+
+ | void SystemInit (void) |
+ Setup the microcontroller system. Typically this function configures the
+ oscillator (PLL) that is part of the microcontroller device. For systems
+ with variable clock speed it also updates the variable SystemFrequency. |
+
+
+
+
+
+ Also part of the file system_device.c
+ is the variable SystemFrequency which contains the current CPU clock speed shown below.
+
+
+
+
+
+ | Variable Definition |
+ Description |
+
+
+ | uint32_t SystemFrequency |
+ Contains the system frequency (which is the system clock frequency supplied
+ to the SysTick timer and the processor core clock). This variable can be
+ used by the user application after the call to the function SystemInit()
+ to setup the SysTick timer or configure other parameters. It may also be
+ used by debugger to query the frequency of the debug timer or configure
+ the trace clock speed.
+ This variable may also be defined in the const space.
+ The compiler must be configured to avoid the removal of this variable in
+ case that the application program is not using it. It is important for
+ debug systems that the variable is physically present in memory so that
+ it can be examined to configure the debugger. |
+
+
+
+
+Note
+
+
+
+Core Peripheral Access Layer
+
+Cortex-Mx Core Register Access
+
+ The following functions are defined in core_cm0.h / core_cm3.h
+ and provide access to Cortex-Mx core registers.
+
+
+
+
+
+ | Function Definition |
+ Core |
+ Core Register |
+ Description |
+
+
+ | void __enable_irq (void) |
+ M0, M3 |
+ PRIMASK = 0 |
+ Global Interrupt enable (using the instruction CPSIE
+ i) |
+
+
+ | void __disable_irq (void) |
+ M0, M3 |
+ PRIMASK = 1 |
+ Global Interrupt disable (using the instruction
+ CPSID i) |
+
+
+ | void __set_PRIMASK (uint32_t value) |
+ M0, M3 |
+ PRIMASK = value |
+ Assign value to Priority Mask Register (using the instruction
+ MSR) |
+
+
+ | uint32_t __get_PRIMASK (void) |
+ M0, M3 |
+ return PRIMASK |
+ Return Priority Mask Register (using the instruction
+ MRS) |
+
+
+ | void __enable_fault_irq (void) |
+ M3 |
+ FAULTMASK = 0 |
+ Global Fault exception and Interrupt enable (using the
+ instruction CPSIE
+ f) |
+
+
+ | void __disable_fault_irq (void) |
+ M3 |
+ FAULTMASK = 1 |
+ Global Fault exception and Interrupt disable (using the
+ instruction CPSID f) |
+
+
+ | void __set_FAULTMASK (uint32_t value) |
+ M3 |
+ FAULTMASK = value |
+ Assign value to Fault Mask Register (using the instruction
+ MSR) |
+
+
+ | uint32_t __get_FAULTMASK (void) |
+ M3 |
+ return FAULTMASK |
+ Return Fault Mask Register (using the instruction MRS) |
+
+
+ | void __set_BASEPRI (uint32_t value) |
+ M3 |
+ BASEPRI = value |
+ Set Base Priority (using the instruction MSR) |
+
+
+ | uiuint32_t __get_BASEPRI (void) |
+ M3 |
+ return BASEPRI |
+ Return Base Priority (using the instruction MRS) |
+
+
+ | void __set_CONTROL (uint32_t value) |
+ M0, M3 |
+ CONTROL = value |
+ Set CONTROL register value (using the instruction MSR) |
+
+
+ | uint32_t __get_CONTROL (void) |
+ M0, M3 |
+ return CONTROL |
+ Return Control Register Value (using the instruction
+ MRS) |
+
+
+ | void __set_PSP (uint32_t TopOfProcStack) |
+ M0, M3 |
+ PSP = TopOfProcStack |
+ Set Process Stack Pointer value (using the instruction
+ MSR) |
+
+
+ | uint32_t __get_PSP (void) |
+ M0, M3 |
+ return PSP |
+ Return Process Stack Pointer (using the instruction MRS) |
+
+
+ | void __set_MSP (uint32_t TopOfMainStack) |
+ M0, M3 |
+ MSP = TopOfMainStack |
+ Set Main Stack Pointer (using the instruction MSR) |
+
+
+ | uint32_t __get_MSP (void) |
+ M0, M3 |
+ return MSP |
+ Return Main Stack Pointer (using the instruction MRS) |
+
+
+
+
+Cortex-Mx Instruction Access
+
+ The following functions are defined in core_cm0.h / core_cm3.hand
+ generate specific Cortex-Mx instructions. The functions are implemented in the file
+ core_cm0.c / core_cm3.c.
+
+
+
+
+
+ | Name |
+ Core |
+ Generated CPU Instruction |
+ Description |
+
+
+ | void __WFI (void) |
+ M0, M3 |
+ WFI |
+ Wait for Interrupt |
+
+
+ | void __WFE (void) |
+ M0, M3 |
+ WFE |
+ Wait for Event |
+
+
+ | void __SEV (void) |
+ M0, M3 |
+ SEV |
+ Set Event |
+
+
+ | void __ISB (void) |
+ M0, M3 |
+ ISB |
+ Instruction Synchronization Barrier |
+
+
+ | void __DSB (void) |
+ M0, M3 |
+ DSB |
+ Data Synchronization Barrier |
+
+
+ | void __DMB (void) |
+ M0, M3 |
+ DMB |
+ Data Memory Barrier |
+
+
+ | uint32_t __REV (uint32_t value) |
+ M0, M3 |
+ REV |
+ Reverse byte order in integer value. |
+
+
+ | uint32_t __REV16 (uint16_t value) |
+ M0, M3 |
+ REV16 |
+ Reverse byte order in unsigned short value. |
+
+
+ | sint32_t __REVSH (sint16_t value) |
+ M0, M3 |
+ REVSH |
+ Reverse byte order in signed short value with sign extension to integer. |
+
+
+ | uint32_t __RBIT (uint32_t value) |
+ M3 |
+ RBIT |
+ Reverse bit order of value |
+
+
+ | uint8_t __LDREXB (uint8_t *addr) |
+ M3 |
+ LDREXB |
+ Load exclusive byte |
+
+
+ | uint16_t __LDREXH (uint16_t *addr) |
+ M3 |
+ LDREXH |
+ Load exclusive half-word |
+
+
+ | uint32_t __LDREXW (uint32_t *addr) |
+ M3 |
+ LDREXW |
+ Load exclusive word |
+
+
+ | uint32_t __STREXB (uint8_t value, uint8_t *addr) |
+ M3 |
+ STREXB |
+ Store exclusive byte |
+
+
+ | uint32_t __STREXB (uint16_t value, uint16_t *addr) |
+ M3 |
+ STREXH |
+ Store exclusive half-word |
+
+
+ | uint32_t __STREXB (uint32_t value, uint32_t *addr) |
+ M3 |
+ STREXW |
+ Store exclusive word |
+
+
+ | void __CLREX (void) |
+ M3 |
+ CLREX |
+ Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW |
+
+
+
+
+
+NVIC Access Functions
+
+ The CMSIS provides access to the NVIC via the register interface structure and several helper
+ functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
+ identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
+ IRQn values are used for processor core exceptions.
+
+
+ For the IRQn values of core exceptions the file device.h provides
+ the following enum names.
+
+
+
+
+
+ | Core Exception enum Value |
+ Core |
+ IRQn |
+ Description |
+
+
+ | NonMaskableInt_IRQn |
+ M0, M3 |
+ -14 |
+ Cortex-Mx Non Maskable Interrupt |
+
+
+ | HardFault_IRQn |
+ M0, M3 |
+ -13 |
+ Cortex-Mx Hard Fault Interrupt |
+
+
+ | MemoryManagement_IRQn |
+ M3 |
+ -12 |
+ Cortex-Mx Memory Management Interrupt |
+
+
+ | BusFault_IRQn |
+ M3 |
+ -11 |
+ Cortex-Mx Bus Fault Interrupt |
+
+
+ | UsageFault_IRQn |
+ M3 |
+ -10 |
+ Cortex-Mx Usage Fault Interrupt |
+
+
+ | SVCall_IRQn |
+ M0, M3 |
+ -5 |
+ Cortex-Mx SV Call Interrupt |
+
+
+ | DebugMonitor_IRQn |
+ M3 |
+ -4 |
+ Cortex-Mx Debug Monitor Interrupt |
+
+
+ | PendSV_IRQn |
+ M0, M3 |
+ -2 |
+ Cortex-Mx Pend SV Interrupt |
+
+
+ | SysTick_IRQn |
+ M0, M3 |
+ -1 |
+ Cortex-Mx System Tick Interrupt |
+
+
+
+
+The following functions simplify the setup of the NVIC.
+The functions are defined as static inline.
+
+
+
+
+ | Name |
+ Core |
+ Parameter |
+ Description |
+
+
+ | void NVIC_SetPriorityGrouping (uint32_t PriorityGroup) |
+ M3 |
+ Priority Grouping Value |
+ Set the Priority Grouping (Groups . Subgroups) |
+
+
+ | void NVIC_EnableIRQ (IRQn_Type IRQn) |
+ M0, M3 |
+ IRQ Number |
+ Enable IRQn |
+
+
+ | void NVIC_DisableIRQ (IRQn_Type IRQn) |
+ M0, M3 |
+ IRQ Number |
+ Disable IRQn |
+
+
+ | uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn) |
+ M0, M3 |
+ IRQ Number |
+ Return 1 if IRQn is pending else 0 |
+
+
+ | void NVIC_SetPendingIRQ (IRQn_Type IRQn) |
+ M0, M3 |
+ IRQ Number |
+ Set IRQn Pending |
+
+
+ | void NVIC_ClearPendingIRQ (IRQn_Type IRQn) |
+ M0, M3 |
+ IRQ Number |
+ Clear IRQn Pending Status |
+
+
+ | uint32_t NVIC_GetActive (IRQn_Type IRQn) |
+ M3 |
+ IRQ Number |
+ Return 1 if IRQn is active else 0 |
+
+
+ | void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority) |
+ M0, M3 |
+ IRQ Number, Priority |
+ Set Priority for IRQn
+ (not threadsafe for Cortex-M0) |
+
+
+ | uint32_t NVIC_GetPriority (IRQn_Type IRQn) |
+ M0, M3 |
+ IRQ Number |
+ Get Priority for IRQn |
+
+
+
+ | uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
+ M3 |
+ IRQ Number, Priority Group, Preemtive Priority, Sub Priority |
+ Encode priority for given group, preemtive and sub priority |
+
+
+ NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
+ M3 |
+ IRQ Number, Priority, pointer to Priority Group, pointer to Preemtive Priority, pointer to Sub Priority |
+ Deccode given priority to group, preemtive and sub priority |
+
+
+ | void NVIC_SystemReset (void) |
+ M0, M3 |
+ (void) |
+ Resets the System |
+
+
+
+Note
+
+ The processor exceptions have negative enum values. Device specific interrupts
+ have positive enum values and start with 0. The values are defined in
+ device.h file.
+
+ The values for PreemptPriority and SubPriority
+ used in functions NVIC_EncodePriority and NVIC_DecodePriority
+ depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
+
+
+
+
+SysTick Configuration Function
+
+The following function is used to configure the SysTick timer and start the
+SysTick interrupt.
+
+
+
+
+ | Name |
+ Parameter |
+ Description |
+
+
+ | uint32_t SysTickConfig
+ (uint32_t ticks) |
+ ticks is SysTick counter reload value |
+ Setup the SysTick timer and enable the SysTick interrupt. After this
+ call the SysTick timer creates interrupts with the specified time
+ interval.
+
+ Return: 0 when successful, 1 on failure.
+ |
+
+
+
+
+
+Cortex-M3 ITM Debug Access
+
+The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
+provides together with the Serial Viewer Output trace capabilities for the
+microcontroller system. The ITM has 32 communication channels; two ITM
+communication channels are used by CMSIS to output the following information:
+
+ - ITM Channel 0: implements the ITM_putchar function
+ which can be used for printf-style output via the debug interface.
+ - ITM Channel 31: is reserved for the RTOS kernel and can be used for
+ kernel awareness debugging.
+
+Note
+
+ The ITM channel 31 is selected for the RTOS kernel since some kernels
+ may use the Privileged level for program execution. ITM
+ channels have 4 groups with 8 channels each, whereby each group can be
+ configured for access rights in the Unprivileged level. The ITM channel 0
+ may be therefore enabled for the user task whereas ITM channel 31 may be
+ accessible only in Privileged level from the RTOS kernel itself.
+
+
+The prototype of the ITM_putchar routine is shown in the
+table below.
+
+
+
+
+ | Name |
+ Parameter |
+ Description |
+
+
+ | void uint32_t ITM_putchar(uint32_t chr) |
+ character to output |
+ The function outputs a character via the ITM channel 0. The
+ function returns when no debugger is connected that has booked the
+ output. It is blocking when a debugger is connected, but the
+ previous character send is not transmitted.
+ Return: the input character 'chr'. |
+
+
+
+
+
+
+ Example for the usage of the ITM Channel 31 for RTOS Kernels:
+
+
+ // check if debugger connected and ITM channel enabled for tracing
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 31))) {
+ // transmit trace data
+ while (ITM->PORT31_U32 == 0);
+ ITM->PORT[31].u8 = task_id; // id of next task
+ while (ITM->PORT[31].u32 == 0);
+ ITM->PORT[31].u32 = task_status; // status information
+ }
+
+
+CMSIS Example
+
+ The following section shows a typical example for using the CMSIS layer in user applications.
+
+
+#include <device.h> // file name depends on the device used.
+
+void SysTick_Handler (void) { // SysTick Interrupt Handler
+ ;
+}
+
+void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler
+ ;
+}
+
+void timer1_init(int frequency) {
+ // set up Timer (device specific)
+ NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority
+ NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt
+}
+
+void main (void) {
+ SystemInit ();
+
+ if (SysTick_Config (SystemFrequency / 1000)) { // Setup SysTick Timer for 1 msec interrupts
+ : // Handle Error
+ :
+ while (1);
+ }
+
+ timer1_init (); // device specific timer
+
+ while (1);
+}
+
+
+
\ No newline at end of file
diff --git a/F107/Libraries/CMSIS/License.doc b/F107/Libraries/CMSIS/License.doc
new file mode 100644
index 0000000..b6b8ace
Binary files /dev/null and b/F107/Libraries/CMSIS/License.doc differ
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
new file mode 100644
index 0000000..bd41cd1
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/misc.h
@@ -0,0 +1,219 @@
+/**
+ ******************************************************************************
+ * @file misc.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type
+ (For the complete STM32 Devices IRQ Channels list, please
+ refer to stm32f10x.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup SysTick_clock_source
+ * @{
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Functions
+ * @{
+ */
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h
new file mode 100644
index 0000000..b16269f
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_adc.h
@@ -0,0 +1,479 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the ADC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_ADC_H
+#define __STM32F10x_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ADC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
+ dual mode.
+ This parameter can be a value of @ref ADC_mode */
+
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
+ Scan (multichannels) or Single (one channel) mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
+ Continuous or Single mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
+ to digital conversion of regular channels. This parameter
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
+ This parameter can be a value of @ref ADC_data_align */
+
+ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
+ using the sequencer for regular channel group.
+ This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Constants
+ * @{
+ */
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC2) || \
+ ((PERIPH) == ADC3))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+ ((PERIPH) == ADC3))
+
+/** @defgroup ADC_mode
+ * @{
+ */
+
+#define ADC_Mode_Independent ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+ ((MODE) == ADC_Mode_RegInjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
+ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
+ ((MODE) == ADC_Mode_InjecSimult) || \
+ ((MODE) == ADC_Mode_RegSimult) || \
+ ((MODE) == ADC_Mode_FastInterl) || \
+ ((MODE) == ADC_Mode_SlowInterl) || \
+ ((MODE) == ADC_Mode_AlterTrig))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
+ * @{
+ */
+
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_None) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_data_align
+ * @{
+ */
+
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+ ((ALIGN) == ADC_DataAlign_Left))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_channels
+ * @{
+ */
+
+#define ADC_Channel_0 ((uint8_t)0x00)
+#define ADC_Channel_1 ((uint8_t)0x01)
+#define ADC_Channel_2 ((uint8_t)0x02)
+#define ADC_Channel_3 ((uint8_t)0x03)
+#define ADC_Channel_4 ((uint8_t)0x04)
+#define ADC_Channel_5 ((uint8_t)0x05)
+#define ADC_Channel_6 ((uint8_t)0x06)
+#define ADC_Channel_7 ((uint8_t)0x07)
+#define ADC_Channel_8 ((uint8_t)0x08)
+#define ADC_Channel_9 ((uint8_t)0x09)
+#define ADC_Channel_10 ((uint8_t)0x0A)
+#define ADC_Channel_11 ((uint8_t)0x0B)
+#define ADC_Channel_12 ((uint8_t)0x0C)
+#define ADC_Channel_13 ((uint8_t)0x0D)
+#define ADC_Channel_14 ((uint8_t)0x0E)
+#define ADC_Channel_15 ((uint8_t)0x0F)
+#define ADC_Channel_16 ((uint8_t)0x10)
+#define ADC_Channel_17 ((uint8_t)0x11)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_sampling_time
+ * @{
+ */
+
+#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
+ ((TIME) == ADC_SampleTime_7Cycles5) || \
+ ((TIME) == ADC_SampleTime_13Cycles5) || \
+ ((TIME) == ADC_SampleTime_28Cycles5) || \
+ ((TIME) == ADC_SampleTime_41Cycles5) || \
+ ((TIME) == ADC_SampleTime_55Cycles5) || \
+ ((TIME) == ADC_SampleTime_71Cycles5) || \
+ ((TIME) == ADC_SampleTime_239Cycles5))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
+ * @{
+ */
+
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */
+#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */
+
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */
+
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_channel_selection
+ * @{
+ */
+
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+ ((CHANNEL) == ADC_InjectedChannel_2) || \
+ ((CHANNEL) == ADC_InjectedChannel_3) || \
+ ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_analog_watchdog_selection
+ * @{
+ */
+
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @{
+ */
+
+#define ADC_IT_EOC ((uint16_t)0x0220)
+#define ADC_IT_AWD ((uint16_t)0x0140)
+#define ADC_IT_JEOC ((uint16_t)0x0480)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+ ((IT) == ADC_IT_JEOC))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @{
+ */
+
+#define ADC_FLAG_AWD ((uint8_t)0x01)
+#define ADC_FLAG_EOC ((uint8_t)0x02)
+#define ADC_FLAG_JEOC ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)
+#define ADC_FLAG_STRT ((uint8_t)0x10)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
+ ((FLAG) == ADC_FLAG_STRT))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_thresholds
+ * @{
+ */
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_offset
+ * @{
+ */
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_length
+ * @{
+ */
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_injected_rank
+ * @{
+ */
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_regular_length
+ * @{
+ */
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_rank
+ * @{
+ */
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+ * @{
+ */
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Exported_Functions
+ * @{
+ */
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_StartCalibration(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_ADC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
new file mode 100644
index 0000000..4a6a774
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_bkp.h
@@ -0,0 +1,194 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the BKP firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_BKP_H
+#define __STM32F10x_BKP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup BKP
+ * @{
+ */
+
+/** @defgroup BKP_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Tamper_Pin_active_level
+ * @{
+ */
+
+#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+ ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
+ * @{
+ */
+
+#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+ ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+ * @}
+ */
+
+/** @defgroup Data_Backup_Register
+ * @{
+ */
+
+#define BKP_DR1 ((uint16_t)0x0004)
+#define BKP_DR2 ((uint16_t)0x0008)
+#define BKP_DR3 ((uint16_t)0x000C)
+#define BKP_DR4 ((uint16_t)0x0010)
+#define BKP_DR5 ((uint16_t)0x0014)
+#define BKP_DR6 ((uint16_t)0x0018)
+#define BKP_DR7 ((uint16_t)0x001C)
+#define BKP_DR8 ((uint16_t)0x0020)
+#define BKP_DR9 ((uint16_t)0x0024)
+#define BKP_DR10 ((uint16_t)0x0028)
+#define BKP_DR11 ((uint16_t)0x0040)
+#define BKP_DR12 ((uint16_t)0x0044)
+#define BKP_DR13 ((uint16_t)0x0048)
+#define BKP_DR14 ((uint16_t)0x004C)
+#define BKP_DR15 ((uint16_t)0x0050)
+#define BKP_DR16 ((uint16_t)0x0054)
+#define BKP_DR17 ((uint16_t)0x0058)
+#define BKP_DR18 ((uint16_t)0x005C)
+#define BKP_DR19 ((uint16_t)0x0060)
+#define BKP_DR20 ((uint16_t)0x0064)
+#define BKP_DR21 ((uint16_t)0x0068)
+#define BKP_DR22 ((uint16_t)0x006C)
+#define BKP_DR23 ((uint16_t)0x0070)
+#define BKP_DR24 ((uint16_t)0x0074)
+#define BKP_DR25 ((uint16_t)0x0078)
+#define BKP_DR26 ((uint16_t)0x007C)
+#define BKP_DR27 ((uint16_t)0x0080)
+#define BKP_DR28 ((uint16_t)0x0084)
+#define BKP_DR29 ((uint16_t)0x0088)
+#define BKP_DR30 ((uint16_t)0x008C)
+#define BKP_DR31 ((uint16_t)0x0090)
+#define BKP_DR32 ((uint16_t)0x0094)
+#define BKP_DR33 ((uint16_t)0x0098)
+#define BKP_DR34 ((uint16_t)0x009C)
+#define BKP_DR35 ((uint16_t)0x00A0)
+#define BKP_DR36 ((uint16_t)0x00A4)
+#define BKP_DR37 ((uint16_t)0x00A8)
+#define BKP_DR38 ((uint16_t)0x00AC)
+#define BKP_DR39 ((uint16_t)0x00B0)
+#define BKP_DR40 ((uint16_t)0x00B4)
+#define BKP_DR41 ((uint16_t)0x00B8)
+#define BKP_DR42 ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \
+ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \
+ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \
+ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Exported_Functions
+ * @{
+ */
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_BKP_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
new file mode 100644
index 0000000..fc79f56
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_can.h
@@ -0,0 +1,535 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the CAN firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CAN_H
+#define __STM32F10x_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Types
+ * @{
+ */
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+ ((PERIPH) == CAN2))
+
+/**
+ * @brief CAN init structure definition
+ */
+
+typedef struct
+{
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */
+
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set either to ENABLE or DISABLE. */
+
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter init structure definition
+ */
+
+typedef struct
+{
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter can be a value between 0x0000 and 0xFFFF */
+
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
+} CanTxMsg;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter can be a value between 0 to 0x7FF. */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_identifier_type */
+
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter can be a value between 0 to 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */
+
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter can be a value between 0 to 0xFF */
+} CanRxMsg;
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Constants
+ * @{
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+
+#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode
+ * @{
+ */
+
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \
+ ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width
+ * @{
+ */
+
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1
+ * @{
+ */
+
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2
+ * @{
+ */
+
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_clock_prescaler
+ * @{
+ */
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_number
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#else
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode
+ * @{
+ */
+
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+ ((MODE) == CAN_FilterMode_IdList))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale
+ * @{
+ */
+
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+ ((SCALE) == CAN_FilterScale_32bit))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO
+ * @{
+ */
+
+#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+ ((FIFO) == CAN_FilterFIFO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup Start_bank_filter_for_slave_CAN
+ * @{
+ */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx
+ * @{
+ */
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_identifier_type
+ * @{
+ */
+
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request
+ * @{
+ */
+
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_transmit_constants
+ * @{
+ */
+
+#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */
+#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants
+ * @{
+ */
+
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_sleep_constants
+ * @{
+ */
+
+#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_wake_up_constants
+ * @{
+ */
+
+#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags
+ * @{
+ */
+
+#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */
+#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */
+#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */
+
+#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\
+ ((FLAG) == CAN_FLAG_BOF))
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_interrupts
+ * @{
+ */
+
+#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */
+#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */
+#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */
+
+#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\
+ ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\
+ ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions
+ * @{
+ */
+
+void CAN_DeInit(CAN_TypeDef* CANx);
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CAN_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
new file mode 100644
index 0000000..15dbe29
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_crc.h
@@ -0,0 +1,93 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the CRC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CRC_H
+#define __STM32F10x_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @defgroup CRC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Exported_Functions
+ * @{
+ */
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_CRC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
new file mode 100644
index 0000000..eb287e7
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dac.h
@@ -0,0 +1,282 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DAC_H
+#define __STM32F10x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/** @defgroup DAC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+ This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in High-density devices*/
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
+ only in Connectivity line devices */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_output_buffer
+ * @{
+ */
+
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+ ((STATE) == DAC_OutputBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement
+ * @{
+ */
+
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Exported_Functions
+ * @{
+ */
+
+void DAC_DeInit(void);
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DAC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
new file mode 100644
index 0000000..9bc014e
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dbgmcu.h
@@ -0,0 +1,109 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the DBGMCU
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DBGMCU_H
+#define __STM32F10x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBGMCU
+ * @{
+ */
+
+/** @defgroup DBGMCU_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
+#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
+#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
+
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Exported_Functions
+ * @{
+ */
+
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_DBGMCU_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
new file mode 100644
index 0000000..ca3cfb5
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_dma.h
@@ -0,0 +1,437 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_DMA_H
+#define __STM32F10x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/** @defgroup DMA_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief DMA Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode.
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+ ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+ ((STATE) == DMA_PeripheralInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+ ((STATE) == DMA_MemoryInc_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Circular ((uint32_t)0x00000020)
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
+#define DMA_Priority_High ((uint32_t)0x00002000)
+#define DMA_Priority_Medium ((uint32_t)0x00001000)
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Enable ((uint32_t)0x00004000)
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Buffer_Size
+ * @{
+ */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Exported_Functions
+ * @{
+ */
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+void DMA_ClearFlag(uint32_t DMA_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_DMA_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h
new file mode 100644
index 0000000..4392f87
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_exti.h
@@ -0,0 +1,183 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the EXTI firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_EXTI_H
+#define __STM32F10x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
+ Wakeup from suspend event */
+#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions
+ * @{
+ */
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_EXTI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
new file mode 100644
index 0000000..c6fc4b4
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_flash.h
@@ -0,0 +1,346 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FLASH_H
+#define __STM32F10x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/** @defgroup FLASH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief FLASH Status
+ */
+
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_PG,
+ FLASH_ERROR_WRP,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Flash_Latency
+ * @{
+ */
+
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1) || \
+ ((LATENCY) == FLASH_Latency_2))
+/**
+ * @}
+ */
+
+/** @defgroup Half_Cycle_Enable_Disable
+ * @{
+ */
+
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+ ((STATE) == FLASH_HalfCycleAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Prefetch_Buffer_Enable_Disable
+ * @{
+ */
+
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+ ((STATE) == FLASH_PrefetchBuffer_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+
+/* Values to be used with STM32 Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with STM32 Medium-density devices */
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */
+
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */
+#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 Medium-density and Connectivity line devices:
+ Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
+
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+ ((FLAG) == FLASH_FLAG_OPTERR))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Exported_Functions
+ * @{
+ */
+
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
+void FLASH_ClearFlag(uint16_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_FLASH_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
new file mode 100644
index 0000000..e85e8c3
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_fsmc.h
@@ -0,0 +1,716 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the FSMC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_FSMC_H
+#define __STM32F10x_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FSMC
+ * @{
+ */
+
+/** @defgroup FSMC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief Timing parameters For NOR/SRAM Banks
+ */
+
+typedef struct
+{
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address setup time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories. */
+
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the address hold time.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is not used with synchronous NOR Flash memories.*/
+
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
+ the duration of the data setup time.
+ This parameter can be a value between 0 and 0xFF.
+ @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
+ the duration of the bus turnaround.
+ This parameter can be a value between 0 and 0xF.
+ @note: It is only used for multiplexed NOR Flash memories. */
+
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+ This parameter can be a value between 1 and 0xF.
+ @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
+ to the memory before getting the first data.
+ The value of this parameter depends on the memory type as shown below:
+ - It must be set to 0 in case of a CRAM
+ - It is don抰 care in asynchronous NOR, SRAM or ROM accesses
+ - It may assume a value between 0 and 0xF in NOR Flash memories
+ with synchronous burst mode enable */
+
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
+ This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/**
+ * @brief FSMC NOR/SRAM Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
+ multiplexed on the databus or not.
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
+ the corresponding memory bank.
+ This parameter can be a value of @ref FSMC_Memory_Type */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be a value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
+ valid only with synchronous burst Flash memories.
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
+ the Flash memory in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
+ memory, valid only when accessing Flash memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
+ clock cycle before the wait state or during the wait state,
+ valid only when accessing memories in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Timing */
+
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
+ This parameter can be a value of @ref FSMC_Write_Operation */
+
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
+ signal, valid for Flash memory access in burst mode.
+ This parameter can be a value of @ref FSMC_Wait_Signal */
+
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
+ This parameter can be a value of @ref FSMC_Extended_Mode */
+
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
+ This parameter can be a value of @ref FSMC_Write_Burst */
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
+
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
+}FSMC_NORSRAMInitTypeDef;
+
+/**
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks
+ */
+
+typedef struct
+{
+ uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
+ the command assertion for NAND-Flash read or write access
+ to common/Attribute or I/O memory space (depending on
+ the memory space timing to be configured).
+ This parameter can be a value between 0 and 0xFF.*/
+
+ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
+ command for NAND-Flash read or write access to
+ common/Attribute or I/O memory space (depending on the
+ memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
+ (and data for write access) after the command deassertion
+ for NAND-Flash read or write access to common/Attribute
+ or I/O memory space (depending on the memory space timing
+ to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
+ databus is kept in HiZ after the start of a NAND-Flash
+ write access to common/Attribute or I/O memory space (depending
+ on the memory space timing to be configured).
+ This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/**
+ * @brief FSMC NAND Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
+ This parameter can be a value of @ref FSMC_NAND_Bank */
+
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
+ This parameter can be any value of @ref FSMC_Data_Width */
+
+ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
+ This parameter can be any value of @ref FSMC_ECC */
+
+ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/**
+ * @brief FSMC PCCARD Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
+ This parameter can be any value of @ref FSMC_Wait_feature */
+
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between CLE low and RE low.
+ This parameter can be a value between 0 and 0xFF. */
+
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
+ delay between ALE low and RE low.
+ This parameter can be a number between 0x0 and 0xFF */
+
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
+}FSMC_PCCARDInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup FSMC_NORSRAM_Bank
+ * @{
+ */
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Bank
+ * @{
+ */
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Bank
+ * @{
+ */
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
+/**
+ * @}
+ */
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \
+ ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+ ((BANK) == FSMC_Bank3_NAND) || \
+ ((BANK) == FSMC_Bank4_PCCARD))
+
+/** @defgroup NOR_SRAM_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing
+ * @{
+ */
+
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+ ((MUX) == FSMC_DataAddressMux_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Memory_Type
+ * @{
+ */
+
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+ ((MEMORY) == FSMC_MemoryType_NOR))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Width
+ * @{
+ */
+
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Burst_Access_Mode
+ * @{
+ */
+
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+ ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal_Polarity
+ * @{
+ */
+
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+ ((POLARITY) == FSMC_WaitSignalPolarity_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wrap_Mode
+ * @{
+ */
+
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+ ((MODE) == FSMC_WrapMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Timing
+ * @{
+ */
+
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Operation
+ * @{
+ */
+
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+ ((OPERATION) == FSMC_WriteOperation_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Signal
+ * @{
+ */
+
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+ ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Extended_Mode
+ * @{
+ */
+
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+ ((MODE) == FSMC_ExtendedMode_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Write_Burst
+ * @{
+ */
+
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+ ((BURST) == FSMC_WriteBurst_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time
+ * @{
+ */
+
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration
+ * @{
+ */
+
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_CLK_Division
+ * @{
+ */
+
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Latency
+ * @{
+ */
+
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Access_Mode
+ * @{
+ */
+
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B ((uint32_t)0x10000000)
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+ ((MODE) == FSMC_AccessMode_B) || \
+ ((MODE) == FSMC_AccessMode_C) || \
+ ((MODE) == FSMC_AccessMode_D))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup NAND_PCCARD_Controller
+ * @{
+ */
+
+/** @defgroup FSMC_Wait_feature
+ * @{
+ */
+
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+ ((FEATURE) == FSMC_Waitfeature_Enable))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup FSMC_ECC
+ * @{
+ */
+
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+ ((STATE) == FSMC_ECC_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_ECC_Page_Size
+ * @{
+ */
+
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TCLR_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TAR_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Hold_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_HiZ_Setup_Time
+ * @{
+ */
+
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Interrupt_sources
+ * @{
+ */
+
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)
+#define FSMC_IT_Level ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+ ((IT) == FSMC_IT_Level) || \
+ ((IT) == FSMC_IT_FallingEdge))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Flags
+ * @{
+ */
+
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+ ((FLAG) == FSMC_FLAG_Level) || \
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \
+ ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Exported_Functions
+ * @{
+ */
+
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_PCCARDDeInit(void);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_FSMC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
new file mode 100644
index 0000000..6a62661
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_gpio.h
@@ -0,0 +1,359 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_GPIO_H
+#define __STM32F10x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Types
+ * @{
+ */
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF) || \
+ ((PERIPH) == GPIOG))
+
+/**
+ * @brief Output Maximum frequency selection
+ */
+
+typedef enum
+{
+ GPIO_Speed_10MHz = 1,
+ GPIO_Speed_2MHz,
+ GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+ ((SPEED) == GPIO_Speed_50MHz))
+
+/**
+ * @brief Configuration Mode enumeration
+ */
+
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+ GPIO_Mode_IN_FLOATING = 0x04,
+ GPIO_Mode_IPD = 0x28,
+ GPIO_Mode_IPU = 0x48,
+ GPIO_Mode_Out_OD = 0x14,
+ GPIO_Mode_Out_PP = 0x10,
+ GPIO_Mode_AF_OD = 0x1C,
+ GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
+ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
+ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
+ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
+
+/**
+ * @brief GPIO Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+
+/**
+ * @brief Bit_SET and Bit_RESET enumeration
+ */
+
+typedef enum
+{ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Remap_define
+ * @{
+ */
+
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ to TIM2 Internal Trigger 1 for calibration
+ (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
+ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \
+ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \
+ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
+ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
+ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
+ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
+ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
+ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
+ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
+ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \
+ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \
+ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Port_Sources
+ * @{
+ */
+
+#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+ ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+
+/**
+ * @}
+ */
+
+/** @defgroup Ethernet_Media_Interface
+ * @{
+ */
+#define GPIO_ETH_MediaInterface_MII ((uint32_t)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
+
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \
+ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions
+ * @{
+ */
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_GPIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h
new file mode 100644
index 0000000..243f10a
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_i2c.h
@@ -0,0 +1,472 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_I2C_H
+#define __STM32F10x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/** @defgroup I2C_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz */
+
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
+ This parameter can be a 7-bit or 10-bit address. */
+
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode
+ * @{
+ */
+
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+ ((CYCLE) == I2C_DutyCycle_2))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_Ack_Enable ((uint16_t)0x0400)
+#define I2C_Ack_Disable ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+ ((STATE) == I2C_Ack_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_Direction_Transmitter ((uint8_t)0x00)
+#define I2C_Direction_Receiver ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_registers
+ * @{
+ */
+
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_DR ((uint8_t)0x10)
+#define I2C_Register_SR1 ((uint8_t)0x14)
+#define I2C_Register_SR2 ((uint8_t)0x18)
+#define I2C_Register_CCR ((uint8_t)0x1C)
+#define I2C_Register_TRISE ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_DR) || \
+ ((REGISTER) == I2C_Register_SR1) || \
+ ((REGISTER) == I2C_Register_SR2) || \
+ ((REGISTER) == I2C_Register_CCR) || \
+ ((REGISTER) == I2C_Register_TRISE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_SMBus_alert_pin_level
+ * @{
+ */
+
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+ ((ALERT) == I2C_SMBusAlert_High))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_PEC_position
+ * @{
+ */
+
+#define I2C_PECPosition_Next ((uint16_t)0x0800)
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+ ((POSITION) == I2C_PECPosition_Current))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_BUF ((uint16_t)0x0400)
+#define I2C_IT_EVT ((uint16_t)0x0200)
+#define I2C_IT_ERR ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
+#define I2C_IT_PECERR ((uint32_t)0x01001000)
+#define I2C_IT_OVR ((uint32_t)0x01000800)
+#define I2C_IT_AF ((uint32_t)0x01000400)
+#define I2C_IT_ARLO ((uint32_t)0x01000200)
+#define I2C_IT_BERR ((uint32_t)0x01000100)
+#define I2C_IT_TXE ((uint32_t)0x06000080)
+#define I2C_IT_RXNE ((uint32_t)0x06000040)
+#define I2C_IT_STOPF ((uint32_t)0x02000010)
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)
+#define I2C_IT_BTF ((uint32_t)0x02000004)
+#define I2C_IT_ADDR ((uint32_t)0x02000002)
+#define I2C_IT_SB ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+
+/**
+ * @brief SR2 register flags
+ */
+
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)
+
+/**
+ * @brief SR1 register flags
+ */
+
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)
+#define I2C_FLAG_AF ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
+#define I2C_FLAG_SB ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_SB))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Events
+ * @{
+ */
+
+/**
+ * @brief EV1
+ */
+
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/**
+ * @brief EV2
+ */
+
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+
+/**
+ * @brief EV3
+ */
+
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+
+/**
+ * @brief EV4
+ */
+
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
+
+/**
+ * @brief EV5
+ */
+
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/**
+ * @brief EV6
+ */
+
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+
+/**
+ * @brief EV7
+ */
+
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/**
+ * @brief EV8
+ */
+
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+
+/**
+ * @brief EV8_2
+ */
+
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/**
+ * @brief EV9
+ */
+
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/**
+ * @brief EV3_2
+ */
+
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_clock_speed
+ * @{
+ */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Exported_Functions
+ * @{
+ */
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_I2C_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
new file mode 100644
index 0000000..1c4b784
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_iwdg.h
@@ -0,0 +1,139 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IWDG_H
+#define __STM32F10x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/** @defgroup IWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions
+ * @{
+ */
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IWDG_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
new file mode 100644
index 0000000..0bc92e7
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_pwr.h
@@ -0,0 +1,155 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the PWR firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_PWR_H
+#define __STM32F10x_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup PWR
+ * @{
+ */
+
+/** @defgroup PWR_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Constants
+ * @{
+ */
+
+/** @defgroup PVD_detection_level
+ * @{
+ */
+
+#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \
+ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \
+ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))
+/**
+ * @}
+ */
+
+/** @defgroup Regulator_state_is_STOP_mode
+ * @{
+ */
+
+#define PWR_Regulator_ON ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+ ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+ * @}
+ */
+
+/** @defgroup STOP_mode_entry
+ * @{
+ */
+
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Flag
+ * @{
+ */
+
+#define PWR_FLAG_WU ((uint32_t)0x00000001)
+#define PWR_FLAG_SB ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+ ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Exported_Functions
+ * @{
+ */
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_PWR_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
new file mode 100644
index 0000000..91e44ee
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rcc.h
@@ -0,0 +1,700 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the RCC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RCC_H
+#define __STM32F10x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RCC
+ * @{
+ */
+
+/** @defgroup RCC_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
+ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
+ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
+ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
+ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup HSE_configuration
+ * @{
+ */
+
+#define RCC_HSE_OFF ((uint32_t)0x00000000)
+#define RCC_HSE_ON ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+ ((HSE) == RCC_HSE_Bypass))
+
+/**
+ * @}
+ */
+
+/** @defgroup PLL_entry_clock_source
+ * @{
+ */
+
+#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
+
+#ifndef STM32F10X_CL
+ #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
+ #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
+ ((SOURCE) == RCC_PLLSource_HSE_Div2))
+#else
+ #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
+ ((SOURCE) == RCC_PLLSource_PREDIV1))
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+/** @defgroup PLL_multiplication_factor
+ * @{
+ */
+#ifndef STM32F10X_CL
+ #define RCC_PLLMul_2 ((uint32_t)0x00000000)
+ #define RCC_PLLMul_3 ((uint32_t)0x00040000)
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_10 ((uint32_t)0x00200000)
+ #define RCC_PLLMul_11 ((uint32_t)0x00240000)
+ #define RCC_PLLMul_12 ((uint32_t)0x00280000)
+ #define RCC_PLLMul_13 ((uint32_t)0x002C0000)
+ #define RCC_PLLMul_14 ((uint32_t)0x00300000)
+ #define RCC_PLLMul_15 ((uint32_t)0x00340000)
+ #define RCC_PLLMul_16 ((uint32_t)0x00380000)
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+ ((MUL) == RCC_PLLMul_16))
+
+#else
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)
+ #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)
+
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
+ ((MUL) == RCC_PLLMul_6_5))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+#ifdef STM32F10X_CL
+/** @defgroup PREDIV1_division_factor
+ * @{
+ */
+ #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
+ #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
+ #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
+ #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
+ #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
+ #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
+ #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
+ #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
+ #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
+ #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
+ #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
+ #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
+ #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
+ #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
+ #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
+
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
+/**
+ * @}
+ */
+
+
+/** @defgroup PREDIV1_clock_source
+ * @{
+ */
+/* PREDIV1 clock source (only for STM32 connectivity line devices) */
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
+ #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
+
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
+ ((SOURCE) == RCC_PREDIV1_Source_PLL2))
+/**
+ * @}
+ */
+
+
+/** @defgroup PREDIV2_division_factor
+ * @{
+ */
+
+ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
+ #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
+ #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
+ #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
+ #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
+ #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
+ #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
+ #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
+ #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
+ #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
+ #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
+ #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
+ #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
+ #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
+ #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
+ #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
+
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
+ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \
+ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \
+ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \
+ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \
+ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \
+ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \
+ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL2_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
+ #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
+ #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
+ #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
+ #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
+ #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
+ #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
+ #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
+ #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
+
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
+ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \
+ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \
+ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \
+ ((MUL) == RCC_PLL2Mul_20))
+/**
+ * @}
+ */
+
+
+/** @defgroup PLL3_multiplication_factor
+ * @{
+ */
+
+ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
+ #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
+ #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
+ #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
+ #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
+ #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
+ #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
+ #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
+ #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
+
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
+ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \
+ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \
+ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \
+ ((MUL) == RCC_PLL3Mul_20))
+/**
+ * @}
+ */
+
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup System_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+ * @}
+ */
+
+/** @defgroup AHB_clock_source
+ * @{
+ */
+
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+ ((HCLK) == RCC_SYSCLK_Div512))
+/**
+ * @}
+ */
+
+/** @defgroup APB1_APB2_clock_source
+ * @{
+ */
+
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+ ((PCLK) == RCC_HCLK_Div16))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Interrupt_source
+ * @{
+ */
+
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_LSERDY ((uint8_t)0x02)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+#else
+ #define RCC_IT_PLL2RDY ((uint8_t)0x20)
+ #define RCC_IT_PLL3RDY ((uint8_t)0x40)
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
+#endif /* STM32F10X_CL */
+
+
+/**
+ * @}
+ */
+
+#ifndef STM32F10X_CL
+/** @defgroup USB_Device_clock_source
+ * @{
+ */
+
+ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
+ #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
+
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
+#else
+/** @defgroup USB_OTG_FS_clock_source
+ * @{
+ */
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)
+
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
+ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+#ifdef STM32F10X_CL
+/** @defgroup I2S2_clock_source
+ * @{
+ */
+ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+
+/** @defgroup I2S3_clock_source
+ * @{
+ */
+ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
+ #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
+
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO))
+/**
+ * @}
+ */
+#endif /* STM32F10X_CL */
+
+
+/** @defgroup ADC_clock_source
+ * @{
+ */
+
+#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+/**
+ * @}
+ */
+
+/** @defgroup LSE_configuration
+ * @{
+ */
+
+#define RCC_LSE_OFF ((uint8_t)0x00)
+#define RCC_LSE_ON ((uint8_t)0x01)
+#define RCC_LSE_Bypass ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+ ((LSE) == RCC_LSE_Bypass))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_clock_source
+ * @{
+ */
+
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+/**
+ * @}
+ */
+
+/** @defgroup AHB_peripheral
+ * @{
+ */
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F10X_CL */
+/**
+ * @}
+ */
+
+/** @defgroup APB2_peripheral
+ * @{
+ */
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFF0002) == 0x00) && ((PERIPH) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup APB1_peripheral
+ * @{
+ */
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC10137C0) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup Clock_source_to_output_on_MCO_pin
+ * @{
+ */
+
+#define RCC_MCO_NoClock ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2))
+#else
+ #define RCC_MCO_PLL2CLK ((uint8_t)0x08)
+ #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
+ #define RCC_MCO_XT1 ((uint8_t)0x0A)
+ #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
+
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
+ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \
+ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \
+ ((MCO) == RCC_MCO_PLL3CLK))
+#endif /* STM32F10X_CL */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Flag
+ * @{
+ */
+
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+#ifndef STM32F10X_CL
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#else
+ #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
+ #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+ ((FLAG) == RCC_FLAG_LPWRRST))
+#endif /* STM32F10X_CL */
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Exported_Functions
+ * @{
+ */
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+
+#ifdef STM32F10X_CL
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+ void RCC_PLL2Cmd(FunctionalState NewState);
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+ void RCC_PLL3Cmd(FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+
+#ifndef STM32F10X_CL
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+#else
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+
+#ifdef STM32F10X_CL
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+#endif /* STM32F10X_CL */
+
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+
+#ifdef STM32F10X_CL
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+#endif /* STM32F10X_CL */
+
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RCC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h
new file mode 100644
index 0000000..66589f2
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_rtc.h
@@ -0,0 +1,134 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the RTC firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_RTC_H
+#define __STM32F10x_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup RTC
+ * @{
+ */
+
+/** @defgroup RTC_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup RTC_interrupts_define
+ * @{
+ */
+
+#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
+#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
+#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
+ ((IT) == RTC_IT_SEC))
+/**
+ * @}
+ */
+
+/** @defgroup RTC_interrupts_flags
+ * @{
+ */
+
+#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
+#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
+#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
+ ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
+ ((FLAG) == RTC_FLAG_SEC))
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions
+ * @{
+ */
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_RTC_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
new file mode 100644
index 0000000..146e33e
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_sdio.h
@@ -0,0 +1,530 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the SDIO firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SDIO_H
+#define __STM32F10x_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @defgroup SDIO_Exported_Types
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref SDIO_Clock_Edge */
+
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
+ enabled or disabled.
+ This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
+ disabled when the bus is idle.
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
+ This parameter can be a value of @ref SDIO_Bus_Wide */
+
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
+ This parameter can be a value between 0x00 and 0xFF. */
+
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
+ to a card as part of a command message. If a command
+ contains an argument, it must be loaded into this register
+ before writing the command to the command register */
+
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
+ This parameter can be a value of @ref SDIO_Response_Type */
+
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
+
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
+
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
+ This parameter can be a value of @ref SDIO_Data_Block_Size */
+
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
+ is a read or write.
+ This parameter can be a value of @ref SDIO_Transfer_Direction */
+
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
+ This parameter can be a value of @ref SDIO_Transfer_Type */
+
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
+ is enabled or disabled.
+ This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup SDIO_Clock_Edge
+ * @{
+ */
+
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+ ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Bypass
+ * @{
+ */
+
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+ ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Clock_Power_Save
+ * @{
+ */
+
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+ ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Bus_Wide
+ * @{
+ */
+
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+ ((WIDE) == SDIO_BusWide_8b))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Hardware_Flow_Control
+ * @{
+ */
+
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Power_State
+ * @{
+ */
+
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+/**
+ * @}
+ */
+
+
+/** @defgroup SDIO_Interrupt_soucres
+ * @{
+ */
+
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Command_Index
+ * @{
+ */
+
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Type
+ * @{
+ */
+
+#define SDIO_Response_No ((uint32_t)0x00000000)
+#define SDIO_Response_Short ((uint32_t)0x00000040)
+#define SDIO_Response_Long ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+ ((RESPONSE) == SDIO_Response_Short) || \
+ ((RESPONSE) == SDIO_Response_Long))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+ * @{
+ */
+
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+ ((WAIT) == SDIO_Wait_Pend))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_CPSM_State
+ * @{
+ */
+
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Response_Registers
+ * @{
+ */
+
+#define SDIO_RESP1 ((uint32_t)0x00000000)
+#define SDIO_RESP2 ((uint32_t)0x00000004)
+#define SDIO_RESP3 ((uint32_t)0x00000008)
+#define SDIO_RESP4 ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Length
+ * @{
+ */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Data_Block_Size
+ * @{
+ */
+
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+ ((SIZE) == SDIO_DataBlockSize_2b) || \
+ ((SIZE) == SDIO_DataBlockSize_4b) || \
+ ((SIZE) == SDIO_DataBlockSize_8b) || \
+ ((SIZE) == SDIO_DataBlockSize_16b) || \
+ ((SIZE) == SDIO_DataBlockSize_32b) || \
+ ((SIZE) == SDIO_DataBlockSize_64b) || \
+ ((SIZE) == SDIO_DataBlockSize_128b) || \
+ ((SIZE) == SDIO_DataBlockSize_256b) || \
+ ((SIZE) == SDIO_DataBlockSize_512b) || \
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \
+ ((SIZE) == SDIO_DataBlockSize_16384b))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Direction
+ * @{
+ */
+
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+ ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Transfer_Type
+ * @{
+ */
+
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+ ((MODE) == SDIO_TransferMode_Block))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_DPSM_State
+ * @{
+ */
+
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Flags
+ * @{
+ */
+
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \
+ ((FLAG) == SDIO_FLAG_CMDREND) || \
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \
+ ((FLAG) == SDIO_FLAG_DATAEND) || \
+ ((FLAG) == SDIO_FLAG_STBITERR) || \
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \
+ ((FLAG) == SDIO_FLAG_CMDACT) || \
+ ((FLAG) == SDIO_FLAG_TXACT) || \
+ ((FLAG) == SDIO_FLAG_RXACT) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \
+ ((FLAG) == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
+ ((IT) == SDIO_IT_DCRCFAIL) || \
+ ((IT) == SDIO_IT_CTIMEOUT) || \
+ ((IT) == SDIO_IT_DTIMEOUT) || \
+ ((IT) == SDIO_IT_TXUNDERR) || \
+ ((IT) == SDIO_IT_RXOVERR) || \
+ ((IT) == SDIO_IT_CMDREND) || \
+ ((IT) == SDIO_IT_CMDSENT) || \
+ ((IT) == SDIO_IT_DATAEND) || \
+ ((IT) == SDIO_IT_STBITERR) || \
+ ((IT) == SDIO_IT_DBCKEND) || \
+ ((IT) == SDIO_IT_CMDACT) || \
+ ((IT) == SDIO_IT_TXACT) || \
+ ((IT) == SDIO_IT_RXACT) || \
+ ((IT) == SDIO_IT_TXFIFOHE) || \
+ ((IT) == SDIO_IT_RXFIFOHF) || \
+ ((IT) == SDIO_IT_TXFIFOF) || \
+ ((IT) == SDIO_IT_RXFIFOF) || \
+ ((IT) == SDIO_IT_TXFIFOE) || \
+ ((IT) == SDIO_IT_RXFIFOE) || \
+ ((IT) == SDIO_IT_TXDAVL) || \
+ ((IT) == SDIO_IT_RXDAVL) || \
+ ((IT) == SDIO_IT_SDIOIT) || \
+ ((IT) == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Read_Wait_Mode
+ * @{
+ */
+
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000)
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+ ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Exported_Functions
+ * @{
+ */
+
+void SDIO_DeInit(void);
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+void SDIO_DMACmd(FunctionalState NewState);
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_SDIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
new file mode 100644
index 0000000..920da0e
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_spi.h
@@ -0,0 +1,490 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the SPI firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_SPI_H
+#define __STM32F10x_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief SPI Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be any combination of @ref SPI_data_direction */
+
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
+ This parameter can be any combination of @ref SPI_mode */
+
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
+ This parameter can be any combination of @ref SPI_data_size */
+
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
+ This parameter can be any combination of @ref SPI_Clock_Polarity */
+
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be any combination of @ref SPI_Clock_Phase */
+
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
+ hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be any combination of @ref SPI_Slave_Select_management */
+
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
+ used to configure the transmit and receive SCK clock.
+ This parameter can be any combination of @ref SPI_BaudRate_Prescaler.
+ @note The communication clock is derived from the master
+ clock. The slave clock does not need to be set. */
+
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be any combination of @ref SPI_MSB_LSB_transmission */
+
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be any combination of @ref I2S_Mode */
+
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be any combination of @ref I2S_Standard */
+
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be any combination of @ref I2S_Data_Format */
+
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be any combination of @ref I2S_MCLK_Output */
+
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be any combination of @ref I2S_Audio_Frequency */
+
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be any combination of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Constants
+ * @{
+ */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+ ((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
+ ((PERIPH) == SPI3))
+
+/** @defgroup SPI_data_direction
+ * @{
+ */
+
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+ ((MODE) == SPI_Direction_1Line_Rx) || \
+ ((MODE) == SPI_Direction_1Line_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_mode
+ * @{
+ */
+
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+ ((MODE) == SPI_Mode_Slave))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_data_size
+ * @{
+ */
+
+#define SPI_DataSize_16b ((uint16_t)0x0800)
+#define SPI_DataSize_8b ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+ ((DATASIZE) == SPI_DataSize_8b))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Polarity
+ * @{
+ */
+
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+ ((CPOL) == SPI_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Clock_Phase
+ * @{
+ */
+
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+ ((CPHA) == SPI_CPHA_2Edge))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Slave_Select_management
+ * @{
+ */
+
+#define SPI_NSS_Soft ((uint16_t)0x0200)
+#define SPI_NSS_Hard ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+ ((NSS) == SPI_NSS_Hard))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_BaudRate_Prescaler
+ * @{
+ */
+
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_MSB_LSB_transmission
+ * @{
+ */
+
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+ ((BIT) == SPI_FirstBit_LSB))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Mode
+ * @{
+ */
+
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+ ((MODE) == I2S_Mode_SlaveRx) || \
+ ((MODE) == I2S_Mode_MasterTx) || \
+ ((MODE) == I2S_Mode_MasterRx) )
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Standard
+ * @{
+ */
+
+#define I2S_Standard_Phillips ((uint16_t)0x0000)
+#define I2S_Standard_MSB ((uint16_t)0x0010)
+#define I2S_Standard_LSB ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+ ((STANDARD) == I2S_Standard_MSB) || \
+ ((STANDARD) == I2S_Standard_LSB) || \
+ ((STANDARD) == I2S_Standard_PCMShort) || \
+ ((STANDARD) == I2S_Standard_PCMLong))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Data_Format
+ * @{
+ */
+
+#define I2S_DataFormat_16b ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
+#define I2S_DataFormat_24b ((uint16_t)0x0003)
+#define I2S_DataFormat_32b ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+ ((FORMAT) == I2S_DataFormat_16bextended) || \
+ ((FORMAT) == I2S_DataFormat_24b) || \
+ ((FORMAT) == I2S_DataFormat_32b))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_MCLK_Output
+ * @{
+ */
+
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+ ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Audio_Frequency
+ * @{
+ */
+
+#define I2S_AudioFreq_96k ((uint32_t)96000)
+#define I2S_AudioFreq_48k ((uint32_t)48000)
+#define I2S_AudioFreq_44k ((uint32_t)44100)
+#define I2S_AudioFreq_32k ((uint32_t)32000)
+#define I2S_AudioFreq_22k ((uint32_t)22050)
+#define I2S_AudioFreq_16k ((uint32_t)16000)
+#define I2S_AudioFreq_11k ((uint32_t)11025)
+#define I2S_AudioFreq_8k ((uint32_t)8000)
+#define I2S_AudioFreq_Default ((uint32_t)2)
+#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \
+ ((FREQ) == I2S_AudioFreq_48k) || \
+ ((FREQ) == I2S_AudioFreq_44k) || \
+ ((FREQ) == I2S_AudioFreq_32k) || \
+ ((FREQ) == I2S_AudioFreq_22k) || \
+ ((FREQ) == I2S_AudioFreq_16k) || \
+ ((FREQ) == I2S_AudioFreq_11k) || \
+ ((FREQ) == I2S_AudioFreq_8k) || \
+ ((FREQ) == I2S_AudioFreq_Default))
+/**
+ * @}
+ */
+
+/** @defgroup I2S_Clock_Polarity
+ * @{
+ */
+
+#define I2S_CPOL_Low ((uint16_t)0x0000)
+#define I2S_CPOL_High ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+ ((CPOL) == I2S_CPOL_High))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests
+ * @{
+ */
+
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_NSS_internal_software_mangement
+ * @{
+ */
+
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_Transmit_Receive
+ * @{
+ */
+
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_direction_transmit_receive
+ * @{
+ */
+
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+ ((DIRECTION) == SPI_Direction_Tx))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_interrupts_definition
+ * @{
+ */
+
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == SPI_I2S_IT_RXNE) || \
+ ((IT) == SPI_I2S_IT_ERR))
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_IT_CRCERR ((uint8_t)0x54)
+#define I2S_IT_UDR ((uint8_t)0x53)
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
+ ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
+ ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_I2S_flags_definition
+ * @{
+ */
+
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+#define I2S_FLAG_UDR ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+#define SPI_FLAG_MODF ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
+/**
+ * @}
+ */
+
+/** @defgroup SPI_CRC_polynomial
+ * @{
+ */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions
+ * @{
+ */
+
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_SPI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
new file mode 100644
index 0000000..6ef0436
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_tim.h
@@ -0,0 +1,1040 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the TIM firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_TIM_H
+#define __STM32F10x_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIM
+ * @{
+ */
+
+/** @defgroup TIM_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base Init structure definition
+ * @note This sturcture is used with all TIMx except for TIM6 and TIM7.
+ */
+
+typedef struct
+{
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_Counter_Mode */
+
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between 0x0000 and 0xFFFF. */
+
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;
+
+/**
+ * @brief TIM Output Compare Init structure definition
+ */
+
+typedef struct
+{
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_state */
+
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_state
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between 0x0000 and 0xFFFF */
+
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+ @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/**
+ * @brief TIM Input Capture Init structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.
+ This parameter can be a value of @ref TIM_Channel */
+
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+ uint16_t TIM_ICSelection; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/**
+ * @brief BDTR structure definition
+ * @note This sturcture is used only with TIM1 and TIM8.
+ */
+
+typedef struct
+{
+
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref Lock_level */
+
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between 0x00 and 0xFF */
+
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref Break_Input_enable_disable */
+
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref Break_Polarity */
+
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/** @defgroup TIM_Exported_constants
+ * @{
+ */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM6) || \
+ ((PERIPH) == TIM7) || \
+ ((PERIPH) == TIM8))
+
+#define IS_TIM_18_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM8))
+
+#define IS_TIM_123458_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+ ((PERIPH) == TIM2) || \
+ ((PERIPH) == TIM3) || \
+ ((PERIPH) == TIM4) || \
+ ((PERIPH) == TIM5) || \
+ ((PERIPH) == TIM8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+ * @{
+ */
+
+#define TIM_OCMode_Timing ((uint16_t)0x0000)
+#define TIM_OCMode_Active ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+ ((MODE) == TIM_OCMode_Active) || \
+ ((MODE) == TIM_OCMode_Inactive) || \
+ ((MODE) == TIM_OCMode_Toggle)|| \
+ ((MODE) == TIM_OCMode_PWM1) || \
+ ((MODE) == TIM_OCMode_PWM2) || \
+ ((MODE) == TIM_ForcedAction_Active) || \
+ ((MODE) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_One_Pulse_Mode
+ * @{
+ */
+
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+ ((MODE) == TIM_OPMode_Repetitive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel
+ * @{
+ */
+
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3) || \
+ ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+ ((CHANNEL) == TIM_Channel_2) || \
+ ((CHANNEL) == TIM_Channel_3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Clock_Division_CKD
+ * @{
+ */
+
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+ ((DIV) == TIM_CKD_DIV2) || \
+ ((DIV) == TIM_CKD_DIV4))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Counter_Mode
+ * @{
+ */
+
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
+ ((MODE) == TIM_CounterMode_Down) || \
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \
+ ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Polarity
+ * @{
+ */
+
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+ ((POLARITY) == TIM_OCPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+ * @{
+ */
+
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+ ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_state
+ * @{
+ */
+
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+ ((STATE) == TIM_OutputState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_state
+ * @{
+ */
+
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+ ((STATE) == TIM_OutputNState_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_state
+ * @{
+ */
+
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+ ((CCX) == TIM_CCx_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Capture_Compare_N_state
+ * @{
+ */
+
+#define TIM_CCxN_Enable ((uint16_t)0x0004)
+#define TIM_CCxN_Disable ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+ ((CCXN) == TIM_CCxN_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Break_Input_enable_disable
+ * @{
+ */
+
+#define TIM_Break_Enable ((uint16_t)0x1000)
+#define TIM_Break_Disable ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+ ((STATE) == TIM_Break_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Break_Polarity
+ * @{
+ */
+
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+ ((POLARITY) == TIM_BreakPolarity_High))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+ * @{
+ */
+
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+ ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup Lock_level
+ * @{
+ */
+
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+ ((LEVEL) == TIM_LOCKLevel_1) || \
+ ((LEVEL) == TIM_LOCKLevel_2) || \
+ ((LEVEL) == TIM_LOCKLevel_3))
+/**
+ * @}
+ */
+
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
+ * @{
+ */
+
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+ ((STATE) == TIM_OSSIState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
+ * @{
+ */
+
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+ ((STATE) == TIM_OSSRState_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_Idle_State
+ * @{
+ */
+
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+ ((STATE) == TIM_OCIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+ * @{
+ */
+
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+ ((STATE) == TIM_OCNIdleState_Reset))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Polarity
+ * @{
+ */
+
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+ ((POLARITY) == TIM_ICPolarity_Falling))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Selection
+ * @{
+ */
+
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+ ((SELECTION) == TIM_ICSelection_TRC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Prescaler
+ * @{
+ */
+
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \
+ ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_interrupt_sources
+ * @{
+ */
+
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_COM ((uint16_t)0x0020)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define TIM_IT_Break ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+ ((IT) == TIM_IT_CC1) || \
+ ((IT) == TIM_IT_CC2) || \
+ ((IT) == TIM_IT_CC3) || \
+ ((IT) == TIM_IT_CC4) || \
+ ((IT) == TIM_IT_COM) || \
+ ((IT) == TIM_IT_Trigger) || \
+ ((IT) == TIM_IT_Break))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address
+ * @{
+ */
+
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_RCR ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+ ((BASE) == TIM_DMABase_CR2) || \
+ ((BASE) == TIM_DMABase_SMCR) || \
+ ((BASE) == TIM_DMABase_DIER) || \
+ ((BASE) == TIM_DMABase_SR) || \
+ ((BASE) == TIM_DMABase_EGR) || \
+ ((BASE) == TIM_DMABase_CCMR1) || \
+ ((BASE) == TIM_DMABase_CCMR2) || \
+ ((BASE) == TIM_DMABase_CCER) || \
+ ((BASE) == TIM_DMABase_CNT) || \
+ ((BASE) == TIM_DMABase_PSC) || \
+ ((BASE) == TIM_DMABase_ARR) || \
+ ((BASE) == TIM_DMABase_RCR) || \
+ ((BASE) == TIM_DMABase_CCR1) || \
+ ((BASE) == TIM_DMABase_CCR2) || \
+ ((BASE) == TIM_DMABase_CCR3) || \
+ ((BASE) == TIM_DMABase_CCR4) || \
+ ((BASE) == TIM_DMABase_BDTR) || \
+ ((BASE) == TIM_DMABase_DCR))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Burst_Length
+ * @{
+ */
+
+#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_sources
+ * @{
+ */
+
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Prescaler
+ * @{
+ */
+
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Internal_Trigger_Selection
+ * @{
+ */
+
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3) || \
+ ((SELECTION) == TIM_TS_TI1F_ED) || \
+ ((SELECTION) == TIM_TS_TI1FP1) || \
+ ((SELECTION) == TIM_TS_TI2FP2) || \
+ ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+ ((SELECTION) == TIM_TS_ITR1) || \
+ ((SELECTION) == TIM_TS_ITR2) || \
+ ((SELECTION) == TIM_TS_ITR3))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_TIx_External_Clock_Source
+ * @{
+ */
+
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Polarity
+ * @{
+ */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+ * @{
+ */
+
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Forced_Action
+ * @{
+ */
+
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+ ((ACTION) == TIM_ForcedAction_InActive))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Mode
+ * @{
+ */
+
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+ ((MODE) == TIM_EncoderMode_TI2) || \
+ ((MODE) == TIM_EncoderMode_TI12))
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_Event_Source
+ * @{
+ */
+
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_COM ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define TIM_EventSource_Break ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Update_Source
+ * @{
+ */
+
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+ ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Ouput_Compare_Preload_State
+ * @{
+ */
+
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+ ((STATE) == TIM_OCPreload_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Ouput_Compare_Fast_State
+ * @{
+ */
+
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+ ((STATE) == TIM_OCFast_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Ouput_Compare_Clear_State
+ * @{
+ */
+
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+ ((STATE) == TIM_OCClear_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Trigger_Output_Source
+ * @{
+ */
+
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+ ((SOURCE) == TIM_TRGOSource_Enable) || \
+ ((SOURCE) == TIM_TRGOSource_Update) || \
+ ((SOURCE) == TIM_TRGOSource_OC1) || \
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Slave_Mode
+ * @{
+ */
+
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+ ((MODE) == TIM_SlaveMode_Gated) || \
+ ((MODE) == TIM_SlaveMode_Trigger) || \
+ ((MODE) == TIM_SlaveMode_External1))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Master_Slave_Mode
+ * @{
+ */
+
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+ ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Flags
+ * @{
+ */
+
+#define TIM_FLAG_Update ((uint16_t)0x0001)
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)
+#define TIM_FLAG_COM ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)
+#define TIM_FLAG_Break ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+ ((FLAG) == TIM_FLAG_CC1) || \
+ ((FLAG) == TIM_FLAG_CC2) || \
+ ((FLAG) == TIM_FLAG_CC3) || \
+ ((FLAG) == TIM_FLAG_CC4) || \
+ ((FLAG) == TIM_FLAG_COM) || \
+ ((FLAG) == TIM_FLAG_Trigger) || \
+ ((FLAG) == TIM_FLAG_Break) || \
+ ((FLAG) == TIM_FLAG_CC1OF) || \
+ ((FLAG) == TIM_FLAG_CC2OF) || \
+ ((FLAG) == TIM_FLAG_CC3OF) || \
+ ((FLAG) == TIM_FLAG_CC4OF))
+
+
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+ * @{
+ */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_External_Trigger_Filter
+ * @{
+ */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Exported_Functions
+ * @{
+ */
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F10x_TIM_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
new file mode 100644
index 0000000..5a5e99b
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_usart.h
@@ -0,0 +1,409 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the USART
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_USART_H
+#define __STM32F10x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @defgroup USART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief USART Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
+ The baud rate is computed using the following formula:
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+ - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
+
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_Word_Length */
+
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_Stop_Bits */
+
+ uint16_t USART_Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_Parity
+ @note When parity is enabled, the computed parity is inserted
+ at the MSB position of the transmitted data (9th bit when
+ the word length is set to 9 data bits; 8th bit when the
+ word length is set to 8 data bits). */
+
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_Mode */
+
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+ or disabled.
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/**
+ * @brief USART Clock Init Structure definition
+ */
+
+typedef struct
+{
+
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_Clock */
+
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
+ This parameter can be a value of @ref USART_Clock_Polarity */
+
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_Clock_Phase */
+
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Constants
+ * @{
+ */
+
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4) || \
+ ((PERIPH) == UART5))
+
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3))
+
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+ ((PERIPH) == USART2) || \
+ ((PERIPH) == USART3) || \
+ ((PERIPH) == UART4))
+/** @defgroup USART_Word_Length
+ * @{
+ */
+
+#define USART_WordLength_8b ((uint16_t)0x0000)
+#define USART_WordLength_9b ((uint16_t)0x1000)
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+ ((LENGTH) == USART_WordLength_9b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Stop_Bits
+ * @{
+ */
+
+#define USART_StopBits_1 ((uint16_t)0x0000)
+#define USART_StopBits_0_5 ((uint16_t)0x1000)
+#define USART_StopBits_2 ((uint16_t)0x2000)
+#define USART_StopBits_1_5 ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+ ((STOPBITS) == USART_StopBits_0_5) || \
+ ((STOPBITS) == USART_StopBits_2) || \
+ ((STOPBITS) == USART_StopBits_1_5))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Parity
+ * @{
+ */
+
+#define USART_Parity_No ((uint16_t)0x0000)
+#define USART_Parity_Even ((uint16_t)0x0400)
+#define USART_Parity_Odd ((uint16_t)0x0600)
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+ ((PARITY) == USART_Parity_Even) || \
+ ((PARITY) == USART_Parity_Odd))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Mode
+ * @{
+ */
+
+#define USART_Mode_Rx ((uint16_t)0x0004)
+#define USART_Mode_Tx ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Hardware_Flow_Control
+ * @{
+ */
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == USART_HardwareFlowControl_None) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock
+ * @{
+ */
+#define USART_Clock_Disable ((uint16_t)0x0000)
+#define USART_Clock_Enable ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+ ((CLOCK) == USART_Clock_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Polarity
+ * @{
+ */
+
+#define USART_CPOL_Low ((uint16_t)0x0000)
+#define USART_CPOL_High ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Clock_Phase
+ * @{
+ */
+
+#define USART_CPHA_1Edge ((uint16_t)0x0000)
+#define USART_CPHA_2Edge ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Last_Bit
+ * @{
+ */
+
+#define USART_LastBit_Disable ((uint16_t)0x0000)
+#define USART_LastBit_Enable ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+ ((LASTBIT) == USART_LastBit_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Interrupt_definition
+ * @{
+ */
+
+#define USART_IT_PE ((uint16_t)0x0028)
+#define USART_IT_TXE ((uint16_t)0x0727)
+#define USART_IT_TC ((uint16_t)0x0626)
+#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_IDLE ((uint16_t)0x0424)
+#define USART_IT_LBD ((uint16_t)0x0846)
+#define USART_IT_CTS ((uint16_t)0x096A)
+#define USART_IT_ERR ((uint16_t)0x0060)
+#define USART_IT_ORE ((uint16_t)0x0360)
+#define USART_IT_NE ((uint16_t)0x0260)
+#define USART_IT_FE ((uint16_t)0x0160)
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+ * @}
+ */
+
+/** @defgroup USART_DMA_Requests
+ * @{
+ */
+
+#define USART_DMAReq_Tx ((uint16_t)0x0080)
+#define USART_DMAReq_Rx ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_WakeUp_methods
+ * @{
+ */
+
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+ ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+ * @}
+ */
+
+/** @defgroup USART_LIN_Break_Detection_Length
+ * @{
+ */
+
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+ ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+ * @}
+ */
+
+/** @defgroup USART_IrDA_Low_Power
+ * @{
+ */
+
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+ ((MODE) == USART_IrDAMode_Normal))
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags
+ * @{
+ */
+
+#define USART_FLAG_CTS ((uint16_t)0x0200)
+#define USART_FLAG_LBD ((uint16_t)0x0100)
+#define USART_FLAG_TXE ((uint16_t)0x0080)
+#define USART_FLAG_TC ((uint16_t)0x0040)
+#define USART_FLAG_RXNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLE ((uint16_t)0x0010)
+#define USART_FLAG_ORE ((uint16_t)0x0008)
+#define USART_FLAG_NE ((uint16_t)0x0004)
+#define USART_FLAG_FE ((uint16_t)0x0002)
+#define USART_FLAG_PE ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\
+ ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
+ || ((USART_FLAG) != USART_FLAG_CTS))
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Exported_Functions
+ * @{
+ */
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_USART_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h
new file mode 100644
index 0000000..21b1ddb
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/inc/stm32f10x_wwdg.h
@@ -0,0 +1,114 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the WWDG firmware
+ * library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_WWDG_H
+#define __STM32F10x_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WWDG
+ * @{
+ */
+
+/** @defgroup WWDG_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup WWDG_Prescaler
+ * @{
+ */
+
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+ ((PRESCALER) == WWDG_Prescaler_2) || \
+ ((PRESCALER) == WWDG_Prescaler_4) || \
+ ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Exported_Functions
+ * @{
+ */
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_WWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
new file mode 100644
index 0000000..764fa72
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/misc.c
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file misc.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the miscellaneous firmware functions (add-on
+ * to CMSIS functions).
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @defgroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Defines
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+ * 4 bits for subpriority
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.
+ * @retval None
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
new file mode 100644
index 0000000..634f98d
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c
@@ -0,0 +1,1306 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_adc.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the ADC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_adc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+/** @defgroup ADC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Defines
+ * @{
+ */
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_Set ((uint32_t)0x00000800)
+#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_Set ((uint32_t)0x00001000)
+#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
+
+/* CR1 register Mask */
+#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CR2_ADON_Set ((uint32_t)0x00000001)
+#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_Set ((uint32_t)0x00000100)
+#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_Set ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CR2_CAL_Set ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CR2_SWSTART_Set ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CR2_JSWSTART_Set ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_Set ((uint32_t)0x00800000)
+#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
+
+/* CR2 register Mask */
+#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_Set ((uint32_t)0x0000001F)
+#define SQR2_SQ_Set ((uint32_t)0x0000001F)
+#define SQR1_SQ_Set ((uint32_t)0x0000001F)
+
+/* SQR1 register Mask */
+#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_Set ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define JSQR_JL_Set ((uint32_t)0x00300000)
+#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_Set ((uint32_t)0x00000007)
+#define SMPR2_SMP_Set ((uint32_t)0x00000007)
+
+/* ADC JDRx registers offset */
+#define JDR_Offset ((uint8_t)0x28)
+
+/* ADC1 DR register base address */
+#define DR_ADDRESS ((uint32_t)0x4001244C)
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+
+ if (ADCx == ADC1)
+ {
+ /* Enable ADC1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+ /* Release ADC1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+ }
+ else if (ADCx == ADC2)
+ {
+ /* Enable ADC2 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+ /* Release ADC2 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+ }
+ else
+ {
+ if (ADCx == ADC3)
+ {
+ /* Enable ADC3 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
+ /* Release ADC3 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the ADCx peripheral according to the specified parameters
+ * in the ADC_InitStruct.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+ * the configuration information for the specified ADC peripheral.
+ * @retval None
+ */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+ uint32_t tmpreg1 = 0;
+ uint8_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+
+ /*---------------------------- ADCx CR1 Configuration -----------------*/
+ /* Get the ADCx CR1 value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear DUALMOD and SCAN bits */
+ tmpreg1 &= CR1_CLEAR_Mask;
+ /* Configure ADCx: Dual mode and scan conversion mode */
+ /* Set DUALMOD bits according to ADC_Mode value */
+ /* Set SCAN bit according to ADC_ScanConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+ /* Write to ADCx CR1 */
+ ADCx->CR1 = tmpreg1;
+
+ /*---------------------------- ADCx CR2 Configuration -----------------*/
+ /* Get the ADCx CR2 value */
+ tmpreg1 = ADCx->CR2;
+ /* Clear CONT, ALIGN and EXTSEL bits */
+ tmpreg1 &= CR2_CLEAR_Mask;
+ /* Configure ADCx: external trigger event and continuous conversion mode */
+ /* Set ALIGN bit according to ADC_DataAlign value */
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+ /* Set CONT bit according to ADC_ContinuousConvMode value */
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+ /* Write to ADCx CR2 */
+ ADCx->CR2 = tmpreg1;
+
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/
+ /* Get the ADCx SQR1 value */
+ tmpreg1 = ADCx->SQR1;
+ /* Clear L bits */
+ tmpreg1 &= SQR1_CLEAR_Mask;
+ /* Configure ADCx: regular channel sequence length */
+ /* Set L bits according to ADC_NbrOfChannel value */
+ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;
+ /* Write to ADCx SQR1 */
+ ADCx->SQR1 = tmpreg1;
+}
+
+/**
+ * @brief Fills each ADC_InitStruct member with its default value.
+ * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+ /* Reset ADC init structure parameters values */
+ /* Initialize the ADC_Mode member */
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+ /* initialize the ADC_ScanConvMode member */
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+ /* Initialize the ADC_ContinuousConvMode member */
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+ /* Initialize the ADC_ExternalTrigConv member */
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+ /* Initialize the ADC_DataAlign member */
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+ /* Initialize the ADC_NbrOfChannel member */
+ ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/**
+ * @brief Enables or disables the specified ADC peripheral.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the ADCx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ADON bit to wake up the ADC from power down mode */
+ ADCx->CR2 |= CR2_ADON_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC peripheral */
+ ADCx->CR2 &= CR2_ADON_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC DMA request.
+ * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.
+ * Note: ADC2 hasn't a DMA capability.
+ * @param NewState: new state of the selected ADC DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC DMA request */
+ ADCx->CR2 |= CR2_DMA_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC DMA request */
+ ADCx->CR2 &= CR2_DMA_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ADC interrupts.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @param NewState: new state of the specified ADC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)ADC_IT;
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC interrupts */
+ ADCx->CR1 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected ADC interrupts */
+ ADCx->CR1 &= (~(uint32_t)itmask);
+ }
+}
+
+/**
+ * @brief Resets the selected ADC calibration registers.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Resets the selected ADC calibartion registers */
+ ADCx->CR2 |= CR2_RSTCAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC reset calibration registers status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC reset calibration registers (SET or RESET).
+ */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of RSTCAL bit */
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)
+ {
+ /* RSTCAL bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* RSTCAL bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the RSTCAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Starts the selected ADC calibration process.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval None
+ */
+void ADC_StartCalibration(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Enable the selected ADC calibration process */
+ ADCx->CR2 |= CR2_CAL_Set;
+}
+
+/**
+ * @brief Gets the selected ADC calibration status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC calibration (SET or RESET).
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of CAL bit */
+ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)
+ {
+ /* CAL bit is set: calibration on going */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAL bit is reset: end of calibration */
+ bitstatus = RESET;
+ }
+ /* Return the CAL bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the selected ADC software start conversion .
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event and start the selected
+ ADC conversion */
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event and stop the selected
+ ADC conversion */
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of SWSTART bit */
+ if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)
+ {
+ /* SWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures the discontinuous mode for the selected ADC regular
+ * group channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Number: specifies the discontinuous mode regular channel
+ * count value. This number must be between 1 and 8.
+ * @retval None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+ /* Get the old register value */
+ tmpreg1 = ADCx->CR1;
+ /* Clear the old discontinuous mode channel count */
+ tmpreg1 &= CR1_DISCNUM_Reset;
+ /* Set the discontinuous mode channel count */
+ tmpreg2 = Number - 1;
+ tmpreg1 |= tmpreg2 << 13;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg1;
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode on regular group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on regular group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC regular discontinuous mode */
+ ADCx->CR1 |= CR1_DISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC regular discontinuous mode */
+ ADCx->CR1 &= CR1_DISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures for the selected ADC regular channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_REGULAR_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* For Rank 1 to 6 */
+ if (Rank < 7)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR3;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR3 = tmpreg1;
+ }
+ /* For Rank 7 to 12 */
+ else if (Rank < 13)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR2 = tmpreg1;
+ }
+ /* For Rank 13 to 16 */
+ else
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SQR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));
+ /* Clear the old SQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+ /* Set the SQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SQR1 = tmpreg1;
+ }
+}
+
+/**
+ * @brief Enables or disables the ADCx conversion through external trigger.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion on external event */
+ ADCx->CR2 |= CR2_EXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event */
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Returns the last ADCx conversion result data for regular channel.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Return the selected ADC conversion value */
+ return (uint16_t) ADCx->DR;
+}
+
+/**
+ * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ * @retval The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+ /* Return the dual mode conversion value */
+ return (*(__IO uint32_t *) DR_ADDRESS);
+}
+
+/**
+ * @brief Enables or disables the selected ADC automatic injected group
+ * conversion after regular one.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC auto injected conversion
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC automatic injected group conversion */
+ ADCx->CR1 |= CR1_JAUTO_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC automatic injected group conversion */
+ ADCx->CR1 &= CR1_JAUTO_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the discontinuous mode for injected group
+ * channel for the specified ADC
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC discontinuous mode
+ * on injected group channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC injected discontinuous mode */
+ ADCx->CR1 |= CR1_JDISCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC injected discontinuous mode */
+ ADCx->CR1 &= CR1_JDISCEN_Reset;
+ }
+}
+
+/**
+ * @brief Configures the ADCx external trigger for injected channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
+ * This parameter can be one of the following values:
+ * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8
+ * capture compare4 event selected (for ADC1 and ADC2)
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only)
+ * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not
+ * by external trigger (for ADC1, ADC2 and ADC3)
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+ /* Get the old register value */
+ tmpreg = ADCx->CR2;
+ /* Clear the old external event selection for injected group */
+ tmpreg &= CR2_JEXTSEL_Reset;
+ /* Set the external event selection for injected group */
+ tmpreg |= ADC_ExternalTrigInjecConv;
+ /* Store the new register value */
+ ADCx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the ADCx injected channels conversion through
+ * external trigger
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC external trigger start of
+ * injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC external event selection for injected group */
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC external event selection for injected group */
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected ADC start of the injected
+ * channels conversion.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param NewState: new state of the selected ADC software start injected conversion.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ADC conversion for injected group on external event and start the selected
+ ADC injected conversion */
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;
+ }
+ else
+ {
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected
+ ADC injected conversion */
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;
+ }
+}
+
+/**
+ * @brief Gets the selected ADC Software start injected conversion Status.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @retval The new state of ADC software start injected conversion (SET or RESET).
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ /* Check the status of JSWSTART bit */
+ if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
+ {
+ /* JSWSTART bit is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* JSWSTART bit is reset */
+ bitstatus = RESET;
+ }
+ /* Return the JSWSTART bit status */
+ return bitstatus;
+}
+
+/**
+ * @brief Configures for the selected ADC injected channel its corresponding
+ * rank in the sequencer and its sample time.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles
+ * @retval None
+ */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ assert_param(IS_ADC_INJECTED_RANK(Rank));
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
+ if (ADC_Channel > ADC_Channel_9)
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR1;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR1 = tmpreg1;
+ }
+ else /* ADC_Channel include in ADC_Channel_[0..9] */
+ {
+ /* Get the old register value */
+ tmpreg1 = ADCx->SMPR2;
+ /* Calculate the mask to clear */
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
+ /* Clear the old channel sample time */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set */
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+ /* Set the new channel sample time */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->SMPR2 = tmpreg1;
+ }
+ /* Rank configuration */
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Get JL value: Number = JL+1 */
+ tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Clear the old JSQx bits for the selected rank */
+ tmpreg1 &= ~tmpreg2;
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+ /* Set the JSQx bits for the selected rank */
+ tmpreg1 |= tmpreg2;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Configures the sequencer length for injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param Length: The sequencer length.
+ * This parameter must be a number between 1 to 4.
+ * @retval None
+ */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+ uint32_t tmpreg1 = 0;
+ uint32_t tmpreg2 = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));
+
+ /* Get the old register value */
+ tmpreg1 = ADCx->JSQR;
+ /* Clear the old injected sequnence lenght JL bits */
+ tmpreg1 &= JSQR_JL_Reset;
+ /* Set the injected sequnence lenght JL bits */
+ tmpreg2 = Length - 1;
+ tmpreg1 |= tmpreg2 << 20;
+ /* Store the new register value */
+ ADCx->JSQR = tmpreg1;
+}
+
+/**
+ * @brief Set the injected channels conversion value offset
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @param Offset: the offset value for the selected ADC injected channel
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+ assert_param(IS_ADC_OFFSET(Offset));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel;
+
+ /* Set the selected injected channel data offset */
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+/**
+ * @brief Returns the ADC injected channel conversion result
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_InjectedChannel: the converted ADC injected channel.
+ * This parameter can be one of the following values:
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected
+ * @retval The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+ tmp = (uint32_t)ADCx;
+ tmp += ADC_InjectedChannel + JDR_Offset;
+
+ /* Returns the selected injected channel conversion data value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @brief Enables or disables the analog watchdog on single/all regular
+ * or injected channels
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+ * This parameter can be one of the following values:
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+ * @retval None
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */
+ tmpreg &= CR1_AWDMode_Reset;
+ /* Set the analog watchdog enable mode */
+ tmpreg |= ADC_AnalogWatchdog;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Configures the high and low thresholds of the analog watchdog.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param HighThreshold: the ADC analog watchdog High threshold value.
+ * This parameter must be a 12bit value.
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.
+ * This parameter must be a 12bit value.
+ * @retval None
+ */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+ uint16_t LowThreshold)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));
+ /* Set the ADCx high threshold */
+ ADCx->HTR = HighThreshold;
+ /* Set the ADCx low threshold */
+ ADCx->LTR = LowThreshold;
+}
+
+/**
+ * @brief Configures the analog watchdog guarded single channel
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
+ * This parameter can be one of the following values:
+ * @arg ADC_Channel_0: ADC Channel0 selected
+ * @arg ADC_Channel_1: ADC Channel1 selected
+ * @arg ADC_Channel_2: ADC Channel2 selected
+ * @arg ADC_Channel_3: ADC Channel3 selected
+ * @arg ADC_Channel_4: ADC Channel4 selected
+ * @arg ADC_Channel_5: ADC Channel5 selected
+ * @arg ADC_Channel_6: ADC Channel6 selected
+ * @arg ADC_Channel_7: ADC Channel7 selected
+ * @arg ADC_Channel_8: ADC Channel8 selected
+ * @arg ADC_Channel_9: ADC Channel9 selected
+ * @arg ADC_Channel_10: ADC Channel10 selected
+ * @arg ADC_Channel_11: ADC Channel11 selected
+ * @arg ADC_Channel_12: ADC Channel12 selected
+ * @arg ADC_Channel_13: ADC Channel13 selected
+ * @arg ADC_Channel_14: ADC Channel14 selected
+ * @arg ADC_Channel_15: ADC Channel15 selected
+ * @arg ADC_Channel_16: ADC Channel16 selected
+ * @arg ADC_Channel_17: ADC Channel17 selected
+ * @retval None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));
+ /* Get the old register value */
+ tmpreg = ADCx->CR1;
+ /* Clear the Analog watchdog channel select bits */
+ tmpreg &= CR1_AWDCH_Reset;
+ /* Set the Analog watchdog channel */
+ tmpreg |= ADC_Channel;
+ /* Store the new register value */
+ ADCx->CR1 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the temperature sensor and Vrefint channel.
+ * @param NewState: new state of the temperature sensor.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 |= CR2_TSVREFE_Set;
+ }
+ else
+ {
+ /* Disable the temperature sensor and Vrefint channel*/
+ ADC1->CR2 &= CR2_TSVREFE_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified ADC flag is set or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval The new state of ADC_FLAG (SET or RESET).
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+ /* Check the status of the specified ADC flag */
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+ {
+ /* ADC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx's pending flags.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_FLAG_AWD: Analog watchdog flag
+ * @arg ADC_FLAG_EOC: End of conversion flag
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag
+ * @retval None
+ */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+ /* Clear the selected ADC flags */
+ ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified ADC interrupt has occurred or not.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval The new state of ADC_IT (SET or RESET).
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t itmask = 0, enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_GET_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = ADC_IT >> 8;
+ /* Get the ADC_IT enable bit status */
+ enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;
+ /* Check the status of the specified ADC interrupt */
+ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+ {
+ /* ADC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* ADC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the ADC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ADCx抯 interrupt pending bits.
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ADC_IT_EOC: End of conversion interrupt mask
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+ * @retval None
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+ uint8_t itmask = 0;
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));
+ assert_param(IS_ADC_IT(ADC_IT));
+ /* Get the ADC IT index */
+ itmask = (uint8_t)(ADC_IT >> 8);
+ /* Clear the selected ADC interrupt pending bits */
+ ADCx->SR = ~(uint32_t)itmask;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
new file mode 100644
index 0000000..731f51c
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c
@@ -0,0 +1,311 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_bkp.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the BKP firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_bkp.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup BKP
+ * @brief BKP driver modules
+ * @{
+ */
+
+/** @defgroup BKP_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Defines
+ * @{
+ */
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
+
+/* --- CR Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CR_OFFSET (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber 0x01
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber 0x00
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber 0x02
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber 0x09
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber 0x08
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCR_CAL_Mask ((uint16_t)0xFF80)
+#define RTCCR_Mask ((uint16_t)0xFC7F)
+
+/* CSR register bit mask */
+#define CSR_CTE_Set ((uint16_t)0x0001)
+#define CSR_CTI_Set ((uint16_t)0x0002)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup BKP_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup BKP_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the BKP peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void BKP_DeInit(void)
+{
+ RCC_BackupResetCmd(ENABLE);
+ RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+ * @brief Configures the Tamper Pin active level.
+ * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ * This parameter can be one of the following values:
+ * @arg BKP_TamperPinLevel_High: Tamper pin active on high level
+ * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
+ * @retval None
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+ /* Check the parameters */
+ assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+ *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin activation.
+ * @param NewState: new state of the Tamper Pin activation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Tamper Pin Interrupt.
+ * @param NewState: new state of the Tamper Pin Interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Select the RTC output source to output on the Tamper pin.
+ * @param BKP_RTCOutputSource: specifies the RTC output source.
+ * This parameter can be one of the following values:
+ * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+ * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency
+ * divided by 64 on the Tamper pin.
+ * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on
+ * the Tamper pin.
+ * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on
+ * the Tamper pin.
+ * @retval None
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
+ tmpreg = BKP->RTCCR;
+ /* Clear CCO, ASOE and ASOS bits */
+ tmpreg &= RTCCR_Mask;
+
+ /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+ tmpreg |= BKP_RTCOutputSource;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Sets RTC Clock Calibration value.
+ * @param CalibrationValue: specifies the RTC Clock Calibration value.
+ * This parameter must be a number between 0 and 0x7F.
+ * @retval None
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+ tmpreg = BKP->RTCCR;
+ /* Clear CAL[6:0] bits */
+ tmpreg &= RTCCR_CAL_Mask;
+ /* Set CAL[6:0] bits according to CalibrationValue value */
+ tmpreg |= CalibrationValue;
+ /* Store the new value */
+ BKP->RTCCR = tmpreg;
+}
+
+/**
+ * @brief Writes user data to the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @param Data: data to write
+ * @retval None
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Reads data from the specified Data Backup Register.
+ * @param BKP_DR: specifies the Data Backup Register.
+ * This parameter can be BKP_DRx where x:[1, 42]
+ * @retval The content of the specified Data Backup Register
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_BKP_DR(BKP_DR));
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += BKP_DR;
+
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Event flag is set or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Event flag (SET or RESET).
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+ return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Event pending flag.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearFlag(void)
+{
+ /* Set CTE bit to clear Tamper Pin Event flag */
+ BKP->CSR |= CSR_CTE_Set;
+}
+
+/**
+ * @brief Checks whether the Tamper Pin Interrupt has occurred or not.
+ * @param None
+ * @retval The new state of the Tamper Pin Interrupt (SET or RESET).
+ */
+ITStatus BKP_GetITStatus(void)
+{
+ return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
+}
+
+/**
+ * @brief Clears Tamper Pin Interrupt pending bit.
+ * @param None
+ * @retval None
+ */
+void BKP_ClearITPendingBit(void)
+{
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+ BKP->CSR |= CSR_CTI_Set;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
new file mode 100644
index 0000000..63b0a6d
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c
@@ -0,0 +1,990 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_can.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the CAN firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_can.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+/** @defgroup CAN_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Defines
+ * @{
+ */
+
+/* CAN Master Control Register bits */
+#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */
+#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */
+#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */
+#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */
+#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */
+#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */
+#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */
+#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */
+#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Master Status Register bits */
+#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */
+#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */
+#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */
+
+/* CAN Transmit Status Register bits */
+#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */
+#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */
+#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */
+#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */
+#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */
+#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */
+#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */
+#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */
+#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */
+#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */
+#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */
+#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */
+
+/* CAN Receive FIFO 0 Register bits */
+#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */
+#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */
+#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */
+
+/* CAN Receive FIFO 1 Register bits */
+#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */
+#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */
+#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */
+
+/* CAN Error Status Register bits */
+#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */
+#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */
+#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TimeOut ((uint32_t)0x0000FFFF)
+
+/* Time out for SLAK bit */
+#define SLAK_TimeOut ((uint32_t)0x0000FFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_FunctionPrototypes
+ * @{
+ */
+
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.
+ * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @retval None.
+ */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ if (CANx == CAN1)
+ {
+ /* Enable CAN1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+ /* Release CAN1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+ }
+ else
+ {
+ /* Enable CAN2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+ /* Release CAN2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+ * contains the configuration information for the CAN peripheral.
+ * @retval Constant indicates initialization succeed which will be
+ * CANINITFAILED or CANINITOK.
+ */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+ uint8_t InitStatus = CANINITFAILED;
+ uint32_t wait_ack = 0x00000000;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+ /* exit from sleep mode */
+ CANx->MCR &= ~MCR_SLEEP;
+
+ /* Request initialisation */
+ CANx->MCR |= MCR_INRQ ;
+
+ /* Wait the acknowledge */
+ while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSR & MSR_INAK) != MSR_INAK)
+ {
+ InitStatus = CANINITFAILED;
+ }
+ else
+ {
+ /* Set the time triggered communication mode */
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)
+ {
+ CANx->MCR |= MCR_TTCM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)
+ {
+ CANx->MCR |= MCR_ABOM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)
+ {
+ CANx->MCR |= MCR_AWUM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (CAN_InitStruct->CAN_NART == ENABLE)
+ {
+ CANx->MCR |= MCR_NART;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)
+ {
+ CANx->MCR |= MCR_RFLM;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)
+ {
+ CANx->MCR |= MCR_TXFP;
+ }
+ else
+ {
+ CANx->MCR &= ~MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+ /* Request leave initialisation */
+ CANx->MCR &= ~MCR_INRQ;
+
+ /* Wait the acknowledge */
+ wait_ack = 0x00;
+
+ while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut))
+ {
+ wait_ack++;
+ }
+
+ /* ...and check acknowledged */
+ if ((CANx->MSR & MSR_INAK) == MSR_INAK)
+ {
+ InitStatus = CANINITFAILED;
+ }
+ else
+ {
+ InitStatus = CANINITOK ;
+ }
+ }
+
+ /* At this step, return the status of initialization */
+ return InitStatus;
+}
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+ * structure that contains the configuration information.
+ * @retval None.
+ */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+ filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+ /* Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+
+ /* Filter Deactivation */
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+ {
+ /* 16-bit scale for the filter */
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+ {
+ /* 32-bit scale for the filter */
+ CAN1->FS1R |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+ {
+ /*Id/Mask mode for the filter*/
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter FIFO assignment */
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+ {
+ CAN1->FA1R |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Fills each CAN_InitStruct member with its default value.
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
+ * will be initialized.
+ * @retval None.
+ */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+ /* Reset CAN init structure parameters values */
+ /* Initialize the time triggered communication mode */
+ CAN_InitStruct->CAN_TTCM = DISABLE;
+ /* Initialize the automatic bus-off management */
+ CAN_InitStruct->CAN_ABOM = DISABLE;
+ /* Initialize the automatic wake-up mode */
+ CAN_InitStruct->CAN_AWUM = DISABLE;
+ /* Initialize the no automatic retransmission */
+ CAN_InitStruct->CAN_NART = DISABLE;
+ /* Initialize the receive FIFO locked mode */
+ CAN_InitStruct->CAN_RFLM = DISABLE;
+ /* Initialize the transmit FIFO priority */
+ CAN_InitStruct->CAN_TXFP = DISABLE;
+ /* Initialize the CAN_Mode member */
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+ /* Initialize the CAN_SJW member */
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+ /* Initialize the CAN_BS1 member */
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+ /* Initialize the CAN_BS2 member */
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+ /* Initialize the CAN_Prescaler member */
+ CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+ * @brief Select the start bank filter for slave CAN.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
+ * @retval None.
+ */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+ /* enter Initialisation mode for the filter */
+ CAN1->FMR |= FMR_FINIT;
+ /* Select the start slave bank */
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+ /* Leave Initialisation mode for the filter */
+ CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+ * @brief Enables or disables the specified CAN interrupts.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+ * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0,
+ * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1,
+ * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
+ * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or
+ * CAN_IT_SLK.
+ * @param NewState: new state of the CAN interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ITConfig(CAN_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected CAN interrupt */
+ CANx->IER |= CAN_IT;
+ }
+ else
+ {
+ /* Disable the selected CAN interrupt */
+ CANx->IER &= ~CAN_IT;
+ }
+}
+
+/**
+ * @brief Initiates the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN
+ * DLC and CAN datas.
+ * @retval The number of the mailbox that is used for transmission
+ * or CAN_NO_MB if there is no empty mailbox.
+ */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+ uint8_t transmit_mailbox = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+ assert_param(IS_CAN_RTR(TxMessage->RTR));
+ assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+ /* Select one empty transmit mailbox */
+ if ((CANx->TSR&TSR_TME0) == TSR_TME0)
+ {
+ transmit_mailbox = 0;
+ }
+ else if ((CANx->TSR&TSR_TME1) == TSR_TME1)
+ {
+ transmit_mailbox = 1;
+ }
+ else if ((CANx->TSR&TSR_TME2) == TSR_TME2)
+ {
+ transmit_mailbox = 2;
+ }
+ else
+ {
+ transmit_mailbox = CAN_NO_MB;
+ }
+
+ if (transmit_mailbox != CAN_NO_MB)
+ {
+ /* Set up the Id */
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+ if (TxMessage->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(TxMessage->StdId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE |
+ TxMessage->RTR);
+ }
+
+
+ /* Set up the DLC */
+ TxMessage->DLC &= (uint8_t)0x0000000F;
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+ /* Set up the data field */
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
+ ((uint32_t)TxMessage->Data[2] << 16) |
+ ((uint32_t)TxMessage->Data[1] << 8) |
+ ((uint32_t)TxMessage->Data[0]));
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
+ ((uint32_t)TxMessage->Data[6] << 16) |
+ ((uint32_t)TxMessage->Data[5] << 8) |
+ ((uint32_t)TxMessage->Data[4]));
+ /* Request transmission */
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+ }
+ return transmit_mailbox;
+}
+
+/**
+ * @brief Checks the transmission of a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param TransmitMailbox: the number of the mailbox that is used for transmission.
+ * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.
+ */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+ /* RQCP, TXOK and TME bits */
+ uint8_t state = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+ switch (TransmitMailbox)
+ {
+ case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2);
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0);
+ state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26);
+ break;
+ case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6);
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8);
+ state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27);
+ break;
+ case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14);
+ state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16);
+ state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28);
+ break;
+ default:
+ state = CANTXFAILED;
+ break;
+ }
+ switch (state)
+ {
+ /* transmit pending */
+ case (0x0): state = CANTXPENDING;
+ break;
+ /* transmit failed */
+ case (0x5): state = CANTXFAILED;
+ break;
+ /* transmit succedeed */
+ case (0x7): state = CANTXOK;
+ break;
+ default:
+ state = CANTXFAILED;
+ break;
+ }
+ return state;
+}
+
+/**
+ * @brief Cancels a transmit request.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param Mailbox: Mailbox number.
+ * @retval None.
+ */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+ /* abort transmission */
+ switch (Mailbox)
+ {
+ case (0): CANx->TSR |= TSR_ABRQ0;
+ break;
+ case (1): CANx->TSR |= TSR_ABRQ1;
+ break;
+ case (2): CANx->TSR |= TSR_ABRQ2;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Releases a FIFO.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None.
+ */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ CANx->RF0R = RF0R_RFOM0;
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ CANx->RF1R = RF1R_RFOM1;
+ }
+}
+
+/**
+ * @brief Returns the number of pending messages.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval NbMessage which is the number of pending message.
+ */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+ uint8_t message_pending=0;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ if (FIFONumber == CAN_FIFO0)
+ {
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+ }
+ else if (FIFONumber == CAN_FIFO1)
+ {
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+ }
+ else
+ {
+ message_pending = 0;
+ }
+ return message_pending;
+}
+
+/**
+ * @brief Receives a message.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @param RxMessage: pointer to a structure receive message which
+ * contains CAN Id, CAN DLC, CAN datas and FMI number.
+ * @retval None.
+ */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FIFO(FIFONumber));
+ /* Get the Id */
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ if (RxMessage->IDE == CAN_ID_STD)
+ {
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+ }
+ else
+ {
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+ }
+
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ /* Get the data field */
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ /* Release the FIFO */
+ CAN_FIFORelease(CANx, FIFONumber);
+}
+
+/**
+ * @brief Enables or disables the DBG Freeze for CAN.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param NewState: new state of the CAN peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Debug Freeze */
+ CANx->MCR |= MCR_DBF;
+ }
+ else
+ {
+ /* Disable Debug Freeze */
+ CANx->MCR &= ~MCR_DBF;
+ }
+}
+
+/**
+ * @brief Enters the low power mode.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.
+ */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+ uint8_t sleepstatus = CANSLEEPFAILED;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Request Sleep mode */
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+ {
+ /* Sleep mode not entered */
+ sleepstatus = CANSLEEPOK;
+ }
+ /* At this step, sleep mode status */
+ return (uint8_t)sleepstatus;
+}
+
+/**
+ * @brief Wakes the CAN up.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.
+ */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+ uint32_t wait_slak = SLAK_TimeOut ;
+ uint8_t wakeupstatus = CANWAKEUPFAILED;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+ /* Wake up request */
+ CANx->MCR &= ~MCR_SLEEP;
+
+ /* Sleep mode status */
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+ {
+ wait_slak--;
+ }
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+ {
+ /* Sleep mode exited */
+ wakeupstatus = CANWAKEUPOK;
+ }
+ /* At this step, sleep mode status */
+ return (uint8_t)wakeupstatus;
+}
+
+/**
+ * @brief Checks whether the specified CAN flag is set or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to check.
+ * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF.
+ * @retval The new state of CAN_FLAG (SET or RESET).
+ */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FLAG(CAN_FLAG));
+ /* Check the status of the specified CAN flag */
+ if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET)
+ {
+ /* CAN_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* CAN_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the CAN_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the CAN's pending flags.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_FLAG: specifies the flag to clear.
+ * @retval None.
+ */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_FLAG(CAN_FLAG));
+ /* Clear the selected CAN flags */
+ CANx->ESR &= ~CAN_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified CAN interrupt has occurred or not.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the CAN interrupt source to check.
+ * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2,
+ * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1,
+ * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV,
+ * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK.
+ * @retval The new state of CAN_IT (SET or RESET).
+ */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ ITStatus pendingbitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ITStatus(CAN_IT));
+ switch (CAN_IT)
+ {
+ case CAN_IT_RQCP0:
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0);
+ break;
+ case CAN_IT_RQCP1:
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1);
+ break;
+ case CAN_IT_RQCP2:
+ pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2);
+ break;
+ case CAN_IT_FF0:
+ pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0);
+ break;
+ case CAN_IT_FOV0:
+ pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0);
+ break;
+ case CAN_IT_FF1:
+ pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1);
+ break;
+ case CAN_IT_FOV1:
+ pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1);
+ break;
+ case CAN_IT_EWG:
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF);
+ break;
+ case CAN_IT_EPV:
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF);
+ break;
+ case CAN_IT_BOF:
+ pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF);
+ break;
+ case CAN_IT_SLK:
+ pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI);
+ break;
+ case CAN_IT_WKU:
+ pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI);
+ break;
+ default :
+ pendingbitstatus = RESET;
+ break;
+ }
+ /* Return the CAN_IT status */
+ return pendingbitstatus;
+}
+
+/**
+ * @brief Clears the CAN抯 interrupt pending bits.
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CAN_IT: specifies the interrupt pending bit to clear.
+ * @retval None.
+ */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_PERIPH(CANx));
+ assert_param(IS_CAN_ITStatus(CAN_IT));
+ switch (CAN_IT)
+ {
+ case CAN_IT_RQCP0:
+ CANx->TSR = TSR_RQCP0; /* rc_w1*/
+ break;
+ case CAN_IT_RQCP1:
+ CANx->TSR = TSR_RQCP1; /* rc_w1*/
+ break;
+ case CAN_IT_RQCP2:
+ CANx->TSR = TSR_RQCP2; /* rc_w1*/
+ break;
+ case CAN_IT_FF0:
+ CANx->RF0R = RF0R_FULL0; /* rc_w1*/
+ break;
+ case CAN_IT_FOV0:
+ CANx->RF0R = RF0R_FOVR0; /* rc_w1*/
+ break;
+ case CAN_IT_FF1:
+ CANx->RF1R = RF1R_FULL1; /* rc_w1*/
+ break;
+ case CAN_IT_FOV1:
+ CANx->RF1R = RF1R_FOVR1; /* rc_w1*/
+ break;
+ case CAN_IT_EWG:
+ CANx->ESR &= ~ ESR_EWGF; /* rw */
+ break;
+ case CAN_IT_EPV:
+ CANx->ESR &= ~ ESR_EPVF; /* rw */
+ break;
+ case CAN_IT_BOF:
+ CANx->ESR &= ~ ESR_BOFF; /* rw */
+ break;
+ case CAN_IT_WKU:
+ CANx->MSR = MSR_WKUI; /* rc_w1*/
+ break;
+ case CAN_IT_SLK:
+ CANx->MSR = MSR_SLAKI; /* rc_w1*/
+ break;
+ default :
+ break;
+ }
+}
+
+/**
+ * @brief Checks whether the CAN interrupt has occurred or not.
+ * @param CAN_Reg: specifies the CAN interrupt register to check.
+ * @param It_Bit: specifies the interrupt source bit to check.
+ * @retval The new state of the CAN Interrupt (SET or RESET).
+ */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+ ITStatus pendingbitstatus = RESET;
+
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+ {
+ /* CAN_IT is set */
+ pendingbitstatus = SET;
+ }
+ else
+ {
+ /* CAN_IT is reset */
+ pendingbitstatus = RESET;
+ }
+ return pendingbitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
new file mode 100644
index 0000000..812aff0
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
@@ -0,0 +1,163 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_crc.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the CRC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_crc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+/** @defgroup CRC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Defines
+ * @{
+ */
+
+/* CR register bit mask */
+
+#define CR_RESET_Set ((uint32_t)0x00000001)
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the CRC Data register (DR).
+ * @param None
+ * @retval None
+ */
+void CRC_ResetDR(void)
+{
+ /* Reset CRC generator */
+ CRC->CR = CR_RESET_Set;
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).
+ * @param Data: data word(32-bit) to compute its CRC
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+ CRC->DR = Data;
+
+ return (CRC->DR);
+}
+
+/**
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ * @param pBuffer: pointer to the buffer containing the data to be computed
+ * @param BufferLength: length of the buffer to be computed
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+ uint32_t index = 0;
+
+ for(index = 0; index < BufferLength; index++)
+ {
+ CRC->DR = pBuffer[index];
+ }
+ return (CRC->DR);
+}
+
+/**
+ * @brief Returns the current CRC value.
+ * @param None
+ * @retval 32-bit CRC
+ */
+uint32_t CRC_GetCRC(void)
+{
+ return (CRC->DR);
+}
+
+/**
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @param IDValue: 8-bit value to be stored in the ID register
+ * @retval None
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+ CRC->IDR = IDValue;
+}
+
+/**
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register
+ * @param None
+ * @retval 8-bit value of the ID register
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+ return (CRC->IDR);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c
new file mode 100644
index 0000000..b2c1e60
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c
@@ -0,0 +1,431 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dac.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the DAC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dac.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/** @defgroup DAC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Defines
+ * @{
+ */
+
+/* DAC EN mask */
+#define CR_EN_Set ((uint32_t)0x00000001)
+
+/* DAC DMAEN mask */
+#define CR_DMAEN_Set ((uint32_t)0x00001000)
+
+/* CR register Mask */
+#define CR_CLEAR_Mask ((uint32_t)0x00000FFE)
+
+/* DAC SWTRIG mask */
+#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_Set ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_Offset ((uint32_t)0x00000008)
+#define DHR12R2_Offset ((uint32_t)0x00000014)
+#define DHR12RD_Offset ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_Offset ((uint32_t)0x0000002C)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void DAC_DeInit(void)
+{
+ /* Enable DAC reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+ /* Release DAC from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+ * contains the configuration information for the specified DAC channel.
+ * @retval None
+ */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+/*---------------------------- DAC CR Configuration --------------------------*/
+ /* Get the DAC CR value */
+ tmpreg1 = DAC->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger, wave genration,
+ mask/amplitude for wave genration */
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set WAVEx bits according to DAC_WaveGeneration value */
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+ /* Set BOFFx bit according to DAC_OutputBuffer value */
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << DAC_Channel;
+ /* Write to DAC CR */
+ DAC->CR = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the DAC_Trigger member */
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+ /* Initialize the DAC_WaveGeneration member */
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+ /* Initialize the DAC_OutputBuffer member */
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DAC->CR |= CR_EN_Set << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DAC->CR &= ~(CR_EN_Set << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DAC->CR |= CR_DMAEN_Set << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4);
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4));
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param NewState: new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DAC->SWTRIGR |= DUAL_SWTRIG_Set ;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DAC->SWTRIGR &= DUAL_SWTRIG_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_Wave: Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_Wave_Noise: noise wave generation
+ * @arg DAC_Wave_Triangle: triangle wave generation
+ * @param NewState: new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ DAC->CR |= DAC_Wave << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DAC_Align: Specifies the data alignement for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R1_Offset + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel2.
+ * @param DAC_Align: Specifies the data alignement for DAC channel2.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12R2_Offset + DAC_Align;
+
+ /* Set the DAC channel2 selected data holding register */
+ *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual channel
+ * DAC.
+ * @param DAC_Align: Specifies the data alignement for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data
+ * holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data
+ * holding register.
+ * @retval None
+ */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (DAC_Align == DAC_Align_8b_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)DAC_BASE;
+ tmp += DHR12RD_Offset + DAC_Align;
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC cahnnel.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+ tmp = (uint32_t) DAC_BASE ;
+ tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2);
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
new file mode 100644
index 0000000..1cf5447
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c
@@ -0,0 +1,152 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dbgmcu.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the DBGMCU firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dbgmcu.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DBGMCU
+ * @brief DBGMCU driver modules
+ * @{
+ */
+
+/** @defgroup DBGMCU_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Defines
+ * @{
+ */
+
+#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF)
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Returns the device revision identifier.
+ * @param None
+ * @retval Device revision identifier
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+ return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @param None
+ * @retval Device identifier
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+ return(DBGMCU->IDCODE & IDCODE_DEVID_Mask);
+}
+
+/**
+ * @brief Configures the specified peripheral and low power mode behavior
+ * when the MCU under Debug mode.
+ * @param DBGMCU_Periph: specifies the peripheral and low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+ * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
+ * @param NewState: new state of the specified peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->CR |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->CR &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
new file mode 100644
index 0000000..f2c2cb3
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c
@@ -0,0 +1,693 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_dma.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the DMA firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_dma.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/** @defgroup DMA_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Defines
+ * @{
+ */
+
+/* DMA ENABLE mask */
+#define CCR_ENABLE_Set ((uint32_t)0x00000001)
+#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
+#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
+#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
+#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
+#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
+#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)
+#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F)
+#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0)
+#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00)
+#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000)
+#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000)
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval None
+ */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
+ /* Reset DMAy Channelx control register */
+ DMAy_Channelx->CCR = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAy_Channelx->CNDTR = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAy_Channelx->CPAR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAy_Channelx->CMAR = 0;
+
+ if (DMAy_Channelx == DMA1_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA1->IFCR |= DMA1_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA1->IFCR |= DMA1_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA1->IFCR |= DMA1_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA1->IFCR |= DMA1_Channel4_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA1->IFCR |= DMA1_Channel5_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA1->IFCR |= DMA1_Channel6_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA1_Channel7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA1->IFCR |= DMA1_Channel7_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel1 */
+ DMA2->IFCR |= DMA2_Channel1_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel2 */
+ DMA2->IFCR |= DMA2_Channel2_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel3 */
+ DMA2->IFCR |= DMA2_Channel3_IT_Mask;
+ }
+ else if (DMAy_Channelx == DMA2_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel4 */
+ DMA2->IFCR |= DMA2_Channel4_IT_Mask;
+ }
+ else
+ {
+ if (DMAy_Channelx == DMA2_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel5 */
+ DMA2->IFCR |= DMA2_Channel5_IT_Mask;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified
+ * parameters in the DMA_InitStruct.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+ * contains the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+ /* Get the DMAy_Channelx CCR value */
+ tmpreg = DMAy_Channelx->CCR;
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpreg &= CCR_CLEAR_Mask;
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to DMA_DIR value */
+ /* Set CIRC bit according to DMA_Mode value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set the MEM2MEM bit according to DMA_M2M value */
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+ /* Write to DMAy Channelx CCR */
+ DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+ /* Write to DMAy Channelx CPAR */
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+ /* Write to DMAy Channelx CMAR */
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+ /* Initialize the DMA_MemoryBaseAddr member */
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+ /* Initialize the DMA_M2M member */
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param NewState: new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAy_Channelx->CCR |= CCR_ENABLE_Set;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @param NewState: new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAy_Channelx->CCR |= DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAy_Channelx->CCR &= ~DMA_IT;
+ }
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval The number of remaining data units in the current DMAy Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.
+ * @param DMA_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval The new state of DMA_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
+
+ /* Calculate the used DMA */
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMA flag */
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
+ {
+ /* DMA_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMA_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's pending flags.
+ * @param DMA_FLAG: specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ * @retval None
+ */
+void DMA_ClearFlag(uint32_t DMA_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+ /* Calculate the used DMA */
+
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMA flags */
+ DMA2->IFCR = DMA_FLAG;
+ }
+ else
+ {
+ /* Clear the selected DMA flags */
+ DMA1->IFCR = DMA_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
+ * @param DMA_IT: specifies the DMA interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval The new state of DMA_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMA_IT));
+
+ /* Calculate the used DMA */
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMA interrupt */
+ if ((tmpreg & DMA_IT) != (uint32_t)RESET)
+ {
+ /* DMA_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMA_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMA_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx抯 interrupt pending bits.
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ * @retval None
+ */
+void DMA_ClearITPendingBit(uint32_t DMA_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));
+
+ /* Calculate the used DMA */
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMA interrupt pending bits */
+ DMA2->IFCR = DMA_IT;
+ }
+ else
+ {
+ /* Clear the selected DMA interrupt pending bits */
+ DMA1->IFCR = DMA_IT;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c
new file mode 100644
index 0000000..b489e18
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c
@@ -0,0 +1,268 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_exti.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the EXTI firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_exti.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+/** @defgroup EXTI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Defines
+ * @{
+ */
+
+#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMR = 0x00000000;
+ EXTI->EMR = 0x00000000;
+ EXTI->RTSR = 0x00000000;
+ EXTI->FTSR = 0x00000000;
+ EXTI->PR = 0x000FFFFF;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ * that contains the configuration information for the EXTI peripheral.
+ * @retval None
+ */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+ /* Clear Rising Falling edge configuration */
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+ /* Select the trigger for the selected external interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+ }
+ else
+ {
+ tmp = (uint32_t)EXTI_BASE;
+ tmp += EXTI_InitStruct->EXTI_Trigger;
+
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+ }
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode;
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+ }
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt.
+ * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line: specifies the EXTI line flag to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI抯 line pending flags.
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line: specifies the EXTI line to check.
+ * This parameter can be:
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ enablestatus = EXTI->IMR & EXTI_Line;
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI抯 line pending bits.
+ * @param EXTI_Line: specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).
+ * @retval None
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(EXTI_Line));
+
+ EXTI->PR = EXTI_Line;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
new file mode 100644
index 0000000..013deb4
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c
@@ -0,0 +1,878 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_flash.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the FLASH firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_flash.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/** @defgroup FLASH_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Defines
+ * @{
+ */
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
+
+/* Flash Control Register bits */
+#define CR_PG_Set ((uint32_t)0x00000001)
+#define CR_PG_Reset ((uint32_t)0x00001FFE)
+#define CR_PER_Set ((uint32_t)0x00000002)
+#define CR_PER_Reset ((uint32_t)0x00001FFD)
+#define CR_MER_Set ((uint32_t)0x00000004)
+#define CR_MER_Reset ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set ((uint32_t)0x00000020)
+#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
+#define CR_STRT_Set ((uint32_t)0x00000040)
+#define CR_LOCK_Set ((uint32_t)0x00000080)
+
+/* FLASH Mask */
+#define RDPRT_Mask ((uint32_t)0x00000002)
+#define WRP0_Mask ((uint32_t)0x000000FF)
+#define WRP1_Mask ((uint32_t)0x0000FF00)
+#define WRP2_Mask ((uint32_t)0x00FF0000)
+#define WRP3_Mask ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define RDP_Key ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x00000FFF)
+#define ProgramTimeout ((uint32_t)0x0000000F)
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+ * @{
+ */
+
+static void delay(void);
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @param FLASH_Latency: specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle
+ * @arg FLASH_Latency_1: FLASH One Latency cycle
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles
+ * @retval None
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpreg = FLASH->ACR;
+
+ /* Sets the Latency value */
+ tmpreg &= ACR_LATENCY_Mask;
+ tmpreg |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->ACR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Half cycle flash access.
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+ * This parameter can be one of the following values:
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+ * @retval None
+ */
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
+
+ /* Enable or disable the Half cycle access */
+ FLASH->ACR &= ACR_HLFCYA_Mask;
+ FLASH->ACR |= FLASH_HalfCycleAccess;
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
+ * This parameter can be one of the following values:
+ * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+ * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+ * @retval None
+ */
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
+
+ /* Enable or disable the Prefetch Buffer */
+ FLASH->ACR &= ACR_PRFTBE_Mask;
+ FLASH->ACR |= FLASH_PrefetchBuffer;
+}
+
+/**
+ * @brief Unlocks the FLASH Program Erase Controller.
+ * @param None
+ * @retval None
+ */
+void FLASH_Unlock(void)
+{
+ /* Authorize the FPEC Access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+ * @brief Locks the FLASH Program Erase Controller.
+ * @param None
+ * @retval None
+ */
+void FLASH_Lock(void)
+{
+ /* Set the Lock Bit to lock the FPEC and the FCR */
+ FLASH->CR |= CR_LOCK_Set;
+}
+
+/**
+ * @brief Erases a specified FLASH page.
+ * @param Page_Address: The page address to be erased.
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Page_Address));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase the page */
+ FLASH->CR|= CR_PER_Set;
+ FLASH->AR = Page_Address;
+ FLASH->CR|= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the erase operation is completed, disable the PER Bit */
+ FLASH->CR &= CR_PER_Reset;
+ }
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= CR_MER_Set;
+ FLASH->CR |= CR_STRT_Set;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the erase operation is completed, disable the MER Bit */
+ FLASH->CR &= CR_MER_Reset;
+ }
+ }
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes and then deactivates the Read
+ * protection. If the user needs to keep the Read protection activated,
+ * he has to enable it after this function call (using
+ * FLASH_ReadOutProtection function)
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* if the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ /* Disable the Read protection */
+ OB->RDP= RDP_Key;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ }
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified address.
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FLASH_ADDRESS(Address));
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= CR_PG_Set;
+
+ *(__IO uint16_t*)Address = Data;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the PG Bit */
+ FLASH->CR &= CR_PG_Reset;
+ }
+ }
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @param FLASH_Pages: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31
+ * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3
+ * and FLASH_WRProt_Pages124to127
+ * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255
+ * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127
+ * @arg FLASH_WRProt_AllPages
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
+
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTPG_Set;
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 = WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 = WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+ if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+ {
+ OB->WRP2 = WRP2_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
+ {
+ OB->WRP3 = WRP3_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ }
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note If the user has already programmed the other option bytes before calling
+ * this function, he must re-program them since this function erases all option bytes.
+ * @param Newstate: new state of the ReadOut Protection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* Authorizes the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+ FLASH->CR |= CR_OPTER_Set;
+ FLASH->CR |= CR_STRT_Set;
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+ if(NewState != DISABLE)
+ {
+ OB->RDP = 0x00;
+ }
+ else
+ {
+ OB->RDP = RDP_Key;
+ }
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(EraseTimeout);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ else
+ {
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CR &= CR_OPTER_Reset;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @param OB_IWDG: Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param OB_STOP: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param OB_STDBY: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= CR_OPTPG_Set;
+
+ OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(ProgramTimeout);
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= CR_OPTPG_Reset;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @param None
+ * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ * and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+ /* Return the User Option Byte */
+ return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.
+ * @param None
+ * @retval The FLASH Write Protection Option Bytes Register value
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+ /* Return the Falsh write protection Register value */
+ return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.
+ * @param None
+ * @retval FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+ FlagStatus readoutstatus = RESET;
+ if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+ {
+ readoutstatus = SET;
+ }
+ else
+ {
+ readoutstatus = RESET;
+ }
+ return readoutstatus;
+}
+
+/**
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
+ * @param None
+ * @retval FLASH Prefetch Buffer Status (SET or RESET).
+ */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+
+ if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_ERROR: FLASH Error Interrupt
+ * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+ * @param NewState: new state of the specified Flash interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @param FLASH_FLAG: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+ {
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH抯 pending flags.
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @retval None
+ */
+void FLASH_ClearFlag(uint16_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP or FLASH_COMPLETE
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+ FLASH_Status flashstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+ {
+ flashstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_PGERR) != 0)
+ {
+ flashstatus = FLASH_ERROR_PG;
+ }
+ else
+ {
+ if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )
+ {
+ flashstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ flashstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the Flash Status */
+ return flashstatus;
+}
+
+/**
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.
+ * @param Timeout: FLASH progamming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the Flash Status */
+ status = FLASH_GetStatus();
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ delay();
+ status = FLASH_GetStatus();
+ Timeout--;
+ }
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @brief Inserts a time delay.
+ * @param None
+ * @retval None
+ */
+static void delay(void)
+{
+ __IO uint32_t i = 0;
+ for(i = 0xFF; i != 0; i--)
+ {
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
new file mode 100644
index 0000000..187cb45
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c
@@ -0,0 +1,858 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_fsmc.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the FSMC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_fsmc.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FSMC
+ * @brief FSMC driver modules
+ * @{
+ */
+
+/** @defgroup FSMC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Defines
+ * @{
+ */
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_Set ((uint32_t)0x00000001)
+#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_Set ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_Set ((uint32_t)0x00000004)
+#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_Set ((uint32_t)0x00000040)
+#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
+#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
+ * reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @retval None
+ */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+
+ /* FSMC_Bank1_NORSRAM1 */
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
+ }
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+ else
+ {
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
+ }
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval None
+ */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Set the FSMC_Bank2 registers to their reset values */
+ FSMC_Bank2->PCR2 = 0x00000018;
+ FSMC_Bank2->SR2 = 0x00000040;
+ FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+ FSMC_Bank2->PATT2 = 0xFCFCFCFC;
+ }
+ /* FSMC_Bank3_NAND */
+ else
+ {
+ /* Set the FSMC_Bank3 registers to their reset values */
+ FSMC_Bank3->PCR3 = 0x00000018;
+ FSMC_Bank3->SR3 = 0x00000040;
+ FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+ FSMC_Bank3->PATT3 = 0xFCFCFCFC;
+ }
+}
+
+/**
+ * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void FSMC_PCCARDDeInit(void)
+{
+ /* Set the FSMC_Bank4 registers to their reset values */
+ FSMC_Bank4->PCR4 = 0x00000018;
+ FSMC_Bank4->SR4 = 0x00000000;
+ FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+ FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+ FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
+ * parameters in the FSMC_NORSRAMInitStruct.
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
+ * structure that contains the configuration information for
+ * the FSMC NOR/SRAM specified Banks.
+ * @retval None
+ */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
+
+ /* Bank1 NOR/SRAM control register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+ {
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
+ }
+ /* Bank1 NOR/SRAM timing register configuration */
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+
+
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+ {
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+ }
+ else
+ {
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC NAND Banks according to the specified
+ * parameters in the FSMC_NANDInitStruct.
+ * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
+ * structure that contains the configuration information for the FSMC NAND specified Banks.
+ * @retval None
+ */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+ /* Check the parameters */
+ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+ assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+ assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+ assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+ assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+ assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+ assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+ PCR_MemoryType_NAND |
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NANDInitStruct->FSMC_ECC |
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* FSMC_Bank2_NAND registers configuration */
+ FSMC_Bank2->PCR2 = tmppcr;
+ FSMC_Bank2->PMEM2 = tmppmem;
+ FSMC_Bank2->PATT2 = tmppatt;
+ }
+ else
+ {
+ /* FSMC_Bank3_NAND registers configuration */
+ FSMC_Bank3->PCR3 = tmppcr;
+ FSMC_Bank3->PMEM3 = tmppmem;
+ FSMC_Bank3->PATT3 = tmppatt;
+ }
+}
+
+/**
+ * @brief Initializes the FSMC PCCARD Bank according to the specified
+ * parameters in the FSMC_PCCARDInitStruct.
+ * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
+ * structure that contains the configuration information for the FSMC PCCARD Bank.
+ * @retval None
+ */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+ assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+ assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+
+ /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+ FSMC_MemoryDataWidth_16b |
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+
+ /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+}
+
+/**
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{
+ /* Reset NOR/SRAM Init structure parameters values */
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+ * @brief Fills each FSMC_NANDInitStruct member with its default value.
+ * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+ /* Reset NAND Init structure parameters values */
+ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+ FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+ FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+ FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+ FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
+ * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+ /* Reset PCCARD Init structure parameters values */
+ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+ FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
+ }
+ else
+ {
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified NAND Memory Bank.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the PCCARD Memory Bank.
+ * @param NewState: new state of the PCCARD Memory Bank.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
+ }
+ else
+ {
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the FSMC NAND ECC feature.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @param NewState: new state of the FSMC NAND ECC feature.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
+ }
+ else
+ {
+ FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
+ }
+ }
+}
+
+/**
+ * @brief Returns the error correction code register value.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @retval The Error Correction Code (ECC) value.
+ */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+ uint32_t eccval = 0x00000000;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Get the ECCR2 register value */
+ eccval = FSMC_Bank2->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ eccval = FSMC_Bank3->ECCR3;
+ }
+ /* Return the error correction code value */
+ return(eccval);
+}
+
+/**
+ * @brief Enables or disables the specified FSMC interrupts.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @param NewState: new state of the specified FSMC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 |= FSMC_IT;
+ }
+ /* Enable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 |= FSMC_IT;
+ }
+ }
+ else
+ {
+ /* Disable the selected FSMC_Bank2 interrupts */
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+
+ FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank3 interrupts */
+ else if (FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+ }
+ /* Disable the selected FSMC_Bank4 interrupts */
+ else
+ {
+ FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC flag is set or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
+ * @retval The new state of FSMC_FLAG (SET or RESET).
+ */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ /* Get the flag status */
+ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC抯 pending flags.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
+ * @arg FSMC_FLAG_Level: Level detection Flag.
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
+ * @retval None
+ */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~FSMC_FLAG;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FSMC interrupt has occurred or not.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the FSMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval The new state of FSMC_IT (SET or RESET).
+ */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_GET_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ tmpsr = FSMC_Bank2->SR2;
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ tmpsr = FSMC_Bank3->SR3;
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ tmpsr = FSMC_Bank4->SR4;
+ }
+
+ itstatus = tmpsr & FSMC_IT;
+
+ itenable = tmpsr & (FSMC_IT >> 3);
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FSMC抯 interrupt pending bits.
+ * @param FSMC_Bank: specifies the FSMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+ * @param FSMC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FSMC_IT_Level: Level edge detection interrupt.
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @retval None
+ */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+ assert_param(IS_FSMC_IT(FSMC_IT));
+
+ if(FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
+ }
+ else if(FSMC_Bank == FSMC_Bank3_NAND)
+ {
+ FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+ }
+ /* FSMC_Bank4_PCCARD*/
+ else
+ {
+ FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
new file mode 100644
index 0000000..171037d
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
@@ -0,0 +1,617 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_gpio.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the GPIO firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_gpio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @defgroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber ((uint8_t)0x07)
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+
+
+/* --- MAPR Register ---*/
+/* Alias word address of MII_RMII_SEL bit */
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
+#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
+
+
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
+#define LSB_MASK ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval None
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if (GPIOx == GPIOA)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+ }
+ else if (GPIOx == GPIOE)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+ }
+ else if (GPIOx == GPIOF)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
+ }
+ else
+ {
+ if (GPIOx == GPIOG)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Deinitializes the Alternate Functions (remap, event control
+ * and EXTI configuration) registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void GPIO_AFIODeInit(void)
+{
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+ * contains the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+ uint32_t tmpreg = 0x00, pinmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+
+/*---------------------------- GPIO Mode Configuration -----------------------*/
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+ {
+ /* Check the parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+ /* Output mode */
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+ }
+/*---------------------------- GPIO CRL Configuration ------------------------*/
+ /* Configure the eight low port pins */
+ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+ {
+ tmpreg = GPIOx->CRL;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding low control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << pinpos);
+ }
+ else
+ {
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
+ }
+ }
+ }
+ }
+ GPIOx->CRL = tmpreg;
+ }
+/*---------------------------- GPIO CRH Configuration ------------------------*/
+ /* Configure the eight high port pins */
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+ {
+ tmpreg = GPIOx->CRH;
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+ {
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));
+ /* Get the port pins position */
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+ if (currentpin == pos)
+ {
+ pos = pinpos << 2;
+ /* Clear the corresponding high control register bits */
+ pinmask = ((uint32_t)0x0F) << pos;
+ tmpreg &= ~pinmask;
+ /* Write the mode configuration in the corresponding bits */
+ tmpreg |= (currentmode << pos);
+ /* Reset the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+ {
+ GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ /* Set the corresponding ODR bit */
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+ {
+ GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
+ }
+ }
+ }
+ GPIOx->CRH = tmpreg;
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO input data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO input data port value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * This parameter can be GPIO_Pin_x where x can be (0..15).
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enum values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param PortVal: specifies the value to be written to the port output data register.
+ * @retval None
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit*/
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @brief Selects the GPIO pin used as Event output.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source
+ * for Event output.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ * @param GPIO_PinSource: specifies the pin for the Event output.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmpreg = AFIO->EVCR;
+ /* Clear the PORT[6:4] and PIN[3:0] bits */
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;
+ tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+ tmpreg |= GPIO_PinSource;
+ AFIO->EVCR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Event Output.
+ * @param NewState: new state of the Event output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Changes the mapping of the specified pin.
+ * @param GPIO_Remap: selects the pin to remap.
+ * This parameter can be one of the following values:
+ * @arg GPIO_Remap_SPI1
+ * @arg GPIO_Remap_I2C1
+ * @arg GPIO_Remap_USART1
+ * @arg GPIO_Remap_USART2
+ * @arg GPIO_PartialRemap_USART3
+ * @arg GPIO_FullRemap_USART3
+ * @arg GPIO_PartialRemap_TIM1
+ * @arg GPIO_FullRemap_TIM1
+ * @arg GPIO_PartialRemap1_TIM2
+ * @arg GPIO_PartialRemap2_TIM2
+ * @arg GPIO_FullRemap_TIM2
+ * @arg GPIO_PartialRemap_TIM3
+ * @arg GPIO_FullRemap_TIM3
+ * @arg GPIO_Remap_TIM4
+ * @arg GPIO_Remap1_CAN1
+ * @arg GPIO_Remap2_CAN1
+ * @arg GPIO_Remap_PD01
+ * @arg GPIO_Remap_TIM5CH4_LSI
+ * @arg GPIO_Remap_ADC1_ETRGINJ
+ * @arg GPIO_Remap_ADC1_ETRGREG
+ * @arg GPIO_Remap_ADC2_ETRGINJ
+ * @arg GPIO_Remap_ADC2_ETRGREG
+ * @arg GPIO_Remap_ETH
+ * @arg GPIO_Remap_CAN2
+ * @arg GPIO_Remap_SWJ_NoJTRST
+ * @arg GPIO_Remap_SWJ_JTAGDisable
+ * @arg GPIO_Remap_SWJ_Disable
+ * @arg GPIO_Remap_SPI3
+ * @arg GPIO_Remap_TIM2ITR1_PTP_SOF
+ * @arg GPIO_Remap_PTP_PPS
+ * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected
+ * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
+ * @param NewState: new state of the port pin remapping.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ tmpreg = AFIO->MAPR;
+
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+ tmp = GPIO_Remap & LSB_MASK;
+
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+ {
+ tmpreg &= DBGAFR_SWJCFG_MASK;
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
+ }
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+ {
+ tmp1 = ((uint32_t)0x03) << tmpmask;
+ tmpreg &= ~tmp1;
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+ else
+ {
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;
+ }
+
+ if (NewState != DISABLE)
+ {
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
+ }
+
+ AFIO->MAPR = tmpreg;
+}
+
+/**
+ * @brief Selects the GPIO pin used as EXTI Line.
+ * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ * @param GPIO_PinSource: specifies the EXTI line to be configured.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @retval None
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+ uint32_t tmp = 0x00;
+ /* Check the parameters */
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+ tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+ * @brief Selects the Ethernet media interface.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
+ * This parameter can be one of the following values:
+ * @arg GPIO_ETH_MediaInterface_MII: MII mode
+ * @arg GPIO_ETH_MediaInterface_RMII: RMII mode
+ * @retval None
+ */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
+{
+ assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface));
+
+ /* Configure MII_RMII selection bit */
+ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
new file mode 100644
index 0000000..d06f225
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c
@@ -0,0 +1,1152 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_i2c.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the I2C firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_i2c.h"
+#include "stm32f10x_rcc.h"
+
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/** @defgroup I2C_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Defines
+ * @{
+ */
+
+/* I2C SPE mask */
+#define CR1_PE_Set ((uint16_t)0x0001)
+#define CR1_PE_Reset ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CR1_START_Set ((uint16_t)0x0100)
+#define CR1_START_Reset ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CR1_STOP_Set ((uint16_t)0x0200)
+#define CR1_STOP_Reset ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CR1_ACK_Set ((uint16_t)0x0400)
+#define CR1_ACK_Reset ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CR1_ENGC_Set ((uint16_t)0x0040)
+#define CR1_ENGC_Reset ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CR1_SWRST_Set ((uint16_t)0x8000)
+#define CR1_SWRST_Reset ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CR1_PEC_Set ((uint16_t)0x1000)
+#define CR1_PEC_Reset ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CR1_ENPEC_Set ((uint16_t)0x0020)
+#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CR1_ENARP_Set ((uint16_t)0x0010)
+#define CR1_ENARP_Reset ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)
+#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CR2_DMAEN_Set ((uint16_t)0x0800)
+#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CR2_LAST_Set ((uint16_t)0x1000)
+#define CR2_LAST_Reset ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CR2_FREQ_Reset ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OAR1_ADD0_Set ((uint16_t)0x0001)
+#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OAR2_ENDUAL_Set ((uint16_t)0x0001)
+#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OAR2_ADD2_Reset ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CCR_FS_Set ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CCR_CCR_Set ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask ((uint32_t)0x07000000)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Enable I2C1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+ /* Release I2C1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+ }
+ else
+ {
+ /* Enable I2C2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+ /* Release I2C2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the I2Cx peripheral according to the specified
+ * parameters in the I2C_InitStruct.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+ * contains the configuration information for the specified I2C peripheral.
+ * @retval None
+ */
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+ uint16_t tmpreg = 0, freqrange = 0;
+ uint16_t result = 0x04;
+ uint32_t pclk1 = 8000000;
+ RCC_ClocksTypeDef rcc_clocks;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+ /* Get the I2Cx CR2 value */
+ tmpreg = I2Cx->CR2;
+ /* Clear frequency FREQ[5:0] bits */
+ tmpreg &= CR2_FREQ_Reset;
+ /* Get pclk1 frequency value */
+ RCC_GetClocksFreq(&rcc_clocks);
+ pclk1 = rcc_clocks.PCLK1_Frequency;
+ /* Set frequency bits depending on pclk1 value */
+ freqrange = (uint16_t)(pclk1 / 1000000);
+ tmpreg |= freqrange;
+ /* Write to I2Cx CR2 */
+ I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+ /* Disable the selected I2C peripheral to configure TRISE */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ /* Reset tmpreg value */
+ /* Clear F/S, DUTY and CCR[11:0] bits */
+ tmpreg = 0;
+
+ /* Configure speed in standard mode */
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+ {
+ /* Standard mode speed calculate */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+ /* Test if CCR value is under 0x4*/
+ if (result < 0x04)
+ {
+ /* Set minimum allowed value */
+ result = 0x04;
+ }
+ /* Set speed value for standard mode */
+ tmpreg |= result;
+ /* Set Maximum Rise Time for standard mode */
+ I2Cx->TRISE = freqrange + 1;
+ }
+ /* Configure speed in fast mode */
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+ {
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+ }
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+ {
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+ /* Set DUTY bit */
+ result |= I2C_DutyCycle_16_9;
+ }
+
+ /* Test if CCR value is under 0x1*/
+ if ((result & CCR_CCR_Set) == 0)
+ {
+ /* Set minimum allowed value */
+ result |= (uint16_t)0x0001;
+ }
+ /* Set speed value and set F/S bit for fast mode */
+ tmpreg |= (uint16_t)(result | CCR_FS_Set);
+ /* Set Maximum Rise Time for fast mode */
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+ }
+
+ /* Write to I2Cx CCR */
+ I2Cx->CCR = tmpreg;
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+ /* Get the I2Cx CR1 value */
+ tmpreg = I2Cx->CR1;
+ /* Clear ACK, SMBTYPE and SMBUS bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure I2Cx: mode and acknowledgement */
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+ /* Set ACK bit according to I2C_Ack value */
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+ /* Set I2Cx Own Address1 and acknowledged address */
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+ /* initialize the I2C_ClockSpeed member */
+ I2C_InitStruct->I2C_ClockSpeed = 5000;
+ /* Initialize the I2C_Mode member */
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+ /* Initialize the I2C_DutyCycle member */
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+ /* Initialize the I2C_OwnAddress1 member */
+ I2C_InitStruct->I2C_OwnAddress1 = 0;
+ /* Initialize the I2C_Ack member */
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+ /* Initialize the I2C_AcknowledgedAddress member */
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= CR1_PE_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CR1 &= CR1_PE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C DMA requests.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CR2 |= CR2_DMAEN_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CR2 &= CR2_DMAEN_Reset;
+ }
+}
+
+/**
+ * @brief Specifies that the next DMA transfer is the last one.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C DMA last transfer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Next DMA transfer is the last transfer */
+ I2Cx->CR2 |= CR2_LAST_Set;
+ }
+ else
+ {
+ /* Next DMA transfer is not the last transfer */
+ I2Cx->CR2 &= CR2_LAST_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CR1 |= CR1_START_Set;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CR1 &= CR1_START_Reset;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CR1 |= CR1_STOP_Set;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CR1 &= CR1_STOP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C acknowledge feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C Acknowledgement.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None.
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the acknowledgement */
+ I2Cx->CR1 |= CR1_ACK_Set;
+ }
+ else
+ {
+ /* Disable the acknowledgement */
+ I2Cx->CR1 &= CR1_ACK_Reset;
+ }
+}
+
+/**
+ * @brief Configures the specified I2C own address2.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the 7bit I2C own address2.
+ * @retval None.
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+ uint16_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->OAR2;
+
+ /* Reset I2Cx Own address2 bit [7:1] */
+ tmpreg &= OAR2_ADD2_Reset;
+
+ /* Set I2Cx Own address2 */
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+ /* Store the new register value */
+ I2Cx->OAR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified I2C dual addressing mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C dual addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable dual addressing mode */
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;
+ }
+ else
+ {
+ /* Disable dual addressing mode */
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C general call feature.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C General call.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable generall call */
+ I2Cx->CR1 |= CR1_ENGC_Set;
+ }
+ else
+ {
+ /* Disable generall call */
+ I2Cx->CR1 &= CR1_ENGC_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_BUF: Buffer interrupt mask
+ * @arg I2C_IT_EVT: Event interrupt mask
+ * @arg I2C_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CR2 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;
+ }
+}
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data: Byte to be transmitted..
+ * @retval None
+ */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Write in the DR register the data to be sent */
+ I2Cx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the data in the DR register */
+ return (uint8_t)I2Cx->DR;
+}
+
+/**
+ * @brief Transmits the address byte to select the slave device.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address which will be transmitted
+ * @param I2C_Direction: specifies whether the I2C device will be a
+ * Transmitter or a Receiver. This parameter can be one of the following values
+ * @arg I2C_Direction_Transmitter: Transmitter mode
+ * @arg I2C_Direction_Receiver: Receiver mode
+ * @retval None.
+ */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction != I2C_Direction_Transmitter)
+ {
+ /* Set the address bit0 for read */
+ Address |= OAR1_ADD0_Set;
+ }
+ else
+ {
+ /* Reset the address bit0 for write */
+ Address &= OAR1_ADD0_Reset;
+ }
+ /* Send the address */
+ I2Cx->DR = Address;
+}
+
+/**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2C_Register: specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_Register_CR1: CR1 register.
+ * @arg I2C_Register_CR2: CR2 register.
+ * @arg I2C_Register_OAR1: OAR1 register.
+ * @arg I2C_Register_OAR2: OAR2 register.
+ * @arg I2C_Register_DR: DR register.
+ * @arg I2C_Register_SR1: SR1 register.
+ * @arg I2C_Register_SR2: SR2 register.
+ * @arg I2C_Register_CCR: CCR register.
+ * @arg I2C_Register_TRISE: TRISE register.
+ * @retval The value of the read register.
+ */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_REGISTER(I2C_Register));
+
+ tmp = (uint32_t) I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint16_t *) tmp);
+}
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C software reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Peripheral under reset */
+ I2Cx->CR1 |= CR1_SWRST_Set;
+ }
+ else
+ {
+ /* Peripheral not under reset */
+ I2Cx->CR1 &= CR1_SWRST_Reset;
+ }
+}
+
+/**
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level.
+ * This parameter can be one of the following values:
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+ * @retval None
+ */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+ {
+ /* Drive the SMBusAlert pin Low */
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;
+ }
+ else
+ {
+ /* Drive the SMBusAlert pin High */
+ I2Cx->CR1 &= I2C_SMBusAlert_High;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C PEC transfer.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C PEC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC transmission */
+ I2Cx->CR1 |= CR1_PEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC transmission */
+ I2Cx->CR1 &= CR1_PEC_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C PEC position.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_PECPosition: specifies the PEC position.
+ * This parameter can be one of the following values:
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC
+ * @retval None
+ */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+ if (I2C_PECPosition == I2C_PECPosition_Next)
+ {
+ /* Next byte in shift register is PEC */
+ I2Cx->CR1 |= I2C_PECPosition_Next;
+ }
+ else
+ {
+ /* Current byte in shift register is PEC */
+ I2Cx->CR1 &= I2C_PECPosition_Current;
+ }
+}
+
+/**
+ * @brief Enables or disables the PEC value calculation of the transfered bytes.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C PEC calculation */
+ I2Cx->CR1 |= CR1_ENPEC_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C PEC calculation */
+ I2Cx->CR1 &= CR1_ENPEC_Reset;
+ }
+}
+
+/**
+ * @brief Returns the PEC value for the specified I2C.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The PEC value.
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Return the selected I2C PEC value */
+ return ((I2Cx->SR2) >> 8);
+}
+
+/**
+ * @brief Enables or disables the specified I2C ARP.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx ARP.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C ARP */
+ I2Cx->CR1 |= CR1_ENARP_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C ARP */
+ I2Cx->CR1 &= CR1_ENARP_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified I2C Clock stretching.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState == DISABLE)
+ {
+ /* Enable the selected I2C Clock stretching */
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;
+ }
+ else
+ {
+ /* Disable the selected I2C Clock stretching */
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;
+ }
+}
+
+/**
+ * @brief Selects the specified I2C fast mode duty cycle.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.
+ * This parameter can be one of the following values:
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+ * @retval None
+ */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+ {
+ /* I2C fast mode Tlow/Thigh=2 */
+ I2Cx->CCR &= I2C_DutyCycle_2;
+ }
+ else
+ {
+ /* I2C fast mode Tlow/Thigh=16/9 */
+ I2Cx->CCR |= I2C_DutyCycle_16_9;
+ }
+}
+
+/**
+ * @brief Returns the last I2Cx Event.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The last event
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+ /* Return status */
+ return lastevent;
+}
+
+/**
+ * @brief Checks whether the last I2Cx Event is equal to the one passed
+ * as parameter.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_EVENT: specifies the event to be checked.
+ * This parameter can be one of the following values:
+ * @arg I2C_EVENT_SLAVE_ADDRESS_MATCHED : EV1
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3-2
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5
+ * @arg I2C_EVENT_MASTER_MODE_SELECTED : EV6
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4
+ * @retval An ErrorStatus enumuration value:
+ * - SUCCESS: Last event is equal to the I2C_EVENT
+ * - ERROR: Last event is different from the I2C_EVENT
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+ uint32_t lastevent = 0;
+ uint32_t flag1 = 0, flag2 = 0;
+ ErrorStatus status = ERROR;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_EVENT(I2C_EVENT));
+ /* Read the I2Cx status register */
+ flag1 = I2Cx->SR1;
+ flag2 = I2Cx->SR2;
+ flag2 = flag2 << 16;
+ /* Get the last event value from I2C status register */
+ lastevent = (flag1 | flag2) & FLAG_Mask;
+ /* Check whether the last event is equal to I2C_EVENT */
+ if (lastevent == I2C_EVENT )
+ {
+ /* SUCCESS: last event is equal to I2C_EVENT */
+ status = SUCCESS;
+ }
+ else
+ {
+ /* ERROR: last event is different from I2C_EVENT */
+ status = ERROR;
+ }
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) 揂DSL
+ * Address matched flag (Slave mode)擡NDAD
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the I2Cx peripheral base address */
+ i2cxbase = (uint32_t)I2Cx;
+
+ /* Read flag register index */
+ i2creg = I2C_FLAG >> 28;
+
+ /* Get bit[23:0] of the flag */
+ I2C_FLAG &= FLAG_Mask;
+
+ if(i2creg != 0)
+ {
+ /* Get the I2Cx SR1 register address */
+ i2cxbase += 0x14;
+ }
+ else
+ {
+ /* Flag in I2Cx SR2 Register */
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+ /* Get the I2Cx SR2 register address */
+ i2cxbase += 0x18;
+ }
+
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
+ * second byte of the address in DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+ * register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+ /* Get the I2C flag position */
+ flagpos = I2C_FLAG & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_IT_PECERR: PEC error in reception flag
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure flag
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_IT_BERR: Bus error flag
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+ * @arg I2C_IT_BTF: Byte transfer finished flag
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) 揂DSL
+ * Address matched flag (Slave mode)擡NDAD
+ * @arg I2C_IT_SB: Start bit flag (Master mode)
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_IT(I2C_IT));
+ /* Check if the interrupt source is enabled or not */
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;
+ /* Get bit[23:0] of the flag */
+ I2C_IT &= FLAG_Mask;
+ /* Check the status of the specified I2C flag */
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx抯 interrupt pending bits.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+ * @arg I2C_IT_AF: Acknowledge failure interrupt
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+ * @arg I2C_IT_BERR: Bus error interrupt
+ *
+ * @note
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
+ * byte of the address in I2C_DR register.
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
+ * read/write to I2C_DR register (I2C_SendData()).
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
+ * I2C_SR2 register ((void)(I2Cx->SR2)).
+ * - SB (Start Bit) is cleared by software sequence: a read operation to
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
+ * I2C_DR register (I2C_SendData()).
+ * @retval None
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t flagpos = 0;
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+ /* Get the I2C flag position */
+ flagpos = I2C_IT & FLAG_Mask;
+ /* Clear the selected I2C flag */
+ I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
new file mode 100644
index 0000000..fd4bef2
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c
@@ -0,0 +1,189 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_iwdg.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the IWDG firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_iwdg.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/** @defgroup IWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Defines
+ * @{
+ */
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload ((uint16_t)0xAAAA)
+#define KR_KEY_Enable ((uint16_t)0xCCCC)
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+ * @retval None
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+ IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+ * @retval None
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+ IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload: specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ * @retval None
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RLR = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_KEY_Reload;
+}
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_KEY_Enable;
+}
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going
+ * @retval The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
new file mode 100644
index 0000000..946a834
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c
@@ -0,0 +1,311 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_pwr.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the PWR firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_pwr.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup PWR
+ * @brief PWR driver modules
+ * @{
+ */
+
+/** @defgroup PWR_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Defines
+ * @{
+ */
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET (PWR_OFFSET + 0x00)
+#define DBP_BitNumber 0x08
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber 0x04
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber 0x08
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_PDDS_Set ((uint32_t)0x00000002)
+#define CR_DS_Mask ((uint32_t)0xFFFFFFFC)
+#define CR_CWUF_Set ((uint32_t)0x00000004)
+#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F)
+
+/* --------- Cortex System Control register bit mask ---------------- */
+
+/* Cortex System Control register address */
+#define SCB_SysCtrl ((uint32_t)0xE000ED10)
+
+/* SLEEPDEEP bit mask */
+#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void PWR_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+ * @brief Enables or disables access to the RTC and backup registers.
+ * @param NewState: new state of the access to the RTC and backup registers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Power Voltage Detector(PVD).
+ * @param NewState: new state of the PVD.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+ * @param PWR_PVDLevel: specifies the PVD detection level
+ * This parameter can be one of the following values:
+ * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
+ * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
+ * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+ * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
+ * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
+ * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+ * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
+ * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
+ * @retval None
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+ tmpreg = PWR->CR;
+ /* Clear PLS[7:5] bits */
+ tmpreg &= CR_PLS_Mask;
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+ tmpreg |= PWR_PVDLevel;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param NewState: new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enters STOP mode.
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.
+ * This parameter can be one of the following values:
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * This parameter can be one of the following values:
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+ * @retval None
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+ /* Select the regulator state in STOP mode ---------------------------------*/
+ tmpreg = PWR->CR;
+ /* Clear PDDS and LPDS bits */
+ tmpreg &= CR_DS_Mask;
+ /* Set LPDS bit according to PWR_Regulator value */
+ tmpreg |= PWR_Regulator;
+ /* Store the new value */
+ PWR->CR = tmpreg;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+
+ /* Select STOP mode entry --------------------------------------------------*/
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+ {
+ /* Request Wait For Interrupt */
+ __WFI();
+ }
+ else
+ {
+ /* Request Wait For Event */
+ __WFE();
+ }
+}
+
+/**
+ * @brief Enters STANDBY mode.
+ * @param None
+ * @retval None
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+ /* Clear Wake-up flag */
+ PWR->CR |= CR_CWUF_Set;
+ /* Select STANDBY mode */
+ PWR->CR |= CR_PDDS_Set;
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set;
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM )
+ __force_stores();
+#endif
+ /* Request Wait For Interrupt */
+ __WFI();
+}
+
+/**
+ * @brief Checks whether the specified PWR flag is set or not.
+ * @param PWR_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @arg PWR_FLAG_PVDO: PVD Output
+ * @retval The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the PWR's pending flags.
+ * @param PWR_FLAG: specifies the flag to clear.
+ * This parameter can be one of the following values:
+ * @arg PWR_FLAG_WU: Wake Up flag
+ * @arg PWR_FLAG_SB: StandBy flag
+ * @retval None
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+ PWR->CR |= PWR_FLAG << 2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
new file mode 100644
index 0000000..f3a2c74
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
@@ -0,0 +1,1447 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rcc.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the RCC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RCC
+ * @brief RCC driver modules
+ * @{
+ */
+
+/** @defgroup RCC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Defines
+ * @{
+ */
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET (RCC_OFFSET + 0x00)
+#define HSION_BitNumber 0x00
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber 0x18
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+ /* Alias word address of PLL2ON bit */
+ #define PLL2ON_BitNumber 0x1A
+ #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
+
+ /* Alias word address of PLL3ON bit */
+ #define PLL3ON_BitNumber 0x1C
+ #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber 0x13
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)
+
+#ifndef STM32F10X_CL
+ #define USBPRE_BitNumber 0x16
+ #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+#else
+ #define OTGFSPRE_BitNumber 0x16
+ #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber 0x0F
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber 0x10
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET (RCC_OFFSET + 0x24)
+#define LSION_BitNumber 0x00
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+#ifdef STM32F10X_CL
+/* --- CFGR2 Register ---*/
+
+ /* Alias word address of I2S2SRC bit */
+ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
+ #define I2S2SRC_BitNumber 0x11
+ #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
+
+ /* Alias word address of I2S3SRC bit */
+ #define I2S3SRC_BitNumber 0x12
+ #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
+#endif /* STM32F10X_CL */
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
+#define CR_HSEBYP_Set ((uint32_t)0x00040000)
+#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
+#define CR_HSEON_Set ((uint32_t)0x00010000)
+#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#ifndef STM32F10X_CL
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
+#else
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
+#endif /* STM32F10X_CL */
+
+#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
+#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
+#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
+#define CFGR_SWS_Mask ((uint32_t)0x0000000C)
+#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
+#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RMVF_Set ((uint32_t)0x01000000)
+
+#ifdef STM32F10X_CL
+/* CFGR2 register bit mask */
+ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
+ #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
+ #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
+ #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
+ #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
+#endif /* STM32F10X_CL */
+
+/* RCC Flag Mask */
+#define FLAG_Mask ((uint8_t)0x1F)
+
+#ifndef HSI_Value
+/* Typical Value of the HSI in Hz */
+ #define HSI_Value ((uint32_t)8000000)
+#endif /* HSI_Value */
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
+
+/* CFGR register byte 4 (Bits[31:24]) base address */
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
+
+/* BDCR register base address */
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
+
+#ifndef HSEStartUp_TimeOut
+/* Time out for HSE start up */
+ #define HSEStartUp_TimeOut ((uint16_t)0x0500)
+#endif /* HSEStartUp_TimeOut */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Variables
+ * @{
+ */
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Resets the RCC clock configuration to the default reset state.
+ * @param None
+ * @retval None
+ */
+void RCC_DeInit(void)
+{
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+ RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+ RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifndef STM32F10X_CL
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x009F0000;
+#else
+ /* Reset PLL2ON and PLL3ON bits */
+ RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+ /* Disable all interrupts and clear pending bits */
+ RCC->CIR = 0x00FF0000;
+
+ /* Reset CFGR2 register */
+ RCC->CFGR2 = 0x00000000;
+#endif /* STM32F10X_CL */
+}
+
+/**
+ * @brief Configures the External High Speed oscillator (HSE).
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
+ * @param RCC_HSE: specifies the new state of the HSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_HSE_OFF: HSE oscillator OFF
+ * @arg RCC_HSE_ON: HSE oscillator ON
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_HSE(RCC_HSE));
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+ /* Reset HSEON bit */
+ RCC->CR &= CR_HSEON_Reset;
+ /* Reset HSEBYP bit */
+ RCC->CR &= CR_HSEBYP_Reset;
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+ switch(RCC_HSE)
+ {
+ case RCC_HSE_ON:
+ /* Set HSEON bit */
+ RCC->CR |= CR_HSEON_Set;
+ break;
+
+ case RCC_HSE_Bypass:
+ /* Set HSEBYP and HSEON bits */
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Waits for HSE start-up.
+ * @param None
+ * @retval An ErrorStatus enumuration value:
+ * - SUCCESS: HSE oscillator is stable and ready to use
+ * - ERROR: HSE oscillator not yet ready
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+ __IO uint32_t StartUpCounter = 0;
+ ErrorStatus status = ERROR;
+ FlagStatus HSEStatus = RESET;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+ StartUpCounter++;
+ } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET));
+
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+ {
+ status = SUCCESS;
+ }
+ else
+ {
+ status = ERROR;
+ }
+ return (status);
+}
+
+/**
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ * @param HSICalibrationValue: specifies the calibration trimming value.
+ * This parameter must be a number between 0 and 0x1F.
+ * @retval None
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+ tmpreg = RCC->CR;
+ /* Clear HSITRIM[4:0] bits */
+ tmpreg &= CR_HSITRIM_Mask;
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;
+ /* Store the new value */
+ RCC->CR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
+ * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the PLL clock source and multiplication factor.
+ * @note This function must be used only when the PLL is disabled.
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
+ * @param RCC_PLLMul: specifies the PLL multiplication factor.
+ * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
+ * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+
+ tmpreg = RCC->CFGR;
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+ tmpreg &= CFGR_PLL_Mask;
+ /* Set the PLL configuration bits */
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the PLL.
+ * @note The PLL can not be disabled if it is used as system clock.
+ * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the PREDIV1 division factor.
+ * @note
+ * - This function must be used only when the PLL is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
+ * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
+ tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
+ /* Set the PREDIV1 clock source and division factor */
+ tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Configures the PREDIV2 division factor.
+ * @note
+ * - This function must be used only when both PLL2 and PLL3 are disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
+ * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
+ * @retval None
+ */
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PREDIV2[3:0] bits */
+ tmpreg &= ~CFGR2_PREDIV2;
+ /* Set the PREDIV2 division factor */
+ tmpreg |= RCC_PREDIV2_Div;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the PLL2 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL2 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
+ * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL2Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL2MUL;
+ /* Set the PLL2 configuration bits */
+ tmpreg |= RCC_PLL2Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL2.
+ * @note
+ * - The PLL2 can not be disabled if it is used indirectly as system clock
+ * (i.e. it is used as PLL clock entry that is used as System clock).
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL2Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
+}
+
+
+/**
+ * @brief Configures the PLL3 multiplication factor.
+ * @note
+ * - This function must be used only when the PLL3 is disabled.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
+ * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
+ * @retval None
+ */
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
+
+ tmpreg = RCC->CFGR2;
+ /* Clear PLL3Mul[3:0] bits */
+ tmpreg &= ~CFGR2_PLL3MUL;
+ /* Set the PLL3 configuration bits */
+ tmpreg |= RCC_PLL3Mul;
+ /* Store the new value */
+ RCC->CFGR2 = tmpreg;
+}
+
+
+/**
+ * @brief Enables or disables the PLL3.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_PLL3Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the system clock (SYSCLK).
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+ * @retval None
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+ tmpreg = RCC->CFGR;
+ /* Clear SW[1:0] bits */
+ tmpreg &= CFGR_SW_Mask;
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+ tmpreg |= RCC_SYSCLKSource;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Returns the clock source used as system clock.
+ * @param None
+ * @retval The clock source used as system clock. The returned value can
+ * be one of the following:
+ * - 0x00: HSI used as system clock
+ * - 0x04: HSE used as system clock
+ * - 0x08: PLL used as system clock
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+ return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/**
+ * @brief Configures the AHB clock (HCLK).
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+ * the system clock (SYSCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+ * @retval None
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear HPRE[3:0] bits */
+ tmpreg &= CFGR_HPRE_Reset_Mask;
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+ tmpreg |= RCC_SYSCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the Low Speed APB clock (PCLK1).
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE1[2:0] bits */
+ tmpreg &= CFGR_PPRE1_Reset_Mask;
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the High Speed APB clock (PCLK2).
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+ * the AHB clock (HCLK).
+ * This parameter can be one of the following values:
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+ * @retval None
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_PCLK(RCC_HCLK));
+ tmpreg = RCC->CFGR;
+ /* Clear PPRE2[2:0] bits */
+ tmpreg &= CFGR_PPRE2_Reset_Mask;
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+ tmpreg |= RCC_HCLK << 3;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the specified RCC interrupts.
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @param NewState: new state of the specified RCC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_IT(RCC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+ }
+ else
+ {
+ /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+ }
+}
+
+#ifndef STM32F10X_CL
+/**
+ * @brief Configures the USB clock (USBCLK).
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
+ * derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ * clock source
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+ * @retval None
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
+}
+#else
+/**
+ * @brief Configures the USB OTG FS clock (OTGFSCLK).
+ * This function applies only to STM32 Connectivity line devices.
+ * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
+ * This clock is derived from the PLL output.
+ * This parameter can be one of the following values:
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
+ * @retval None
+ */
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
+
+ *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the ADC clock (ADCCLK).
+ * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
+ * the APB2 clock (PCLK2).
+ * This parameter can be one of the following values:
+ * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
+ * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
+ * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
+ * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
+ * @retval None
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
+ tmpreg = RCC->CFGR;
+ /* Clear ADCPRE[1:0] bits */
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
+ tmpreg |= RCC_PCLK2;
+ /* Store the new value */
+ RCC->CFGR = tmpreg;
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Configures the I2S2 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S2 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
+ * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
+ * @retval None
+ */
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
+}
+
+/**
+ * @brief Configures the I2S3 clock source(I2S2CLK).
+ * @note
+ * - This function must be called before enabling I2S3 APB clock.
+ * - This function applies only to STM32 Connectivity line devices.
+ * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
+ * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
+ * @retval None
+ */
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
+
+ *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Configures the External Low Speed oscillator (LSE).
+ * @param RCC_LSE: specifies the new state of the LSE.
+ * This parameter can be one of the following values:
+ * @arg RCC_LSE_OFF: LSE oscillator OFF
+ * @arg RCC_LSE_ON: LSE oscillator ON
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+ * @retval None
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LSE(RCC_LSE));
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+ /* Reset LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Reset LSEBYP bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+ switch(RCC_LSE)
+ {
+ case RCC_LSE_ON:
+ /* Set LSEON bit */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
+ break;
+
+ case RCC_LSE_Bypass:
+ /* Set LSEBYP and LSEON bits */
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).
+ * @note LSI can not be disabled if the IWDG is running.
+ * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Configures the RTC clock (RTCCLK).
+ * @note Once the RTC clock is selected it can抰 be changed unless the Backup domain is reset.
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+ * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
+ * @retval None
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+ /* Select the RTC clock source */
+ RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+ * @brief Enables or disables the RTC clock.
+ * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Returns the frequencies of different on chip clocks.
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+ * the clocks frequencies.
+ * @retval None
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+#ifdef STM32F10X_CL
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+#endif /* STM32F10X_CL */
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & CFGR_SWS_Mask;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+ break;
+ case 0x04: /* HSE used as system clock */
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value;
+ break;
+ case 0x08: /* PLL used as system clock */
+
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+
+#ifndef STM32F10X_CL
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
+ }
+ else
+ {/* HSE selected as PLL clock entry */
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
+ {/* HSE oscillator clock divided by 2 */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
+ }
+ else
+ {
+ RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
+ }
+ }
+#else
+ pllmull = pllmull >> 18;
+
+ if (pllmull != 0x0D)
+ {
+ pllmull += 2;
+ }
+ else
+ { /* PLL multiplication factor = PLL input clock * 6.5 */
+ pllmull = 13 / 2;
+ }
+
+ if (pllsource == 0x00)
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
+ }
+ else
+ {/* PREDIV1 selected as PLL clock entry */
+
+ /* Get PREDIV1 clock source and division factor */
+ prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
+
+ if (prediv1source == 0)
+ { /* HSE oscillator clock selected as PREDIV1 clock entry */
+ RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull;
+ }
+ else
+ {/* PLL2 clock selected as PREDIV1 clock entry */
+
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */
+ prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
+ pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
+ }
+ }
+#endif /* STM32F10X_CL */
+ break;
+
+ default:
+ RCC_Clocks->SYSCLK_Frequency = HSI_Value;
+ break;
+ }
+
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+ /* Get HCLK prescaler */
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+ tmp = tmp >> 4;
+ presc = APBAHBPrescTable[tmp];
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+ /* Get PCLK1 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+ tmp = tmp >> 8;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get PCLK2 prescaler */
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+ tmp = tmp >> 11;
+ presc = APBAHBPrescTable[tmp];
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+ /* Get ADCCLK prescaler */
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+ tmp = tmp >> 14;
+ presc = ADCPrescTable[tmp];
+ /* ADCCLK clock frequency */
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/**
+ * @brief Enables or disables the AHB peripheral clock.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @arg RCC_AHBPeriph_ETH_MAC_Tx
+ * @arg RCC_AHBPeriph_ETH_MAC_Rx
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_AHBPeriph_DMA1
+ * @arg RCC_AHBPeriph_DMA2
+ * @arg RCC_AHBPeriph_SRAM
+ * @arg RCC_AHBPeriph_FLITF
+ * @arg RCC_AHBPeriph_CRC
+ * @arg RCC_AHBPeriph_FSMC
+ * @arg RCC_AHBPeriph_SDIO
+ *
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBENR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBENR &= ~RCC_AHBPeriph;
+ }
+}
+
+/**
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2ENR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2ENR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1ENR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1ENR &= ~RCC_APB1Periph;
+ }
+}
+
+#ifdef STM32F10X_CL
+/**
+ * @brief Forces or releases AHB peripheral reset.
+ * @note This function applies only to STM32 Connectivity line devices.
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHBPeriph_OTG_FS
+ * @arg RCC_AHBPeriph_ETH_MAC
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RCC->AHBRSTR |= RCC_AHBPeriph;
+ }
+ else
+ {
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;
+ }
+}
+#endif /* STM32F10X_CL */
+
+/**
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3
+ * @param NewState: new state of the specified peripheral reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB2RSTR |= RCC_APB2Periph;
+ }
+ else
+ {
+ RCC->APB2RSTR &= ~RCC_APB2Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->APB1RSTR |= RCC_APB1Periph;
+ }
+ else
+ {
+ RCC->APB1RSTR &= ~RCC_APB1Periph;
+ }
+}
+
+/**
+ * @brief Forces or releases the Backup domain reset.
+ * @param NewState: new state of the Backup domain reset.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the Clock Security System.
+ * @param NewState: new state of the Clock Security System..
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Selects the clock source to output on MCO pin.
+ * @param RCC_MCO: specifies the clock source to output.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
+ * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
+ * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
+ * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_MCO_NoClock: No clock selected
+ * @arg RCC_MCO_SYSCLK: System clock selected
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+ *
+ * @retval None
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_MCO(RCC_MCO));
+
+ /* Perform Byte access to MCO bits to select the MCO source */
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/**
+ * @brief Checks whether the specified RCC flag is set or not.
+ * @param RCC_FLAG: specifies the flag to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+ * @arg RCC_FLAG_PINRST: Pin reset
+ * @arg RCC_FLAG_PORRST: POR/PDR reset
+ * @arg RCC_FLAG_SFTRST: Software reset
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+ * @arg RCC_FLAG_LPWRRST: Low Power reset
+ *
+ * @retval The new state of RCC_FLAG (SET or RESET).
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+ uint32_t tmp = 0;
+ uint32_t statusreg = 0;
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+ /* Get the RCC register index */
+ tmp = RCC_FLAG >> 5;
+ if (tmp == 1) /* The flag to check is in CR register */
+ {
+ statusreg = RCC->CR;
+ }
+ else if (tmp == 2) /* The flag to check is in BDCR register */
+ {
+ statusreg = RCC->BDCR;
+ }
+ else /* The flag to check is in CSR register */
+ {
+ statusreg = RCC->CSR;
+ }
+
+ /* Get the flag position */
+ tmp = RCC_FLAG & FLAG_Mask;
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC reset flags.
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+ * @param None
+ * @retval None
+ */
+void RCC_ClearFlag(void)
+{
+ /* Set RMVF bit to clear the reset flags */
+ RCC->CSR |= CSR_RMVF_Set;
+}
+
+/**
+ * @brief Checks whether the specified RCC interrupt has occurred or not.
+ * @param RCC_IT: specifies the RCC interrupt source to check.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be one of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * @retval The new state of RCC_IT (SET or RESET).
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RCC_GET_IT(RCC_IT));
+
+ /* Check the status of the specified RCC interrupt */
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ /* Return the RCC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RCC抯 interrupt pending bits.
+ * @param RCC_IT: specifies the interrupt pending bit to clear.
+ *
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination
+ * of the following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ *
+ * For @b other_STM32_devices, this parameter can be any combination of the
+ * following values:
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt
+ * @arg RCC_IT_LSERDY: LSE ready interrupt
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt
+ * @arg RCC_IT_HSERDY: HSE ready interrupt
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt
+ *
+ * @arg RCC_IT_CSS: Clock Security System interrupt
+ * @retval None
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+ pending bits */
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
new file mode 100644
index 0000000..14dcc65
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c
@@ -0,0 +1,341 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_rtc.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the RTC firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_rtc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup RTC
+ * @brief RTC driver modules
+ * @{
+ */
+
+/** @defgroup RTC_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Defines
+ * @{
+ */
+
+#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */
+#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */
+#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
+#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified RTC interrupts.
+ * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @param NewState: new state of the specified RTC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ RTC->CRH |= RTC_IT;
+ }
+ else
+ {
+ RTC->CRH &= (uint16_t)~RTC_IT;
+ }
+}
+
+/**
+ * @brief Enters the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_EnterConfigMode(void)
+{
+ /* Set the CNF flag to enter in the Configuration Mode */
+ RTC->CRL |= CRL_CNF_Set;
+}
+
+/**
+ * @brief Exits from the RTC configuration mode.
+ * @param None
+ * @retval None
+ */
+void RTC_ExitConfigMode(void)
+{
+ /* Reset the CNF flag to exit from the Configuration Mode */
+ RTC->CRL &= CRL_CNF_Reset;
+}
+
+/**
+ * @brief Gets the RTC counter value.
+ * @param None
+ * @retval RTC counter value.
+ */
+uint32_t RTC_GetCounter(void)
+{
+ uint16_t tmp = 0;
+ tmp = RTC->CNTL;
+ return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+ * @brief Sets the RTC counter value.
+ * @param CounterValue: RTC counter new value.
+ * @retval None
+ */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+ RTC_EnterConfigMode();
+ /* Set RTC COUNTER MSB word */
+ RTC->CNTH = CounterValue >> 16;
+ /* Set RTC COUNTER LSB word */
+ RTC->CNTL = (CounterValue & RTC_LSB_Mask);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC prescaler value.
+ * @param PrescalerValue: RTC prescaler new value.
+ * @retval None
+ */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_PRESCALER(PrescalerValue));
+
+ RTC_EnterConfigMode();
+ /* Set RTC PRESCALER MSB word */
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16;
+ /* Set RTC PRESCALER LSB word */
+ RTC->PRLL = (PrescalerValue & RTC_LSB_Mask);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Sets the RTC alarm value.
+ * @param AlarmValue: RTC alarm new value.
+ * @retval None
+ */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+ RTC_EnterConfigMode();
+ /* Set the ALARM MSB word */
+ RTC->ALRH = AlarmValue >> 16;
+ /* Set the ALARM LSB word */
+ RTC->ALRL = (AlarmValue & RTC_LSB_Mask);
+ RTC_ExitConfigMode();
+}
+
+/**
+ * @brief Gets the RTC divider value.
+ * @param None
+ * @retval RTC Divider value.
+ */
+uint32_t RTC_GetDivider(void)
+{
+ uint32_t tmp = 0x00;
+ tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+ tmp |= RTC->DIVL;
+ return tmp;
+}
+
+/**
+ * @brief Waits until last write operation on RTC registers has finished.
+ * @note This function must be called before any write to RTC registers.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForLastTask(void)
+{
+ /* Loop until RTOFF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+ * are synchronized with RTC APB clock.
+ * @note This function must be called before any read operation after an APB reset
+ * or an APB clock stop.
+ * @param None
+ * @retval None
+ */
+void RTC_WaitForSynchro(void)
+{
+ /* Clear RSF flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
+ /* Loop until RSF flag is set */
+ while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+ {
+ }
+}
+
+/**
+ * @brief Checks whether the specified RTC flag is set or not.
+ * @param RTC_FLAG: specifies the flag to check.
+ * This parameter can be one the following values:
+ * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval The new state of RTC_FLAG (SET or RESET).
+ */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+ if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC抯 pending flags.
+ * @param RTC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
+ * an APB reset or an APB Clock stop.
+ * @arg RTC_FLAG_OW: Overflow flag
+ * @arg RTC_FLAG_ALR: Alarm flag
+ * @arg RTC_FLAG_SEC: Second flag
+ * @retval None
+ */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+ /* Clear the coressponding RTC flag */
+ RTC->CRL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified RTC interrupt has occured or not.
+ * @param RTC_IT: specifies the RTC interrupts sources to check.
+ * This parameter can be one of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval The new state of the RTC_IT (SET or RESET).
+ */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_RTC_GET_IT(RTC_IT));
+
+ bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
+ if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the RTC抯 interrupt pending bits.
+ * @param RTC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_OW: Overflow interrupt
+ * @arg RTC_IT_ALR: Alarm interrupt
+ * @arg RTC_IT_SEC: Second interrupt
+ * @retval None
+ */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_RTC_IT(RTC_IT));
+
+ /* Clear the coressponding RTC pending bit */
+ RTC->CRL &= (uint16_t)~RTC_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c
new file mode 100644
index 0000000..7588c55
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c
@@ -0,0 +1,798 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_sdio.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the SDIO firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_sdio.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SDIO
+ * @brief SDIO driver modules
+ * @{
+ */
+
+/** @defgroup SDIO_Private_TypesDefinitions
+ * @{
+ */
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber 0x08
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber 0x0B
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber 0x0C
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber 0x0D
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber 0x0E
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber 0x03
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber 0x08
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber 0x09
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber 0x0A
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber 0x0B
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+
+/* --- CLKCR Register ---*/
+
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
+
+/* --- PWRCTRL Register ---*/
+
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void SDIO_DeInit(void)
+{
+ SDIO->POWER = 0x00000000;
+ SDIO->CLKCR = 0x00000000;
+ SDIO->ARG = 0x00000000;
+ SDIO->CMD = 0x00000000;
+ SDIO->DTIMER = 0x00000000;
+ SDIO->DLEN = 0x00000000;
+ SDIO->DCTRL = 0x00000000;
+ SDIO->ICR = 0x00C007FF;
+ SDIO->MASK = 0x00000000;
+}
+
+/**
+ * @brief Initializes the SDIO peripheral according to the specified
+ * parameters in the SDIO_InitStruct.
+ * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
+ * that contains the configuration information for the SDIO peripheral.
+ * @retval None
+ */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
+
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/
+ /* Get the SDIO CLKCR value */
+ tmpreg = SDIO->CLKCR;
+
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+ tmpreg &= CLKCR_CLEAR_MASK;
+
+ /* Set CLKDIV bits according to SDIO_ClockDiv value */
+ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+ /* Set BYPASS bit according to SDIO_ClockBypass value */
+ /* Set WIDBUS bits according to SDIO_BusWide value */
+ /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
+ SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+ SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
+
+ /* Write to SDIO CLKCR */
+ SDIO->CLKCR = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_InitStruct member with its default value.
+ * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+ /* SDIO_InitStruct members default value */
+ SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+ SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+ SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+ SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+ SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+ SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+ * @brief Enables or disables the SDIO Clock.
+ * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Sets the power status of the controller.
+ * @param SDIO_PowerState: new state of the Power state.
+ * This parameter can be one of the following values:
+ * @arg SDIO_PowerState_OFF
+ * @arg SDIO_PowerState_ON
+ * @retval None
+ */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+
+ SDIO->POWER &= PWR_PWRCTRL_MASK;
+ SDIO->POWER |= SDIO_PowerState;
+}
+
+/**
+ * @brief Gets the power status of the controller.
+ * @param None
+ * @retval Power status of the controller. The returned value can
+ * be one of the following:
+ * - 0x00: Power OFF
+ * - 0x02: Power UP
+ * - 0x03: Power ON
+ */
+uint32_t SDIO_GetPowerState(void)
+{
+ return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+ * @brief Enables or disables the SDIO interrupts.
+ * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @param NewState: new state of the specified SDIO interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_IT(SDIO_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the SDIO interrupts */
+ SDIO->MASK |= SDIO_IT;
+ }
+ else
+ {
+ /* Disable the SDIO interrupts */
+ SDIO->MASK &= ~SDIO_IT;
+ }
+}
+
+/**
+ * @brief Enables or disables the SDIO DMA request.
+ * @param NewState: new state of the selected SDIO DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Initializes the SDIO Command according to the specified
+ * parameters in the SDIO_CmdInitStruct and send the command.
+ * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
+ * structure that contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+ assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+ /* Set the SDIO Argument value */
+ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+
+/*---------------------------- SDIO CMD Configuration ------------------------*/
+ /* Get the SDIO CMD value */
+ tmpreg = SDIO->CMD;
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+ tmpreg &= CMD_CLEAR_MASK;
+ /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+ /* Set WAITRESP bits according to SDIO_Response value */
+ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+ /* Set CPSMEN bits according to SDIO_CPSM value */
+ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+ | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+
+ /* Write to SDIO CMD */
+ SDIO->CMD = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.
+ * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+ /* SDIO_CmdInitStruct members default value */
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+ SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+ * @brief Returns command index of last command for which response received.
+ * @param None
+ * @retval Returns the command index of the last command response received.
+ */
+uint8_t SDIO_GetCommandResponse(void)
+{
+ return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+ * @brief Returns response received from the card for the last command.
+ * @param SDIO_RESP: Specifies the SDIO response register.
+ * This parameter can be one of the following values:
+ * @arg SDIO_RESP1: Response Register 1
+ * @arg SDIO_RESP2: Response Register 2
+ * @arg SDIO_RESP3: Response Register 3
+ * @arg SDIO_RESP4: Response Register 4
+ * @retval The Corresponding response register value.
+ */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+ tmp = SDIO_RESP_ADDR + SDIO_RESP;
+
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @brief Initializes the SDIO data path according to the specified
+ * parameters in the SDIO_DataInitStruct.
+ * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
+ * contains the configuration information for the SDIO command.
+ * @retval None
+ */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+ assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+ assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+ assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+ /* Set the SDIO Data TimeOut value */
+ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+ /* Set the SDIO DataLength value */
+ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/
+ /* Get the SDIO DCTRL value */
+ tmpreg = SDIO->DCTRL;
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+ tmpreg &= DCTRL_CLEAR_MASK;
+ /* Set DEN bit according to SDIO_DPSM value */
+ /* Set DTMODE bit according to SDIO_TransferMode value */
+ /* Set DTDIR bit according to SDIO_TransferDir value */
+ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+ | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+ /* Write to SDIO DCTRL */
+ SDIO->DCTRL = tmpreg;
+}
+
+/**
+ * @brief Fills each SDIO_DataInitStruct member with its default value.
+ * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+ /* SDIO_DataInitStruct members default value */
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+ SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
+ SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+ * @brief Returns number of remaining data bytes to be transferred.
+ * @param None
+ * @retval Number of remaining data bytes to be transferred
+ */
+uint32_t SDIO_GetDataCounter(void)
+{
+ return SDIO->DCOUNT;
+}
+
+/**
+ * @brief Read one data word from Rx FIFO.
+ * @param None
+ * @retval Data received
+ */
+uint32_t SDIO_ReadData(void)
+{
+ return SDIO->FIFO;
+}
+
+/**
+ * @brief Write one data word to Tx FIFO.
+ * @param Data: 32-bit data word to write.
+ * @retval None
+ */
+void SDIO_WriteData(uint32_t Data)
+{
+ SDIO->FIFO = Data;
+}
+
+/**
+ * @brief Returns the number of words left to be written to or read from FIFO.
+ * @param None
+ * @retval Remaining number of words.
+ */
+uint32_t SDIO_GetFIFOCount(void)
+{
+ return SDIO->FIFOCNT;
+}
+
+/**
+ * @brief Starts the SD I/O Read Wait operation.
+ * @param NewState: new state of the Start SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Stops the SD I/O Read Wait operation.
+ * @param NewState: new state of the Stop SDIO Read Wait operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+ * @brief Sets one of the two options of inserting read wait interval.
+ * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+ * This parametre can be:
+ * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+ * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+ * @retval None
+ */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+
+ *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode Operation.
+ * @param NewState: new state of SDIO specific operation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the SD I/O Mode suspend command sending.
+ * @param NewState: new state of the SD I/O Mode suspend command.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the command completion signal.
+ * @param NewState: new state of command completion signal.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the CE-ATA interrupt.
+ * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+ * @brief Sends CE-ATA command (CMD61).
+ * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Checks whether the specified SDIO flag is set or not.
+ * @param SDIO_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode.
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval The new state of SDIO_FLAG (SET or RESET).
+ */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+
+ if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO's pending flags.
+ * @param SDIO_FLAG: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+
+ SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.
+ * @param SDIO_IT: specifies the SDIO interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @retval The new state of SDIO_IT (SET or RESET).
+ */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_GET_IT(SDIO_IT));
+ if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SDIO抯 interrupt pending bits.
+ * @param SDIO_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
+ * bus mode interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+ * @retval None
+ */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+
+ SDIO->ICR = SDIO_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
new file mode 100644
index 0000000..a3a2ab0
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c
@@ -0,0 +1,907 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_spi.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the SPI firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_spi.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @defgroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_Private_Defines
+ * @{
+ */
+
+/* SPI SPE mask */
+#define CR1_SPE_Set ((uint16_t)0x0040)
+#define CR1_SPE_Reset ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CR1_CRCNext_Set ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CR1_CRCEN_Set ((uint16_t)0x2000)
+#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CR2_SSOE_Set ((uint16_t)0x0004)
+#define CR2_SSOE_Reset ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CR1_CLEAR_Mask ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select ((uint16_t)0xF7FF)
+#define I2S_Mode_Select ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the SPIx peripheral registers to their default
+ * reset values (Affects also the I2Ss).
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ if (SPIx == SPI1)
+ {
+ /* Enable SPI1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+ /* Release SPI1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+ }
+ else if (SPIx == SPI2)
+ {
+ /* Enable SPI2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+ /* Release SPI2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+ }
+ else
+ {
+ if (SPIx == SPI3)
+ {
+ /* Enable SPI3 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+ /* Release SPI3 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the SPI_InitStruct.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral.
+ * @retval None
+ */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+ uint16_t tmpreg = 0;
+
+ /* check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Check the SPI parameters */
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+ /* Get the SPIx CR1 value */
+ tmpreg = SPIx->CR1;
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+ master/salve mode, CPOL and CPHA */
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+ /* Set LSBFirst bit according to SPI_FirstBit value */
+ /* Set BR bits according to SPI_BaudRatePrescaler value */
+ /* Set CPOL bit according to SPI_CPOL value */
+ /* Set CPHA bit according to SPI_CPHA value */
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+ /* Write to SPIx CR1 */
+ SPIx->CR1 = tmpreg;
+
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ SPIx->I2SCFGR &= SPI_Mode_Select;
+
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+ /* Write to SPIx CRCPOLY */
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+ * @brief Initializes the SPIx peripheral according to the specified
+ * parameters in the I2S_InitStruct.
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral
+ * (configured in I2S mode).
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+ * contains the configuration information for the specified SPI peripheral
+ * configured in I2S mode.
+ * @note
+ * The function calculates the optimal prescaler needed to obtain the most
+ * accurate audio frequency (depending on the I2S clock source, the PLL values
+ * and the product configuration). But in case the prescaler value is greater
+ * than 511, the default value (0x02) will be configured instead. *
+ * @retval None
+ */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+ uint32_t tmp = 0;
+ RCC_ClocksTypeDef RCC_Clocks;
+ uint32_t sourceclock = 0;
+
+ /* Check the I2S parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+ SPIx->I2SPR = 0x0002;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = SPIx->I2SCFGR;
+
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+ {
+ i2sodd = (uint16_t)0;
+ i2sdiv = (uint16_t)2;
+ }
+ /* If the requested audio frequency is not the default, compute the prescaler */
+ else
+ {
+ /* Check the frame length (For the Prescaler computing) */
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+ {
+ /* Packet length is 16 bits */
+ packetlength = 1;
+ }
+ else
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2;
+ }
+
+ /* Get the I2S clock source mask depending on the peripheral number */
+ if(((uint32_t)SPIx) == SPI2_BASE)
+ {
+ /* The mask is relative to I2S2 */
+ tmp = I2S2_CLOCK_SRC;
+ }
+ else
+ {
+ /* The mask is relative to I2S3 */
+ tmp = I2S3_CLOCK_SRC;
+ }
+
+ /* Check the I2S clock source configuration depending on the Device:
+ Only Connectivity line devices have the PLL3 VCO clock */
+#ifdef STM32F10X_CL
+ if((RCC->CFGR2 & tmp) != 0)
+ {
+ /* Get the configuration bits of RCC PLL3 multiplier */
+ tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
+
+ /* Get the value of the PLL3 multiplier */
+ if((tmp > 5) && (tmp < 15))
+ {
+ /* Multplier is between 8 and 14 (value 15 is forbidden) */
+ tmp += 2;
+ }
+ else
+ {
+ if (tmp == 15)
+ {
+ /* Multiplier is 20 */
+ tmp = 20;
+ }
+ }
+ /* Get the PREDIV2 value */
+ sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);
+
+ /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
+ sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
+ }
+ else
+ {
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+ }
+#else /* STM32F10X_HD */
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ RCC_GetClocksFreq(&RCC_Clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;
+#endif /* STM32F10X_CL */
+
+ /* Compute the Real divider depending on the MCLK output state with a flaoting point */
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+ }
+
+ /* Remove the flaoting point */
+ tmp = tmp / 10;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t) (i2sodd << 8);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+ {
+ /* Set the default values */
+ i2sdiv = 2;
+ i2sodd = 0;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+
+ /* Configure the I2S with the SPI_InitStruct values */
+ tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));
+
+ /* Write to SPIx I2SCFGR */
+ SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+ * @brief Fills each SPI_InitStruct member with its default value.
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+ /* Initialize the SPI_Direction member */
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ /* initialize the SPI_Mode member */
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+ /* initialize the SPI_DataSize member */
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+ /* Initialize the SPI_CPOL member */
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+ /* Initialize the SPI_CPHA member */
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+ /* Initialize the SPI_NSS member */
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+ /* Initialize the SPI_BaudRatePrescaler member */
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ /* Initialize the SPI_FirstBit member */
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+ /* Initialize the SPI_CRCPolynomial member */
+ SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+ * @brief Fills each I2S_InitStruct member with its default value.
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+ /* Initialize the I2S_Mode member */
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+
+ /* Initialize the I2S_Standard member */
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+
+ /* Initialize the I2S_DataFormat member */
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+
+ /* Initialize the I2S_MCLKOutput member */
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+
+ /* Initialize the I2S_AudioFreq member */
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+
+ /* Initialize the I2S_CPOL member */
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral */
+ SPIx->CR1 |= CR1_SPE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral */
+ SPIx->CR1 &= CR1_SPE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_23_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI peripheral (in I2S mode) */
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified SPI/I2S interrupts.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask
+ * @param NewState: new state of the specified SPI/I2S interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+ uint16_t itpos = 0, itmask = 0 ;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = (uint16_t)1 << (uint16_t)itpos;
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S interrupt */
+ SPIx->CR2 |= itmask;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S interrupt */
+ SPIx->CR2 &= (uint16_t)~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+ * @param NewState: new state of the selected SPI/I2S DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI/I2S DMA requests */
+ SPIx->CR2 |= SPI_I2S_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected SPI/I2S DMA requests */
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+ }
+}
+
+/**
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param Data : Data to be transmitted.
+ * @retval None
+ */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Write in the DR register the data to be sent */
+ SPIx->DR = Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @retval The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the data in the DR register */
+ return SPIx->DR;
+}
+
+/**
+ * @brief Configures internally by software the NSS pin for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+ * This parameter can be one of the following values:
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+ * @retval None
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+ {
+ /* Set NSS pin internally by software */
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+ }
+ else
+ {
+ /* Reset NSS pin internally by software */
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the SS output for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx SS output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI SS output */
+ SPIx->CR2 |= CR2_SSOE_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI SS output */
+ SPIx->CR2 &= CR2_SSOE_Reset;
+ }
+}
+
+/**
+ * @brief Configures the data size for the selected SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_DataSize: specifies the SPI data size.
+ * This parameter can be one of the following values:
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit
+ * @retval None
+ */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+ /* Clear DFF bit */
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+ /* Set new DFF bit value */
+ SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+ * @brief Transmit the SPIx CRC value.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval None
+ */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Enable the selected SPI CRC transmission */
+ SPIx->CR1 |= CR1_CRCNext_Set;
+}
+
+/**
+ * @brief Enables or disables the CRC value calculation of the transfered bytes.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param NewState: new state of the SPIx CRC value calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected SPI CRC calculation */
+ SPIx->CR1 |= CR1_CRCEN_Set;
+ }
+ else
+ {
+ /* Disable the selected SPI CRC calculation */
+ SPIx->CR1 &= CR1_CRCEN_Reset;
+ }
+}
+
+/**
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_CRC: specifies the CRC register to be read.
+ * This parameter can be one of the following values:
+ * @arg SPI_CRC_Tx: Selects Tx CRC register
+ * @arg SPI_CRC_Rx: Selects Rx CRC register
+ * @retval The selected CRC register value..
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+ uint16_t crcreg = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_CRC(SPI_CRC));
+ if (SPI_CRC != SPI_CRC_Rx)
+ {
+ /* Get the Tx CRC register */
+ crcreg = SPIx->TXCRCR;
+ }
+ else
+ {
+ /* Get the Rx CRC register */
+ crcreg = SPIx->RXCRCR;
+ }
+ /* Return the selected CRC register */
+ return crcreg;
+}
+
+/**
+ * @brief Returns the CRC Polynomial register value for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @retval The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+ /* Return the CRC polynomial register */
+ return SPIx->CRCPR;
+}
+
+/**
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+ * @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
+ * This parameter can be one of the following values:
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction
+ * @arg SPI_Direction_Rx: Selects Rx receive direction
+ * @retval None
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));
+ if (SPI_Direction == SPI_Direction_Tx)
+ {
+ /* Set the Tx only mode */
+ SPIx->CR1 |= SPI_Direction_Tx;
+ }
+ else
+ {
+ /* Set the Rx only mode */
+ SPIx->CR1 &= SPI_Direction_Rx;
+ }
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S flag is set or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.
+ * @arg SPI_FLAG_MODF: Mode Fault flag.
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.
+ * @arg I2S_FLAG_UDR: Underrun Error flag.
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+ /* Check the status of the specified SPI/I2S flag */
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+ {
+ /* SPI_I2S_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
+ * This function clears only CRCERR flag.
+ * @note
+ * - OVR (OverRun error) flag is cleared by software sequence: a read
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - UDR (UnderRun error) flag is cleared by a read operation to
+ * SPI_SR register (SPI_I2S_GetFlagStatus()).
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+
+ /* Clear the selected SPI CRC Error (CRCERR) flag */
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * - 2 or 3 in I2S mode
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.
+ * @arg SPI_IT_MODF: Mode Fault interrupt.
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.
+ * @arg I2S_IT_UDR: Underrun Error interrupt.
+ * @retval The new state of SPI_I2S_IT (SET or RESET).
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+ /* Get the SPI/I2S IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Get the SPI/I2S IT mask */
+ itmask = SPI_I2S_IT >> 4;
+
+ /* Set the IT mask */
+ itmask = 0x01 << itmask;
+
+ /* Get the SPI_I2S_IT enable bit status */
+ enablestatus = (SPIx->CR2 & itmask) ;
+
+ /* Check the status of the specified SPI/I2S interrupt */
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+ {
+ /* SPI_I2S_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* SPI_I2S_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the SPI_I2S_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ * @param SPIx: where x can be
+ * - 1, 2 or 3 in SPI mode
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+ * This function clears only CRCERR intetrrupt pending bit.
+ * @note
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()).
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
+ * the SPI).
+ * @retval None
+ */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+ uint16_t itpos = 0;
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+
+ /* Get the SPI IT index */
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+ SPIx->SR = (uint16_t)~itpos;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
new file mode 100644
index 0000000..24d5bae
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
@@ -0,0 +1,2799 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_tim.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the TIM firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_tim.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup TIM
+ * @brief TIM driver modules
+ * @{
+ */
+
+/** @defgroup TIM_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Defines
+ * @{
+ */
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define CR1_CEN_Set ((uint16_t)0x0001)
+#define CR1_CEN_Reset ((uint16_t)0x03FE)
+#define CR1_UDIS_Set ((uint16_t)0x0002)
+#define CR1_UDIS_Reset ((uint16_t)0x03FD)
+#define CR1_URS_Set ((uint16_t)0x0004)
+#define CR1_URS_Reset ((uint16_t)0x03FB)
+#define CR1_OPM_Reset ((uint16_t)0x03F7)
+#define CR1_CounterMode_Mask ((uint16_t)0x038F)
+#define CR1_ARPE_Set ((uint16_t)0x0080)
+#define CR1_ARPE_Reset ((uint16_t)0x037F)
+#define CR1_CKD_Mask ((uint16_t)0x00FF)
+#define CR2_CCPC_Set ((uint16_t)0x0001)
+#define CR2_CCPC_Reset ((uint16_t)0xFFFE)
+#define CR2_CCUS_Set ((uint16_t)0x0004)
+#define CR2_CCUS_Reset ((uint16_t)0xFFFB)
+#define CR2_CCDS_Set ((uint16_t)0x0008)
+#define CR2_CCDS_Reset ((uint16_t)0xFFF7)
+#define CR2_MMS_Mask ((uint16_t)0xFF8F)
+#define CR2_TI1S_Set ((uint16_t)0x0080)
+#define CR2_TI1S_Reset ((uint16_t)0xFF7F)
+#define CR2_OIS1_Reset ((uint16_t)0x7EFF)
+#define CR2_OIS1N_Reset ((uint16_t)0x7DFF)
+#define CR2_OIS2_Reset ((uint16_t)0x7BFF)
+#define CR2_OIS2N_Reset ((uint16_t)0x77FF)
+#define CR2_OIS3_Reset ((uint16_t)0x6FFF)
+#define CR2_OIS3N_Reset ((uint16_t)0x5FFF)
+#define CR2_OIS4_Reset ((uint16_t)0x3FFF)
+#define SMCR_SMS_Mask ((uint16_t)0xFFF8)
+#define SMCR_ETR_Mask ((uint16_t)0x00FF)
+#define SMCR_TS_Mask ((uint16_t)0xFF8F)
+#define SMCR_MSM_Reset ((uint16_t)0xFF7F)
+#define SMCR_ECE_Set ((uint16_t)0x4000)
+#define CCMR_CC13S_Mask ((uint16_t)0xFFFC)
+#define CCMR_CC24S_Mask ((uint16_t)0xFCFF)
+#define CCMR_TI13Direct_Set ((uint16_t)0x0001)
+#define CCMR_TI24Direct_Set ((uint16_t)0x0100)
+#define CCMR_OC13FE_Reset ((uint16_t)0xFFFB)
+#define CCMR_OC24FE_Reset ((uint16_t)0xFBFF)
+#define CCMR_OC13PE_Reset ((uint16_t)0xFFF7)
+#define CCMR_OC24PE_Reset ((uint16_t)0xF7FF)
+#define CCMR_OC13M_Mask ((uint16_t)0xFF8F)
+#define CCMR_OC24M_Mask ((uint16_t)0x8FFF)
+#define CCMR_OC13CE_Reset ((uint16_t)0xFF7F)
+#define CCMR_OC24CE_Reset ((uint16_t)0x7FFF)
+#define CCMR_IC13PSC_Mask ((uint16_t)0xFFF3)
+#define CCMR_IC24PSC_Mask ((uint16_t)0xF3FF)
+#define CCMR_IC13F_Mask ((uint16_t)0xFF0F)
+#define CCMR_IC24F_Mask ((uint16_t)0x0FFF)
+#define CCMR_Offset ((uint16_t)0x0018)
+#define CCER_CCE_Set ((uint16_t)0x0001)
+#define CCER_CCNE_Set ((uint16_t)0x0004)
+#define CCER_CC1P_Reset ((uint16_t)0xFFFD)
+#define CCER_CC2P_Reset ((uint16_t)0xFFDF)
+#define CCER_CC3P_Reset ((uint16_t)0xFDFF)
+#define CCER_CC4P_Reset ((uint16_t)0xDFFF)
+#define CCER_CC1NP_Reset ((uint16_t)0xFFF7)
+#define CCER_CC2NP_Reset ((uint16_t)0xFF7F)
+#define CCER_CC3NP_Reset ((uint16_t)0xF7FF)
+#define CCER_CC1E_Set ((uint16_t)0x0001)
+#define CCER_CC1E_Reset ((uint16_t)0xFFFE)
+#define CCER_CC1NE_Reset ((uint16_t)0xFFFB)
+#define CCER_CC2E_Set ((uint16_t)0x0010)
+#define CCER_CC2E_Reset ((uint16_t)0xFFEF)
+#define CCER_CC2NE_Reset ((uint16_t)0xFFBF)
+#define CCER_CC3E_Set ((uint16_t)0x0100)
+#define CCER_CC3E_Reset ((uint16_t)0xFEFF)
+#define CCER_CC3NE_Reset ((uint16_t)0xFBFF)
+#define CCER_CC4E_Set ((uint16_t)0x1000)
+#define CCER_CC4E_Reset ((uint16_t)0xEFFF)
+#define BDTR_MOE_Set ((uint16_t)0x8000)
+#define BDTR_MOE_Reset ((uint16_t)0x7FFF)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter);
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+ if (TIMx == TIM1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+ }
+ else if (TIMx == TIM2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+ }
+ else if (TIMx == TIM3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+ }
+ else if (TIMx == TIM4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+ }
+ else if (TIMx == TIM5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+ }
+ else if (TIMx == TIM6)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+ }
+ else if (TIMx == TIM7)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+ }
+ else
+ {
+ if (TIMx == TIM8)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the TIMx Time Base Unit peripheral according to
+ * the specified parameters in the TIM_TimeBaseInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+ * structure that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+ /* Select the Counter Mode and set the clock division */
+ TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
+ TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision |
+ TIM_TimeBaseInitStruct->TIM_CounterMode;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+ if ((((uint32_t) TIMx) == TIM1_BASE) || (((uint32_t) TIMx) == TIM8_BASE))
+ {
+ /* Set the Repetition Counter value */
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+ }
+
+ /* Generate an update event to reload the Prescaler value immediatly */
+ TIMx->EGR = TIM_PSCReloadMode_Immediate;
+}
+
+/**
+ * @brief Initializes the TIMx Channel1 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= CCER_CC1E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC1P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+
+ /* Set the Output State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= CCER_CC1NP_Reset;
+ /* Set the Output N Polarity */
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+ /* Reset the Output N State */
+ tmpccer &= CCER_CC1NE_Reset;
+
+ /* Set the Output N State */
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+ /* Reset the Ouput Compare and Output Compare N IDLE State */
+ tmpcr2 &= CR2_OIS1_Reset;
+ tmpcr2 &= CR2_OIS1N_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+ /* Set the Output N Idle state */
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel2 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= CCER_CC2E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmrx = TIMx->CCMR1;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC2P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= CCER_CC2NP_Reset;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+ /* Reset the Output N State */
+ tmpccer &= CCER_CC2NE_Reset;
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+ /* Reset the Ouput Compare and Output Compare N IDLE State */
+ tmpcr2 &= CR2_OIS2_Reset;
+ tmpcr2 &= CR2_OIS2N_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel3 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= CCER_CC3E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= CCMR_OC13M_Mask & CCMR_CC13S_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC3P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+ /* Reset the Output N Polarity level */
+ tmpccer &= CCER_CC3NP_Reset;
+ /* Set the Output N Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+ /* Reset the Output N State */
+ tmpccer &= CCER_CC3NE_Reset;
+
+ /* Set the Output N State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+ /* Reset the Ouput Compare and Output Compare N IDLE State */
+ tmpcr2 &= CR2_OIS3_Reset;
+ tmpcr2 &= CR2_OIS3N_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+ /* Set the Output N Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIMx Channel4 according to the specified
+ * parameters in the TIM_OCInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+ /* Disable the Channel 2: Reset the CC4E Bit */
+ TIMx->CCER &= CCER_CC4E_Reset;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = TIMx->CR2;
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmrx = TIMx->CCMR2;
+
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */
+ tmpccmrx &= CCMR_OC24M_Mask & CCMR_CC24S_Mask;
+
+ /* Select the Output Compare Mode */
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+ /* Reset the Output Polarity level */
+ tmpccer &= CCER_CC4P_Reset;
+ /* Set the Output Compare Polarity */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+
+ /* Set the Output State */
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+ if(((uint32_t) TIMx == TIM1_BASE) || ((uint32_t) TIMx == TIM8_BASE))
+ {
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+ /* Reset the Ouput Compare IDLE State */
+ tmpcr2 &= CR2_OIS4_Reset;
+ /* Set the Output Idle state */
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+ }
+ /* Write to TIMx CR2 */
+ TIMx->CR2 = tmpcr2;
+
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmrx;
+
+ /* Set the Capture Compare Register value */
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Initializes the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+ {
+ /* TI3 Configuration */
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI4 Configuration */
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+ TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the TIM peripheral according to the specified
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+ * that contains the configuration information for the specified TIM peripheral.
+ * @retval None
+ */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Select the Opposite Input Polarity */
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+ {
+ icoppositepolarity = TIM_ICPolarity_Falling;
+ }
+ else
+ {
+ icoppositepolarity = TIM_ICPolarity_Rising;
+ }
+ /* Select the Opposite Input */
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+ {
+ icoppositeselection = TIM_ICSelection_IndirectTI;
+ }
+ else
+ {
+ icoppositeselection = TIM_ICSelection_DirectTI;
+ }
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+ {
+ /* TI1 Configuration */
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI2 Configuration */
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+ else
+ {
+ /* TI2 Configuration */
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+ TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ /* TI1 Configuration */
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+ /* Set the Input Capture Prescaler value */
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+ }
+}
+
+/**
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,
+ * the OSSR State and the AOE(automatic output enable).
+ * @param TIMx: where x can be 1 or 8 to select the TIM
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+ * contains the BDTR Register configuration information for the TIM peripheral.
+ * @retval None
+ */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+ /* Set the default configuration */
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+ * @brief Fills each TIM_OCInitStruct member with its default value.
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+ /* Set the default configuration */
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+ * @brief Fills each TIM_ICInitStruct member with its default value.
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified TIM peripheral.
+ * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
+ * @param NewState: new state of the TIMx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Counter */
+ TIMx->CR1 |= CR1_CEN_Set;
+ }
+ else
+ {
+ /* Disable the TIM Counter */
+ TIMx->CR1 &= CR1_CEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the TIM peripheral Main Outputs.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral.
+ * @param NewState: new state of the TIM peripheral Main Outputs.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the TIM Main Output */
+ TIMx->BDTR |= BDTR_MOE_Set;
+ }
+ else
+ {
+ /* Disable the TIM Main Output */
+ TIMx->BDTR &= BDTR_MOE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified TIM interrupts.
+ * @param TIMx: where x can be 1 to 8 to select the TIMx peripheral.
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can only generate an update interrupt.
+ * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Interrupt sources */
+ TIMx->DIER |= TIM_IT;
+ }
+ else
+ {
+ /* Disable the Interrupt sources */
+ TIMx->DIER &= (uint16_t)~TIM_IT;
+ }
+}
+
+/**
+ * @brief Configures the TIMx event to be generate by software.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_EventSource: specifies the event source.
+ * This parameter can be one or more of the following values:
+ * @arg TIM_EventSource_Update: Timer update Event source
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+ * @arg TIM_EventSource_COM: Timer COM event source
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source
+ * @arg TIM_EventSource_Break: Timer Break event source
+ * @note
+ * - TIM6 and TIM7 can only generate an update event.
+ * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+
+ /* Set the event sources */
+ TIMx->EGR = TIM_EventSource;
+}
+
+/**
+ * @brief Configures the TIMx抯 DMA interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_DMABase: DMA Base address.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+ * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+ * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+ * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+ * TIM_DMABase_DCR.
+ * @param TIM_DMABurstLength: DMA Burst length.
+ * This parameter can be one value between:
+ * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
+ * @retval None
+ */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+ /* Set the DMA Base and the DMA Burst Length */
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+ * @brief Enables or disables the TIMx抯 DMA Requests.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_DMASource: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_DMA_Update: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA sources */
+ TIMx->DIER |= TIM_DMASource;
+ }
+ else
+ {
+ /* Disable the DMA sources */
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;
+ }
+}
+
+/**
+ * @brief Configures the TIMx interrnal Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval None
+ */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Disable slave mode to clock the prescaler directly with the internal clock */
+ TIMx->SMCR &= SMCR_SMS_Mask;
+}
+
+/**
+ * @brief Configures the TIMx Internal Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ITRSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @param TIM_TS_ITR0: Internal Trigger 0
+ * @param TIM_TS_ITR1: Internal Trigger 1
+ * @param TIM_TS_ITR2: Internal Trigger 2
+ * @param TIM_TS_ITR3: Internal Trigger 3
+ * @retval None
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Select the Internal Trigger */
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the TIMx Trigger as External Clock
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_TIxExternalCLKSource: Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+ * @param TIM_ICPolarity: specifies the TIx Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param ICFilter : specifies the filter value.
+ * This parameter must be a value between 0x0 and 0xF.
+ * @retval None
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+ assert_param(IS_TIM_IC_FILTER(ICFilter));
+ /* Configure the Timer Input Clock Source */
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+ {
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ else
+ {
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+ }
+ /* Select the Trigger source */
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+ /* Select the External clock mode1 */
+ TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+ * @brief Configures the External clock Mode1
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the SMS Bits */
+ tmpsmcr &= SMCR_SMS_Mask;
+ /* Select the External clock mode1 */
+ tmpsmcr |= TIM_SlaveMode_External1;
+ /* Select the Trigger selection : ETRF */
+ tmpsmcr &= SMCR_TS_Mask;
+ tmpsmcr |= TIM_TS_ETRF;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the External clock Mode2
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ /* Configure the ETR Clock source */
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+ /* Enable the External clock mode2 */
+ TIMx->SMCR |= SMCR_ECE_Set;
+}
+
+/**
+ * @brief Configures the TIMx External Trigger (ETR).
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+ * @param ExtTRGFilter: External Trigger Filter.
+ * This parameter must be a value between 0x00 and 0x0F
+ * @retval None
+ */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+ uint16_t ExtTRGFilter)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the ETR Bits */
+ tmpsmcr &= SMCR_ETR_Mask;
+ /* Set the Prescaler, the Filter value and the Polarity */
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Prescaler.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param Prescaler: specifies the Prescaler Register value
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+ * This parameter can be one of the following values:
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
+ * @retval None
+ */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+ /* Set the Prescaler value */
+ TIMx->PSC = Prescaler;
+ /* Set or reset the UG Bit */
+ TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+ * @brief Specifies the TIMx Counter Mode to be used.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_CounterMode: specifies the Counter Mode to be used
+ * This parameter can be one of the following values:
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+ * @retval None
+ */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+ uint16_t tmpcr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+ tmpcr1 = TIMx->CR1;
+ /* Reset the CMS and DIR Bits */
+ tmpcr1 &= CR1_CounterMode_Mask;
+ /* Set the Counter Mode */
+ tmpcr1 |= TIM_CounterMode;
+ /* Write to TIMx CR1 register */
+ TIMx->CR1 = tmpcr1;
+}
+
+/**
+ * @brief Selects the Input Trigger source
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_InputTriggerSource: The Input Trigger source.
+ * This parameter can be one of the following values:
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
+ * @retval None
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+ uint16_t tmpsmcr = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= SMCR_TS_Mask;
+ /* Set the Input Trigger source */
+ tmpsmcr |= TIM_InputTriggerSource;
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+}
+
+/**
+ * @brief Configures the TIMx Encoder Interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
+ * This parameter can be one of the following values:
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+ * on the level of the other input.
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.
+ * @retval None
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+ uint16_t tmpsmcr = 0;
+ uint16_t tmpccmr1 = 0;
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
+ /* Set the encoder Mode */
+ tmpsmcr &= SMCR_SMS_Mask;
+ tmpsmcr |= TIM_EncoderMode;
+
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
+ tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
+
+ /* Set the TI1 and the TI2 Polarities */
+ tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
+
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+
+ /* Write to TIMx CCER */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+ * @retval None
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1M Bits */
+ tmpccmr1 &= CCMR_OC13M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+ * @retval None
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2M Bits */
+ tmpccmr1 &= CCMR_OC24M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+ * @retval None
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC1M Bits */
+ tmpccmr2 &= CCMR_OC13M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= TIM_ForcedAction;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+ * This parameter can be one of the following values:
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+ * @retval None
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC2M Bits */
+ tmpccmr2 &= CCMR_OC24M_Mask;
+ /* Configure The Forced output Mode */
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx peripheral Preload register
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the ARR Preload Bit */
+ TIMx->CR1 |= CR1_ARPE_Set;
+ }
+ else
+ {
+ /* Reset the ARR Preload Bit */
+ TIMx->CR1 &= CR1_ARPE_Reset;
+ }
+}
+
+/**
+ * @brief Selects the TIM peripheral Commutation event.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Commutation event.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the COM Bit */
+ TIMx->CR2 |= CR2_CCUS_Set;
+ }
+ else
+ {
+ /* Reset the COM Bit */
+ TIMx->CR2 &= CR2_CCUS_Reset;
+ }
+}
+
+/**
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the Capture Compare DMA source
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCDS Bit */
+ TIMx->CR2 |= CR2_CCDS_Set;
+ }
+ else
+ {
+ /* Reset the CCDS Bit */
+ TIMx->CR2 &= CR2_CCDS_Reset;
+ }
+}
+
+/**
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral
+ * @param NewState: new state of the Capture Compare Preload Control bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the CCPC Bit */
+ TIMx->CR2 |= CR2_CCPC_Set;
+ }
+ else
+ {
+ /* Reset the CCPC Bit */
+ TIMx->CR2 &= CR2_CCPC_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1PE Bit */
+ tmpccmr1 &= CCMR_OC13PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= TIM_OCPreload;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2PE Bit */
+ tmpccmr1 &= CCMR_OC24PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3PE Bit */
+ tmpccmr2 &= CCMR_OC13PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= TIM_OCPreload;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
+ * This parameter can be one of the following values:
+ * @arg TIM_OCPreload_Enable
+ * @arg TIM_OCPreload_Disable
+ * @retval None
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4PE Bit */
+ tmpccmr2 &= CCMR_OC24PE_Reset;
+ /* Enable or Disable the Output Compare Preload feature */
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 1 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1FE Bit */
+ tmpccmr1 &= CCMR_OC13FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= TIM_OCFast;
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 2 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2FE Bit */
+ tmpccmr1 &= CCMR_OC24FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR1 */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 3 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3FE Bit */
+ tmpccmr2 &= CCMR_OC13FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= TIM_OCFast;
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx Output Compare 4 Fast feature.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable
+ * @retval None
+ */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4FE Bit */
+ tmpccmr2 &= CCMR_OC24FE_Reset;
+ /* Enable or Disable the Output Compare Fast Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+ /* Write to TIMx CCMR2 */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF1 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC1CE Bit */
+ tmpccmr1 &= CCMR_OC13CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= TIM_OCClear;
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF2 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr1 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr1 = TIMx->CCMR1;
+ /* Reset the OC2CE Bit */
+ tmpccmr1 &= CCMR_OC24CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR1 register */
+ TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF3 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC3CE Bit */
+ tmpccmr2 &= CCMR_OC13CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= TIM_OCClear;
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Clears or safeguards the OCREF4 signal on an external event
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+ * This parameter can be one of the following values:
+ * @arg TIM_OCClear_Enable: TIM Output clear enable
+ * @arg TIM_OCClear_Disable: TIM Output clear disable
+ * @retval None
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+ uint16_t tmpccmr2 = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+ tmpccmr2 = TIMx->CCMR2;
+ /* Reset the OC4CE Bit */
+ tmpccmr2 &= CCMR_OC24CE_Reset;
+ /* Enable or Disable the Output Compare Clear Bit */
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+ /* Write to TIMx CCMR2 register */
+ TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+ * @brief Configures the TIMx channel 1 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC1 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1P Bit */
+ tmpccer &= CCER_CC1P_Reset;
+ tmpccer |= TIM_OCPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 1N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC1NP Bit */
+ tmpccer &= CCER_CC1NP_Reset;
+ tmpccer |= TIM_OCNPolarity;
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 2 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC2 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2P Bit */
+ tmpccer &= CCER_CC2P_Reset;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 2N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC2NP Bit */
+ tmpccer &= CCER_CC2NP_Reset;
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 3 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC3 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3P Bit */
+ tmpccer &= CCER_CC3P_Reset;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx Channel 3N polarity.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCNPolarity_High: Output Compare active high
+ * @arg TIM_OCNPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+ uint16_t tmpccer = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC3NP Bit */
+ tmpccer &= CCER_CC3NP_Reset;
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configures the TIMx channel 4 polarity.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_OCPolarity: specifies the OC4 Polarity
+ * This parmeter can be one of the following values:
+ * @arg TIM_OCPolarity_High: Output Compare active high
+ * @arg TIM_OCPolarity_Low: Output Compare active low
+ * @retval None
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+ uint16_t tmpccer = 0;
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+ tmpccer = TIMx->CCER;
+ /* Set or Reset the CC4P Bit */
+ tmpccer &= CCER_CC4P_Reset;
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+ /* Write to TIMx CCER register */
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel x.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parmeter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+ * @retval None
+ */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCX(TIM_CCx));
+
+ tmp = CCER_CCE_Set << TIM_Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t)~ tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+ * @brief Enables or disables the TIM Capture Compare Channel xN.
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parmeter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+ * @retval None
+ */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+ uint16_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_18_PERIPH(TIMx));
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+ tmp = CCER_CCNE_Set << TIM_Channel;
+
+ /* Reset the CCxNE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp;
+
+ /* Set or reset the CCxNE Bit */
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+ * @brief Selects the TIM Ouput Compare Mode.
+ * @note This function disables the selected channel before changing the Ouput
+ * Compare Mode.
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_Channel: specifies the TIM Channel
+ * This parmeter can be one of the following values:
+ * @arg TIM_Channel_1: TIM Channel 1
+ * @arg TIM_Channel_2: TIM Channel 2
+ * @arg TIM_Channel_3: TIM Channel 3
+ * @arg TIM_Channel_4: TIM Channel 4
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.
+ * This paramter can be one of the following values:
+ * @arg TIM_OCMode_Timing
+ * @arg TIM_OCMode_Active
+ * @arg TIM_OCMode_Toggle
+ * @arg TIM_OCMode_PWM1
+ * @arg TIM_OCMode_PWM2
+ * @arg TIM_ForcedAction_Active
+ * @arg TIM_ForcedAction_InActive
+ * @retval None
+ */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+ uint32_t tmp = 0;
+ uint16_t tmp1 = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));
+ assert_param(IS_TIM_OCM(TIM_OCMode));
+
+ tmp = (uint32_t) TIMx;
+ tmp += CCMR_Offset;
+
+ tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+
+ /* Disable the Channel: Reset the CCxE Bit */
+ TIMx->CCER &= (uint16_t) ~tmp1;
+
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+ {
+ tmp += (TIM_Channel>>1);
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC13M_Mask;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= TIM_OCMode;
+ }
+ else
+ {
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+ /* Reset the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp &= CCMR_OC24M_Mask;
+
+ /* Configure the OCxM bits in the CCMRx register */
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+ }
+}
+
+/**
+ * @brief Enables or Disables the TIMx Update event.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx UDIS bit
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the Update Disable Bit */
+ TIMx->CR1 |= CR1_UDIS_Set;
+ }
+ else
+ {
+ /* Reset the Update Disable Bit */
+ TIMx->CR1 &= CR1_UDIS_Reset;
+ }
+}
+
+/**
+ * @brief Configures the TIMx Update Request Interrupt source.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_UpdateSource: specifies the Update source.
+ * This parameter can be one of the following values:
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
+ or the setting of UG bit, or an update generation
+ through the slave mode controller.
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+ * @retval None
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)
+ {
+ /* Set the URS Bit */
+ TIMx->CR1 |= CR1_URS_Set;
+ }
+ else
+ {
+ /* Reset the URS Bit */
+ TIMx->CR1 &= CR1_URS_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the TIMx抯 Hall sensor interface.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param NewState: new state of the TIMx Hall sensor interface.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Set the TI1S Bit */
+ TIMx->CR2 |= CR2_TI1S_Set;
+ }
+ else
+ {
+ /* Reset the TI1S Bit */
+ TIMx->CR2 &= CR2_TI1S_Reset;
+ }
+}
+
+/**
+ * @brief Selects the TIMx抯 One Pulse Mode.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_OPMode: specifies the OPM Mode to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_OPMode_Single
+ * @arg TIM_OPMode_Repetitive
+ * @retval None
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+ /* Reset the OPM Bit */
+ TIMx->CR1 &= CR1_OPM_Reset;
+ /* Configure the OPM Mode */
+ TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+ * @brief Selects the TIMx Trigger Output Mode.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_TRGOSource: specifies the Trigger Output source.
+ * This paramter can be one of the following values:
+ *
+ * - For all TIMx
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
+ *
+ * - For all TIMx except TIM6 and TIM7
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+ * is to be set, as soon as a capture or compare match occurs (TRGO).
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
+ *
+ * @retval None
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+ /* Reset the MMS Bits */
+ TIMx->CR2 &= CR2_MMS_Mask;
+ /* Select the TRGO source */
+ TIMx->CR2 |= TIM_TRGOSource;
+}
+
+/**
+ * @brief Selects the TIMx Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.
+ * This paramter can be one of the following values:
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
+ * the counter and triggers an update of the registers.
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
+ * @retval None
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+ /* Reset the SMS Bits */
+ TIMx->SMCR &= SMCR_SMS_Mask;
+ /* Select the Slave Mode */
+ TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+ * @brief Sets or Resets the TIMx Master/Slave Mode.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+ * This paramter can be one of the following values:
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+ * and its slaves (through TRGO).
+ * @arg TIM_MasterSlaveMode_Disable: No action
+ * @retval None
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+ /* Reset the MSM Bit */
+ TIMx->SMCR &= SMCR_MSM_Reset;
+
+ /* Set or Reset the MSM Bit */
+ TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+ * @brief Sets the TIMx Counter Register value
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param Counter: specifies the Counter register new value.
+ * @retval None
+ */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Counter Register value */
+ TIMx->CNT = Counter;
+}
+
+/**
+ * @brief Sets the TIMx Autoreload Register value
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param Autoreload: specifies the Autoreload register new value.
+ * @retval None
+ */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Set the Autoreload Register value */
+ TIMx->ARR = Autoreload;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare1 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare1: specifies the Capture Compare1 register new value.
+ * @retval None
+ */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare1 Register value */
+ TIMx->CCR1 = Compare1;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare2 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare2: specifies the Capture Compare2 register new value.
+ * @retval None
+ */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare2 Register value */
+ TIMx->CCR2 = Compare2;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare3 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare3: specifies the Capture Compare3 register new value.
+ * @retval None
+ */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare3 Register value */
+ TIMx->CCR3 = Compare3;
+}
+
+/**
+ * @brief Sets the TIMx Capture Compare4 Register value
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param Compare4: specifies the Capture Compare4 register new value.
+ * @retval None
+ */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Set the Capture Compare4 Register value */
+ TIMx->CCR4 = Compare4;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 1 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC1PSC Bits */
+ TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
+ /* Set the IC1PSC value */
+ TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 2 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC2PSC Bits */
+ TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
+ /* Set the IC2PSC value */
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 3 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC3PSC Bits */
+ TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
+ /* Set the IC3PSC value */
+ TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+ * @brief Sets the TIMx Input Capture 4 prescaler.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+ * @retval None
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+ /* Reset the IC4PSC Bits */
+ TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
+ /* Set the IC4PSC value */
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+ * @brief Sets the TIMx Clock Division value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_CKD: specifies the clock division value.
+ * This parameter can be one of the following value:
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+ * @retval None
+ */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+ /* Reset the CKD Bits */
+ TIMx->CR1 &= CR1_CKD_Mask;
+ /* Set the CKD value */
+ TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 1 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 1 Register value */
+ return TIMx->CCR1;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 2 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 2 Register value */
+ return TIMx->CCR2;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 3 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 3 Register value.
+ */
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 3 Register value */
+ return TIMx->CCR3;
+}
+
+/**
+ * @brief Gets the TIMx Input Capture 4 value.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @retval Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_123458_PERIPH(TIMx));
+ /* Get the Capture 4 Register value */
+ return TIMx->CCR4;
+}
+
+/**
+ * @brief Gets the TIMx Counter value.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @retval Counter Register value.
+ */
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Counter Register value */
+ return TIMx->CNT;
+}
+
+/**
+ * @brief Gets the TIMx Prescaler value.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @retval Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ /* Get the Prescaler Register value */
+ return TIMx->PSC;
+}
+
+/**
+ * @brief Checks whether the specified TIM flag is set or not.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+ * @retval The new state of TIM_FLAG (SET or RESET).
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's pending flags.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_FLAG: specifies the flag bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_FLAG_Update: TIM update Flag
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+ * @arg TIM_FLAG_COM: TIM Commutation Flag
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag
+ * @arg TIM_FLAG_Break: TIM Break Flag
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+ * @note
+ * - TIM6 and TIM7 can have only one update flag.
+ * - TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
+
+ /* Clear the flags */
+ TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+ * @brief Checks whether the TIM interrupt has occurred or not.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT: specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_Update: TIM update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ * @retval The new state of the TIM_IT(SET or RESET).
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_GET_IT(TIM_IT));
+
+ itstatus = TIMx->SR & TIM_IT;
+
+ itenable = TIMx->DIER & TIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the TIMx's interrupt pending bits.
+ * @param TIMx: where x can be 1 to 8 to select the TIM peripheral.
+ * @param TIM_IT: specifies the pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg TIM_IT_Update: TIM1 update Interrupt source
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+ * @arg TIM_IT_Break: TIM Break Interrupt source
+ * @note
+ * - TIM6 and TIM7 can generate only an update interrupt.
+ * - TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+ * @retval None
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));
+ assert_param(IS_TIM_IT(TIM_IT));
+ /* Clear the IT pending Bit */
+ TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0;
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= CCER_CC1E_Reset;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+ /* Select the Polarity and set the CC1E Bit */
+ tmpccer &= CCER_CC1P_Reset;
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set);
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI2 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= CCER_CC2E_Reset;
+ tmpccmr1 = TIMx->CCMR1;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 4);
+ /* Select the Input and set the filter */
+ tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+ /* Select the Polarity and set the CC2E Bit */
+ tmpccer &= CCER_CC2P_Reset;
+ tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set);
+ /* Write to TIMx CCMR1 and CCER registers */
+ TIMx->CCMR1 = tmpccmr1 ;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI3 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= CCER_CC3E_Reset;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 8);
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+ /* Select the Polarity and set the CC3E Bit */
+ tmpccer &= CCER_CC3P_Reset;
+ tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set);
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer;
+}
+
+/**
+ * @brief Configure the TI1 as Input.
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+ * @param TIM_ICPolarity : The Input Polarity.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICPolarity_Rising
+ * @arg TIM_ICPolarity_Falling
+ * @param TIM_ICSelection: specifies the input to be used.
+ * This parameter can be one of the following values:
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * This parameter must be a value between 0x00 and 0x0F.
+ * @retval None
+ */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+ uint16_t TIM_ICFilter)
+{
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= CCER_CC4E_Reset;
+ tmpccmr2 = TIMx->CCMR2;
+ tmpccer = TIMx->CCER;
+ tmp = (uint16_t)(TIM_ICPolarity << 12);
+
+ /* Select the Input and set the filter */
+ tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+ /* Select the Polarity and set the CC4E Bit */
+ tmpccer &= CCER_CC4P_Reset;
+ tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set);
+ /* Write to TIMx CCMR2 and CCER registers */
+ TIMx->CCMR2 = tmpccmr2;
+ TIMx->CCER = tmpccer ;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
new file mode 100644
index 0000000..8add38d
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c
@@ -0,0 +1,967 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_usart.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the USART firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_usart.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+/** @defgroup USART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Defines
+ * @{
+ */
+
+#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */
+#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */
+
+#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
+
+#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
+#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
+#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */
+#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */
+#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */
+
+#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
+#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
+
+#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
+#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */
+#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */
+
+#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */
+#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
+
+#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
+#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
+
+#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
+#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
+
+#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
+#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */
+
+#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
+#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
+#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
+#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
+#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ if (USARTx == USART1)
+ {
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+ }
+ else if (USARTx == USART2)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+ }
+ else if (USARTx == USART3)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+ }
+ else if (USARTx == UART4)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+ }
+ else
+ {
+ if (USARTx == UART5)
+ {
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the USARTx peripheral according to the specified
+ * parameters in the USART_InitStruct .
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval None
+ */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+ uint32_t tmpreg = 0x00, apbclock = 0x00;
+ uint32_t integerdivider = 0x00;
+ uint32_t fractionaldivider = 0x00;
+ uint32_t usartxbase = 0;
+ RCC_ClocksTypeDef RCC_ClocksStatus;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */
+ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear STOP[13:12] bits */
+ tmpreg &= CR2_STOP_CLEAR_Mask;
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set STOP[13:12] bits according to USART_StopBits value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = USARTx->CR1;
+ /* Clear M, PCE, PS, TE and RE bits */
+ tmpreg &= CR1_CLEAR_Mask;
+ /* Configure the USART Word Length, Parity and mode ----------------------- */
+ /* Set the M bits according to USART_WordLength value */
+ /* Set PCE and PS bits according to USART_Parity value */
+ /* Set TE and RE bits according to USART_Mode value */
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+ USART_InitStruct->USART_Mode;
+ /* Write to USART CR1 */
+ USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/
+ tmpreg = USARTx->CR3;
+ /* Clear CTSE and RTSE bits */
+ tmpreg &= CR3_CLEAR_Mask;
+ /* Configure the USART HFC -------------------------------------------------*/
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+ /* Write to USART CR3 */
+ USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+ /* Configure the USART Baud Rate -------------------------------------------*/
+ RCC_GetClocksFreq(&RCC_ClocksStatus);
+ if (usartxbase == USART1_BASE)
+ {
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+ }
+ else
+ {
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+ }
+ /* Determine the integer part */
+ integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
+ tmpreg = (integerdivider / 0x64) << 0x04;
+ /* Determine the fractional part */
+ fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
+ tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((uint8_t)0x0F);
+ /* Write to USART BRR */
+ USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_InitStruct member with its default value.
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+ /* USART_InitStruct members default value */
+ USART_InitStruct->USART_BaudRate = 9600;
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;
+ USART_InitStruct->USART_Parity = USART_Parity_No ;
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/**
+ * @brief Initializes the USARTx peripheral Clock according to the
+ * specified parameters in the USART_ClockInitStruct .
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure that contains the configuration information for the specified
+ * USART peripheral.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ uint32_t tmpreg = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+ tmpreg = USARTx->CR2;
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= CR2_CLOCK_CLEAR_Mask;
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+ /* Set CLKEN bit according to USART_Clock value */
+ /* Set CPOL bit according to USART_CPOL value */
+ /* Set CPHA bit according to USART_CPHA value */
+ /* Set LBCL bit according to USART_LastBit value */
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+ /* Write to USART CR2 */
+ USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+ * @brief Fills each USART_ClockInitStruct member with its default value.
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ * structure which will be initialized.
+ * @retval None
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+ /* USART_ClockInitStruct members default value */
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified USART peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USARTx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected USART by setting the UE bit in the CR1 register */
+ USARTx->CR1 |= CR1_UE_Set;
+ }
+ else
+ {
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */
+ USARTx->CR1 &= CR1_UE_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified USART interrupts.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @param NewState: new state of the specified USARTx interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+ uint32_t usartxbase = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CONFIG_IT(USART_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ usartxbase = (uint32_t)USARTx;
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+ /* Get the interrupt position */
+ itpos = USART_IT & IT_Mask;
+ itmask = (((uint32_t)0x01) << itpos);
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ usartxbase += 0x0C;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ usartxbase += 0x10;
+ }
+ else /* The IT is in CR3 register */
+ {
+ usartxbase += 0x14;
+ }
+ if (NewState != DISABLE)
+ {
+ *(__IO uint32_t*)usartxbase |= itmask;
+ }
+ else
+ {
+ *(__IO uint32_t*)usartxbase &= ~itmask;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART抯 DMA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3 or UART4.
+ * @param USART_DMAReq: specifies the DMA request.
+ * This parameter can be any combination of the following values:
+ * @arg USART_DMAReq_Tx: USART DMA transmit request
+ * @arg USART_DMAReq_Rx: USART DMA receive request
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The DMA mode is not available for UART5.
+ * @retval None
+ */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_1234_PERIPH(USARTx));
+ assert_param(IS_USART_DMAREQ(USART_DMAReq));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 |= USART_DMAReq;
+ }
+ else
+ {
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+ DMAR bits in the USART CR3 register */
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+ }
+}
+
+/**
+ * @brief Sets the address of the USART node.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Address: Indicates the address of the USART node.
+ * @retval None
+ */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_ADDRESS(USART_Address));
+
+ /* Clear the USART address */
+ USARTx->CR2 &= CR2_Address_Mask;
+ /* Set the USART address node */
+ USARTx->CR2 |= USART_Address;
+}
+
+/**
+ * @brief Selects the USART WakeUp method.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_WakeUp: specifies the USART wakeup method.
+ * This parameter can be one of the following values:
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+ * @retval None
+ */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));
+
+ USARTx->CR1 &= CR1_WAKE_Mask;
+ USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+ * @brief Determines if the USART is in mute mode or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART mute mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */
+ USARTx->CR1 |= CR1_RWU_Set;
+ }
+ else
+ {
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+ USARTx->CR1 &= CR1_RWU_Reset;
+ }
+}
+
+/**
+ * @brief Sets the USART LIN Break detection length.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+ * @retval None
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+
+ USARTx->CR2 &= CR2_LBDL_Mask;
+ USARTx->CR2 |= USART_LINBreakDetectLength;
+}
+
+/**
+ * @brief Enables or disables the USART抯 LIN mode.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART LIN mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ USARTx->CR2 |= CR2_LINEN_Set;
+ }
+ else
+ {
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+ USARTx->CR2 &= CR2_LINEN_Reset;
+ }
+}
+
+/**
+ * @brief Transmits single data through the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param Data: the data to transmit.
+ * @retval None
+ */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_DATA(Data));
+
+ /* Transmit Data */
+ USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Returns the most recent received data by the USARTx peripheral.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Receive Data */
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+ * @brief Transmits break characters.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @retval None
+ */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Send break characters */
+ USARTx->CR1 |= CR1_SBK_Set;
+}
+
+/**
+ * @brief Sets the specified USART guard time.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param USART_GuardTime: specifies the guard time.
+ * @note The guard time bits are not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+
+ /* Clear the USART Guard time */
+ USARTx->GTPR &= GTPR_LSB_Mask;
+ /* Set the USART guard time */
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+ * @brief Sets the system clock prescaler.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_Prescaler: specifies the prescaler clock.
+ * @note The function is used for IrDA mode with UART4 and UART5.
+ * @retval None
+ */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+ /* Clear the USART prescaler */
+ USARTx->GTPR &= GTPR_MSB_Mask;
+ /* Set the USART prescaler */
+ USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+ * @brief Enables or disables the USART抯 Smart Card mode.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the Smart Card mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+ USARTx->CR3 |= CR3_SCEN_Set;
+ }
+ else
+ {
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+ USARTx->CR3 &= CR3_SCEN_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables NACK transmission.
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.
+ * @param NewState: new state of the NACK transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The Smart Card mode is not available for UART4 and UART5.
+ * @retval None
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+ USARTx->CR3 |= CR3_NACK_Set;
+ }
+ else
+ {
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+ USARTx->CR3 &= CR3_NACK_Reset;
+ }
+}
+
+/**
+ * @brief Enables or disables the USART抯 Half Duplex communication.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the USART Communication.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+ USARTx->CR3 |= CR3_HDSEL_Set;
+ }
+ else
+ {
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+ USARTx->CR3 &= CR3_HDSEL_Reset;
+ }
+}
+
+/**
+ * @brief Configures the USART抯 IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IrDAMode: specifies the IrDA mode.
+ * This parameter can be one of the following values:
+ * @arg USART_IrDAMode_LowPower
+ * @arg USART_IrDAMode_Normal
+ * @retval None
+ */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+
+ USARTx->CR3 &= CR3_IRLP_Mask;
+ USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+ * @brief Enables or disables the USART抯 IrDA interface.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param NewState: new state of the IrDA mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+ USARTx->CR3 |= CR3_IREN_Set;
+ }
+ else
+ {
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+ USARTx->CR3 &= CR3_IREN_Reset;
+ }
+}
+
+/**
+ * @brief Checks whether the specified USART flag is set or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
+ * @arg USART_FLAG_LBD: LIN Break detection flag
+ * @arg USART_FLAG_TXE: Transmit data register empty flag
+ * @arg USART_FLAG_TC: Transmission Complete flag
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag
+ * @arg USART_FLAG_IDLE: Idle Line detection flag
+ * @arg USART_FLAG_ORE: OverRun Error flag
+ * @arg USART_FLAG_NE: Noise Error flag
+ * @arg USART_FLAG_FE: Framing Error flag
+ * @arg USART_FLAG_PE: Parity Error flag
+ * @retval The new state of USART_FLAG (SET or RESET).
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if (USART_FLAG == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx's pending flags.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
+ * @arg USART_FLAG_LBD: LIN Break detection flag.
+ * @arg USART_FLAG_TC: Transmission Complete flag.
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus())
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).
+ * - RXNE flag can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation
+ * to USART_DR register (USART_SendData()).
+ * - TXE flag is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+ /* The CTS flag is not available for UART4 and UART5 */
+ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified USART interrupt has occurred or not.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the USART interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt
+ * @arg USART_IT_IDLE: Idle line detection interrupt
+ * @arg USART_IT_ORE: OverRun Error interrupt
+ * @arg USART_IT_NE: Noise Error interrupt
+ * @arg USART_IT_FE: Framing Error interrupt
+ * @arg USART_IT_PE: Parity Error interrupt
+ * @retval The new state of USART_IT (SET or RESET).
+ */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_GET_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ /* Get the USART register index */
+ usartreg = (((uint8_t)USART_IT) >> 0x05);
+ /* Get the interrupt position */
+ itmask = USART_IT & IT_Mask;
+ itmask = (uint32_t)0x01 << itmask;
+
+ if (usartreg == 0x01) /* The IT is in CR1 register */
+ {
+ itmask &= USARTx->CR1;
+ }
+ else if (usartreg == 0x02) /* The IT is in CR2 register */
+ {
+ itmask &= USARTx->CR2;
+ }
+ else /* The IT is in CR3 register */
+ {
+ itmask &= USARTx->CR3;
+ }
+
+ bitpos = USART_IT >> 0x08;
+ bitpos = (uint32_t)0x01 << bitpos;
+ bitpos &= USARTx->SR;
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the USARTx抯 interrupt pending bits.
+ * @param USARTx: Select the USART or the UART peripheral.
+ * This parameter can be one of the following values:
+ * USART1, USART2, USART3, UART4 or UART5.
+ * @param USART_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+ * @arg USART_IT_LBD: LIN Break detection interrupt
+ * @arg USART_IT_TC: Transmission complete interrupt.
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+ *
+ * @note
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) pending bits are cleared by
+ * software sequence: a read operation to USART_SR register
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register
+ * (USART_ReceiveData()).
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register
+ * (USART_ReceiveData()).
+ * - TC pending bit can be also cleared by software sequence: a read
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write
+ * operation to USART_DR register (USART_SendData()).
+ * - TXE pending bit is cleared only by a write to the USART_DR register
+ * (USART_SendData()).
+ * @retval None
+ */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+ uint16_t bitpos = 0x00, itmask = 0x00;
+ /* Check the parameters */
+ assert_param(IS_USART_ALL_PERIPH(USARTx));
+ assert_param(IS_USART_CLEAR_IT(USART_IT));
+ /* The CTS interrupt is not available for UART4 and UART5 */
+ if (USART_IT == USART_IT_CTS)
+ {
+ assert_param(IS_USART_123_PERIPH(USARTx));
+ }
+
+ bitpos = USART_IT >> 0x08;
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+ USARTx->SR = (uint16_t)~itmask;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
new file mode 100644
index 0000000..6cb6a02
--- /dev/null
+++ b/F107/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_wwdg.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides all the WWDG firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_wwdg.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32F10x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup WWDG
+ * @brief WWDG driver modules
+ * @{
+ */
+
+/** @defgroup WWDG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Defines
+ * @{
+ */
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber 0x09
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_WDGA_Set ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
+#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
+#define BIT_Mask ((uint8_t)0x7F)
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void WWDG_DeInit(void)
+{
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+ * @brief Sets the WWDG Prescaler.
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.
+ * This parameter can be one of the following values:
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+ * @retval None
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+ uint32_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+ /* Clear WDGTB[1:0] bits */
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+ tmpreg |= WWDG_Prescaler;
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Sets the WWDG window value.
+ * @param WindowValue: specifies the window value to be compared to the downcounter.
+ * This parameter value must be lower than 0x80.
+ * @retval None
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+ __IO uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+ /* Clear W[6:0] bits */
+
+ tmpreg = WWDG->CFR & CFR_W_Mask;
+
+ /* Set W[6:0] bits according to WindowValue value */
+ tmpreg |= WindowValue & (uint32_t) BIT_Mask;
+
+ /* Store the new value */
+ WWDG->CFR = tmpreg;
+}
+
+/**
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).
+ * @param None
+ * @retval None
+ */
+void WWDG_EnableIT(void)
+{
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+ * @brief Sets the WWDG counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ /* Write to T[6:0] bits to configure the counter value, no need to do
+ a read-modify-write; writing a 0 to WDGA bit does nothing */
+ WWDG->CR = Counter & BIT_Mask;
+}
+
+/**
+ * @brief Enables WWDG and load the counter value.
+ * @param Counter: specifies the watchdog counter value.
+ * This parameter must be a number between 0x40 and 0x7F.
+ * @retval None
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+ /* Check the parameters */
+ assert_param(IS_WWDG_COUNTER(Counter));
+ WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/**
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.
+ * @param None
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+ return (FlagStatus)(WWDG->SR);
+}
+
+/**
+ * @brief Clears Early Wakeup interrupt flag.
+ * @param None
+ * @retval None
+ */
+void WWDG_ClearFlag(void)
+{
+ WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32_ETH_Driver/inc/stm32_eth.h b/F107/Libraries/STM32_ETH_Driver/inc/stm32_eth.h
new file mode 100644
index 0000000..7aac819
--- /dev/null
+++ b/F107/Libraries/STM32_ETH_Driver/inc/stm32_eth.h
@@ -0,0 +1,1742 @@
+/**
+ ******************************************************************************
+ * @file stm32_eth.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 11/20/2009
+ * @brief This file contains all the functions prototypes for the Ethernet
+ * firmware library.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ETH_H
+#define __STM32_ETH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup STM32_ETH_Driver
+ * @{
+ */
+
+/** @defgroup ETH_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief ETH MAC Init structure definition
+ * @note The user should not configure all the ETH_InitTypeDef structure's fields.
+ * By calling the ETH_StructInit function the structure抯 fields are set to their default values.
+ * Only the parameters that will be set to a non-default value should be configured.
+ */
+typedef struct {
+/**
+ * @brief / * MAC
+ */
+ uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+ and the mode (half/full-duplex).
+ This parameter can be a value of @ref ETH_AutoNegotiation */
+
+ uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes.
+ This parameter can be a value of @ref ETH_watchdog */
+
+ uint32_t ETH_Jabber; /*!< Selects or not Jabber timer
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Jabber */
+
+ uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+
+ uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense
+ This parameter can be a value of @ref ETH_Carrier_Sense */
+
+ uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
+ This parameter can be a value of @ref ETH_Speed */
+
+ uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+ in Half-Duplex mode
+ This parameter can be a value of @ref ETH_Receive_Own */
+
+ uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
+
+ uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref ETH_Duplex_Mode */
+
+ uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+ This parameter can be a value of @ref ETH_Checksum_Offload */
+
+ uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+ when a colision occurs (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Retry_Transmission */
+
+ uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+
+ uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Deferral_Check */
+
+ uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No fitering)
+ This parameter can be a value of @ref ETH_Receive_All */
+
+ uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
+
+ uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
+
+ uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+ uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+
+ uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+ uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+
+ uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+
+ uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */
+
+ uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */
+
+ uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the
+ transmit control frame */
+
+ uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+
+ uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
+ automatic retransmission of PAUSE Frame
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+ unicast address and unique multicast address)
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+
+ uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
+ disable its transmitter for a specified time (Pause Time)
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+ uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+ or the MAC back-pressure operation (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+
+ uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+ comparison and filtering
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+
+ uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
+
+/**
+ * @brief / * DMA
+ */
+
+ uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+
+ uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
+
+ uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
+
+ uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+
+ uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+ uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+ uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes) including pad-bytes and CRC)
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+ uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+ uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining the status for the first frame.
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+ uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+ uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
+ This parameter can be a value of @ref ETH_Fixed_Burst */
+
+ uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+ uint32_t ETH_TxDMABurstLength; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+ uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */
+
+ uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
+}ETH_InitTypeDef;
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief DMA descriptors types
+ */
+/**--------------------------------------------------------------------------**/
+
+/**
+ * @brief ETH DMA Desciptors data structure definition
+ */
+typedef struct {
+ uint32_t Status; /*!< Status */
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
+} ETH_DMADESCTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Constants
+ * @{
+ */
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ * (for precise timing), otherwise default _eth_delay_ function defined within
+ * this driver is used (less precise timing).
+ */
+/* #define USE_Delay */
+
+#ifdef USE_Delay
+#include "main.h"
+ #define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */
+#else
+ #define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */
+#endif
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief ETH Frames defines
+ */
+/**--------------------------------------------------------------------------**/
+
+/** @defgroup ENET_Buffers_setting
+ * @{
+ */
+#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC 4 /*!< Ethernet CRC */
+#define ETH_EXTRA 2 /*!< Extra bytes in some cases */
+#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */
+#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */
+#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief Ethernet DMA descriptors registers bits definition
+ */
+/**--------------------------------------------------------------------------**/
+
+/**
+@code
+ DMA Tx Desciptor
+ -----------------------------------------------------------------------------------------------
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Buffer1 Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+@endcode
+*/
+
+/**
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
+ */
+#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
+#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */
+#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */
+#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */
+#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */
+#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
+#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
+#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
+#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
+#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
+#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
+#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
+#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */
+#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */
+#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
+#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */
+#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
+#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
+
+/**
+ * @brief Bit definition of TDES1 register
+ */
+#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
+#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
+
+/**
+ * @brief Bit definition of TDES2 register
+ */
+#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of TDES3 register
+ */
+#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_Rx_descriptor
+ * @{
+ */
+
+/**
+@code
+ DMA Rx Desciptor
+ --------------------------------------------------------------------------------------------------------------------
+ RDES0 | OWN(31) | Status [30:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | Buffer1 Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+@endcode
+*/
+
+/**
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
+ */
+#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
+#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */
+#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
+#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
+#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
+#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
+#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
+#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
+#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */
+#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
+ * @brief Bit definition of RDES1 register
+ */
+#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
+#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
+#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
+#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
+#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
+
+/**
+ * @brief Bit definition of RDES2 register
+ */
+#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of RDES3 register
+ */
+#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief Desciption of common PHY registers
+ */
+/**--------------------------------------------------------------------------**/
+
+/**
+ * @}
+ */
+
+/** @defgroup PHY_Read_write_Timeouts
+ * @{
+ */
+#define PHY_READ_TO ((uint32_t)0x0004FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0004FFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup PHY_Reset_Delay
+ * @{
+ */
+#define PHY_ResetDelay ((uint32_t)0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup PHY_Config_Delay
+ * @{
+ */
+#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup PHY_Register_address
+ * @{
+ */
+#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */
+#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */
+
+/**
+ * @}
+ */
+
+/** @defgroup PHY_basic_Control_register
+ * @{
+ */
+#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */
+#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */
+#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */
+
+/**
+ * @}
+ */
+
+/** @defgroup PHY_basic_status_register
+ * @{
+ */
+#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */
+#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */
+#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */
+
+/**
+ * @}
+ */
+
+/** @defgroup PHY_status_register
+ * @{
+ */
+/* The PHY status register value change from a PHY to another so the user have
+ to update this value depending on the used external PHY */
+/**
+ * @brief For LAN8700
+ */
+//#define PHY_SR 31 /*!< Tranceiver Status Register */
+/**
+ * @brief For DP83848
+ */
+#define PHY_SR 16 /*!< Tranceiver Status Register */
+
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update
+ this value depending on the used external PHY */
+/**
+ * @brief For LAN8700
+ */
+//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */
+//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */
+
+/**
+ * @brief For DP83848
+ */
+#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */
+#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
+ ((REG) == PHY_BSR) || \
+ ((REG) == PHY_SR))
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief MAC defines
+ */
+/**--------------------------------------------------------------------------**/
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_AutoNegotiation
+ * @{
+ */
+#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001)
+#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
+ ((CMD) == ETH_AutoNegotiation_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_watchdog
+ * @{
+ */
+#define ETH_Watchdog_Enable ((uint32_t)0x00000000)
+#define ETH_Watchdog_Disable ((uint32_t)0x00800000)
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
+ ((CMD) == ETH_Watchdog_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Jabber
+ * @{
+ */
+#define ETH_Jabber_Enable ((uint32_t)0x00000000)
+#define ETH_Jabber_Disable ((uint32_t)0x00400000)
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
+ ((CMD) == ETH_Jabber_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Frame_Gap
+ * @{
+ */
+#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
+ ((GAP) == ETH_InterFrameGap_88Bit) || \
+ ((GAP) == ETH_InterFrameGap_80Bit) || \
+ ((GAP) == ETH_InterFrameGap_72Bit) || \
+ ((GAP) == ETH_InterFrameGap_64Bit) || \
+ ((GAP) == ETH_InterFrameGap_56Bit) || \
+ ((GAP) == ETH_InterFrameGap_48Bit) || \
+ ((GAP) == ETH_InterFrameGap_40Bit))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Carrier_Sense
+ * @{
+ */
+#define ETH_CarrierSense_Enable ((uint32_t)0x00000000)
+#define ETH_CarrierSense_Disable ((uint32_t)0x00010000)
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
+ ((CMD) == ETH_CarrierSense_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Speed
+ * @{
+ */
+#define ETH_Speed_10M ((uint32_t)0x00000000)
+#define ETH_Speed_100M ((uint32_t)0x00004000)
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
+ ((SPEED) == ETH_Speed_100M))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Own
+ * @{
+ */
+#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000)
+#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000)
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
+ ((CMD) == ETH_ReceiveOwn_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Loop_Back_Mode
+ * @{
+ */
+#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000)
+#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000)
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
+ ((CMD) == ETH_LoopbackMode_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Duplex_Mode
+ * @{
+ */
+#define ETH_Mode_FullDuplex ((uint32_t)0x00000800)
+#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000)
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
+ ((MODE) == ETH_Mode_HalfDuplex))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Offload
+ * @{
+ */
+#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400)
+#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000)
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
+ ((CMD) == ETH_ChecksumOffload_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Retry_Transmission
+ * @{
+ */
+#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000)
+#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200)
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
+ ((CMD) == ETH_RetryTransmission_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip
+ * @{
+ */
+#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080)
+#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000)
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
+ ((CMD) == ETH_AutomaticPadCRCStrip_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit
+ * @{
+ */
+#define ETH_BackOffLimit_10 ((uint32_t)0x00000000)
+#define ETH_BackOffLimit_8 ((uint32_t)0x00000020)
+#define ETH_BackOffLimit_4 ((uint32_t)0x00000040)
+#define ETH_BackOffLimit_1 ((uint32_t)0x00000060)
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
+ ((LIMIT) == ETH_BackOffLimit_8) || \
+ ((LIMIT) == ETH_BackOffLimit_4) || \
+ ((LIMIT) == ETH_BackOffLimit_1))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Deferral_Check
+ * @{
+ */
+#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010)
+#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000)
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
+ ((CMD) == ETH_DeferralCheck_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_All
+ * @{
+ */
+#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000)
+#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
+ ((CMD) == ETH_ReceiveAll_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Filter
+ * @{
+ */
+#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200)
+#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300)
+#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000)
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
+ ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \
+ ((CMD) == ETH_SourceAddrFilter_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pass_Control_Frames
+ * @{
+ */
+#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
+#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
+ ((PASS) == ETH_PassControlFrames_ForwardAll) || \
+ ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Broadcast_Frames_Reception
+ * @{
+ */
+#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000)
+#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020)
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
+ ((CMD) == ETH_BroadcastFramesReception_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Destination_Addr_Filter
+ * @{
+ */
+#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000)
+#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008)
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
+ ((FILTER) == ETH_DestinationAddrFilter_Inverse))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Promiscuous_Mode
+ * @{
+ */
+#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001)
+#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000)
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
+ ((CMD) == ETH_PromiscuousMode_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Multicast_Frames_Filter
+ * @{
+ */
+#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404)
+#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004)
+#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000)
+#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010)
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
+ ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \
+ ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \
+ ((FILTER) == ETH_MulticastFramesFilter_None))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Frames_Filter
+ * @{
+ */
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)
+#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002)
+#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
+ ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \
+ ((FILTER) == ETH_UnicastFramesFilter_Perfect))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Time
+ * @{
+ */
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Zero_Quanta_Pause
+ * @{
+ */
+#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000)
+#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
+ ((CMD) == ETH_ZeroQuantaPause_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold
+ * @{
+ */
+#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
+#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
+#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
+#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect
+ * @{
+ */
+#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008)
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
+ ((CMD) == ETH_UnicastPauseFrameDetect_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Flow_Control
+ * @{
+ */
+#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004)
+#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
+ ((CMD) == ETH_ReceiveFlowControl_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Flow_Control
+ * @{
+ */
+#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002)
+#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
+ ((CMD) == ETH_TransmitFlowControl_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison
+ * @{
+ */
+#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000)
+#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000)
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
+ ((COMPARISON) == ETH_VLANTagComparison_16Bit))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Flags
+ * @{
+ */
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts
+ * @{
+ */
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses
+ * @{
+ */
+#define ETH_MAC_Address0 ((uint32_t)0x00000000)
+#define ETH_MAC_Address1 ((uint32_t)0x00000008)
+#define ETH_MAC_Address2 ((uint32_t)0x00000010)
+#define ETH_MAC_Address3 ((uint32_t)0x00000018)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
+ ((ADDRESS) == ETH_MAC_Address1) || \
+ ((ADDRESS) == ETH_MAC_Address2) || \
+ ((ADDRESS) == ETH_MAC_Address3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
+ ((ADDRESS) == ETH_MAC_Address2) || \
+ ((ADDRESS) == ETH_MAC_Address3))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
+ * @{
+ */
+#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000)
+#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008)
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
+ ((FILTER) == ETH_MAC_AddressFilter_DA))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
+ * @{
+ */
+#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
+ ((MASK) == ETH_MAC_AddressMask_Byte5) || \
+ ((MASK) == ETH_MAC_AddressMask_Byte4) || \
+ ((MASK) == ETH_MAC_AddressMask_Byte3) || \
+ ((MASK) == ETH_MAC_AddressMask_Byte2) || \
+ ((MASK) == ETH_MAC_AddressMask_Byte1))
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief Ethernet DMA Desciptors defines
+ */
+/**--------------------------------------------------------------------------**/
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_flags
+ * @{
+ */
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
+ ((FLAG) == ETH_DMATxDesc_IC) || \
+ ((FLAG) == ETH_DMATxDesc_LS) || \
+ ((FLAG) == ETH_DMATxDesc_FS) || \
+ ((FLAG) == ETH_DMATxDesc_DC) || \
+ ((FLAG) == ETH_DMATxDesc_DP) || \
+ ((FLAG) == ETH_DMATxDesc_TTSE) || \
+ ((FLAG) == ETH_DMATxDesc_TER) || \
+ ((FLAG) == ETH_DMATxDesc_TCH) || \
+ ((FLAG) == ETH_DMATxDesc_TTSS) || \
+ ((FLAG) == ETH_DMATxDesc_IHE) || \
+ ((FLAG) == ETH_DMATxDesc_ES) || \
+ ((FLAG) == ETH_DMATxDesc_JT) || \
+ ((FLAG) == ETH_DMATxDesc_FF) || \
+ ((FLAG) == ETH_DMATxDesc_PCE) || \
+ ((FLAG) == ETH_DMATxDesc_LCA) || \
+ ((FLAG) == ETH_DMATxDesc_NC) || \
+ ((FLAG) == ETH_DMATxDesc_LCO) || \
+ ((FLAG) == ETH_DMATxDesc_EC) || \
+ ((FLAG) == ETH_DMATxDesc_VF) || \
+ ((FLAG) == ETH_DMATxDesc_CC) || \
+ ((FLAG) == ETH_DMATxDesc_ED) || \
+ ((FLAG) == ETH_DMATxDesc_UF) || \
+ ((FLAG) == ETH_DMATxDesc_DB))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment
+ * @{
+ */
+#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */
+#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
+ ((SEGMENT) == ETH_DMATxDesc_FirstSegment))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
+ * @{
+ */
+#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */
+#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))
+/**
+ * @brief ETH DMA Tx Desciptor buffer size
+ */
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_flags
+ * @{
+ */
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
+ ((FLAG) == ETH_DMARxDesc_AFM) || \
+ ((FLAG) == ETH_DMARxDesc_ES) || \
+ ((FLAG) == ETH_DMARxDesc_DE) || \
+ ((FLAG) == ETH_DMARxDesc_SAF) || \
+ ((FLAG) == ETH_DMARxDesc_LE) || \
+ ((FLAG) == ETH_DMARxDesc_OE) || \
+ ((FLAG) == ETH_DMARxDesc_VLAN) || \
+ ((FLAG) == ETH_DMARxDesc_FS) || \
+ ((FLAG) == ETH_DMARxDesc_LS) || \
+ ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \
+ ((FLAG) == ETH_DMARxDesc_LC) || \
+ ((FLAG) == ETH_DMARxDesc_FT) || \
+ ((FLAG) == ETH_DMARxDesc_RWT) || \
+ ((FLAG) == ETH_DMARxDesc_RE) || \
+ ((FLAG) == ETH_DMARxDesc_DBE) || \
+ ((FLAG) == ETH_DMARxDesc_CE) || \
+ ((FLAG) == ETH_DMARxDesc_MAMPCE))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_
+ * @{
+ */
+#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
+ ((BUFFER) == ETH_DMARxDesc_Buffer2))
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief Ethernet DMA defines
+ */
+/**--------------------------------------------------------------------------**/
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
+ * @{
+ */
+#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000)
+#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000)
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
+ ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Store_Forward
+ * @{
+ */
+#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000)
+#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000)
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
+ ((CMD) == ETH_ReceiveStoreForward_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Flush_Received_Frame
+ * @{
+ */
+#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000)
+#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000)
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
+ ((CMD) == ETH_FlushReceivedFrame_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Store_Forward
+ * @{
+ */
+#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000)
+#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000)
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
+ ((CMD) == ETH_TransmitStoreForward_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Threshold_Control
+ * @{
+ */
+#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
+ ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \
+ ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \
+ ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \
+ ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \
+ ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \
+ ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \
+ ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Error_Frames
+ * @{
+ */
+#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080)
+#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
+ ((CMD) == ETH_ForwardErrorFrames_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames
+ * @{
+ */
+#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040)
+#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000)
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
+ ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Threshold_Control
+ * @{
+ */
+#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Second_Frame_Operate
+ * @{
+ */
+#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004)
+#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000)
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
+ ((CMD) == ETH_SecondFrameOperate_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Address_Aligned_Beats
+ * @{
+ */
+#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000)
+#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000)
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
+ ((CMD) == ETH_AddressAlignedBeats_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Fixed_Burst
+ * @{
+ */
+#define ETH_FixedBurst_Enable ((uint32_t)0x00010000)
+#define ETH_FixedBurst_Disable ((uint32_t)0x00000000)
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
+ ((CMD) == ETH_FixedBurst_Disable))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length
+ * @{
+ */
+#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length
+ * @{
+ */
+#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))
+/**
+ * @brief ETH DMA Desciptor SkipLength
+ */
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Arbitration
+ * @{
+ */
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000)
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000)
+#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \
+ ((RATIO) == ETH_DMAArbitration_RxPriorTx))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Flags
+ * @{
+ */
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
+
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \
+ ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts
+ * @{
+ */
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
+
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_transmit_process_state_
+ * @{
+ */
+#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */
+#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
+#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */
+#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_receive_process_state_
+ * @{
+ */
+#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */
+#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */
+#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
+#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_overflow_
+ * @{
+ */
+#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
+ ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief Ethernet PMT defines
+ */
+/**--------------------------------------------------------------------------**/
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PMT_Flags
+ * @{
+ */
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief Ethernet MMC defines
+ */
+/**--------------------------------------------------------------------------**/
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Tx_Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Rx_Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
+ ((IT) != 0x00))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Registers
+ * @{
+ */
+#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
+#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
+#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
+#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
+#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
+#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
+#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
+#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
+
+/**
+ * @brief ETH MMC registers
+ */
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
+ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
+ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
+ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
+ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
+ ((REG) == ETH_MMCRGUFCR))
+
+/**--------------------------------------------------------------------------**/
+/**
+ * @brief Ethernet PTP defines
+ */
+/**--------------------------------------------------------------------------**/
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PTP_time_update_method
+ * @{
+ */
+#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */
+#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
+ ((UPDATE) == ETH_PTP_CoarseUpdate))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_PTP_Flags
+ * @{
+ */
+#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */
+#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */
+#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */
+#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
+ ((FLAG) == ETH_PTP_FLAG_TSITE) || \
+ ((FLAG) == ETH_PTP_FLAG_TSSTU) || \
+ ((FLAG) == ETH_PTP_FLAG_TSSTI))
+/**
+ * @brief ETH PTP subsecond increment
+ */
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_PTP_time_sign
+ * @{
+ */
+#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */
+#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
+ ((SIGN) == ETH_PTP_NegativeTime))
+
+/**
+ * @brief ETH PTP time stamp low update
+ */
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)
+
+/**
+ * @brief ETH PTP registers
+ */
+#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */
+#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */
+#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */
+#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */
+#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */
+#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */
+#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */
+#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */
+#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
+ ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \
+ ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \
+ ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \
+ ((REG) == ETH_PTPTTLR))
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Exported_Functions
+ * @{
+ */
+void ETH_DeInit(void);
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
+void ETH_SoftwareReset(void);
+FlagStatus ETH_GetSoftwareResetStatus(void);
+void ETH_Start(void);
+uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength);
+uint32_t ETH_HandleRxPkt(u8 *ppkt);
+uint32_t ETH_GetRxPktSize(void);
+void ETH_DropRxPkt(void);
+
+/**
+ * @brief PHY
+ */
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);
+uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);
+uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);
+
+/**
+ * @brief MAC
+ */
+void ETH_MACTransmissionCmd(FunctionalState NewState);
+void ETH_MACReceptionCmd(FunctionalState NewState);
+FlagStatus ETH_GetFlowControlBusyStatus(void);
+void ETH_InitiatePauseControlFrame(void);
+void ETH_BackPressureActivationCmd(FunctionalState NewState);
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG);
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
+void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr);
+void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr);
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
+
+/**
+ * @brief DMA Tx/Rx descriptors
+ */
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount);
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount);
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount);
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);
+
+/**
+ * @brief DMA
+ */
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
+uint32_t ETH_GetTransmitProcessState(void);
+uint32_t ETH_GetReceiveProcessState(void);
+void ETH_FlushTransmitFIFO(void);
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
+void ETH_DMATransmissionCmd(FunctionalState NewState);
+void ETH_DMAReceptionCmd(FunctionalState NewState);
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
+uint32_t ETH_GetCurrentTxDescStartAddress(void);
+uint32_t ETH_GetCurrentRxDescStartAddress(void);
+uint32_t ETH_GetCurrentTxBufferAddress(void);
+uint32_t ETH_GetCurrentRxBufferAddress(void);
+void ETH_ResumeDMATransmission(void);
+void ETH_ResumeDMAReception(void);
+
+/**
+ * @brief PMT
+ */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
+void ETH_PowerDownCmd(FunctionalState NewState);
+
+/**
+ * @brief MMC
+ */
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
+void ETH_MMCCountersReset(void);
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);
+
+/**
+ * @brief PTP
+ */
+uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab);
+uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab);
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount);
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
+void ETH_EnablePTPTimeStampAddend(void);
+void ETH_EnablePTPTimeStampInterruptTrigger(void);
+void ETH_EnablePTPTimeStampUpdate(void);
+void ETH_InitializePTPTimeStamp(void);
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);
+void ETH_PTPTimeStampCmd(FunctionalState NewState);
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
+void ETH_SetPTPTimeStampAddend(uint32_t Value);
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ETH_H */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Libraries/STM32_ETH_Driver/src/stm32_eth.c b/F107/Libraries/STM32_ETH_Driver/src/stm32_eth.c
new file mode 100644
index 0000000..77b5e32
--- /dev/null
+++ b/F107/Libraries/STM32_ETH_Driver/src/stm32_eth.c
@@ -0,0 +1,3066 @@
+/**
+ ******************************************************************************
+ * @file stm32_eth.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 11/20/2009
+ * @brief This file provides all the ETH firmware functions.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eth.h"
+#include "stm32f10x_rcc.h"
+
+/** @addtogroup STM32_ETH_Driver
+ * @brief ETH driver modules
+ * @{
+ */
+
+/** @defgroup ETH_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_Private_Defines
+ * @{
+ */
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
+ETH_DMADESCTypeDef *DMATxDescToSet;
+ETH_DMADESCTypeDef *DMARxDescToGet;
+ETH_DMADESCTypeDef *DMAPTPTxDescToSet;
+ETH_DMADESCTypeDef *DMAPTPRxDescToGet;
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+
+/* ETHERNET MACCR register Mask */
+#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+
+/* ETHERNET MACFCR register Mask */
+#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+
+/* ETHERNET DMAOMR register Mask */
+#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16
+
+/* ETHERNET errors */
+#define ETH_ERROR ((uint32_t)0)
+#define ETH_SUCCESS ((uint32_t)1)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Private_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Private_Variables
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Private_FunctionPrototypes
+ * @{
+ */
+
+#ifndef USE_Delay
+static void ETH_Delay(__IO uint32_t nCount);
+#endif /* USE_Delay*/
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the ETHERNET peripheral registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void ETH_DeInit(void)
+{
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
+}
+
+/**
+ * @brief Initializes the ETHERNET peripheral according to the specified
+ * parameters in the ETH_InitStruct .
+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains
+ * the configuration information for the specified ETHERNET peripheral.
+ * @param PHYAddress: external PHY address
+ * @retval ETH_ERROR: Ethernet initialization failed
+ * ETH_SUCCESS: Ethernet successfully initialized
+ */
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
+{
+ uint32_t RegValue = 0, tmpreg = 0;
+ __IO uint32_t i = 0;
+ RCC_ClocksTypeDef rcc_clocks;
+ uint32_t hclk = 60000000;
+ __IO uint32_t timeout = 0;
+ /* Check the parameters */
+ /* MAC --------------------------*/
+ assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
+ assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
+ assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
+ assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
+ assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
+ assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
+ assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
+ assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
+ assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
+ assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
+ assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
+ assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
+ assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
+ assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
+ assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
+ assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
+ /* DMA --------------------------*/
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
+ assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength));
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));
+ /*-------------------------------- MAC Config ------------------------------*/
+ /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg = ETH->MACMIIAR;
+ /* Clear CSR Clock Range CR[2:0] bits */
+ tmpreg &= MACMIIAR_CR_MASK;
+ /* Get hclk frequency value */
+ RCC_GetClocksFreq(&rcc_clocks);
+ hclk = rcc_clocks.HCLK_Frequency;
+ /* Set CR bits depending on hclk value */
+ if((hclk >= 20000000)&&(hclk < 35000000))
+ {
+ /* CSR Clock Range between 20-35 MHz */
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+ }
+ else if((hclk >= 35000000)&&(hclk < 60000000))
+ {
+ /* CSR Clock Range between 35-60 MHz */
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+ }
+ else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */
+ {
+ /* CSR Clock Range between 60-72 MHz */
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+ }
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+ ETH->MACMIIAR = (uint32_t)tmpreg;
+ /*-------------------- PHY initialization and configuration ----------------*/
+ /* Put the PHY in reset mode */
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
+ {
+ /* Return ERROR in case of write timeout */
+ return ETH_ERROR;
+ }
+
+ /* Delay to assure PHY reset */
+ _eth_delay_(PHY_ResetDelay);
+
+
+ if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
+ {
+ /* We wait for linked satus... */
+ do
+ {
+ timeout++;
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
+ /* Return ERROR in case of timeout */
+ if(timeout == PHY_READ_TO)
+ {
+ return ETH_ERROR;
+ }
+ /* Reset Timeout counter */
+ timeout = 0;
+
+ /* Enable Auto-Negotiation */
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
+ {
+ /* Return ERROR in case of write timeout */
+ return ETH_ERROR;
+ }
+
+ /* Wait until the autonegotiation will be completed */
+ do
+ {
+ timeout++;
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));
+ /* Return ERROR in case of timeout */
+ if(timeout == PHY_READ_TO)
+ {
+ return ETH_ERROR;
+ }
+ /* Reset Timeout counter */
+ timeout = 0;
+
+ /* Read the result of the autonegotiation */
+ RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
+
+ /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
+ if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
+ {
+ /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
+ ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
+
+ }
+ else
+ {
+ /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+ }
+ /* Configure the MAC with the speed fixed by the autonegotiation process */
+ if(RegValue & PHY_Speed_Status)
+ {
+ /* Set Ethernet speed to 10M following the autonegotiation */
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+ }
+ else
+ {
+ /* Set Ethernet speed to 100M following the autonegotiation */
+ ETH_InitStruct->ETH_Speed = ETH_Speed_100M;
+ }
+ }
+ else
+ {
+ if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
+ (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
+ {
+ /* Return ERROR in case of write timeout */
+ return ETH_ERROR;
+ }
+ /* Delay to assure PHY configuration */
+ _eth_delay_(PHY_ConfigDelay);
+
+ }
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/
+ /* Get the ETHERNET MACCR value */
+ tmpreg = ETH->MACCR;
+ /* Clear WD, PCE, PS, TE and RE bits */
+ tmpreg &= MACCR_CLEAR_MASK;
+ /* Set the WD bit according to ETH_Watchdog value */
+ /* Set the JD: bit according to ETH_Jabber value */
+ /* Set the IFG bit according to ETH_InterFrameGap value */
+ /* Set the DCRS bit according to ETH_CarrierSense value */
+ /* Set the FES bit according to ETH_Speed value */
+ /* Set the DO bit according to ETH_ReceiveOwn value */
+ /* Set the LM bit according to ETH_LoopbackMode value */
+ /* Set the DM bit according to ETH_Mode value */
+ /* Set the IPC bit according to ETH_ChecksumOffload value */
+ /* Set the DR bit according to ETH_RetryTransmission value */
+ /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */
+ /* Set the BL bit according to ETH_BackOffLimit value */
+ /* Set the DC bit according to ETH_DeferralCheck value */
+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog |
+ ETH_InitStruct->ETH_Jabber |
+ ETH_InitStruct->ETH_InterFrameGap |
+ ETH_InitStruct->ETH_CarrierSense |
+ ETH_InitStruct->ETH_Speed |
+ ETH_InitStruct->ETH_ReceiveOwn |
+ ETH_InitStruct->ETH_LoopbackMode |
+ ETH_InitStruct->ETH_Mode |
+ ETH_InitStruct->ETH_ChecksumOffload |
+ ETH_InitStruct->ETH_RetryTransmission |
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip |
+ ETH_InitStruct->ETH_BackOffLimit |
+ ETH_InitStruct->ETH_DeferralCheck);
+ /* Write to ETHERNET MACCR */
+ ETH->MACCR = (uint32_t)tmpreg;
+
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/
+ /* Set the RA bit according to ETH_ReceiveAll value */
+ /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
+ /* Set the PCF bit according to ETH_PassControlFrames value */
+ /* Set the DBF bit according to ETH_BroadcastFramesReception value */
+ /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
+ /* Set the PR bit according to ETH_PromiscuousMode value */
+ /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
+ /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
+ /* Write to ETHERNET MACFFR */
+ ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
+ ETH_InitStruct->ETH_SourceAddrFilter |
+ ETH_InitStruct->ETH_PassControlFrames |
+ ETH_InitStruct->ETH_BroadcastFramesReception |
+ ETH_InitStruct->ETH_DestinationAddrFilter |
+ ETH_InitStruct->ETH_PromiscuousMode |
+ ETH_InitStruct->ETH_MulticastFramesFilter |
+ ETH_InitStruct->ETH_UnicastFramesFilter);
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
+ /* Write to ETHERNET MACHTHR */
+ ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
+ /* Write to ETHERNET MACHTLR */
+ ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/
+ /* Get the ETHERNET MACFCR value */
+ tmpreg = ETH->MACFCR;
+ /* Clear xx bits */
+ tmpreg &= MACFCR_CLEAR_MASK;
+
+ /* Set the PT bit according to ETH_PauseTime value */
+ /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */
+ /* Set the PLT bit according to ETH_PauseLowThreshold value */
+ /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */
+ /* Set the RFE bit according to ETH_ReceiveFlowControl value */
+ /* Set the TFE bit according to ETH_TransmitFlowControl value */
+ tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
+ ETH_InitStruct->ETH_ZeroQuantaPause |
+ ETH_InitStruct->ETH_PauseLowThreshold |
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect |
+ ETH_InitStruct->ETH_ReceiveFlowControl |
+ ETH_InitStruct->ETH_TransmitFlowControl);
+ /* Write to ETHERNET MACFCR */
+ ETH->MACFCR = (uint32_t)tmpreg;
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
+ /* Set the ETV bit according to ETH_VLANTagComparison value */
+ /* Set the VL bit according to ETH_VLANTagIdentifier value */
+ ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
+ ETH_InitStruct->ETH_VLANTagIdentifier);
+
+ /*-------------------------------- DMA Config ------------------------------*/
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
+ /* Get the ETHERNET DMAOMR value */
+ tmpreg = ETH->DMAOMR;
+ /* Clear xx bits */
+ tmpreg &= DMAOMR_CLEAR_MASK;
+
+ /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */
+ /* Set the RSF bit according to ETH_ReceiveStoreForward value */
+ /* Set the DFF bit according to ETH_FlushReceivedFrame value */
+ /* Set the TSF bit according to ETH_TransmitStoreForward value */
+ /* Set the TTC bit according to ETH_TransmitThresholdControl value */
+ /* Set the FEF bit according to ETH_ForwardErrorFrames value */
+ /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */
+ /* Set the RTC bit according to ETH_ReceiveThresholdControl value */
+ /* Set the OSF bit according to ETH_SecondFrameOperate value */
+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
+ ETH_InitStruct->ETH_ReceiveStoreForward |
+ ETH_InitStruct->ETH_FlushReceivedFrame |
+ ETH_InitStruct->ETH_TransmitStoreForward |
+ ETH_InitStruct->ETH_TransmitThresholdControl |
+ ETH_InitStruct->ETH_ForwardErrorFrames |
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |
+ ETH_InitStruct->ETH_ReceiveThresholdControl |
+ ETH_InitStruct->ETH_SecondFrameOperate);
+ /* Write to ETHERNET DMAOMR */
+ ETH->DMAOMR = (uint32_t)tmpreg;
+
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/
+ /* Set the AAL bit according to ETH_AddressAlignedBeats value */
+ /* Set the FB bit according to ETH_FixedBurst value */
+ /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */
+ /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */
+ /* Set the DSL bit according to ETH_DesciptorSkipLength value */
+ /* Set the PR and DA bits according to ETH_DMAArbitration value */
+ ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats |
+ ETH_InitStruct->ETH_FixedBurst |
+ ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
+ ETH_InitStruct->ETH_TxDMABurstLength |
+ (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |
+ ETH_InitStruct->ETH_DMAArbitration |
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
+ /* Return Ethernet configuration success */
+ return ETH_SUCCESS;
+}
+
+/**
+ * @brief Fills each ETH_InitStruct member with its default value.
+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)
+{
+ /* ETH_InitStruct members default value */
+ /*------------------------ MAC -----------------------------------*/
+ ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;
+ ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;
+ ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;
+ ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
+ ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M;
+ ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;
+ ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;
+ ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
+ ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
+ ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;
+ ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;
+ ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;
+ ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
+ ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
+ ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;
+ ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
+ ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
+ ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
+ ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
+ ETH_InitStruct->ETH_HashTableHigh = 0x0;
+ ETH_InitStruct->ETH_HashTableLow = 0x0;
+ ETH_InitStruct->ETH_PauseTime = 0x0;
+ ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;
+ ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
+ ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
+ ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
+ ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
+ ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;
+ /*------------------------ DMA -----------------------------------*/
+ ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;
+ ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+ ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;
+ ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+ ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;
+ ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+ ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;
+ ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;
+ ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+ ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;
+ ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;
+ ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;
+ ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;
+ ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;
+}
+
+/**
+ * @brief Enables ENET MAC and DMA reception/transmission
+ * @param None
+ * @retval None
+ */
+void ETH_Start(void)
+{
+ /* Enable transmit state machine of the MAC for transmission on the MII */
+ ETH_MACTransmissionCmd(ENABLE);
+ /* Flush Transmit FIFO */
+ ETH_FlushTransmitFIFO();
+ /* Enable receive state machine of the MAC for reception from the MII */
+ ETH_MACReceptionCmd(ENABLE);
+
+ /* Start DMA transmission */
+ ETH_DMATransmissionCmd(ENABLE);
+ /* Start DMA reception */
+ ETH_DMAReceptionCmd(ENABLE);
+}
+
+/**
+ * @brief Transmits a packet, from application buffer, pointed by ppkt.
+ * @param ppkt: pointer to the application's packet buffer to transmit.
+ * @param FrameLength: Tx Packet size.
+ * @retval ETH_ERROR: in case of Tx desc owned by DMA
+ * ETH_SUCCESS: for correct transmission
+ */
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)
+{
+ uint32_t offset = 0;
+
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+ {
+ /* Return ERROR: OWN bit set */
+ return ETH_ERROR;
+ }
+
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+ for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset));
+ }
+
+ /* Setting the Frame Length: bits[12:0] */
+ DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);
+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+ {
+ /* Clear TBUS ETHERNET DMA flag */
+ ETH->DMASR = ETH_DMASR_TBUS;
+ /* Resume DMA transmission*/
+ ETH->DMATPDR = 0;
+ }
+
+ /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
+ /* Chained Mode */
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+ {
+ /* Selects the next DMA Tx descriptor list for next buffer to send */
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
+ }
+ else /* Ring Mode */
+ {
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+ {
+ /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+ }
+ else
+ {
+ /* Selects the next DMA Tx descriptor list for next buffer to send */
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+ }
+ }
+ /* Return SUCCESS */
+ return ETH_SUCCESS;
+}
+
+/**
+ * @brief Receives a packet and copies it to memory pointed by ppkt.
+ * @param ppkt: pointer to the application packet receive buffer.
+ * @retval ETH_ERROR: if there is error in reception
+ * framelength: received packet size if packet reception is correct
+ */
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)
+{
+ uint32_t offset = 0, framelength = 0;
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+ {
+ /* Return error: OWN bit set */
+ return ETH_ERROR;
+ }
+
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+ {
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+ for(offset=0; offsetBuffer1Addr) + offset));
+ }
+ }
+ else
+ {
+ /* Return ERROR */
+ framelength = ETH_ERROR;
+ }
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+ {
+ /* Clear RBUS ETHERNET DMA flag */
+ ETH->DMASR = ETH_DMASR_RBUS;
+ /* Resume DMA reception */
+ ETH->DMARPDR = 0;
+ }
+
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+ /* Chained Mode */
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+ {
+ /* Selects the next DMA Rx descriptor list for next buffer to read */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+ }
+ else /* Ring Mode */
+ {
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+ {
+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+ }
+ else
+ {
+ /* Selects the next DMA Rx descriptor list for next buffer to read */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+ }
+ }
+
+ /* Return Frame Length/ERROR */
+ return (framelength);
+}
+
+/**
+ * @brief Get the size of received the received packet.
+ * @param None
+ * @retval framelength: received packet size
+ */
+uint32_t ETH_GetRxPktSize(void)
+{
+ uint32_t frameLength = 0;
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+ {
+ /* Get the size of the packet: including 4 bytes of the CRC */
+ frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);
+ }
+
+ /* Return Frame Length */
+ return frameLength;
+}
+
+/**
+ * @brief Drop a Received packet (too small packet, etc...)
+ * @param None
+ * @retval None
+ */
+void ETH_DropRxPkt(void)
+{
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN;
+ /* Chained Mode */
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+ {
+ /* Selects the next DMA Rx descriptor list for next buffer read */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);
+ }
+ else /* Ring Mode */
+ {
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+ {
+ /* Selects the next DMA Rx descriptor list for next buffer read: this will
+ be the first Rx descriptor in this case */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+ }
+ else
+ {
+ /* Selects the next DMA Rx descriptor list for next buffer read */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+ }
+ }
+}
+
+/*--------------------------------- PHY ------------------------------------*/
+/**
+ * @brief Read a PHY register
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
+ * This parameter can be one of the following values: 0,..,31
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
+ * This parameter can be one of the following values:
+ * @arg PHY_BCR: Tranceiver Basic Control Register
+ * @arg PHY_BSR: Tranceiver Basic Status Register
+ * @arg PHY_SR : Tranceiver Status Register
+ * @arg More PHY register could be read depending on the used PHY
+ * @retval ETH_ERROR: in case of timeout
+ * MAC MIIDR register value: Data read from the selected PHY register (correct read )
+ */
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)
+{
+ uint32_t tmpreg = 0;
+__IO uint32_t timeout = 0;
+ /* Check the parameters */
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+ assert_param(IS_ETH_PHY_REG(PHYReg));
+
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg = ETH->MACMIIAR;
+ /* Keep only the CSR Clock Range CR[2:0] bits value */
+ tmpreg &= ~MACMIIAR_CR_MASK;
+ /* Prepare the MII address register value */
+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ /* Write the result value into the MII Address register */
+ ETH->MACMIIAR = tmpreg;
+ /* Check for the Busy flag */
+ do
+ {
+ timeout++;
+ tmpreg = ETH->MACMIIAR;
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));
+ /* Return ERROR in case of timeout */
+ if(timeout == PHY_READ_TO)
+ {
+ return (uint16_t)ETH_ERROR;
+ }
+
+ /* Return data register value */
+ return (uint16_t)(ETH->MACMIIDR);
+}
+
+/**
+ * @brief Write to a PHY register
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
+ * This parameter can be one of the following values: 0,..,31
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
+ * This parameter can be one of the following values:
+ * @arg PHY_BCR : Tranceiver Control Register
+ * @arg More PHY register could be written depending on the used PHY
+ * @param PHYValue: the value to write
+ * @retval ETH_ERROR: in case of timeout
+ * ETH_SUCCESS: for correct write
+ */
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)
+{
+ uint32_t tmpreg = 0;
+ __IO uint32_t timeout = 0;
+ /* Check the parameters */
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+ assert_param(IS_ETH_PHY_REG(PHYReg));
+
+ /* Get the ETHERNET MACMIIAR value */
+ tmpreg = ETH->MACMIIAR;
+ /* Keep only the CSR Clock Range CR[2:0] bits value */
+ tmpreg &= ~MACMIIAR_CR_MASK;
+ /* Prepare the MII register address value */
+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ /* Give the value to the MII data register */
+ ETH->MACMIIDR = PHYValue;
+ /* Write the result value into the MII Address register */
+ ETH->MACMIIAR = tmpreg;
+ /* Check for the Busy flag */
+ do
+ {
+ timeout++;
+ tmpreg = ETH->MACMIIAR;
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));
+ /* Return ERROR in case of timeout */
+ if(timeout == PHY_WRITE_TO)
+ {
+ return ETH_ERROR;
+ }
+
+ /* Return SUCCESS */
+ return ETH_SUCCESS;
+}
+
+/**
+ * @brief Enables or disables the PHY loopBack mode.
+ * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal
+ * loopback at MII level
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices.
+ * This parameter can be one of the following values:
+ * @param NewState: new state of the PHY loopBack mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval ETH_ERROR: in case of bad PHY configuration
+ * ETH_SUCCESS: for correct PHY configuration
+ */
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)
+{
+ uint16_t tmpreg = 0;
+ /* Check the parameters */
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ /* Get the PHY configuration to update it */
+ tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR);
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PHY loopback mode */
+ tmpreg |= PHY_Loopback;
+ }
+ else
+ {
+ /* Disable the PHY loopback mode: normal mode */
+ tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);
+ }
+ /* Update the PHY control register with the new configuration */
+ if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)
+ {
+ return ETH_SUCCESS;
+ }
+ else
+ {
+ /* Return SUCCESS */
+ return ETH_ERROR;
+ }
+}
+
+/*--------------------------------- MAC ------------------------------------*/
+/**
+ * @brief Enables or disables the MAC transmission.
+ * @param NewState: new state of the MAC transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MACTransmissionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MAC transmission */
+ ETH->MACCR |= ETH_MACCR_TE;
+ }
+ else
+ {
+ /* Disable the MAC transmission */
+ ETH->MACCR &= ~ETH_MACCR_TE;
+ }
+}
+
+/**
+ * @brief Enables or disables the MAC reception.
+ * @param NewState: new state of the MAC reception.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MACReceptionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MAC reception */
+ ETH->MACCR |= ETH_MACCR_RE;
+ }
+ else
+ {
+ /* Disable the MAC reception */
+ ETH->MACCR &= ~ETH_MACCR_RE;
+ }
+}
+
+/**
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.
+ * @param None
+ * @retval The new state of flow control busy status bit (SET or RESET).
+ */
+FlagStatus ETH_GetFlowControlBusyStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+ /* The Flow Control register should not be written to until this bit is cleared */
+ if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Initiate a Pause Control Frame (Full-duplex only).
+ * @param None
+ * @retval None
+ */
+void ETH_InitiatePauseControlFrame(void)
+{
+ /* When Set In full duplex MAC initiates pause control frame */
+ ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+}
+
+/**
+ * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only).
+ * @param NewState: new state of the MAC BackPressure operation activation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_BackPressureActivationCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Activate the MAC BackPressure operation */
+ /* In Half duplex: during backpressure, when the MAC receives a new frame,
+ the transmitter starts sending a JAM pattern resulting in a collision */
+ ETH->MACFCR |= ETH_MACFCR_FCBBPA;
+ }
+ else
+ {
+ /* Desactivate the MAC BackPressure operation */
+ ETH->MACFCR &= ~ETH_MACFCR_FCBBPA;
+ }
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param ETH_MAC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval The new state of ETHERNET MAC flag (SET or RESET).
+ */
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG));
+ if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not.
+ * @param ETH_MAC_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt
+ * @arg ETH_MAC_IT_MMCR : MMC receive interrupt
+ * @arg ETH_MAC_IT_MMC : MMC interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval The new state of ETHERNET MAC interrupt (SET or RESET).
+ */
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT));
+ if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the specified ETHERNET MAC interrupts.
+ * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @param NewState: new state of the specified ETHERNET MAC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ETHERNET MAC interrupts */
+ ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);
+ }
+ else
+ {
+ /* Disable the selected ETHERNET MAC interrupts */
+ ETH->MACIMR |= ETH_MAC_IT;
+ }
+}
+
+/**
+ * @brief Configures the selected MAC address.
+ * @param MacAddr: The MAC addres to configure.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_Address0 : MAC Address0
+ * @arg ETH_MAC_Address1 : MAC Address1
+ * @arg ETH_MAC_Address2 : MAC Address2
+ * @arg ETH_MAC_Address3 : MAC Address3
+ * @param Addr: Pointer on MAC address buffer data (6 bytes).
+ * @retval None
+ */
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)
+{
+ uint32_t tmpreg;
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+ /* Calculate the selectecd MAC address high register */
+ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+ /* Load the selectecd MAC address high register */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;
+ /* Calculate the selectecd MAC address low register */
+ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+
+ /* Load the selectecd MAC address low register */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;
+}
+
+/**
+ * @brief Get the selected MAC address.
+ * @param MacAddr: The MAC addres to return.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_Address0 : MAC Address0
+ * @arg ETH_MAC_Address1 : MAC Address1
+ * @arg ETH_MAC_Address2 : MAC Address2
+ * @arg ETH_MAC_Address3 : MAC Address3
+ * @param Addr: Pointer on MAC address buffer data (6 bytes).
+ * @retval None
+ */
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)
+{
+ uint32_t tmpreg;
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
+
+ /* Get the selectecd MAC address high register */
+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));
+
+ /* Calculate the selectecd MAC address buffer */
+ Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);
+ Addr[4] = (tmpreg & (uint8_t)0xFF);
+ /* Load the selectecd MAC address low register */
+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));
+ /* Calculate the selectecd MAC address buffer */
+ Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);
+ Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);
+ Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);
+ Addr[0] = (tmpreg & (uint8_t)0xFF);
+}
+
+/**
+ * @brief Enables or disables the Address filter module uses the specified
+ * ETHERNET MAC address for perfect filtering
+ * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_Address1 : MAC Address1
+ * @arg ETH_MAC_Address2 : MAC Address2
+ * @arg ETH_MAC_Address3 : MAC Address3
+ * @param NewState: new state of the specified ETHERNET MAC address use.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ETHERNET MAC address for perfect filtering */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;
+ }
+ else
+ {
+ /* Disable the selected ETHERNET MAC address for perfect filtering */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);
+ }
+}
+
+/**
+ * @brief Set the filter type for the specified ETHERNET MAC address
+ * @param MacAddr: specifies the ETHERNET MAC address
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_Address1 : MAC Address1
+ * @arg ETH_MAC_Address2 : MAC Address2
+ * @arg ETH_MAC_Address3 : MAC Address3
+ * @param Filter: specifies the used frame received field for comparaison
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the
+ * SA fields of the received frame.
+ * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the
+ * DA fields of the received frame.
+ * @retval None
+ */
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+ assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));
+
+ if (Filter != ETH_MAC_AddressFilter_DA)
+ {
+ /* The selected ETHERNET MAC address is used to compare with the SA fields of the
+ received frame. */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;
+ }
+ else
+ {
+ /* The selected ETHERNET MAC address is used to compare with the DA fields of the
+ received frame. */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);
+ }
+}
+
+/**
+ * @brief Set the filter type for the specified ETHERNET MAC address
+ * @param MacAddr: specifies the ETHERNET MAC address
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_Address1 : MAC Address1
+ * @arg ETH_MAC_Address2 : MAC Address2
+ * @arg ETH_MAC_Address3 : MAC Address3
+ * @param MaskByte: specifies the used address bytes for comparaison
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].
+ * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].
+ * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].
+ * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].
+ * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].
+ * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].
+ * @retval None
+ */
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));
+ assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));
+
+ /* Clear MBC bits in the selected MAC address high register */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);
+ /* Set the selected Filetr mask bytes */
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;
+}
+/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/
+
+/**
+ * @brief Initializes the DMA Tx descriptors in chain mode.
+ * @param DMATxDescTab: Pointer on the first Tx desc list
+ * @param TxBuff: Pointer on the first TxBuffer list
+ * @param TxBuffCount: Number of the used Tx desc in the list
+ * @retval None
+ */
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADESCTypeDef *DMATxDesc;
+
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+ DMATxDescToSet = DMATxDescTab;
+ /* Fill each DMATxDesc descriptor with the right values */
+ for(i=0; i < TxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Tx Desc list */
+ DMATxDesc = DMATxDescTab + i;
+ /* Set Second Address Chained bit */
+ DMATxDesc->Status = ETH_DMATxDesc_TCH;
+
+ /* Set Buffer1 address pointer */
+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+ if(i < (TxBuffCount-1))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
+ }
+ }
+
+ /* Set Transmit Desciptor List Address Register */
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;
+}
+
+/**
+ * @brief Initializes the DMA Tx descriptors in ring mode.
+ * @param DMATxDescTab: Pointer on the first Tx desc list
+ * @param TxBuff1: Pointer on the first TxBuffer1 list
+ * @param TxBuff2: Pointer on the first TxBuffer2 list
+ * @param TxBuffCount: Number of the used Tx desc in the list
+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct
+ * for the number of Words to skip between two unchained descriptors.
+ * @retval None
+ */
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADESCTypeDef *DMATxDesc;
+
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+ DMATxDescToSet = DMATxDescTab;
+ /* Fill each DMATxDesc descriptor with the right values */
+ for(i=0; i < TxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Tx Desc list */
+ DMATxDesc = DMATxDescTab + i;
+ /* Set Buffer1 address pointer */
+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Set Buffer2 address pointer */
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base
+ address of the list, creating a Desciptor Ring */
+ if(i == (TxBuffCount-1))
+ {
+ /* Set Transmit End of Ring bit */
+ DMATxDesc->Status = ETH_DMATxDesc_TER;
+ }
+ }
+
+ /* Set Transmit Desciptor List Address Register */
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @param ETH_DMATxDescFlag: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine
+ * @arg ETH_DMATxDesc_IC : Interrupt on completetion
+ * @arg ETH_DMATxDesc_LS : Last Segment
+ * @arg ETH_DMATxDesc_FS : First Segment
+ * @arg ETH_DMATxDesc_DC : Disable CRC
+ * @arg ETH_DMATxDesc_DP : Disable Pad
+ * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable
+ * @arg ETH_DMATxDesc_TER : Transmit End of Ring
+ * @arg ETH_DMATxDesc_TCH : Second Address Chained
+ * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status
+ * @arg ETH_DMATxDesc_IHE : IP Header Error
+ * @arg ETH_DMATxDesc_ES : Error summary
+ * @arg ETH_DMATxDesc_JT : Jabber Timeout
+ * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush
+ * @arg ETH_DMATxDesc_PCE : Payload Checksum Error
+ * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission
+ * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver
+ * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision
+ * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions
+ * @arg ETH_DMATxDesc_VF : VLAN Frame
+ * @arg ETH_DMATxDesc_CC : Collision Count
+ * @arg ETH_DMATxDesc_ED : Excessive Deferral
+ * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory
+ * @arg ETH_DMATxDesc_DB : Deferred Bit
+ * @retval The new state of ETH_DMATxDescFlag (SET or RESET).
+ */
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));
+
+ if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @retval The Transmit descriptor collision counter value.
+ */
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)
+{
+ /* Return the Receive descriptor frame length */
+ return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);
+}
+
+/**
+ * @brief Set the specified DMA Tx Desc Own bit.
+ * @param DMATxDesc: Pointer on a Tx desc
+ * @retval None
+ */
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)
+{
+ /* Set the DMA Tx Desc Own bit */
+ DMATxDesc->Status |= ETH_DMATxDesc_OWN;
+}
+
+/**
+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.
+ * @param DMATxDesc: Pointer on a Tx desc
+ * @param NewState: new state of the DMA Tx Desc transmit interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA Tx Desc Transmit interrupt */
+ DMATxDesc->Status |= ETH_DMATxDesc_IC;
+ }
+ else
+ {
+ /* Disable the DMA Tx Desc Transmit interrupt */
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);
+ }
+}
+
+/**
+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.
+ * @param DMATxDesc: Pointer on a Tx desc
+ * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment
+ * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment
+ * @retval None
+ */
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));
+
+ /* Selects the DMA Tx Desc Frame segment */
+ DMATxDesc->Status |= DMATxDesc_FrameSegment;
+}
+
+/**
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass
+ * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum
+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @retval None
+ */
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));
+
+ /* Set the selected DMA Tx desc checksum insertion control */
+ DMATxDesc->Status |= DMATxDesc_Checksum;
+}
+
+/**
+ * @brief Enables or disables the DMA Tx Desc CRC.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @param NewState: new state of the specified DMA Tx Desc CRC.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Tx Desc CRC */
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);
+ }
+ else
+ {
+ /* Disable the selected DMA Tx Desc CRC */
+ DMATxDesc->Status |= ETH_DMATxDesc_DC;
+ }
+}
+
+/**
+ * @brief Enables or disables the DMA Tx Desc end of ring.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @param NewState: new state of the specified DMA Tx Desc end of ring.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Tx Desc end of ring */
+ DMATxDesc->Status |= ETH_DMATxDesc_TER;
+ }
+ else
+ {
+ /* Disable the selected DMA Tx Desc end of ring */
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER);
+ }
+}
+
+/**
+ * @brief Enables or disables the DMA Tx Desc second address chained.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @param NewState: new state of the specified DMA Tx Desc second address chained.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Tx Desc second address chained */
+ DMATxDesc->Status |= ETH_DMATxDesc_TCH;
+ }
+ else
+ {
+ /* Disable the selected DMA Tx Desc second address chained */
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH);
+ }
+}
+
+/**
+ * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);
+ }
+ else
+ {
+ /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/
+ DMATxDesc->Status |= ETH_DMATxDesc_DP;
+ }
+}
+
+/**
+ * @brief Enables or disables the DMA Tx Desc time stamp.
+ * @param DMATxDesc: pointer on a DMA Tx descriptor
+ * @param NewState: new state of the specified DMA Tx Desc time stamp.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Tx Desc time stamp */
+ DMATxDesc->Status |= ETH_DMATxDesc_TTSE;
+ }
+ else
+ {
+ /* Disable the selected DMA Tx Desc time stamp */
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE);
+ }
+}
+
+/**
+ * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.
+ * @param DMATxDesc: Pointer on a Tx desc
+ * @param BufferSize1: specifies the Tx desc buffer1 size.
+ * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).
+ * @retval None
+ */
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));
+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));
+
+ /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */
+ DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));
+}
+
+/**
+ * @brief Initializes the DMA Rx descriptors in chain mode.
+ * @param DMARxDescTab: Pointer on the first Rx desc list
+ * @param RxBuff: Pointer on the first RxBuffer list
+ * @param RxBuffCount: Number of the used Rx desc in the list
+ * @retval None
+ */
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADESCTypeDef *DMARxDesc;
+
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+ DMARxDescToGet = DMARxDescTab;
+ /* Fill each DMARxDesc descriptor with the right values */
+ for(i=0; i < RxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Rx Desc list */
+ DMARxDesc = DMARxDescTab+i;
+ /* Set Own bit of the Rx descriptor Status */
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+ /* Set Buffer1 size and Second Address Chained bit */
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
+ /* Set Buffer1 address pointer */
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+ if(i < (RxBuffCount-1))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+ }
+ }
+
+ /* Set Receive Desciptor List Address Register */
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab;
+}
+
+/**
+ * @brief Initializes the DMA Rx descriptors in ring mode.
+ * @param DMARxDescTab: Pointer on the first Rx desc list
+ * @param RxBuff1: Pointer on the first RxBuffer1 list
+ * @param RxBuff2: Pointer on the first RxBuffer2 list
+ * @param RxBuffCount: Number of the used Rx desc in the list
+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct
+ * for the number of Words to skip between two unchained descriptors.
+ * @retval None
+ */
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADESCTypeDef *DMARxDesc;
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+ DMARxDescToGet = DMARxDescTab;
+ /* Fill each DMARxDesc descriptor with the right values */
+ for(i=0; i < RxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Rx Desc list */
+ DMARxDesc = DMARxDescTab+i;
+ /* Set Own bit of the Rx descriptor Status */
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;
+ /* Set Buffer1 size */
+ DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE;
+ /* Set Buffer1 address pointer */
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Set Buffer2 address pointer */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base
+ address of the list, creating a Desciptor Ring */
+ if(i == (RxBuffCount-1))
+ {
+ /* Set Receive End of Ring bit */
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+ }
+ }
+
+ /* Set Receive Desciptor List Address Register */
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab;
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not.
+ * @param DMARxDesc: pointer on a DMA Rx descriptor
+ * @param ETH_DMARxDescFlag: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine
+ * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame
+ * @arg ETH_DMARxDesc_ES: Error summary
+ * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame
+ * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame
+ * @arg ETH_DMARxDesc_LE: Frame size not matching with length field
+ * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow
+ * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame
+ * @arg ETH_DMARxDesc_FS: First descriptor of the frame
+ * @arg ETH_DMARxDesc_LS: Last descriptor of the frame
+ * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error
+ * @arg ETH_DMARxDesc_LC: Late collision occurred during reception
+ * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3
+ * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception
+ * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface
+ * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits
+ * @arg ETH_DMARxDesc_CE: CRC error
+ * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error
+ * @retval The new state of ETH_DMARxDescFlag (SET or RESET).
+ */
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));
+ if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Set the specified DMA Rx Desc Own bit.
+ * @param DMARxDesc: Pointer on a Rx desc
+ * @retval None
+ */
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)
+{
+ /* Set the DMA Rx Desc Own bit */
+ DMARxDesc->Status |= ETH_DMARxDesc_OWN;
+}
+
+/**
+ * @brief Returns the specified DMA Rx Desc frame length.
+ * @param DMARxDesc: pointer on a DMA Rx descriptor
+ * @retval The Rx descriptor received frame length.
+ */
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)
+{
+ /* Return the Receive descriptor frame length */
+ return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);
+}
+
+/**
+ * @brief Enables or disables the specified DMA Rx Desc receive interrupt.
+ * @param DMARxDesc: Pointer on a Rx desc
+ * @param NewState: new state of the specified DMA Rx Desc interrupt.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA Rx Desc receive interrupt */
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);
+ }
+ else
+ {
+ /* Disable the DMA Rx Desc receive interrupt */
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;
+ }
+}
+
+/**
+ * @brief Enables or disables the DMA Rx Desc end of ring.
+ * @param DMARxDesc: pointer on a DMA Rx descriptor
+ * @param NewState: new state of the specified DMA Rx Desc end of ring.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Rx Desc end of ring */
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;
+ }
+ else
+ {
+ /* Disable the selected DMA Rx Desc end of ring */
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER);
+ }
+}
+
+/**
+ * @brief Enables or disables the DMA Rx Desc second address chained.
+ * @param DMARxDesc: pointer on a DMA Rx descriptor
+ * @param NewState: new state of the specified DMA Rx Desc second address chained.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA Rx Desc second address chained */
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH;
+ }
+ else
+ {
+ /* Disable the selected DMA Rx Desc second address chained */
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH);
+ }
+}
+
+/**
+ * @brief Returns the specified ETHERNET DMA Rx Desc buffer size.
+ * @param DMARxDesc: pointer on a DMA Rx descriptor
+ * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.
+ * This parameter can be any one of the following values:
+ * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1
+ * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2
+ * @retval The Receive descriptor frame length.
+ */
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));
+
+ if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)
+ {
+ /* Return the DMA Rx Desc buffer2 size */
+ return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT);
+ }
+ else
+ {
+ /* Return the DMA Rx Desc buffer1 size */
+ return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1);
+ }
+}
+
+/*--------------------------------- DMA ------------------------------------*/
+/**
+ * @brief Resets all MAC subsystem internal registers and logic.
+ * @param None
+ * @retval None
+ */
+void ETH_SoftwareReset(void)
+{
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+ /* After reset all the registers holds their respective reset values */
+ ETH->DMABMR |= ETH_DMABMR_SR;
+}
+
+/**
+ * @brief Checks whether the ETHERNET software reset bit is set or not.
+ * @param None
+ * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).
+ */
+FlagStatus ETH_GetSoftwareResetStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+ if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+ * @param ETH_DMA_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag
+ * @arg ETH_DMA_FLAG_PMT : PMT flag
+ * @arg ETH_DMA_FLAG_MMC : MMC flag
+ * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access
+ * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr
+ * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA
+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
+ * @arg ETH_DMA_FLAG_ER : Early receive flag
+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
+ * @arg ETH_DMA_FLAG_ET : Early transmit flag
+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
+ * @arg ETH_DMA_FLAG_R : Receive flag
+ * @arg ETH_DMA_FLAG_TU : Underflow flag
+ * @arg ETH_DMA_FLAG_RO : Overflow flag
+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
+ * @arg ETH_DMA_FLAG_T : Transmit flag
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));
+ if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ETHERNET抯 DMA pending flag.
+ * @param ETH_DMA_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag
+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag
+ * @arg ETH_DMA_FLAG_ER : Early receive flag
+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag
+ * @arg ETH_DMA_FLAG_ETI : Early transmit flag
+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag
+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag
+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag
+ * @arg ETH_DMA_FLAG_R : Receive flag
+ * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag
+ * @arg ETH_DMA_FLAG_RO : Receive Overflow flag
+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag
+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag
+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag
+ * @arg ETH_DMA_FLAG_T : Transmit flag
+ * @retval None
+ */
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));
+
+ /* Clear the selected ETHERNET DMA FLAG */
+ ETH->DMASR = (uint32_t) ETH_DMA_FLAG;
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not.
+ * @param ETH_DMA_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt
+ * @arg ETH_DMA_IT_PMT : PMT interrupt
+ * @arg ETH_DMA_IT_MMC : MMC interrupt
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
+ * @arg ETH_DMA_IT_ER : Early receive interrupt
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
+ * @arg ETH_DMA_IT_ET : Early transmit interrupt
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+ * @arg ETH_DMA_IT_R : Receive interrupt
+ * @arg ETH_DMA_IT_TU : Underflow interrupt
+ * @arg ETH_DMA_IT_RO : Overflow interrupt
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
+ * @arg ETH_DMA_IT_T : Transmit interrupt
+ * @retval The new state of ETH_DMA_IT (SET or RESET).
+ */
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));
+ if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the ETHERNET抯 DMA IT pending bit.
+ * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
+ * @arg ETH_DMA_IT_ER : Early receive interrupt
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
+ * @arg ETH_DMA_IT_ETI : Early transmit interrupt
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+ * @arg ETH_DMA_IT_R : Receive interrupt
+ * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt
+ * @arg ETH_DMA_IT_RO : Receive Overflow interrupt
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
+ * @arg ETH_DMA_IT_T : Transmit interrupt
+ * @retval None
+ */
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+
+ /* Clear the selected ETHERNET DMA IT */
+ ETH->DMASR = (uint32_t) ETH_DMA_IT;
+}
+
+/**
+ * @brief Returns the ETHERNET DMA Transmit Process State.
+ * @param None
+ * @retval The new ETHERNET DMA Transmit Process State:
+ * This can be one of the following values:
+ * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued
+ * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor
+ * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status
+ * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory
+ * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe
+ * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor
+ */
+uint32_t ETH_GetTransmitProcessState(void)
+{
+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS));
+}
+
+/**
+ * @brief Returns the ETHERNET DMA Receive Process State.
+ * @param None
+ * @retval The new ETHERNET DMA Receive Process State:
+ * This can be one of the following values:
+ * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued
+ * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor
+ * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet
+ * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable
+ * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor
+ * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory
+ */
+uint32_t ETH_GetReceiveProcessState(void)
+{
+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS));
+}
+
+/**
+ * @brief Clears the ETHERNET transmit FIFO.
+ * @param None
+ * @retval None
+ */
+void ETH_FlushTransmitFIFO(void)
+{
+ /* Set the Flush Transmit FIFO bit */
+ ETH->DMAOMR |= ETH_DMAOMR_FTF;
+}
+
+/**
+ * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not.
+ * @param None
+ * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).
+ */
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)
+{
+ FlagStatus bitstatus = RESET;
+ if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the DMA transmission.
+ * @param NewState: new state of the DMA transmission.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMATransmissionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA transmission */
+ ETH->DMAOMR |= ETH_DMAOMR_ST;
+ }
+ else
+ {
+ /* Disable the DMA transmission */
+ ETH->DMAOMR &= ~ETH_DMAOMR_ST;
+ }
+}
+
+/**
+ * @brief Enables or disables the DMA reception.
+ * @param NewState: new state of the DMA reception.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMAReceptionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the DMA reception */
+ ETH->DMAOMR |= ETH_DMAOMR_SR;
+ }
+ else
+ {
+ /* Disable the DMA reception */
+ ETH->DMAOMR &= ~ETH_DMAOMR_SR;
+ }
+}
+
+/**
+ * @brief Enables or disables the specified ETHERNET DMA interrupts.
+ * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary
+ * @arg ETH_DMA_IT_ER : Early receive interrupt
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt
+ * @arg ETH_DMA_IT_ET : Early transmit interrupt
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt
+ * @arg ETH_DMA_IT_R : Receive interrupt
+ * @arg ETH_DMA_IT_TU : Underflow interrupt
+ * @arg ETH_DMA_IT_RO : Overflow interrupt
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt
+ * @arg ETH_DMA_IT_T : Transmit interrupt
+ * @param NewState: new state of the specified ETHERNET DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ETHERNET DMA interrupts */
+ ETH->DMAIER |= ETH_DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected ETHERNET DMA interrupts */
+ ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);
+ }
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
+ * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter
+ * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter
+ * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).
+ */
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));
+
+ if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.
+ * @param None
+ * @retval The value of Rx overflow Missed Frame Counter.
+ */
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)
+{
+ return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));
+}
+
+/**
+ * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.
+ * @param None
+ * @retval The value of Buffer unavailable Missed Frame Counter.
+ */
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)
+{
+ return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);
+}
+
+/**
+ * @brief Get the ETHERNET DMA DMACHTDR register value.
+ * @param None
+ * @retval The value of the current Tx desc start address.
+ */
+uint32_t ETH_GetCurrentTxDescStartAddress(void)
+{
+ return ((uint32_t)(ETH->DMACHTDR));
+}
+
+/**
+ * @brief Get the ETHERNET DMA DMACHRDR register value.
+ * @param None
+ * @retval The value of the current Rx desc start address.
+ */
+uint32_t ETH_GetCurrentRxDescStartAddress(void)
+{
+ return ((uint32_t)(ETH->DMACHRDR));
+}
+
+/**
+ * @brief Get the ETHERNET DMA DMACHTBAR register value.
+ * @param None
+ * @retval The value of the current Tx buffer address.
+ */
+uint32_t ETH_GetCurrentTxBufferAddress(void)
+{
+ return ((uint32_t)(ETH->DMACHTBAR));
+}
+
+/**
+ * @brief Get the ETHERNET DMA DMACHRBAR register value.
+ * @param None
+ * @retval The value of the current Rx buffer address.
+ */
+uint32_t ETH_GetCurrentRxBufferAddress(void)
+{
+ return ((uint32_t)(ETH->DMACHRBAR));
+}
+
+/**
+ * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register
+ * (the data written could be anything). This forces the DMA to resume transmission.
+ * @param None
+ * @retval None.
+ */
+void ETH_ResumeDMATransmission(void)
+{
+ ETH->DMATPDR = 0;
+}
+
+/**
+ * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register
+ * (the data written could be anything). This forces the DMA to resume reception.
+ * @param None
+ * @retval None.
+ */
+void ETH_ResumeDMAReception(void)
+{
+ ETH->DMARPDR = 0;
+}
+
+/*--------------------------------- PMT ------------------------------------*/
+/**
+ * @brief Reset Wakeup frame filter register pointer.
+ * @param None
+ * @retval None
+ */
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)
+{
+ /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR;
+}
+
+/**
+ * @brief Populates the remote wakeup frame registers.
+ * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).
+ * @retval None
+ */
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)
+{
+ uint32_t i = 0;
+
+ /* Fill Remote Wake-up Frame Filter register with Buffer data */
+ for(i =0; iMACRWUFFR = Buffer[i];
+ }
+}
+
+/**
+ * @brief Enables or disables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param NewState: new state of the MAC Global Unicast Wake-Up.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MAC Global Unicast Wake-Up */
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_GU;
+ }
+ else
+ {
+ /* Disable the MAC Global Unicast Wake-Up */
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;
+ }
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.
+ * @param ETH_PMT_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+ */
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));
+
+ if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the MAC Wake-Up Frame Detection.
+ * @param NewState: new state of the MAC Wake-Up Frame Detection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MAC Wake-Up Frame Detection */
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE;
+ }
+ else
+ {
+ /* Disable the MAC Wake-Up Frame Detection */
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;
+ }
+}
+
+/**
+ * @brief Enables or disables the MAC Magic Packet Detection.
+ * @param NewState: new state of the MAC Magic Packet Detection.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MAC Magic Packet Detection */
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE;
+ }
+ else
+ {
+ /* Disable the MAC Magic Packet Detection */
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;
+ }
+}
+
+/**
+ * @brief Enables or disables the MAC Power Down.
+ * @param NewState: new state of the MAC Power Down.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_PowerDownCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MAC Power Down */
+ /* This puts the MAC in power down mode */
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_PD;
+ }
+ else
+ {
+ /* Disable the MAC Power Down */
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;
+ }
+}
+
+/*--------------------------------- MMC ------------------------------------*/
+/**
+ * @brief Enables or disables the MMC Counter Freeze.
+ * @param NewState: new state of the MMC Counter Freeze.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MMC Counter Freeze */
+ ETH->MMCCR |= ETH_MMCCR_MCF;
+ }
+ else
+ {
+ /* Disable the MMC Counter Freeze */
+ ETH->MMCCR &= ~ETH_MMCCR_MCF;
+ }
+}
+
+/**
+ * @brief Enables or disables the MMC Reset On Read.
+ * @param NewState: new state of the MMC Reset On Read.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the MMC Counter reset on read */
+ ETH->MMCCR |= ETH_MMCCR_ROR;
+ }
+ else
+ {
+ /* Disable the MMC Counter reset on read */
+ ETH->MMCCR &= ~ETH_MMCCR_ROR;
+ }
+}
+
+/**
+ * @brief Enables or disables the MMC Counter Stop Rollover.
+ * @param NewState: new state of the MMC Counter Stop Rollover.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Disable the MMC Counter Stop Rollover */
+ ETH->MMCCR &= ~ETH_MMCCR_CSR;
+ }
+ else
+ {
+ /* Enable the MMC Counter Stop Rollover */
+ ETH->MMCCR |= ETH_MMCCR_CSR;
+ }
+}
+
+/**
+ * @brief Resets the MMC Counters.
+ * @param None
+ * @retval None
+ */
+void ETH_MMCCountersReset(void)
+{
+ /* Resets the MMC Counters */
+ ETH->MMCCR |= ETH_MMCCR_CR;
+}
+
+/**
+ * @brief Enables or disables the specified ETHERNET MMC interrupts.
+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of Tx interrupt or
+ * any combination of Rx interrupt (but not both)of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @param NewState: new state of the specified ETHERNET MMC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_MMC_IT(ETH_MMC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+ {
+ /* Remove egister mak from IT */
+ ETH_MMC_IT &= 0xEFFFFFFF;
+
+ /* ETHERNET MMC Rx interrupts selected */
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ETHERNET MMC interrupts */
+ ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);
+ }
+ else
+ {
+ /* Disable the selected ETHERNET MMC interrupts */
+ ETH->MMCRIMR |= ETH_MMC_IT;
+ }
+ }
+ else
+ {
+ /* ETHERNET MMC Tx interrupts selected */
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected ETHERNET MMC interrupts */
+ ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);
+ }
+ else
+ {
+ /* Disable the selected ETHERNET MMC interrupts */
+ ETH->MMCTIMR |= ETH_MMC_IT;
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET MMC IT is set or not.
+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value
+ * @retval The value of ETHERNET MMC IT (SET or RESET).
+ */
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)
+{
+ ITStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT));
+
+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)
+ {
+ /* ETHERNET MMC Rx interrupts selected */
+ /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */
+ if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ /* ETHERNET MMC Tx interrupts selected */
+ /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */
+ if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Get the specified ETHERNET MMC register value.
+ * @param ETH_MMCReg: specifies the ETHERNET MMC register.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMCCR : MMC CR register
+ * @arg ETH_MMCRIR : MMC RIR register
+ * @arg ETH_MMCTIR : MMC TIR register
+ * @arg ETH_MMCRIMR : MMC RIMR register
+ * @arg ETH_MMCTIMR : MMC TIMR register
+ * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register
+ * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register
+ * @arg ETH_MMCTGFCR : MMC TGFCR register
+ * @arg ETH_MMCRFCECR : MMC RFCECR register
+ * @arg ETH_MMCRFAECR : MMC RFAECR register
+ * @arg ETH_MMCRGUFCR : MMC RGUFCRregister
+ * @retval The value of ETHERNET MMC Register value.
+ */
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));
+
+ /* Return the selected register value */
+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));
+}
+/*--------------------------------- PTP ------------------------------------*/
+
+/**
+ * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value.
+ * @param None
+ * @retval None
+ */
+void ETH_EnablePTPTimeStampAddend(void)
+{
+ /* Enable the PTP block update with the Time Stamp Addend register value */
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSARU;
+}
+
+/**
+ * @brief Enable the PTP Time Stamp interrupt trigger
+ * @param None
+ * @retval None
+ */
+void ETH_EnablePTPTimeStampInterruptTrigger(void)
+{
+ /* Enable the PTP target time interrupt */
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSITE;
+}
+
+/**
+ * @brief Updated the PTP system time with the Time Stamp Update register value.
+ * @param None
+ * @retval None
+ */
+void ETH_EnablePTPTimeStampUpdate(void)
+{
+ /* Enable the PTP system time update with the Time Stamp Update register value */
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU;
+}
+
+/**
+ * @brief Initialize the PTP Time Stamp
+ * @param None
+ * @retval None
+ */
+void ETH_InitializePTPTimeStamp(void)
+{
+ /* Initialize the PTP Time Stamp */
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI;
+}
+
+/**
+ * @brief Selects the PTP Update method
+ * @param UpdateMethod: the PTP Update method
+ * This parameter can be one of the following values:
+ * @arg ETH_PTP_FineUpdate : Fine Update method
+ * @arg ETH_PTP_CoarseUpdate : Coarse Update method
+ * @retval None
+ */
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));
+
+ if (UpdateMethod != ETH_PTP_CoarseUpdate)
+ {
+ /* Enable the PTP Fine Update method */
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;
+ }
+ else
+ {
+ /* Disable the PTP Coarse Update method */
+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);
+ }
+}
+
+/**
+ * @brief Enables or disables the PTP time stamp for transmit and receive frames.
+ * @param NewState: new state of the PTP time stamp for transmit and receive frames
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void ETH_PTPTimeStampCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PTP time stamp for transmit and receive frames */
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSE;
+ }
+ else
+ {
+ /* Disable the PTP time stamp for transmit and receive frames */
+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);
+ }
+}
+
+/**
+ * @brief Checks whether the specified ETHERNET PTP flag is set or not.
+ * @param ETH_PTP_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_PTP_FLAG_TSARU : Addend Register Update
+ * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable
+ * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update
+ * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize
+ * @retval The new state of ETHERNET PTP Flag (SET or RESET).
+ */
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));
+
+ if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Sets the system time Sub-Second Increment value.
+ * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value.
+ * @retval None
+ */
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));
+ /* Set the PTP Sub-Second Increment Register */
+ ETH->PTPSSIR = SubSecondValue;
+}
+
+/**
+ * @brief Sets the Time Stamp update sign and values.
+ * @param Sign: specifies the PTP Time update value sign.
+ * This parameter can be one of the following values:
+ * @arg ETH_PTP_PositiveTime : positive time value.
+ * @arg ETH_PTP_NegativeTime : negative time value.
+ * @param SecondValue: specifies the PTP Time update second value.
+ * @param SubSecondValue: specifies the PTP Time update sub-second value.
+ * This parameter is a 31 bit value, bit32 correspond to the sign.
+ * @retval None
+ */
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_PTP_TIME_SIGN(Sign));
+ assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue));
+ /* Set the PTP Time Update High Register */
+ ETH->PTPTSHUR = SecondValue;
+
+ /* Set the PTP Time Update Low Register with sign */
+ ETH->PTPTSLUR = Sign | SubSecondValue;
+}
+
+/**
+ * @brief Sets the Time Stamp Addend value.
+ * @param Value: specifies the PTP Time Stamp Addend Register value.
+ * @retval None
+ */
+void ETH_SetPTPTimeStampAddend(uint32_t Value)
+{
+ /* Set the PTP Time Stamp Addend Register */
+ ETH->PTPTSAR = Value;
+}
+
+/**
+ * @brief Sets the Target Time registers values.
+ * @param HighValue: specifies the PTP Target Time High Register value.
+ * @param LowValue: specifies the PTP Target Time Low Register value.
+ * @retval None
+ */
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)
+{
+ /* Set the PTP Target Time High Register */
+ ETH->PTPTTHR = HighValue;
+ /* Set the PTP Target Time Low Register */
+ ETH->PTPTTLR = LowValue;
+}
+
+/**
+ * @brief Get the specified ETHERNET PTP register value.
+ * @param ETH_PTPReg: specifies the ETHERNET PTP register.
+ * This parameter can be one of the following values:
+ * @arg ETH_PTPTSCR : Sub-Second Increment Register
+ * @arg ETH_PTPSSIR : Sub-Second Increment Register
+ * @arg ETH_PTPTSHR : Time Stamp High Register
+ * @arg ETH_PTPTSLR : Time Stamp Low Register
+ * @arg ETH_PTPTSHUR : Time Stamp High Update Register
+ * @arg ETH_PTPTSLUR : Time Stamp Low Update Register
+ * @arg ETH_PTPTSAR : Time Stamp Addend Register
+ * @arg ETH_PTPTTHR : Target Time High Register
+ * @arg ETH_PTPTTLR : Target Time Low Register
+ * @retval The value of ETHERNET PTP Register value.
+ */
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)
+{
+ /* Check the parameters */
+ assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));
+
+ /* Return the selected register value */
+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));
+}
+
+/**
+ * @brief Initializes the DMA Tx descriptors in chain mode with PTP.
+ * @param DMATxDescTab: Pointer on the first Tx desc list
+ * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list
+ * @param TxBuff: Pointer on the first TxBuffer list
+ * @param TxBuffCount: Number of the used Tx desc in the list
+ * @retval None
+ */
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,
+ uint8_t* TxBuff, uint32_t TxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADESCTypeDef *DMATxDesc;
+
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
+ DMATxDescToSet = DMATxDescTab;
+ DMAPTPTxDescToSet = DMAPTPTxDescTab;
+ /* Fill each DMATxDesc descriptor with the right values */
+ for(i=0; i < TxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Tx Desc list */
+ DMATxDesc = DMATxDescTab+i;
+ /* Set Second Address Chained bit and enable PTP */
+ DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE;
+
+ /* Set Buffer1 address pointer */
+ DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+ if(i < (TxBuffCount-1))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
+ }
+ /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */
+ (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;
+ (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;
+ }
+ /* Store on the last DMAPTPTxDescTab desc status record the first list address */
+ (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;
+
+ /* Set Transmit Desciptor List Address Register */
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;
+}
+
+/**
+ * @brief Initializes the DMA Rx descriptors in chain mode.
+ * @param DMARxDescTab: Pointer on the first Rx desc list
+ * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list
+ * @param RxBuff: Pointer on the first RxBuffer list
+ * @param RxBuffCount: Number of the used Rx desc in the list
+ * @retval None
+ */
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,
+ uint8_t *RxBuff, uint32_t RxBuffCount)
+{
+ uint32_t i = 0;
+ ETH_DMADESCTypeDef *DMARxDesc;
+
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */
+ DMARxDescToGet = DMARxDescTab;
+ DMAPTPRxDescToGet = DMAPTPRxDescTab;
+ /* Fill each DMARxDesc descriptor with the right values */
+ for(i=0; i < RxBuffCount; i++)
+ {
+ /* Get the pointer on the ith member of the Rx Desc list */
+ DMARxDesc = DMARxDescTab+i;
+ /* Set Own bit of the Rx descriptor Status */
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;
+
+ /* Set Buffer1 size and Second Address Chained bit */
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE;
+ /* Set Buffer1 address pointer */
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);
+
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */
+ if(i < (RxBuffCount-1))
+ {
+ /* Set next descriptor address register with next descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
+ }
+ else
+ {
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
+ }
+ /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */
+ (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;
+ (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;
+ }
+ /* Store on the last DMAPTPRxDescTab desc status record the first list address */
+ (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;
+
+ /* Set Receive Desciptor List Address Register */
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab;
+}
+
+/**
+ * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values.
+ * @param ppkt: pointer to application packet buffer to transmit.
+ * @param FrameLength: Tx Packet size.
+ * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.
+ * @retval ETH_ERROR: in case of Tx desc owned by DMA
+ * ETH_SUCCESS: for correct transmission
+ */
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)
+{
+ uint32_t offset = 0, timeout = 0;
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
+ {
+ /* Return ERROR: OWN bit set */
+ return ETH_ERROR;
+ }
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
+ for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset));
+ }
+ /* Setting the Frame Length: bits[12:0] */
+ DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);
+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
+ {
+ /* Clear TBUS ETHERNET DMA flag */
+ ETH->DMASR = ETH_DMASR_TBUS;
+ /* Resume DMA transmission*/
+ ETH->DMATPDR = 0;
+ }
+ /* Wait for ETH_DMATxDesc_TTSS flag to be set */
+ do
+ {
+ timeout++;
+ } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));
+ /* Return ERROR in case of timeout */
+ if(timeout == PHY_READ_TO)
+ {
+ return ETH_ERROR;
+ }
+ /* Clear the DMATxDescToSet status register TTSS flag */
+ DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;
+ *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;
+ *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;
+ /* Update the ENET DMA current descriptor */
+ /* Chained Mode */
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)
+ {
+ /* Selects the next DMA Tx descriptor list for next buffer read */
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);
+ if(DMAPTPTxDescToSet->Status != 0)
+ {
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);
+ }
+ else
+ {
+ DMAPTPTxDescToSet++;
+ }
+ }
+ else /* Ring Mode */
+ {
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)
+ {
+ /* Selects the next DMA Tx descriptor list for next buffer read: this will
+ be the first Tx descriptor in this case */
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);
+ }
+ else
+ {
+ /* Selects the next DMA Tx descriptor list for next buffer read */
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+ }
+ }
+ /* Return SUCCESS */
+ return ETH_SUCCESS;
+}
+
+/**
+ * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values.
+ * @param ppkt: pointer to application packet receive buffer.
+ * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.
+ * @retval ETH_ERROR: if there is error in reception
+ * framelength: received packet size if packet reception is correct
+ */
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
+{
+ uint32_t offset = 0, framelength = 0;
+ /* Check if the descriptor is owned by the ENET or CPU */
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)
+ {
+ /* Return error: OWN bit set */
+ return ETH_ERROR;
+ }
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+ {
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
+ for(offset=0; offsetBuffer1Addr) + offset));
+ }
+ }
+ else
+ {
+ /* Return ERROR */
+ framelength = ETH_ERROR;
+ }
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */
+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
+ {
+ /* Clear RBUS ETHERNET DMA flag */
+ ETH->DMASR = ETH_DMASR_RBUS;
+ /* Resume DMA reception */
+ ETH->DMARPDR = 0;
+ }
+ *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;
+ *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
+ DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
+ /* Chained Mode */
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)
+ {
+ /* Selects the next DMA Rx descriptor list for next buffer read */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);
+ if(DMAPTPRxDescToGet->Status != 0)
+ {
+ DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);
+ }
+ else
+ {
+ DMAPTPRxDescToGet++;
+ }
+ }
+ else /* Ring Mode */
+ {
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)
+ {
+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);
+ }
+ else
+ {
+ /* Selects the next DMA Rx descriptor list for next buffer to read */
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));
+ }
+ }
+ /* Return Frame Length/ERROR */
+ return (framelength);
+}
+
+#ifndef USE_Delay
+/**
+ * @brief Inserts a delay time.
+ * @param nCount: specifies the delay time length.
+ * @retval None
+ */
+static void ETH_Delay(__IO uint32_t nCount)
+{
+ __IO uint32_t index = 0;
+ for(index = nCount; index != 0; index--)
+ {
+ }
+}
+#endif /* USE_Delay*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Project/RVMDK/EventRecorderStub.scvd b/F107/Project/RVMDK/EventRecorderStub.scvd
new file mode 100644
index 0000000..2956b29
--- /dev/null
+++ b/F107/Project/RVMDK/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+
+
+
+
+
+
+
+
+
diff --git a/F107/Project/RVMDK/JLink Regs CM3.txt b/F107/Project/RVMDK/JLink Regs CM3.txt
new file mode 100644
index 0000000..08327ff
--- /dev/null
+++ b/F107/Project/RVMDK/JLink Regs CM3.txt
@@ -0,0 +1,32 @@
+0: R0: 0x00
+1: R1: 0x01
+2: R2: 0x02
+3: R3: 0x03
+4: R4: 0x04
+5: R5: 0x05
+6: R6: 0x06
+7: R7: 0x07
+8: R8: 0x08
+9: R9: 0x09
+10: R10: 0x0a
+11: R11: 0x0b
+12: R12: 0x0c
+13: R13: 0x0d
+14: R14: 0x0e
+15: R15: 0x0f
+16: XPSR: 0x10
+17: MSP: 0x11
+18: PSP: 0x12
+19: RAZ: 0x13
+20: CFBP: 0x14
+21: APSR: 0x15
+22: EPSR: 0x16
+23: IPSR: 0x17
+24: PRIMASK: 0x18
+25: BASEPRI: 0x19
+26: FAULTMASK: 0x1a
+27: CONTROL: 0x1b
+28: BASEPRI_MAX: 0x1c
+29: IAPSR: 0x1d
+30: EAPSR: 0x1e
+31: IEPSR: 0x1f
diff --git a/F107/Project/RVMDK/JLinkLog.txt b/F107/Project/RVMDK/JLinkLog.txt
new file mode 100644
index 0000000..2984b91
--- /dev/null
+++ b/F107/Project/RVMDK/JLinkLog.txt
@@ -0,0 +1,2526 @@
+
+T01AC 000:002 SEGGER J-Link V6.30h Log File (0020ms, 0022ms total)
+T01AC 000:002 DLL Compiled: Mar 16 2018 18:02:51 (0020ms, 0022ms total)
+T01AC 000:002 Logging started @ 2019-05-15 17:08 (0020ms, 0022ms total)
+T01AC 000:022 JLINK_SetWarnOutHandler(...) (0000ms, 0022ms total)
+T01AC 000:022 JLINK_OpenEx(...)
+Firmware: J-Link V9 compiled Mar 2 2018 17:07:57
+Hardware: V9.40
+S/N: 59400616
+Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
+TELNET listener socket opened on port 19021WEBSRV
+Starting webserver (0014ms, 0036ms total)
+T01AC 000:022 WEBSRV Webserver running on local port 19080 (0014ms, 0036ms total)
+T01AC 000:022 returns O.K. (0014ms, 0036ms total)
+T01AC 000:036 JLINK_GetEmuCaps() returns 0xB9FF7BBF (0000ms, 0036ms total)
+T01AC 000:036 JLINK_TIF_GetAvailable(...) (0000ms, 0036ms total)
+T01AC 000:036 JLINK_SetErrorOutHandler(...) (0000ms, 0036ms total)
+T01AC 000:036 JLINK_ExecCommand("ProjectFile = "D:\项目\Compile\基于IOT的无人快递站点\Two\F107\Project\RVMDK\JLinkSettings.ini"", ...). returns 0x00 (0088ms, 0124ms total)
+T01AC 000:125 JLINK_ExecCommand("Device = STM32F107VC", ...). Device "STM32F107VC" selected. returns 0x00 (0002ms, 0126ms total)
+T01AC 000:127 JLINK_ExecCommand("DisableConnectionTimeout", ...). returns 0x01 (0000ms, 0126ms total)
+T01AC 000:127 JLINK_GetHardwareVersion() returns 0x16F30 (0000ms, 0126ms total)
+T01AC 000:127 JLINK_GetDLLVersion() returns 63008 (0000ms, 0126ms total)
+T01AC 000:127 JLINK_GetFirmwareString(...) (0000ms, 0126ms total)
+T01AC 000:133 JLINK_GetDLLVersion() returns 63008 (0000ms, 0126ms total)
+T01AC 000:133 JLINK_GetCompileDateTime() (0000ms, 0126ms total)
+T01AC 000:134 JLINK_GetFirmwareString(...) (0000ms, 0126ms total)
+T01AC 000:136 JLINK_GetHardwareVersion() returns 0x16F30 (0000ms, 0126ms total)
+T01AC 000:142 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0000ms, 0126ms total)
+T01AC 000:142 JLINK_SetSpeed(5000) (0000ms, 0126ms total)
+T01AC 000:142 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x50 JTAG>JTAG chain detection found 2 devices: #0 Id: 0x3BA00477, IRLen: 04, CoreSight JTAG-DP #1 Id: 0x06418041, IRLen: 05, STM32 Boundary Scan >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG>
+ >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x50 JTAG>JTAG chain detection found 2 devices: #0 Id: 0x3BA00477, IRLen: 04, CoreSight JTAG-DP #1 Id: 0x06418041, IRLen: 05, STM32 Boundary ScanScanning AP map to find all available APs >0x80 JTAG> >0x50 JTAG> >0x40 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG>AP[1]: Stopped AP scan as end of AP map has been reachedAP[0]: AHB-AP (IDR: 0x14770011)
+Iterating through AP map to find AHB-AP to use >0x80 JTAG> >0x50 JTAG> >0x50 JTAG> >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG>AP[0]: Core foundAP[0]: AHB-AP ROM base: 0xE00FF000 >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG>CPUID register: 0x411FC231. Implementer code: 0x41 (ARM)Found Cortex-M3 r1p1, Little endian. -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots
+ -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl[0] @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)
+ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 001BB000 SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 001BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 001BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010)
+ -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl[0][4]: E0040000, CID: B105900D, PID: 001BB923 TPIU-Lite -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl[0][5]: E0041000, CID: B105900D, PID: 101BB924 ETM-M3 ScanLen=9 NumDevices=2 aId[0]=0x3BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0059ms, 0185ms total)
+T01AC 000:201 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x3BA00477 (0000ms, 0185ms total)
+T01AC 000:201 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0185ms total)
+T01AC 000:201 JLINK_JTAG_GetDeviceID(DeviceIndex = 1) returns 0x6418041 (0000ms, 0185ms total)
+T01AC 000:201 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 1) returns 0x00 (0000ms, 0185ms total)
+T01AC 000:201 JLINK_GetDLLVersion() returns 63008 (0000ms, 0185ms total)
+T01AC 000:201 JLINK_CORE_GetFound() returns 0x30000FF (0000ms, 0185ms total)
+T01AC 000:201 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 0185ms total)
+T01AC 000:202 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 0185ms total)
+T01AC 000:202 JLINK_GetDebugInfo(0x101 = JLINKARM_DEBUG_INFO_ETM_ADDR_INDEX) -- Value=0xE0041000 returns 0x00 (0000ms, 0185ms total)
+T01AC 000:202 JLINK_ReadMemEx(0xE0041FD0, 0x0020 Bytes, ..., Flags = 0x02000004) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x20 (0001ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x102 = JLINKARM_DEBUG_INFO_MTB_ADDR_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x103 = JLINKARM_DEBUG_INFO_TPIU_ADDR_INDEX) -- Value=0xE0040000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x104 = JLINKARM_DEBUG_INFO_ITM_ADDR_INDEX) -- Value=0xE0000000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x105 = JLINKARM_DEBUG_INFO_DWT_ADDR_INDEX) -- Value=0xE0001000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x106 = JLINKARM_DEBUG_INFO_FPB_ADDR_INDEX) -- Value=0xE0002000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x107 = JLINKARM_DEBUG_INFO_NVIC_ADDR_INDEX) -- Value=0xE000E000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x10C = JLINKARM_DEBUG_INFO_DBG_ADDR_INDEX) -- Value=0xE000EDF0 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x01 = Unknown) -- Value=0x00000000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41 returns 0x01 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_GetDebugInfo(0x10F = JLINKARM_DEBUG_INFO_HAS_CORTEX_M_SECURITY_EXT_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 0186ms total)
+T01AC 000:203 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) returns JLINKARM_CM3_RESET_TYPE_NORMAL (0000ms, 0186ms total)
+T01AC 000:203 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET.Reset: Reset device via AIRCR.SYSRESETREQ. -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)
+ -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0068ms, 0254ms total)
+T01AC 000:271 JLINK_Halt() returns 0x00 (0001ms, 0255ms total)
+T01AC 000:272 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0000ms, 0255ms total)
+T01AC 000:272 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0000ms, 0255ms total)
+T01AC 000:272 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0000ms, 0255ms total)
+T01AC 000:278 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 0255ms total)
+T01AC 000:282 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 0255ms total)
+T01AC 000:282 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 0255ms total)
+T01AC 000:282 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 0255ms total)
+T01AC 000:286 JLINK_GetSpeed() returns 0x1388 (0000ms, 0255ms total)
+T01AC 000:289 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 0255ms total)
+T01AC 000:289 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0000ms, 0255ms total)
+T01AC 000:289 JLINK_WriteMemEx(0xE0001000, 0x001C Bytes, ..., Flags = 0x02000004) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 0256ms total)
+T01AC 000:290 JLINK_Halt() returns 0x00 (0000ms, 0256ms total)
+T01AC 000:290 JLINK_IsHalted() returns TRUE (0000ms, 0256ms total)
+T01AC 000:292 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0003ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R1, 0x017D7840) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000001 (0000ms, 0259ms total)
+T01AC 000:295 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0004ms, 0263ms total)
+T01AC 000:299 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0265ms total)
+T01AC 000:301 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0263ms total)
+T01AC 000:301 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:301 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 0263ms total)
+T01AC 000:302 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0264ms total)
+T01AC 000:303 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0266ms total)
+T01AC 000:305 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0264ms total)
+T01AC 000:305 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 0264ms total)
+T01AC 000:305 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0264ms total)
+T01AC 000:305 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0264ms total)
+T01AC 000:305 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0264ms total)
+T01AC 000:305 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0264ms total)
+T01AC 000:305 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 0265ms total)
+T01AC 000:306 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0266ms total)
+T01AC 000:307 JLINK_IsHalted() returns FALSE (0000ms, 0266ms total)
+T01AC 000:336 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0268ms total)
+T01AC 000:338 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000004 (0000ms, 0266ms total)
+T01AC 000:338 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0268ms total)
+T01AC 000:340 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0270ms total)
+T01AC 000:342 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 0268ms total)
+T01AC 000:342 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0269ms total)
+T01AC 000:343 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:345 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:347 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:349 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:351 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:353 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:355 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:357 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:359 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:361 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:363 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:365 JLINK_IsHalted() returns FALSE (0000ms, 0269ms total)
+T01AC 000:367 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0001ms, 0270ms total)
+T01AC 000:368 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0270ms total)
+T01AC 000:369 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 0270ms total)
+T01AC 000:369 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0271ms total)
+T01AC 000:370 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0273ms total)
+T01AC 000:372 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0271ms total)
+T01AC 000:372 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 0271ms total)
+T01AC 000:372 JLINK_ReadReg(R0) returns 0x00000001 (0001ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 0272ms total)
+T01AC 000:373 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0273ms total)
+T01AC 000:374 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:376 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:378 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:381 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:383 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:385 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:387 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:388 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:390 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:392 JLINK_IsHalted() returns FALSE (0000ms, 0273ms total)
+T01AC 000:395 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0001ms, 0274ms total)
+T01AC 000:396 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0273ms total)
+T01AC 000:396 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0001ms, 0274ms total)
+T01AC 000:397 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 0274ms total)
+T01AC 000:397 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0275ms total)
+T01AC 000:398 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0277ms total)
+T01AC 000:401 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 0275ms total)
+T01AC 000:401 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0276ms total)
+T01AC 000:402 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:404 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:406 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:410 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:412 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:414 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:416 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:418 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:420 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:422 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:424 JLINK_IsHalted() returns FALSE (0000ms, 0276ms total)
+T01AC 000:427 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0278ms total)
+T01AC 000:429 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0276ms total)
+T01AC 000:429 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 0276ms total)
+T01AC 000:429 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0278ms total)
+T01AC 000:431 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0280ms total)
+T01AC 000:433 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0278ms total)
+T01AC 000:433 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 0278ms total)
+T01AC 000:433 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0279ms total)
+T01AC 000:434 JLINK_IsHalted() returns FALSE (0001ms, 0280ms total)
+T01AC 000:437 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:439 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:441 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:443 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:445 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:447 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:449 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:451 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:453 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:455 JLINK_IsHalted() returns FALSE (0000ms, 0279ms total)
+T01AC 000:457 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0281ms total)
+T01AC 000:459 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0279ms total)
+T01AC 000:459 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 0279ms total)
+T01AC 000:459 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0280ms total)
+T01AC 000:460 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0283ms total)
+T01AC 000:463 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0280ms total)
+T01AC 000:463 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 0280ms total)
+T01AC 000:463 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0281ms total)
+T01AC 000:464 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:466 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:468 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:470 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:472 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:474 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:476 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:478 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:480 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:482 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:484 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:486 JLINK_IsHalted() returns FALSE (0000ms, 0281ms total)
+T01AC 000:488 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0283ms total)
+T01AC 000:490 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0281ms total)
+T01AC 000:490 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 0281ms total)
+T01AC 000:490 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0282ms total)
+T01AC 000:491 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0285ms total)
+T01AC 000:494 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0282ms total)
+T01AC 000:494 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000F (0000ms, 0282ms total)
+T01AC 000:494 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0283ms total)
+T01AC 000:495 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:498 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:500 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:502 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:504 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:506 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:508 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:510 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:512 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:514 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:516 JLINK_IsHalted() returns FALSE (0000ms, 0283ms total)
+T01AC 000:518 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0285ms total)
+T01AC 000:520 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R0, 0x08003800) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 0283ms total)
+T01AC 000:520 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0284ms total)
+T01AC 000:522 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0287ms total)
+T01AC 000:524 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R0, 0x08003800) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000011 (0000ms, 0285ms total)
+T01AC 000:524 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0286ms total)
+T01AC 000:525 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:527 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:529 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:531 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:533 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:535 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:537 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:539 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:541 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:543 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:545 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:547 JLINK_IsHalted() returns FALSE (0000ms, 0286ms total)
+T01AC 000:549 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0288ms total)
+T01AC 000:551 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R0, 0x08004000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 0286ms total)
+T01AC 000:551 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0287ms total)
+T01AC 000:552 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0289ms total)
+T01AC 000:554 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0288ms total)
+T01AC 000:555 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R0, 0x08004000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 0288ms total)
+T01AC 000:555 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0289ms total)
+T01AC 000:556 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:558 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:560 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:562 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:564 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:566 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:568 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:570 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:572 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:574 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:576 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:578 JLINK_IsHalted() returns FALSE (0000ms, 0289ms total)
+T01AC 000:580 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0291ms total)
+T01AC 000:582 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R0, 0x08004800) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000014 (0000ms, 0289ms total)
+T01AC 000:582 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0290ms total)
+T01AC 000:583 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0293ms total)
+T01AC 000:586 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R0, 0x08004800) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 0290ms total)
+T01AC 000:586 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0291ms total)
+T01AC 000:587 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:589 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:591 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:593 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:595 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:597 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:599 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:602 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:604 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:606 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:608 JLINK_IsHalted() returns FALSE (0000ms, 0291ms total)
+T01AC 000:610 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0293ms total)
+T01AC 000:612 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R0, 0x08005000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 0291ms total)
+T01AC 000:612 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0293ms total)
+T01AC 000:614 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0295ms total)
+T01AC 000:616 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R0, 0x08005000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000017 (0000ms, 0293ms total)
+T01AC 000:616 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0294ms total)
+T01AC 000:617 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:619 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:621 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:623 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:625 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:627 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:629 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:631 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:633 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:635 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:637 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:639 JLINK_IsHalted() returns FALSE (0000ms, 0294ms total)
+T01AC 000:641 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0296ms total)
+T01AC 000:643 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R0, 0x08005800) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 0294ms total)
+T01AC 000:643 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0296ms total)
+T01AC 000:645 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0298ms total)
+T01AC 000:647 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R0, 0x08005800) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 0296ms total)
+T01AC 000:647 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0297ms total)
+T01AC 000:648 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:650 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:652 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:654 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:656 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:658 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:660 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:662 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:664 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:666 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:668 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:670 JLINK_IsHalted() returns FALSE (0000ms, 0297ms total)
+T01AC 000:672 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0299ms total)
+T01AC 000:674 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R0, 0x08006000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0297ms total)
+T01AC 000:674 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001A (0000ms, 0297ms total)
+T01AC 000:674 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0298ms total)
+T01AC 000:675 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0301ms total)
+T01AC 000:678 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_ClrBPEx(BPHandle = 0x0000001A) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R0, 0x08006000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0298ms total)
+T01AC 000:678 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001B (0000ms, 0298ms total)
+T01AC 000:678 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0299ms total)
+T01AC 000:679 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:681 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:683 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:685 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:687 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:689 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:691 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:693 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:695 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:697 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:699 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:701 JLINK_IsHalted() returns FALSE (0000ms, 0299ms total)
+T01AC 000:703 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0301ms total)
+T01AC 000:705 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0299ms total)
+T01AC 000:705 JLINK_ClrBPEx(BPHandle = 0x0000001B) returns 0x00 (0000ms, 0299ms total)
+T01AC 000:705 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0299ms total)
+T01AC 000:705 JLINK_WriteReg(R0, 0x08006800) returns 0x00 (0000ms, 0299ms total)
+T01AC 000:705 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0299ms total)
+T01AC 000:706 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0300ms total)
+T01AC 000:706 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001C (0000ms, 0300ms total)
+T01AC 000:706 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0301ms total)
+T01AC 000:707 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0303ms total)
+T01AC 000:709 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_ClrBPEx(BPHandle = 0x0000001C) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R0, 0x08006800) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0301ms total)
+T01AC 000:709 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001D (0000ms, 0301ms total)
+T01AC 000:709 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0302ms total)
+T01AC 000:710 JLINK_IsHalted() returns FALSE (0001ms, 0303ms total)
+T01AC 000:713 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:715 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:717 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:719 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:721 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:723 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:725 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:727 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:729 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:731 JLINK_IsHalted() returns FALSE (0000ms, 0302ms total)
+T01AC 000:733 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0304ms total)
+T01AC 000:735 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_ClrBPEx(BPHandle = 0x0000001D) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R0, 0x08007000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(R15 (PC), 0x20000020) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0302ms total)
+T01AC 000:735 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001E (0000ms, 0302ms total)
+T01AC 000:735 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0303ms total)
+T01AC 000:737 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0305ms total)
+T01AC 000:739 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_ClrBPEx(BPHandle = 0x0000001E) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R0, 0x08007000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(R15 (PC), 0x200000B6) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0303ms total)
+T01AC 000:739 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001F (0000ms, 0303ms total)
+T01AC 000:739 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0304ms total)
+T01AC 000:740 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:742 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:744 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:746 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:748 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:750 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:752 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:754 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:756 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:758 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:759 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:761 JLINK_IsHalted() returns FALSE (0000ms, 0304ms total)
+T01AC 000:763 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0306ms total)
+T01AC 000:765 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_ClrBPEx(BPHandle = 0x0000001F) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R0, 0x00000001) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R1, 0x00000800) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R2, 0x000000FF) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000020 (0000ms, 0304ms total)
+T01AC 000:765 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0305ms total)
+T01AC 000:766 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0307ms total)
+T01AC 000:768 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0306ms total)
+T01AC 000:769 JLINK_ClrBPEx(BPHandle = 0x00000020) returns 0x00 (0000ms, 0306ms total)
+T01AC 000:769 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0306ms total)
+T01AC 000:832 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0003ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R1, 0x017D7840) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R2, 0x00000002) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0309ms total)
+T01AC 000:835 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000021 (0001ms, 0310ms total)
+T01AC 000:836 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0312ms total)
+T01AC 000:838 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0314ms total)
+T01AC 000:840 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0312ms total)
+T01AC 000:840 JLINK_ClrBPEx(BPHandle = 0x00000021) returns 0x00 (0000ms, 0312ms total)
+T01AC 000:840 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0312ms total)
+T01AC 000:841 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 70 9C 00 20 99 02 00 08 11 26 00 08 A5 24 00 08 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0316ms total)
+T01AC 000:845 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 FE E7 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000022 (0000ms, 0319ms total)
+T01AC 000:848 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0321ms total)
+T01AC 000:850 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:857 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:859 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:861 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:863 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:865 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:867 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:869 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:871 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:873 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:875 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:877 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:879 JLINK_IsHalted() returns FALSE (0000ms, 0321ms total)
+T01AC 000:881 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0323ms total)
+T01AC 000:883 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0321ms total)
+T01AC 000:883 JLINK_ClrBPEx(BPHandle = 0x00000022) returns 0x00 (0000ms, 0321ms total)
+T01AC 000:883 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0321ms total)
+T01AC 000:883 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 20 28 05 46 07 DB 31 2D 05 D2 78 19 10 F8 20 0C ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0325ms total)
+T01AC 000:887 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 01 3B 00 F8 01 CB 48 BF 00 F8 01 2B 70 47 4F F0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0327ms total)
+T01AC 000:889 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000023 (0000ms, 0328ms total)
+T01AC 000:890 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0329ms total)
+T01AC 000:891 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:894 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:896 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:898 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:900 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:902 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:904 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:906 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:908 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:910 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:912 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:914 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:916 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:918 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:920 JLINK_IsHalted() returns FALSE (0000ms, 0329ms total)
+T01AC 000:922 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0331ms total)
+T01AC 000:924 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0329ms total)
+T01AC 000:924 JLINK_ClrBPEx(BPHandle = 0x00000023) returns 0x00 (0000ms, 0329ms total)
+T01AC 000:924 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0329ms total)
+T01AC 000:924 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: C0 B2 70 47 C9 05 FC D5 80 B2 70 47 70 B5 0C 46 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0333ms total)
+T01AC 000:928 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 02 E0 49 07 01 D5 0E A6 01 25 11 46 00 24 08 F1 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000024 (0000ms, 0335ms total)
+T01AC 000:931 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0336ms total)
+T01AC 000:932 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:935 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:937 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:939 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:941 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:943 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:945 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:947 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:949 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:951 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:953 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:955 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:957 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:960 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:962 JLINK_IsHalted() returns FALSE (0000ms, 0336ms total)
+T01AC 000:964 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0338ms total)
+T01AC 000:966 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0336ms total)
+T01AC 000:966 JLINK_ClrBPEx(BPHandle = 0x00000024) returns 0x00 (0000ms, 0336ms total)
+T01AC 000:966 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0336ms total)
+T01AC 000:966 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: F5 AF 5F EA 02 7C 24 BF B1 E8 18 50 A0 E8 18 50 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0340ms total)
+T01AC 000:970 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 02 46 0B 98 C0 0F 01 D0 2D 20 07 E0 20 68 81 07 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000025 (0000ms, 0342ms total)
+T01AC 000:972 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0344ms total)
+T01AC 000:974 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:976 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:978 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:980 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:982 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:984 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:986 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:988 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:990 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:992 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:994 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:996 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 000:998 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 001:000 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 001:002 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 001:004 JLINK_IsHalted() returns FALSE (0000ms, 0344ms total)
+T01AC 001:006 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0346ms total)
+T01AC 001:008 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0344ms total)
+T01AC 001:008 JLINK_ClrBPEx(BPHandle = 0x00000025) returns 0x00 (0000ms, 0344ms total)
+T01AC 001:008 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0344ms total)
+T01AC 001:008 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 00 00 DC 5F B1 97 FB F1 FC 97 FB F1 F2 01 FB ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0348ms total)
+T01AC 001:012 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: F1 F2 90 FB F1 F5 A5 F1 80 05 01 FB 12 04 1B 3C ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0350ms total)
+T01AC 001:014 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:014 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:014 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:014 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:014 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:014 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:014 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000026 (0000ms, 0350ms total)
+T01AC 001:015 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0351ms total)
+T01AC 001:016 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:018 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:020 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:022 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:024 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:026 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:028 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:030 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:032 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:035 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:037 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:039 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:041 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:043 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:045 JLINK_IsHalted() returns FALSE (0000ms, 0351ms total)
+T01AC 001:047 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0353ms total)
+T01AC 001:049 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0351ms total)
+T01AC 001:049 JLINK_ClrBPEx(BPHandle = 0x00000026) returns 0x00 (0000ms, 0351ms total)
+T01AC 001:049 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0351ms total)
+T01AC 001:049 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 1C 50 18 BF 00 F5 F0 40 4F EA 30 00 18 BF 41 F0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0355ms total)
+T01AC 001:053 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 0C FB 0B F7 D2 1B 03 FB 0C F7 61 EB 07 01 0C FB ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000027 (0000ms, 0357ms total)
+T01AC 001:055 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0359ms total)
+T01AC 001:057 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:059 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:061 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:063 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:065 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:067 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:069 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:071 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:073 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:075 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:077 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:079 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:081 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:083 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:085 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:087 JLINK_IsHalted() returns FALSE (0000ms, 0359ms total)
+T01AC 001:089 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0361ms total)
+T01AC 001:091 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0359ms total)
+T01AC 001:091 JLINK_ClrBPEx(BPHandle = 0x00000027) returns 0x00 (0000ms, 0359ms total)
+T01AC 001:091 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0359ms total)
+T01AC 001:091 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 42 41 41 41 00 2B 26 D4 77 00 21 D0 1C B5 4F EA ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0363ms total)
+T01AC 001:095 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 01 01 A3 F1 01 03 70 47 95 F0 00 0F 37 D0 4F EA ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000028 (0000ms, 0365ms total)
+T01AC 001:097 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0367ms total)
+T01AC 001:099 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:101 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:103 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:105 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:107 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:109 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:111 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:113 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:115 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:117 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:119 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:121 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:123 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:125 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:127 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:129 JLINK_IsHalted() returns FALSE (0000ms, 0367ms total)
+T01AC 001:131 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0369ms total)
+T01AC 001:133 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0367ms total)
+T01AC 001:133 JLINK_ClrBPEx(BPHandle = 0x00000028) returns 0x00 (0000ms, 0367ms total)
+T01AC 001:133 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0367ms total)
+T01AC 001:133 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 00 BD 00 00 10 00 00 20 D8 00 00 20 20 20 20 25 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0371ms total)
+T01AC 001:137 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 21 62 01 E0 08 E0 27 62 80 07 01 D5 67 61 13 E0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R0, 0x08001C00) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0373ms total)
+T01AC 001:139 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0001ms, 0374ms total)
+T01AC 001:140 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0374ms total)
+T01AC 001:140 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0374ms total)
+T01AC 001:140 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000029 (0000ms, 0374ms total)
+T01AC 001:140 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0375ms total)
+T01AC 001:141 JLINK_IsHalted() returns FALSE (0001ms, 0376ms total)
+T01AC 001:143 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:146 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:148 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:150 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:152 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:154 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:156 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:158 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:160 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:162 JLINK_IsHalted() returns FALSE (0001ms, 0376ms total)
+T01AC 001:165 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:167 JLINK_IsHalted() returns FALSE (0000ms, 0375ms total)
+T01AC 001:169 JLINK_IsHalted() returns FALSE (0001ms, 0376ms total)
+T01AC 001:172 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0377ms total)
+T01AC 001:174 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0375ms total)
+T01AC 001:174 JLINK_ClrBPEx(BPHandle = 0x00000029) returns 0x00 (0000ms, 0375ms total)
+T01AC 001:174 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0375ms total)
+T01AC 001:175 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 08 68 02 D0 40 F0 04 00 01 E0 20 F0 04 00 08 60 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0003ms, 0378ms total)
+T01AC 001:178 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 01 21 68 46 FF F7 9A FD 01 21 02 48 FF F7 C0 FC ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0381ms total)
+T01AC 001:181 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002A (0000ms, 0381ms total)
+T01AC 001:181 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0384ms total)
+T01AC 001:184 JLINK_IsHalted() returns FALSE (0000ms, 0384ms total)
+T01AC 001:186 JLINK_IsHalted() returns FALSE (0000ms, 0384ms total)
+T01AC 001:188 JLINK_IsHalted() returns FALSE (0001ms, 0385ms total)
+T01AC 001:191 JLINK_IsHalted() returns FALSE (0000ms, 0384ms total)
+T01AC 001:193 JLINK_IsHalted() returns FALSE (0000ms, 0384ms total)
+T01AC 001:195 JLINK_IsHalted() returns FALSE (0000ms, 0384ms total)
+T01AC 001:197 JLINK_IsHalted() returns FALSE (0001ms, 0385ms total)
+T01AC 001:200 JLINK_IsHalted() returns FALSE (0001ms, 0385ms total)
+T01AC 001:203 JLINK_IsHalted() returns FALSE (0001ms, 0385ms total)
+T01AC 001:206 JLINK_IsHalted() returns FALSE (0000ms, 0384ms total)
+T01AC 001:208 JLINK_IsHalted() returns FALSE (0000ms, 0384ms total)
+T01AC 001:210 JLINK_IsHalted() returns FALSE (0001ms, 0385ms total)
+T01AC 001:213 JLINK_IsHalted() returns FALSE (0001ms, 0385ms total)
+T01AC 001:215 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0387ms total)
+T01AC 001:218 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0384ms total)
+T01AC 001:218 JLINK_ClrBPEx(BPHandle = 0x0000002A) returns 0x00 (0000ms, 0384ms total)
+T01AC 001:218 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0384ms total)
+T01AC 001:220 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 02 D0 02 E0 44 61 00 E0 04 61 52 1C 08 2A E5 D3 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0388ms total)
+T01AC 001:224 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 02 50 8D F8 03 40 68 46 00 F0 0E F8 1C 20 8D F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0390ms total)
+T01AC 001:226 JLINK_WriteReg(R0, 0x08002400) returns 0x00 (0000ms, 0390ms total)
+T01AC 001:226 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0390ms total)
+T01AC 001:226 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0390ms total)
+T01AC 001:226 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0391ms total)
+T01AC 001:227 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002B (0000ms, 0391ms total)
+T01AC 001:227 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0393ms total)
+T01AC 001:229 JLINK_IsHalted() returns FALSE (0001ms, 0394ms total)
+T01AC 001:232 JLINK_IsHalted() returns FALSE (0001ms, 0394ms total)
+T01AC 001:235 JLINK_IsHalted() returns FALSE (0000ms, 0393ms total)
+T01AC 001:237 JLINK_IsHalted() returns FALSE (0000ms, 0393ms total)
+T01AC 001:239 JLINK_IsHalted() returns FALSE (0000ms, 0393ms total)
+T01AC 001:241 JLINK_IsHalted() returns FALSE (0001ms, 0394ms total)
+T01AC 001:244 JLINK_IsHalted() returns FALSE (0000ms, 0393ms total)
+T01AC 001:246 JLINK_IsHalted() returns FALSE (0001ms, 0394ms total)
+T01AC 001:249 JLINK_IsHalted() returns FALSE (0000ms, 0393ms total)
+T01AC 001:253 JLINK_IsHalted() returns FALSE (0001ms, 0394ms total)
+T01AC 001:256 JLINK_IsHalted() returns FALSE (0001ms, 0394ms total)
+T01AC 001:259 JLINK_IsHalted() returns FALSE (0001ms, 0394ms total)
+T01AC 001:262 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0396ms total)
+T01AC 001:265 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0393ms total)
+T01AC 001:265 JLINK_ClrBPEx(BPHandle = 0x0000002B) returns 0x00 (0000ms, 0393ms total)
+T01AC 001:265 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0393ms total)
+T01AC 001:266 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 02 F4 80 32 0D 29 01 D0 89 1C 00 E0 06 21 BA B1 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0397ms total)
+T01AC 001:271 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: F1 F1 4F F0 FF 35 B1 F1 80 7F 0D D2 21 F0 7F 40 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0400ms total)
+T01AC 001:273 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0401ms total)
+T01AC 001:274 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002C (0000ms, 0401ms total)
+T01AC 001:274 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0403ms total)
+T01AC 001:276 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:278 JLINK_IsHalted() returns FALSE (0001ms, 0404ms total)
+T01AC 001:281 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:283 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:285 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:287 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:290 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:292 JLINK_IsHalted() returns FALSE (0001ms, 0404ms total)
+T01AC 001:295 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:297 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:299 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:301 JLINK_IsHalted() returns FALSE (0001ms, 0404ms total)
+T01AC 001:304 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:306 JLINK_IsHalted() returns FALSE (0000ms, 0403ms total)
+T01AC 001:308 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0405ms total)
+T01AC 001:310 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0403ms total)
+T01AC 001:310 JLINK_ClrBPEx(BPHandle = 0x0000002C) returns 0x00 (0000ms, 0403ms total)
+T01AC 001:310 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0403ms total)
+T01AC 001:311 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 00 F0 81 FC 1D A0 00 F0 A5 FA 4F F4 FA 77 38 46 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0407ms total)
+T01AC 001:315 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 25 51 20 46 00 F0 AE FA 01 21 20 46 00 F0 DA F9 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R0, 0x08002C00) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0410ms total)
+T01AC 001:318 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0411ms total)
+T01AC 001:319 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0411ms total)
+T01AC 001:319 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0411ms total)
+T01AC 001:319 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0411ms total)
+T01AC 001:319 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002D (0000ms, 0411ms total)
+T01AC 001:319 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0413ms total)
+T01AC 001:321 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:323 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:326 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:328 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:330 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:335 JLINK_IsHalted() returns FALSE (0001ms, 0414ms total)
+T01AC 001:338 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:340 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:342 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:344 JLINK_IsHalted() returns FALSE (0001ms, 0414ms total)
+T01AC 001:346 JLINK_IsHalted() returns FALSE (0000ms, 0413ms total)
+T01AC 001:348 JLINK_IsHalted() returns FALSE (0001ms, 0414ms total)
+T01AC 001:351 JLINK_IsHalted() returns FALSE (0001ms, 0414ms total)
+T01AC 001:354 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0415ms total)
+T01AC 001:356 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0414ms total)
+T01AC 001:357 JLINK_ClrBPEx(BPHandle = 0x0000002D) returns 0x00 (0000ms, 0414ms total)
+T01AC 001:357 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0414ms total)
+T01AC 001:358 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 12 40 20 20 13 4D AD F8 10 00 04 A9 28 46 FF F7 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0418ms total)
+T01AC 001:362 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 28 46 FF F7 8B F8 2E 15 AD F8 00 60 4F F0 04 0B ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0421ms total)
+T01AC 001:365 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 0422ms total)
+T01AC 001:366 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0422ms total)
+T01AC 001:366 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0422ms total)
+T01AC 001:366 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0422ms total)
+T01AC 001:366 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002E (0000ms, 0422ms total)
+T01AC 001:366 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0424ms total)
+T01AC 001:368 JLINK_IsHalted() returns FALSE (0001ms, 0425ms total)
+T01AC 001:373 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:375 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:378 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:381 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:384 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:386 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:388 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:390 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:391 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:397 JLINK_IsHalted() returns FALSE (0000ms, 0424ms total)
+T01AC 001:400 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0427ms total)
+T01AC 001:403 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0424ms total)
+T01AC 001:403 JLINK_ClrBPEx(BPHandle = 0x0000002E) returns 0x00 (0000ms, 0424ms total)
+T01AC 001:403 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0424ms total)
+T01AC 001:404 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 10 B5 C1 F3 42 13 01 F0 1F 04 01 21 A1 40 01 2B ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0428ms total)
+T01AC 001:408 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 8D F8 04 00 20 68 01 F0 A3 FA 8D F8 05 00 6B 46 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R0, 0x08003400) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:411 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0431ms total)
+T01AC 001:412 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002F (0000ms, 0431ms total)
+T01AC 001:412 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0433ms total)
+T01AC 001:414 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:416 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:418 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:420 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:422 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:424 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:426 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:428 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:430 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:432 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:434 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:436 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:438 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:440 JLINK_IsHalted() returns FALSE (0000ms, 0433ms total)
+T01AC 001:442 JLINK_IsHalted() returns FALSE (0001ms, 0434ms total)
+T01AC 001:445 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0436ms total)
+T01AC 001:448 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0433ms total)
+T01AC 001:448 JLINK_ClrBPEx(BPHandle = 0x0000002F) returns 0x00 (0000ms, 0433ms total)
+T01AC 001:448 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0433ms total)
+T01AC 001:449 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 03 20 01 F0 F7 F9 05 00 3C D0 6C 68 0D 98 00 F0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0438ms total)
+T01AC 001:454 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 01 EB 81 0B 0E EB 8B 00 83 7B 01 2B 04 D0 02 2B ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0440ms total)
+T01AC 001:456 JLINK_WriteReg(R0, 0x08003800) returns 0x00 (0001ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000030 (0000ms, 0441ms total)
+T01AC 001:457 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0444ms total)
+T01AC 001:460 JLINK_IsHalted() returns FALSE (0000ms, 0444ms total)
+T01AC 001:462 JLINK_IsHalted() returns FALSE (0000ms, 0444ms total)
+T01AC 001:464 JLINK_IsHalted() returns FALSE (0001ms, 0445ms total)
+T01AC 001:467 JLINK_IsHalted() returns FALSE (0000ms, 0444ms total)
+T01AC 001:469 JLINK_IsHalted() returns FALSE (0000ms, 0444ms total)
+T01AC 001:471 JLINK_IsHalted() returns FALSE (0001ms, 0445ms total)
+T01AC 001:473 JLINK_IsHalted() returns FALSE (0000ms, 0444ms total)
+T01AC 001:478 JLINK_IsHalted() returns FALSE (0001ms, 0445ms total)
+T01AC 001:481 JLINK_IsHalted() returns FALSE (0000ms, 0444ms total)
+T01AC 001:483 JLINK_IsHalted() returns FALSE (0001ms, 0445ms total)
+T01AC 001:486 JLINK_IsHalted() returns FALSE (0001ms, 0445ms total)
+T01AC 001:489 JLINK_IsHalted() returns FALSE (0001ms, 0445ms total)
+T01AC 001:492 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0447ms total)
+T01AC 001:495 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0444ms total)
+T01AC 001:495 JLINK_ClrBPEx(BPHandle = 0x00000030) returns 0x00 (0000ms, 0444ms total)
+T01AC 001:495 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0444ms total)
+T01AC 001:497 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 70 40 00 F0 F3 FF 21 69 00 EA 01 07 4F F0 60 40 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0449ms total)
+T01AC 001:502 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 14 00 81 B2 50 46 01 F0 21 F8 00 22 11 46 02 20 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0451ms total)
+T01AC 001:504 JLINK_WriteReg(R0, 0x08003C00) returns 0x00 (0000ms, 0451ms total)
+T01AC 001:504 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0451ms total)
+T01AC 001:504 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0451ms total)
+T01AC 001:504 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000031 (0000ms, 0452ms total)
+T01AC 001:505 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0454ms total)
+T01AC 001:507 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:510 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:511 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:513 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:516 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:517 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:519 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:521 JLINK_IsHalted() returns FALSE (0001ms, 0455ms total)
+T01AC 001:524 JLINK_IsHalted() returns FALSE (0000ms, 0454ms total)
+T01AC 001:525 JLINK_IsHalted() returns FALSE (0001ms, 0455ms total)
+T01AC 001:527 JLINK_IsHalted() returns FALSE (0001ms, 0455ms total)
+T01AC 001:530 JLINK_IsHalted() returns FALSE (0001ms, 0455ms total)
+T01AC 001:533 JLINK_IsHalted() returns FALSE (0001ms, 0455ms total)
+T01AC 001:536 JLINK_IsHalted() returns FALSE (0001ms, 0455ms total)
+T01AC 001:539 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0457ms total)
+T01AC 001:542 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0454ms total)
+T01AC 001:542 JLINK_ClrBPEx(BPHandle = 0x00000031) returns 0x00 (0000ms, 0454ms total)
+T01AC 001:542 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0454ms total)
+T01AC 001:543 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 05 D0 05 F1 10 00 FF F7 C9 FE 70 B1 1D E0 30 46 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0458ms total)
+T01AC 001:547 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 08 01 46 68 30 46 34 68 FC F7 BC F9 A8 8B FF F7 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0461ms total)
+T01AC 001:550 JLINK_WriteReg(R0, 0x08004000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:550 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:550 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:550 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:550 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:550 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000032 (0000ms, 0461ms total)
+T01AC 001:551 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0463ms total)
+T01AC 001:553 JLINK_IsHalted() returns FALSE (0000ms, 0463ms total)
+T01AC 001:556 JLINK_IsHalted() returns FALSE (0000ms, 0463ms total)
+T01AC 001:558 JLINK_IsHalted() returns FALSE (0000ms, 0463ms total)
+T01AC 001:560 JLINK_IsHalted() returns FALSE (0000ms, 0463ms total)
+T01AC 001:561 JLINK_IsHalted() returns FALSE (0001ms, 0464ms total)
+T01AC 001:564 JLINK_IsHalted() returns FALSE (0001ms, 0464ms total)
+T01AC 001:567 JLINK_IsHalted() returns FALSE (0001ms, 0464ms total)
+T01AC 001:570 JLINK_IsHalted() returns FALSE (0001ms, 0464ms total)
+T01AC 001:573 JLINK_IsHalted() returns FALSE (0001ms, 0464ms total)
+T01AC 001:576 JLINK_IsHalted() returns FALSE (0001ms, 0464ms total)
+T01AC 001:579 JLINK_IsHalted() returns FALSE (0000ms, 0463ms total)
+T01AC 001:583 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0467ms total)
+T01AC 001:587 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0463ms total)
+T01AC 001:587 JLINK_ClrBPEx(BPHandle = 0x00000032) returns 0x00 (0000ms, 0463ms total)
+T01AC 001:587 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0463ms total)
+T01AC 001:588 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 07 4A 30 B4 0B 46 54 68 01 68 84 42 01 D1 51 60 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0467ms total)
+T01AC 001:592 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FD F7 30 FF FD F7 B7 FF DF F8 84 A1 DF F8 84 91 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0469ms total)
+T01AC 001:594 JLINK_WriteReg(R0, 0x08004400) returns 0x00 (0000ms, 0469ms total)
+T01AC 001:595 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000033 (0000ms, 0470ms total)
+T01AC 001:595 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0473ms total)
+T01AC 001:598 JLINK_IsHalted() returns FALSE (0000ms, 0473ms total)
+T01AC 001:600 JLINK_IsHalted() returns FALSE (0001ms, 0474ms total)
+T01AC 001:603 JLINK_IsHalted() returns FALSE (0001ms, 0474ms total)
+T01AC 001:606 JLINK_IsHalted() returns FALSE (0001ms, 0474ms total)
+T01AC 001:609 JLINK_IsHalted() returns FALSE (0000ms, 0473ms total)
+T01AC 001:611 JLINK_IsHalted() returns FALSE (0000ms, 0473ms total)
+T01AC 001:613 JLINK_IsHalted() returns FALSE (0000ms, 0473ms total)
+T01AC 001:615 JLINK_IsHalted() returns FALSE (0000ms, 0473ms total)
+T01AC 001:617 JLINK_IsHalted() returns FALSE (0001ms, 0474ms total)
+T01AC 001:619 JLINK_IsHalted() returns FALSE (0001ms, 0474ms total)
+T01AC 001:621 JLINK_IsHalted() returns FALSE (0000ms, 0473ms total)
+T01AC 001:623 JLINK_IsHalted() returns FALSE (0001ms, 0474ms total)
+T01AC 001:626 JLINK_IsHalted() returns FALSE (0001ms, 0474ms total)
+T01AC 001:629 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0476ms total)
+T01AC 001:632 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0473ms total)
+T01AC 001:632 JLINK_ClrBPEx(BPHandle = 0x00000033) returns 0x00 (0000ms, 0473ms total)
+T01AC 001:632 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0473ms total)
+T01AC 001:634 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 43 28 06 D1 1A A0 FB F7 7F FD 08 21 0C 48 FD F7 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0478ms total)
+T01AC 001:639 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 35 F8 10 30 93 42 F1 D8 40 1C 80 B2 09 28 E9 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R0, 0x08004800) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0480ms total)
+T01AC 001:641 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000034 (0000ms, 0481ms total)
+T01AC 001:642 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0483ms total)
+T01AC 001:644 JLINK_IsHalted() returns FALSE (0000ms, 0483ms total)
+T01AC 001:646 JLINK_IsHalted() returns FALSE (0000ms, 0483ms total)
+T01AC 001:648 JLINK_IsHalted() returns FALSE (0001ms, 0484ms total)
+T01AC 001:651 JLINK_IsHalted() returns FALSE (0001ms, 0484ms total)
+T01AC 001:654 JLINK_IsHalted() returns FALSE (0001ms, 0484ms total)
+T01AC 001:657 JLINK_IsHalted() returns FALSE (0000ms, 0483ms total)
+T01AC 001:659 JLINK_IsHalted() returns FALSE (0001ms, 0484ms total)
+T01AC 001:662 JLINK_IsHalted() returns FALSE (0001ms, 0484ms total)
+T01AC 001:665 JLINK_IsHalted() returns FALSE (0001ms, 0484ms total)
+T01AC 001:668 JLINK_IsHalted() returns FALSE (0000ms, 0483ms total)
+T01AC 001:670 JLINK_IsHalted() returns FALSE (0000ms, 0483ms total)
+T01AC 001:673 JLINK_IsHalted() returns FALSE (0000ms, 0483ms total)
+T01AC 001:675 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0485ms total)
+T01AC 001:677 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0483ms total)
+T01AC 001:677 JLINK_ClrBPEx(BPHandle = 0x00000034) returns 0x00 (0000ms, 0483ms total)
+T01AC 001:677 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0483ms total)
+T01AC 001:678 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 28 05 D0 02 28 04 D0 03 28 4B D1 02 E0 14 26 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0488ms total)
+T01AC 001:683 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 02 E0 00 20 10 BD 8B B2 02 7B 44 68 32 B1 03 2A ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R0, 0x08004C00) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0490ms total)
+T01AC 001:685 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 0491ms total)
+T01AC 001:686 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0491ms total)
+T01AC 001:686 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0491ms total)
+T01AC 001:686 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0491ms total)
+T01AC 001:686 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0491ms total)
+T01AC 001:686 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0491ms total)
+T01AC 001:686 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000035 (0000ms, 0491ms total)
+T01AC 001:686 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0493ms total)
+T01AC 001:688 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:691 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:693 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:697 JLINK_IsHalted() returns FALSE (0001ms, 0494ms total)
+T01AC 001:701 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:703 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:705 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:707 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:709 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:711 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:713 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:715 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:717 JLINK_IsHalted() returns FALSE (0000ms, 0493ms total)
+T01AC 001:719 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0495ms total)
+T01AC 001:721 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0493ms total)
+T01AC 001:721 JLINK_ClrBPEx(BPHandle = 0x00000035) returns 0x00 (0000ms, 0493ms total)
+T01AC 001:721 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0493ms total)
+T01AC 001:722 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 2D E9 FF 5F 04 46 00 7C 8B 46 0A 28 32 D0 D4 F8 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0497ms total)
+T01AC 001:726 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 14 48 00 25 21 46 10 30 00 F0 96 FE 21 46 03 20 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R0, 0x08005000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0500ms total)
+T01AC 001:729 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0001ms, 0501ms total)
+T01AC 001:730 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0501ms total)
+T01AC 001:730 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0501ms total)
+T01AC 001:730 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0501ms total)
+T01AC 001:730 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0501ms total)
+T01AC 001:730 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000036 (0000ms, 0501ms total)
+T01AC 001:730 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0502ms total)
+T01AC 001:731 JLINK_IsHalted() returns FALSE (0001ms, 0503ms total)
+T01AC 001:734 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:736 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:738 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:740 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:742 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:744 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:746 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:748 JLINK_IsHalted() returns FALSE (0001ms, 0503ms total)
+T01AC 001:751 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:753 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:755 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:757 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:759 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:761 JLINK_IsHalted() returns FALSE (0000ms, 0502ms total)
+T01AC 001:763 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0504ms total)
+T01AC 001:765 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0502ms total)
+T01AC 001:765 JLINK_ClrBPEx(BPHandle = 0x00000036) returns 0x00 (0000ms, 0502ms total)
+T01AC 001:765 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0502ms total)
+T01AC 001:765 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: F0 8F B5 F8 6E 10 05 98 81 42 05 D2 15 F8 22 0F ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0507ms total)
+T01AC 001:770 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: E8 80 2E 81 84 B1 B9 F1 00 0F 0D D0 20 69 58 B1 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R0, 0x08005400) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000037 (0000ms, 0509ms total)
+T01AC 001:772 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0512ms total)
+T01AC 001:775 JLINK_IsHalted() returns FALSE (0000ms, 0512ms total)
+T01AC 001:777 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:779 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:781 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:783 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:785 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:787 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:790 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:792 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:794 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:797 JLINK_IsHalted() returns FALSE (0001ms, 0513ms total)
+T01AC 001:802 JLINK_IsHalted() returns FALSE (0000ms, 0512ms total)
+T01AC 001:805 JLINK_IsHalted() returns FALSE (0000ms, 0512ms total)
+T01AC 001:807 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0514ms total)
+T01AC 001:809 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0512ms total)
+T01AC 001:809 JLINK_ClrBPEx(BPHandle = 0x00000037) returns 0x00 (0000ms, 0512ms total)
+T01AC 001:809 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0512ms total)
+T01AC 001:810 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 3B 68 00 22 1C 46 21 E0 70 68 B4 F8 20 C0 B0 F8 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0516ms total)
+T01AC 001:814 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: F0 68 B3 68 01 44 30 69 03 F1 10 02 40 1C 0C 33 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R0, 0x08005800) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000038 (0000ms, 0518ms total)
+T01AC 001:816 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0521ms total)
+T01AC 001:819 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:822 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:824 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:826 JLINK_IsHalted() returns FALSE (0001ms, 0522ms total)
+T01AC 001:828 JLINK_IsHalted() returns FALSE (0001ms, 0522ms total)
+T01AC 001:830 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:832 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:834 JLINK_IsHalted() returns FALSE (0001ms, 0522ms total)
+T01AC 001:836 JLINK_IsHalted() returns FALSE (0001ms, 0522ms total)
+T01AC 001:838 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:840 JLINK_IsHalted() returns FALSE (0001ms, 0522ms total)
+T01AC 001:842 JLINK_IsHalted() returns FALSE (0001ms, 0522ms total)
+T01AC 001:844 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:846 JLINK_IsHalted() returns FALSE (0000ms, 0521ms total)
+T01AC 001:847 JLINK_IsHalted() returns FALSE (0001ms, 0522ms total)
+T01AC 001:850 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0525ms total)
+T01AC 001:854 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0521ms total)
+T01AC 001:854 JLINK_ClrBPEx(BPHandle = 0x00000038) returns 0x00 (0000ms, 0521ms total)
+T01AC 001:854 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0521ms total)
+T01AC 001:854 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 08 46 D4 E9 1D 56 81 46 0E B9 03 E0 06 46 30 68 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0526ms total)
+T01AC 001:859 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 68 68 FE F7 DF F8 7C BD B4 05 04 02 64 00 00 20 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R0, 0x08005C00) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0528ms total)
+T01AC 001:861 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0001ms, 0529ms total)
+T01AC 001:862 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0529ms total)
+T01AC 001:862 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0529ms total)
+T01AC 001:862 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000039 (0000ms, 0529ms total)
+T01AC 001:862 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0530ms total)
+T01AC 001:863 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:865 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:867 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:869 JLINK_IsHalted() returns FALSE (0001ms, 0531ms total)
+T01AC 001:871 JLINK_IsHalted() returns FALSE (0001ms, 0531ms total)
+T01AC 001:873 JLINK_IsHalted() returns FALSE (0001ms, 0531ms total)
+T01AC 001:875 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:877 JLINK_IsHalted() returns FALSE (0001ms, 0531ms total)
+T01AC 001:879 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:881 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:883 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:885 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:887 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:889 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:890 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:892 JLINK_IsHalted() returns FALSE (0000ms, 0530ms total)
+T01AC 001:894 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0532ms total)
+T01AC 001:896 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0530ms total)
+T01AC 001:896 JLINK_ClrBPEx(BPHandle = 0x00000039) returns 0x00 (0000ms, 0530ms total)
+T01AC 001:896 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0530ms total)
+T01AC 001:896 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 00 25 20 46 E5 60 FF F7 CD FF 20 7C 0A 28 0C D0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0535ms total)
+T01AC 001:901 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 40 F0 02 00 84 F8 22 00 20 46 FF F7 9D FC 08 20 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0537ms total)
+T01AC 001:903 JLINK_WriteReg(R0, 0x08006000) returns 0x00 (0000ms, 0537ms total)
+T01AC 001:903 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0537ms total)
+T01AC 001:903 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0537ms total)
+T01AC 001:903 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0537ms total)
+T01AC 001:903 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0537ms total)
+T01AC 001:903 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0537ms total)
+T01AC 001:903 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0537ms total)
+T01AC 001:904 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0538ms total)
+T01AC 001:904 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003A (0000ms, 0538ms total)
+T01AC 001:904 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0539ms total)
+T01AC 001:905 JLINK_IsHalted() returns FALSE (0001ms, 0540ms total)
+T01AC 001:912 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:914 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:916 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:918 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:920 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:922 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:924 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:926 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:928 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:930 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:932 JLINK_IsHalted() returns FALSE (0001ms, 0540ms total)
+T01AC 001:935 JLINK_IsHalted() returns FALSE (0000ms, 0539ms total)
+T01AC 001:937 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0541ms total)
+T01AC 001:939 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 0540ms total)
+T01AC 001:940 JLINK_ClrBPEx(BPHandle = 0x0000003A) returns 0x00 (0000ms, 0540ms total)
+T01AC 001:940 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0540ms total)
+T01AC 001:943 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 22 00 40 07 25 D4 20 46 00 F0 1A FA B4 F8 52 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0004ms, 0544ms total)
+T01AC 001:947 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 8A 1A 52 1C 00 2A 71 DC 88 42 6F D1 D8 F8 10 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0001ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R0, 0x08006400) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0545ms total)
+T01AC 001:949 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003B (0000ms, 0545ms total)
+T01AC 001:949 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0547ms total)
+T01AC 001:951 JLINK_IsHalted() returns FALSE (0001ms, 0548ms total)
+T01AC 001:956 JLINK_IsHalted() returns FALSE (0001ms, 0548ms total)
+T01AC 001:959 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:962 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:964 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:966 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:968 JLINK_IsHalted() returns FALSE (0001ms, 0548ms total)
+T01AC 001:972 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:974 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:976 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:978 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:980 JLINK_IsHalted() returns FALSE (0000ms, 0547ms total)
+T01AC 001:982 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0001ms, 0548ms total)
+T01AC 001:983 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0547ms total)
+T01AC 001:983 JLINK_ClrBPEx(BPHandle = 0x0000003B) returns 0x00 (0000ms, 0547ms total)
+T01AC 001:983 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0547ms total)
+T01AC 001:984 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: FE F7 28 BD 10 B5 04 46 00 8D 08 44 80 B2 40 F6 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0552ms total)
+T01AC 001:989 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 46 49 D4 F8 94 00 D6 F8 08 C0 01 44 B1 FB F9 F3 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R0, 0x08006800) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:991 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:992 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0554ms total)
+T01AC 001:992 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003C (0000ms, 0554ms total)
+T01AC 001:992 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0555ms total)
+T01AC 001:993 JLINK_IsHalted() returns FALSE (0001ms, 0556ms total)
+T01AC 001:996 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 001:998 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:000 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:002 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:004 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:006 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:008 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:010 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:012 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:015 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:017 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:020 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:022 JLINK_IsHalted() returns FALSE (0000ms, 0555ms total)
+T01AC 002:023 JLINK_IsHalted() returns FALSE (0001ms, 0556ms total)
+T01AC 002:025 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0558ms total)
+T01AC 002:028 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0555ms total)
+T01AC 002:028 JLINK_ClrBPEx(BPHandle = 0x0000003C) returns 0x00 (0000ms, 0555ms total)
+T01AC 002:028 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0555ms total)
+T01AC 002:028 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 41 85 00 20 30 BD 1C B5 04 7C 04 2C 08 D0 07 2C ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0560ms total)
+T01AC 002:033 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 0A D0 08 78 00 28 07 D0 05 48 78 44 FA F7 5E FA ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R0, 0x08006C00) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0562ms total)
+T01AC 002:035 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003D (0000ms, 0562ms total)
+T01AC 002:035 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0565ms total)
+T01AC 002:038 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:039 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:041 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:043 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:046 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:048 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:050 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:052 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:054 JLINK_IsHalted() returns FALSE (0001ms, 0566ms total)
+T01AC 002:057 JLINK_IsHalted() returns FALSE (0000ms, 0565ms total)
+T01AC 002:059 JLINK_IsHalted() returns FALSE (0001ms, 0566ms total)
+T01AC 002:061 JLINK_IsHalted() returns FALSE (0001ms, 0566ms total)
+T01AC 002:063 JLINK_IsHalted() returns FALSE (0001ms, 0566ms total)
+T01AC 002:065 JLINK_IsHalted() returns FALSE (0001ms, 0566ms total)
+T01AC 002:068 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0568ms total)
+T01AC 002:071 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0565ms total)
+T01AC 002:071 JLINK_ClrBPEx(BPHandle = 0x0000003D) returns 0x00 (0000ms, 0565ms total)
+T01AC 002:071 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0565ms total)
+T01AC 002:072 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: D8 00 00 20 98 9B 00 00 A8 01 00 08 1C 00 00 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 0571ms total)
+T01AC 002:077 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R0, 0x08007000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R1, 0x00000210) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0574ms total)
+T01AC 002:080 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003E (0000ms, 0574ms total)
+T01AC 002:080 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0576ms total)
+T01AC 002:082 JLINK_IsHalted() returns FALSE (0000ms, 0576ms total)
+T01AC 002:084 JLINK_IsHalted() returns FALSE (0000ms, 0576ms total)
+T01AC 002:086 JLINK_IsHalted() returns FALSE (0000ms, 0576ms total)
+T01AC 002:088 JLINK_IsHalted() returns FALSE (0000ms, 0576ms total)
+T01AC 002:090 JLINK_IsHalted() returns FALSE (0001ms, 0577ms total)
+T01AC 002:092 JLINK_IsHalted() returns FALSE (0001ms, 0577ms total)
+T01AC 002:094 JLINK_IsHalted() returns FALSE (0000ms, 0576ms total)
+T01AC 002:096 JLINK_IsHalted() returns FALSE (0000ms, 0576ms total)
+T01AC 002:099 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0578ms total)
+T01AC 002:101 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_ClrBPEx(BPHandle = 0x0000003E) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R0, 0x00000002) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R1, 0x00000210) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0576ms total)
+T01AC 002:101 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 0577ms total)
+T01AC 002:102 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 0577ms total)
+T01AC 002:102 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0577ms total)
+T01AC 002:102 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0577ms total)
+T01AC 002:102 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0577ms total)
+T01AC 002:102 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0577ms total)
+T01AC 002:102 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003F (0000ms, 0577ms total)
+T01AC 002:102 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0001ms, 0578ms total)
+T01AC 002:103 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0580ms total)
+T01AC 002:105 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0578ms total)
+T01AC 002:105 JLINK_ClrBPEx(BPHandle = 0x0000003F) returns 0x00 (0000ms, 0578ms total)
+T01AC 002:105 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0578ms total)
+T01AC 002:186 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0003ms, 0581ms total)
+T01AC 002:189 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 0581ms total)
+T01AC 002:189 JLINK_WriteReg(R1, 0x017D7840) returns 0x00 (0000ms, 0581ms total)
+T01AC 002:189 JLINK_WriteReg(R2, 0x00000003) returns 0x00 (0000ms, 0581ms total)
+T01AC 002:189 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 0581ms total)
+T01AC 002:189 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0581ms total)
+T01AC 002:189 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0581ms total)
+T01AC 002:189 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:190 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0582ms total)
+T01AC 002:191 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000040 (0000ms, 0582ms total)
+T01AC 002:191 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 0585ms total)
+T01AC 002:194 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0003ms, 0588ms total)
+T01AC 002:197 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_ClrBPEx(BPHandle = 0x00000040) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R0, 0xFFFFFFFF) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R2, 0x00007210) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0585ms total)
+T01AC 002:197 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(R15 (PC), 0x20000002) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000041 (0000ms, 0586ms total)
+T01AC 002:198 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0588ms total)
+T01AC 002:200 JLINK_IsHalted() returns FALSE (0002ms, 0590ms total)
+T01AC 002:213 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:215 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:217 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:220 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:223 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:226 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:229 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:232 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:235 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:242 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:245 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:247 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:249 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:252 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:254 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:257 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:260 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:263 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:266 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:268 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:271 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:273 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:275 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:278 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:280 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:282 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:284 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:286 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:289 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:292 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:294 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:297 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:302 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:304 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:307 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:310 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:312 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:314 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:316 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:318 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:320 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:322 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:325 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:327 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:333 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:336 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:339 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:342 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:344 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:347 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:351 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:354 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:356 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:358 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:360 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:362 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:364 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:367 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:369 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:372 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:375 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:378 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:381 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:383 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:385 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:388 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:391 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:398 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:401 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:403 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:406 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:409 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:412 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:415 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:417 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:419 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:421 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:424 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:426 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:428 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:430 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:432 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:435 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:437 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:440 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:443 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:446 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:449 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:452 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:454 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:457 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:463 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:466 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:469 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:472 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:475 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:478 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:481 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:484 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:487 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:491 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:494 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:496 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:498 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:500 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:502 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:504 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:507 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:510 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:513 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:516 JLINK_IsHalted() returns FALSE (0001ms, 0589ms total)
+T01AC 002:519 JLINK_IsHalted() returns FALSE (0000ms, 0588ms total)
+T01AC 002:521 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 0592ms total)
+T01AC 002:525 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0588ms total)
+T01AC 002:525 JLINK_ClrBPEx(BPHandle = 0x00000041) returns 0x00 (0000ms, 0588ms total)
+T01AC 002:525 JLINK_ReadReg(R0) returns 0xFCDBB3CB (0000ms, 0588ms total)
+T01AC 002:532 JLINK_WriteReg(R0, 0x00000003) returns 0x00 (0000ms, 0588ms total)
+T01AC 002:532 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0000ms, 0588ms total)
+T01AC 002:532 JLINK_WriteReg(R2, 0x00007210) returns 0x00 (0001ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R13 (SP), 0x20000800) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 0589ms total)
+T01AC 002:533 JLINK_WriteReg(MSP, 0x20000800) returns 0x00 (0001ms, 0590ms total)
+T01AC 002:534 JLINK_WriteReg(PSP, 0x20000800) returns 0x00 (0000ms, 0590ms total)
+T01AC 002:534 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 0590ms total)
+T01AC 002:534 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000042 (0000ms, 0590ms total)
+T01AC 002:534 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 0592ms total)
+T01AC 002:536 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0002ms, 0594ms total)
+T01AC 002:538 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 0592ms total)
+T01AC 002:538 JLINK_ClrBPEx(BPHandle = 0x00000042) returns 0x00 (0000ms, 0592ms total)
+T01AC 002:538 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 0592ms total)
+T01AC 002:602 JLINK_WriteMemEx(0x20000000, 0x0002 Bytes, ..., Flags = 0x02000000) - Data: FE E7 -- CPU_WriteMem(2 bytes @ 0x20000000) returns 0x02 (0001ms, 0593ms total)
+T01AC 002:603 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) returns JLINKARM_CM3_RESET_TYPE_NORMAL (0000ms, 0593ms total)
+T01AC 002:603 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET.Reset: Reset device via AIRCR.SYSRESETREQ. -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028)
+ -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0073ms, 0666ms total)
+T01AC 002:676 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0004ms, 0670ms total)
+T01AC 002:710 JLINK_Close() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000201C) >0xF0 JTAG> >0x40 JTAG> >0x30 JTAG> >0x30 JTAG> >0x30 JTAG> >0x30 JTAG> >0x50 JTAG> >0x30 JTAG> >0x08 JTAG> (0023ms, 0693ms total)
+T01AC 002:710 (0023ms, 0693ms total)
+T01AC 002:710 Closed (0023ms, 0693ms total)
diff --git a/F107/Project/RVMDK/JLinkSettings.ini b/F107/Project/RVMDK/JLinkSettings.ini
new file mode 100644
index 0000000..c6b2dc4
--- /dev/null
+++ b/F107/Project/RVMDK/JLinkSettings.ini
@@ -0,0 +1,23 @@
+[BREAKPOINTS]
+ShowInfoWin = 1
+EnableFlashBP = 2
+BPDuringExecution = 0
+[CFI]
+CFISize = 0x00
+CFIAddr = 0x00
+[CPU]
+OverrideMemMap = 0
+AllowSimulation = 1
+ScriptFile=""
+[FLASH]
+SkipProgOnCRCMatch = 1
+VerifyDownload = 1
+AllowCaching = 1
+EnableFlashDL = 2
+Override = 0
+Device="ADUC7020X62"
+[GENERAL]
+WorkRAMSize = 0x00
+WorkRAMAddr = 0x00
+[SWO]
+SWOLogFile=""
diff --git a/F107/Project/RVMDK/List/STM3210C-EVAL.map b/F107/Project/RVMDK/List/STM3210C-EVAL.map
new file mode 100644
index 0000000..ad14a96
--- /dev/null
+++ b/F107/Project/RVMDK/List/STM3210C-EVAL.map
@@ -0,0 +1,3189 @@
+Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed]
+
+==============================================================================
+
+Section Cross References
+
+ stm32f10x_it.o(i.ETH_IRQHandler) refers to netconf.o(i.LwIP_Pkt_Handle) for LwIP_Pkt_Handle
+ stm32f10x_it.o(i.ETH_IRQHandler) refers to stm32_eth.o(i.ETH_GetRxPktSize) for ETH_GetRxPktSize
+ stm32f10x_it.o(i.ETH_IRQHandler) refers to stm32_eth.o(i.ETH_DMAClearITPendingBit) for ETH_DMAClearITPendingBit
+ stm32f10x_it.o(i.SysTick_Handler) refers to main.o(i.Time_Update) for Time_Update
+ main.o(i.Delay) refers to main.o(.data) for .data
+ main.o(i.System_Periodic_Handle) refers to netconf.o(i.Display_Periodic_Handle) for Display_Periodic_Handle
+ main.o(i.System_Periodic_Handle) refers to netconf.o(i.LwIP_Periodic_Handle) for LwIP_Periodic_Handle
+ main.o(i.System_Periodic_Handle) refers to main.o(.data) for .data
+ main.o(i.Time_Update) refers to main.o(.data) for .data
+ main.o(i.main) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+ main.o(i.main) refers to stm32f107.o(i.System_Setup) for System_Setup
+ main.o(i.main) refers to netconf.o(i.LwIP_Init) for LwIP_Init
+ main.o(i.main) refers to tcp_client.o(i.TCP_Client_Init) for TCP_Client_Init
+ main.o(i.main) refers to usart.o(i.USART1_Init) for USART1_Init
+ main.o(i.main) refers to usart.o(i.USART2_Init) for USART2_Init
+ main.o(i.main) refers to usart.o(i.USART4_Init) for USART4_Init
+ main.o(i.main) refers to usart.o(i.USART5_Init) for USART5_Init
+ main.o(i.main) refers to led.o(i.LED_Init1) for LED_Init1
+ main.o(i.main) refers to led.o(i.LED_Init2) for LED_Init2
+ main.o(i.main) refers to led.o(i.LED_Init3) for LED_Init3
+ main.o(i.main) refers to stm32f107.o(i.NVIC_Configuration) for NVIC_Configuration
+ main.o(i.main) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus
+ main.o(i.main) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData
+ main.o(i.main) refers to __2printf.o(.text) for __2printf
+ main.o(i.main) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+ main.o(i.main) refers to tcp_client.o(i.Check_TCP_Connect) for Check_TCP_Connect
+ main.o(i.main) refers to tcp_client.o(i.TCP_Client_Send_Data) for TCP_Client_Send_Data
+ main.o(i.main) refers to tcp_client.o(i.Delay_s) for Delay_s
+ main.o(i.main) refers to strncmp.o(.text) for strncmp
+ main.o(i.main) refers to delay.o(i.delay_ms) for delay_ms
+ main.o(i.main) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits
+ main.o(i.main) refers to usart.o(i.USART1_printf) for USART1_printf
+ main.o(i.main) refers to main.o(i.System_Periodic_Handle) for System_Periodic_Handle
+ main.o(i.main) refers to main.o(.constdata) for .constdata
+ main.o(i.main) refers to main.o(.data) for .data
+ main.o(i.main) refers to tcp_client.o(.bss) for member
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig) for GPIO_ETH_MediaInterfaceConfig
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32f10x_rcc.o(i.RCC_PLL3Config) for RCC_PLL3Config
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32f10x_rcc.o(i.RCC_PLL3Cmd) for RCC_PLL3Cmd
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32f10x_rcc.o(i.RCC_MCOConfig) for RCC_MCOConfig
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32_eth.o(i.ETH_DeInit) for ETH_DeInit
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32_eth.o(i.ETH_SoftwareReset) for ETH_SoftwareReset
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32_eth.o(i.ETH_GetSoftwareResetStatus) for ETH_GetSoftwareResetStatus
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32_eth.o(i.ETH_StructInit) for ETH_StructInit
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32_eth.o(i.ETH_Init) for ETH_Init
+ stm32f107.o(i.Ethernet_Configuration) refers to stm32_eth.o(i.ETH_DMAITConfig) for ETH_DMAITConfig
+ stm32f107.o(i.GPIO_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ stm32f107.o(i.GPIO_Configuration) refers to stm32f10x_gpio.o(i.GPIO_PinRemapConfig) for GPIO_PinRemapConfig
+ stm32f107.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_SetVectorTable) for NVIC_SetVectorTable
+ stm32f107.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig
+ stm32f107.o(i.NVIC_Configuration) refers to misc.o(i.NVIC_Init) for NVIC_Init
+ stm32f107.o(i.System_Setup) refers to system_stm32f10x.o(i.SystemInit) for SystemInit
+ stm32f107.o(i.System_Setup) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd
+ stm32f107.o(i.System_Setup) refers to stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd) for RCC_AHBPeriphClockCmd
+ stm32f107.o(i.System_Setup) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ stm32f107.o(i.System_Setup) refers to stm32f107.o(i.NVIC_Configuration) for NVIC_Configuration
+ stm32f107.o(i.System_Setup) refers to stm32f107.o(i.GPIO_Configuration) for GPIO_Configuration
+ stm32f107.o(i.System_Setup) refers to sci.o(i.USART_Configuration) for USART_Configuration
+ stm32f107.o(i.System_Setup) refers to stm32f107.o(i.Ethernet_Configuration) for Ethernet_Configuration
+ stm32f107.o(i.System_Setup) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
+ stm32f107.o(i.System_Setup) refers to stm32f107.o(i.NVIC_SetPriority) for NVIC_SetPriority
+ stm32f107.o(i.TIM2_IRQHandler) refers to stm32f10x_tim.o(i.TIM_GetITStatus) for TIM_GetITStatus
+ stm32f107.o(i.TIM2_IRQHandler) refers to stm32f10x_tim.o(i.TIM_ClearITPendingBit) for TIM_ClearITPendingBit
+ stm32f107.o(i.TIM_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd
+ stm32f107.o(i.TIM_Configuration) refers to stm32f10x_tim.o(i.TIM_DeInit) for TIM_DeInit
+ stm32f107.o(i.TIM_Configuration) refers to stm32f10x_tim.o(i.TIM_TimeBaseInit) for TIM_TimeBaseInit
+ stm32f107.o(i.TIM_Configuration) refers to stm32f10x_tim.o(i.TIM_ClearFlag) for TIM_ClearFlag
+ stm32f107.o(i.TIM_Configuration) refers to stm32f10x_tim.o(i.TIM_ITConfig) for TIM_ITConfig
+ stm32f107.o(i.TIM_Configuration) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd
+ netconf.o(i.Display_Periodic_Handle) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ netconf.o(i.Display_Periodic_Handle) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d
+ netconf.o(i.Display_Periodic_Handle) refers to _printf_dec.o(.text) for _printf_int_dec
+ netconf.o(i.Display_Periodic_Handle) refers to __2sprintf.o(.text) for __2sprintf
+ netconf.o(i.Display_Periodic_Handle) refers to netconf.o(.data) for .data
+ netconf.o(i.Display_Periodic_Handle) refers to netconf.o(.bss) for .bss
+ netconf.o(i.LwIP_Init) refers to mem.o(i.mem_init) for mem_init
+ netconf.o(i.LwIP_Init) refers to memp.o(i.memp_init) for memp_init
+ netconf.o(i.LwIP_Init) refers to netconf.o(i.My_IP4_ADDR) for My_IP4_ADDR
+ netconf.o(i.LwIP_Init) refers to ethernetif.o(i.Set_MAC_Address) for Set_MAC_Address
+ netconf.o(i.LwIP_Init) refers to netif.o(i.netif_add) for netif_add
+ netconf.o(i.LwIP_Init) refers to netif.o(i.netif_set_default) for netif_set_default
+ netconf.o(i.LwIP_Init) refers to netif.o(i.netif_set_up) for netif_set_up
+ netconf.o(i.LwIP_Init) refers to etharp.o(i.ethernet_input) for ethernet_input
+ netconf.o(i.LwIP_Init) refers to ethernetif.o(i.ethernetif_init) for ethernetif_init
+ netconf.o(i.LwIP_Init) refers to netconf.o(.bss) for .bss
+ netconf.o(i.LwIP_Periodic_Handle) refers to tcp.o(i.tcp_tmr) for tcp_tmr
+ netconf.o(i.LwIP_Periodic_Handle) refers to etharp.o(i.etharp_tmr) for etharp_tmr
+ netconf.o(i.LwIP_Periodic_Handle) refers to netconf.o(.data) for .data
+ netconf.o(i.LwIP_Pkt_Handle) refers to ethernetif.o(i.ethernetif_input) for ethernetif_input
+ netconf.o(i.LwIP_Pkt_Handle) refers to netconf.o(.bss) for .bss
+ netconf.o(i.My_IP4_ADDR) refers to inet.o(i.htonl) for htonl
+ tcp_client.o(i.Check_TCP_Connect) refers to tcp_client.o(i.TCP_Client_Init) for TCP_Client_Init
+ tcp_client.o(i.Check_TCP_Connect) refers to tcp_client.o(.data) for .data
+ tcp_client.o(i.Check_TCP_Connect) refers to tcp.o(.data) for tcp_active_pcbs
+ tcp_client.o(i.TCP_Client_Init) refers to inet.o(i.htonl) for htonl
+ tcp_client.o(i.TCP_Client_Init) refers to tcp.o(i.tcp_new) for tcp_new
+ tcp_client.o(i.TCP_Client_Init) refers to tcp.o(i.tcp_bind) for tcp_bind
+ tcp_client.o(i.TCP_Client_Init) refers to tcp.o(i.tcp_connect) for tcp_connect
+ tcp_client.o(i.TCP_Client_Init) refers to tcp.o(i.tcp_recv) for tcp_recv
+ tcp_client.o(i.TCP_Client_Init) refers to ip_addr.o(.constdata) for ip_addr_any
+ tcp_client.o(i.TCP_Client_Init) refers to tcp_client.o(i.TCP_Connected) for TCP_Connected
+ tcp_client.o(i.TCP_Client_Init) refers to tcp_client.o(i.TCP_Client_Recv) for TCP_Client_Recv
+ tcp_client.o(i.TCP_Client_Recv) refers to tcp.o(i.tcp_recved) for tcp_recved
+ tcp_client.o(i.TCP_Client_Recv) refers to strncpy.o(.text) for strncpy
+ tcp_client.o(i.TCP_Client_Recv) refers to usart.o(i.USART4_printf) for USART4_printf
+ tcp_client.o(i.TCP_Client_Recv) refers to delay.o(i.delay_ms) for delay_ms
+ tcp_client.o(i.TCP_Client_Recv) refers to tcp.o(i.tcp_close) for tcp_close
+ tcp_client.o(i.TCP_Client_Recv) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp_client.o(i.TCP_Client_Recv) refers to tcp_client.o(.bss) for .bss
+ tcp_client.o(i.TCP_Client_Recv) refers to tcp_client.o(.data) for .data
+ tcp_client.o(i.TCP_Client_Send_Data) refers to tcp_out.o(i.tcp_write) for tcp_write
+ tcp_client.o(i.TCP_Client_Send_Data) refers to tcp_out.o(i.tcp_output) for tcp_output
+ hx711.o(i.HX711_Read) refers to delay.o(i.delay_us) for delay_us
+ hx711.o(i.Init_HX711pin) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ hx711.o(i.Init_HX711pin) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ hx711.o(i.Init_HX711pin) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+ sci.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus
+ sci.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit
+ sci.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus
+ sci.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit
+ sci.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ sci.o(i.USART_Configuration) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ sci.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init
+ sci.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig
+ sci.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd
+ sci.o(i.USART_Configuration) refers to stm32f10x_usart.o(i.USART_ClearITPendingBit) for USART_ClearITPendingBit
+ sci.o(i.USART_Configuration) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd
+ sci.o(i.USART_Configuration) refers to stm32f10x_gpio.o(i.GPIO_PinRemapConfig) for GPIO_PinRemapConfig
+ stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+ stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
+ stm32f10x_usart.o(i.USART_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
+ stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+ stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+ stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for .data
+ stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus
+ stm32f10x_spi.o(i.I2S_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
+ stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+ stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
+ stm32f10x_flash.o(i.FLASH_EnableWriteProtection) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_EraseAllPages) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_ErasePage) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_ProgramHalfWord) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_ProgramOptionByteData) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_ProgramWord) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_ReadOutProtection) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_UserOptionByteConfig) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation
+ stm32f10x_flash.o(i.FLASH_WaitForLastOperation) refers to stm32f10x_flash.o(i.FLASH_GetStatus) for FLASH_GetStatus
+ stm32f10x_adc.o(i.ADC_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+ stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
+ stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd
+ stm32f10x_tim.o(i.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
+ stm32f10x_tim.o(i.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig
+ stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler
+ stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
+ stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
+ stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
+ stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
+ stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler
+ stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
+ stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
+ stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler
+ stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
+ stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler
+ stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config
+ stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger
+ stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config
+ stm32f10x_i2c.o(i.I2C_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd
+ stm32f10x_i2c.o(i.I2C_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
+ stm32_eth.o(i.ETH_DMAPTPRxDescChainInit) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_DMAPTPTxDescChainInit) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_DMARxDescChainInit) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_DMARxDescRingInit) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_DMATxDescChainInit) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_DMATxDescRingInit) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_DeInit) refers to stm32f10x_rcc.o(i.RCC_AHBPeriphResetCmd) for RCC_AHBPeriphResetCmd
+ stm32_eth.o(i.ETH_DropRxPkt) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_GetRxPktSize) refers to stm32_eth.o(i.ETH_GetDMARxDescFrameLength) for ETH_GetDMARxDescFrameLength
+ stm32_eth.o(i.ETH_GetRxPktSize) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_HandlePTPRxPkt) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_HandlePTPTxPkt) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_HandleRxPkt) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_HandleTxPkt) refers to stm32_eth.o(.data) for .data
+ stm32_eth.o(i.ETH_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq
+ stm32_eth.o(i.ETH_Init) refers to stm32_eth.o(i.ETH_WritePHYRegister) for ETH_WritePHYRegister
+ stm32_eth.o(i.ETH_Init) refers to stm32_eth.o(i.ETH_Delay) for ETH_Delay
+ stm32_eth.o(i.ETH_Init) refers to stm32_eth.o(i.ETH_ReadPHYRegister) for ETH_ReadPHYRegister
+ stm32_eth.o(i.ETH_PHYLoopBackCmd) refers to stm32_eth.o(i.ETH_ReadPHYRegister) for ETH_ReadPHYRegister
+ stm32_eth.o(i.ETH_PHYLoopBackCmd) refers to stm32_eth.o(i.ETH_WritePHYRegister) for ETH_WritePHYRegister
+ stm32_eth.o(i.ETH_Start) refers to stm32_eth.o(i.ETH_MACTransmissionCmd) for ETH_MACTransmissionCmd
+ stm32_eth.o(i.ETH_Start) refers to stm32_eth.o(i.ETH_FlushTransmitFIFO) for ETH_FlushTransmitFIFO
+ stm32_eth.o(i.ETH_Start) refers to stm32_eth.o(i.ETH_MACReceptionCmd) for ETH_MACReceptionCmd
+ stm32_eth.o(i.ETH_Start) refers to stm32_eth.o(i.ETH_DMATransmissionCmd) for ETH_DMATransmissionCmd
+ stm32_eth.o(i.ETH_Start) refers to stm32_eth.o(i.ETH_DMAReceptionCmd) for ETH_DMAReceptionCmd
+ ethernetif.o(i.ETH_GetCurrentTxBuffer) refers to stm32_eth.o(.data) for DMATxDescToSet
+ ethernetif.o(i.ETH_RxPkt_ChainMode) refers to stm32_eth.o(.data) for DMARxDescToGet
+ ethernetif.o(i.ETH_TxPkt_ChainMode) refers to stm32_eth.o(.data) for DMATxDescToSet
+ ethernetif.o(i.Set_MAC_Address) refers to stm32_eth.o(i.ETH_MACAddressConfig) for ETH_MACAddressConfig
+ ethernetif.o(i.Set_MAC_Address) refers to ethernetif.o(.data) for .data
+ ethernetif.o(i.ethernetif_init) refers to mem.o(i.mem_malloc) for mem_malloc
+ ethernetif.o(i.ethernetif_init) refers to ethernetif.o(i.low_level_init) for low_level_init
+ ethernetif.o(i.ethernetif_init) refers to etharp.o(i.etharp_output) for etharp_output
+ ethernetif.o(i.ethernetif_init) refers to ethernetif.o(i.low_level_output) for low_level_output
+ ethernetif.o(i.ethernetif_input) refers to ethernetif.o(i.ETH_RxPkt_ChainMode) for ETH_RxPkt_ChainMode
+ ethernetif.o(i.ethernetif_input) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ ethernetif.o(i.ethernetif_input) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ ethernetif.o(i.ethernetif_input) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ ethernetif.o(i.low_level_init) refers to stm32_eth.o(i.ETH_DMATxDescChainInit) for ETH_DMATxDescChainInit
+ ethernetif.o(i.low_level_init) refers to stm32_eth.o(i.ETH_DMARxDescChainInit) for ETH_DMARxDescChainInit
+ ethernetif.o(i.low_level_init) refers to stm32_eth.o(i.ETH_DMARxDescReceiveITConfig) for ETH_DMARxDescReceiveITConfig
+ ethernetif.o(i.low_level_init) refers to stm32_eth.o(i.ETH_DMATxDescChecksumInsertionConfig) for ETH_DMATxDescChecksumInsertionConfig
+ ethernetif.o(i.low_level_init) refers to stm32_eth.o(i.ETH_Start) for ETH_Start
+ ethernetif.o(i.low_level_init) refers to ethernetif.o(.data) for .data
+ ethernetif.o(i.low_level_init) refers to ethernetif.o(.bss) for .bss
+ ethernetif.o(i.low_level_output) refers to ethernetif.o(i.ETH_GetCurrentTxBuffer) for ETH_GetCurrentTxBuffer
+ ethernetif.o(i.low_level_output) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ ethernetif.o(i.low_level_output) refers to ethernetif.o(i.ETH_TxPkt_ChainMode) for ETH_TxPkt_ChainMode
+ ethernetif.o(.data) refers to ethernetif.o(.bss) for DMATxDscrTab
+ tcp.o(i.tcp_abandon) refers to tcp.o(i.tcp_pcb_remove) for tcp_pcb_remove
+ tcp.o(i.tcp_abandon) refers to tcp.o(i.tcp_segs_free) for tcp_segs_free
+ tcp.o(i.tcp_abandon) refers to memp.o(i.memp_free) for memp_free
+ tcp.o(i.tcp_abandon) refers to tcp_out.o(i.tcp_rst) for tcp_rst
+ tcp.o(i.tcp_abandon) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_alloc) refers to memp.o(i.memp_malloc) for memp_malloc
+ tcp.o(i.tcp_alloc) refers to tcp.o(i.tcp_abandon) for tcp_abandon
+ tcp.o(i.tcp_alloc) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+ tcp.o(i.tcp_alloc) refers to tcp.o(i.tcp_next_iss) for tcp_next_iss
+ tcp.o(i.tcp_alloc) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_alloc) refers to tcp.o(i.tcp_recv_null) for tcp_recv_null
+ tcp.o(i.tcp_bind) refers to tcp.o(i.tcp_new_port) for tcp_new_port
+ tcp.o(i.tcp_bind) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_close) refers to memp.o(i.memp_free) for memp_free
+ tcp.o(i.tcp_close) refers to tcp.o(i.tcp_pcb_remove) for tcp_pcb_remove
+ tcp.o(i.tcp_close) refers to tcp_out.o(i.tcp_send_ctrl) for tcp_send_ctrl
+ tcp.o(i.tcp_close) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp.o(i.tcp_close) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_connect) refers to tcp.o(i.tcp_new_port) for tcp_new_port
+ tcp.o(i.tcp_connect) refers to tcp.o(i.tcp_next_iss) for tcp_next_iss
+ tcp.o(i.tcp_connect) refers to tcp.o(i.tcp_eff_send_mss) for tcp_eff_send_mss
+ tcp.o(i.tcp_connect) refers to tcp_out.o(i.tcp_enqueue) for tcp_enqueue
+ tcp.o(i.tcp_connect) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp.o(i.tcp_connect) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_eff_send_mss) refers to ip.o(i.ip_route) for ip_route
+ tcp.o(i.tcp_fasttmr) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp.o(i.tcp_fasttmr) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp.o(i.tcp_fasttmr) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_listen_with_backlog) refers to memp.o(i.memp_malloc) for memp_malloc
+ tcp.o(i.tcp_listen_with_backlog) refers to memp.o(i.memp_free) for memp_free
+ tcp.o(i.tcp_listen_with_backlog) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_listen_with_backlog) refers to tcp.o(i.tcp_accept_null) for tcp_accept_null
+ tcp.o(i.tcp_new) refers to tcp.o(i.tcp_alloc) for tcp_alloc
+ tcp.o(i.tcp_new_port) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_next_iss) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_pcb_purge) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp.o(i.tcp_pcb_purge) refers to tcp.o(i.tcp_segs_free) for tcp_segs_free
+ tcp.o(i.tcp_pcb_remove) refers to tcp.o(i.tcp_pcb_purge) for tcp_pcb_purge
+ tcp.o(i.tcp_pcb_remove) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp.o(i.tcp_pcb_remove) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_recv_null) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp.o(i.tcp_recv_null) refers to tcp.o(i.tcp_close) for tcp_close
+ tcp.o(i.tcp_recved) refers to tcp.o(i.tcp_update_rcv_ann_wnd) for tcp_update_rcv_ann_wnd
+ tcp.o(i.tcp_recved) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp.o(i.tcp_seg_free) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp.o(i.tcp_seg_free) refers to memp.o(i.memp_free) for memp_free
+ tcp.o(i.tcp_segs_free) refers to tcp.o(i.tcp_seg_free) for tcp_seg_free
+ tcp.o(i.tcp_slowtmr) refers to tcp_out.o(i.tcp_zero_window_probe) for tcp_zero_window_probe
+ tcp.o(i.tcp_slowtmr) refers to tcp_out.o(i.tcp_rexmit_rto) for tcp_rexmit_rto
+ tcp.o(i.tcp_slowtmr) refers to tcp.o(i.tcp_abandon) for tcp_abandon
+ tcp.o(i.tcp_slowtmr) refers to tcp_out.o(i.tcp_keepalive) for tcp_keepalive
+ tcp.o(i.tcp_slowtmr) refers to tcp.o(i.tcp_pcb_purge) for tcp_pcb_purge
+ tcp.o(i.tcp_slowtmr) refers to memp.o(i.memp_free) for memp_free
+ tcp.o(i.tcp_slowtmr) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp.o(i.tcp_slowtmr) refers to tcp.o(.data) for .data
+ tcp.o(i.tcp_slowtmr) refers to tcp.o(.constdata) for .constdata
+ tcp.o(i.tcp_tmr) refers to tcp.o(i.tcp_fasttmr) for tcp_fasttmr
+ tcp.o(i.tcp_tmr) refers to tcp.o(i.tcp_slowtmr) for tcp_slowtmr
+ tcp.o(i.tcp_tmr) refers to tcp.o(.data) for .data
+ tcp_in.o(i.tcp_input) refers to inet.o(i.ntohs) for ntohs
+ tcp_in.o(i.tcp_input) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ tcp_in.o(i.tcp_input) refers to ip_addr.o(i.ip_addr_isbroadcast) for ip_addr_isbroadcast
+ tcp_in.o(i.tcp_input) refers to inet.o(i.ntohl) for ntohl
+ tcp_in.o(i.tcp_input) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp_in.o(i.tcp_input) refers to tcp_in.o(i.tcp_listen_input) for tcp_listen_input
+ tcp_in.o(i.tcp_input) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp_in.o(i.tcp_input) refers to tcp_in.o(i.tcp_process) for tcp_process
+ tcp_in.o(i.tcp_input) refers to tcp.o(i.tcp_pcb_remove) for tcp_pcb_remove
+ tcp_in.o(i.tcp_input) refers to memp.o(i.memp_free) for memp_free
+ tcp_in.o(i.tcp_input) refers to tcp_out.o(i.tcp_rst) for tcp_rst
+ tcp_in.o(i.tcp_input) refers to tcp_in.o(.data) for .data
+ tcp_in.o(i.tcp_input) refers to tcp.o(.data) for tcp_active_pcbs
+ tcp_in.o(i.tcp_input) refers to tcp_in.o(.bss) for .bss
+ tcp_in.o(i.tcp_listen_input) refers to tcp_out.o(i.tcp_rst) for tcp_rst
+ tcp_in.o(i.tcp_listen_input) refers to tcp.o(i.tcp_alloc) for tcp_alloc
+ tcp_in.o(i.tcp_listen_input) refers to tcp_in.o(i.tcp_parseopt) for tcp_parseopt
+ tcp_in.o(i.tcp_listen_input) refers to tcp.o(i.tcp_eff_send_mss) for tcp_eff_send_mss
+ tcp_in.o(i.tcp_listen_input) refers to tcp_out.o(i.tcp_enqueue) for tcp_enqueue
+ tcp_in.o(i.tcp_listen_input) refers to tcp.o(i.tcp_abandon) for tcp_abandon
+ tcp_in.o(i.tcp_listen_input) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp_in.o(i.tcp_listen_input) refers to tcp_in.o(.data) for .data
+ tcp_in.o(i.tcp_listen_input) refers to tcp.o(.data) for tcp_active_pcbs
+ tcp_in.o(i.tcp_parseopt) refers to inet.o(i.ntohs) for ntohs
+ tcp_in.o(i.tcp_parseopt) refers to tcp_in.o(.data) for .data
+ tcp_in.o(i.tcp_process) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp_in.o(i.tcp_process) refers to tcp_in.o(i.tcp_parseopt) for tcp_parseopt
+ tcp_in.o(i.tcp_process) refers to inet.o(i.ntohl) for ntohl
+ tcp_in.o(i.tcp_process) refers to tcp.o(i.tcp_eff_send_mss) for tcp_eff_send_mss
+ tcp_in.o(i.tcp_process) refers to tcp.o(i.tcp_seg_free) for tcp_seg_free
+ tcp_in.o(i.tcp_process) refers to tcp.o(i.tcp_abandon) for tcp_abandon
+ tcp_in.o(i.tcp_process) refers to tcp_in.o(i.tcp_receive) for tcp_receive
+ tcp_in.o(i.tcp_process) refers to tcp_out.o(i.tcp_rst) for tcp_rst
+ tcp_in.o(i.tcp_process) refers to tcp_out.o(i.tcp_rexmit) for tcp_rexmit
+ tcp_in.o(i.tcp_process) refers to tcp.o(i.tcp_pcb_purge) for tcp_pcb_purge
+ tcp_in.o(i.tcp_process) refers to tcp_in.o(.data) for .data
+ tcp_in.o(i.tcp_process) refers to tcp.o(.data) for tcp_ticks
+ tcp_in.o(i.tcp_receive) refers to tcp_out.o(i.tcp_rexmit) for tcp_rexmit
+ tcp_in.o(i.tcp_receive) refers to pbuf.o(i.pbuf_clen) for pbuf_clen
+ tcp_in.o(i.tcp_receive) refers to tcp.o(i.tcp_seg_free) for tcp_seg_free
+ tcp_in.o(i.tcp_receive) refers to inet.o(i.ntohl) for ntohl
+ tcp_in.o(i.tcp_receive) refers to inet.o(i.ntohs) for ntohs
+ tcp_in.o(i.tcp_receive) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ tcp_in.o(i.tcp_receive) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp_in.o(i.tcp_receive) refers to inet.o(i.htons) for htons
+ tcp_in.o(i.tcp_receive) refers to pbuf.o(i.pbuf_realloc) for pbuf_realloc
+ tcp_in.o(i.tcp_receive) refers to tcp.o(i.tcp_update_rcv_ann_wnd) for tcp_update_rcv_ann_wnd
+ tcp_in.o(i.tcp_receive) refers to tcp_in.o(.data) for .data
+ tcp_in.o(i.tcp_receive) refers to tcp.o(.data) for tcp_ticks
+ tcp_in.o(i.tcp_receive) refers to tcp_in.o(.bss) for .bss
+ tcp_out.o(i.tcp_enqueue) refers to memp.o(i.memp_malloc) for memp_malloc
+ tcp_out.o(i.tcp_enqueue) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ tcp_out.o(i.tcp_enqueue) refers to pbuf.o(i.pbuf_clen) for pbuf_clen
+ tcp_out.o(i.tcp_enqueue) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ tcp_out.o(i.tcp_enqueue) refers to pbuf.o(i.pbuf_cat) for pbuf_cat
+ tcp_out.o(i.tcp_enqueue) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ tcp_out.o(i.tcp_enqueue) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp_out.o(i.tcp_enqueue) refers to inet.o(i.htons) for htons
+ tcp_out.o(i.tcp_enqueue) refers to inet.o(i.htonl) for htonl
+ tcp_out.o(i.tcp_enqueue) refers to inet.o(i.ntohs) for ntohs
+ tcp_out.o(i.tcp_enqueue) refers to tcp.o(i.tcp_segs_free) for tcp_segs_free
+ tcp_out.o(i.tcp_enqueue) refers to memp.o(i.memp_free) for memp_free
+ tcp_out.o(i.tcp_keepalive) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ tcp_out.o(i.tcp_keepalive) refers to inet.o(i.htonl) for htonl
+ tcp_out.o(i.tcp_keepalive) refers to tcp_out.o(i.tcp_output_set_header) for tcp_output_set_header
+ tcp_out.o(i.tcp_keepalive) refers to ip.o(i.ip_output) for ip_output
+ tcp_out.o(i.tcp_keepalive) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp_out.o(i.tcp_output) refers to inet.o(i.ntohl) for ntohl
+ tcp_out.o(i.tcp_output) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ tcp_out.o(i.tcp_output) refers to inet.o(i.htonl) for htonl
+ tcp_out.o(i.tcp_output) refers to tcp_out.o(i.tcp_output_set_header) for tcp_output_set_header
+ tcp_out.o(i.tcp_output) refers to ip.o(i.ip_output) for ip_output
+ tcp_out.o(i.tcp_output) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp_out.o(i.tcp_output) refers to inet.o(i.ntohs) for ntohs
+ tcp_out.o(i.tcp_output) refers to inet.o(i.htons) for htons
+ tcp_out.o(i.tcp_output) refers to tcp_out.o(i.tcp_output_segment) for tcp_output_segment
+ tcp_out.o(i.tcp_output) refers to tcp.o(i.tcp_seg_free) for tcp_seg_free
+ tcp_out.o(i.tcp_output) refers to tcp_in.o(.data) for tcp_input_pcb
+ tcp_out.o(i.tcp_output_segment) refers to inet.o(i.htonl) for htonl
+ tcp_out.o(i.tcp_output_segment) refers to inet.o(i.htons) for htons
+ tcp_out.o(i.tcp_output_segment) refers to ip.o(i.ip_route) for ip_route
+ tcp_out.o(i.tcp_output_segment) refers to inet.o(i.ntohl) for ntohl
+ tcp_out.o(i.tcp_output_segment) refers to ip.o(i.ip_output) for ip_output
+ tcp_out.o(i.tcp_output_segment) refers to tcp.o(.data) for tcp_ticks
+ tcp_out.o(i.tcp_output_set_header) refers to inet.o(i.htons) for htons
+ tcp_out.o(i.tcp_output_set_header) refers to inet.o(i.htonl) for htonl
+ tcp_out.o(i.tcp_output_set_header) refers to inet.o(i.ntohs) for ntohs
+ tcp_out.o(i.tcp_rexmit) refers to inet.o(i.ntohl) for ntohl
+ tcp_out.o(i.tcp_rexmit) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp_out.o(i.tcp_rexmit_rto) refers to tcp_out.o(i.tcp_output) for tcp_output
+ tcp_out.o(i.tcp_rst) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ tcp_out.o(i.tcp_rst) refers to inet.o(i.htons) for htons
+ tcp_out.o(i.tcp_rst) refers to inet.o(i.htonl) for htonl
+ tcp_out.o(i.tcp_rst) refers to inet.o(i.ntohs) for ntohs
+ tcp_out.o(i.tcp_rst) refers to ip.o(i.ip_output) for ip_output
+ tcp_out.o(i.tcp_rst) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ tcp_out.o(i.tcp_send_ctrl) refers to tcp_out.o(i.tcp_enqueue) for tcp_enqueue
+ tcp_out.o(i.tcp_write) refers to tcp_out.o(i.tcp_enqueue) for tcp_enqueue
+ tcp_out.o(i.tcp_zero_window_probe) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ tcp_out.o(i.tcp_zero_window_probe) refers to tcp_out.o(i.tcp_output_set_header) for tcp_output_set_header
+ tcp_out.o(i.tcp_zero_window_probe) refers to ip.o(i.ip_output) for ip_output
+ tcp_out.o(i.tcp_zero_window_probe) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ udp.o(i.udp_bind) refers to udp.o(.data) for .data
+ udp.o(i.udp_connect) refers to udp.o(i.udp_bind) for udp_bind
+ udp.o(i.udp_connect) refers to udp.o(.data) for .data
+ udp.o(i.udp_disconnect) refers to ip_addr.o(.constdata) for ip_addr_any
+ udp.o(i.udp_input) refers to inet.o(i.ntohs) for ntohs
+ udp.o(i.udp_input) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ udp.o(i.udp_input) refers to ip_addr.o(i.ip_addr_isbroadcast) for ip_addr_isbroadcast
+ udp.o(i.udp_input) refers to inet.o(i.ntohl) for ntohl
+ udp.o(i.udp_input) refers to icmp.o(i.icmp_dest_unreach) for icmp_dest_unreach
+ udp.o(i.udp_input) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ udp.o(i.udp_input) refers to udp.o(.data) for .data
+ udp.o(i.udp_new) refers to memp.o(i.memp_malloc) for memp_malloc
+ udp.o(i.udp_new) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+ udp.o(i.udp_remove) refers to memp.o(i.memp_free) for memp_free
+ udp.o(i.udp_remove) refers to udp.o(.data) for .data
+ udp.o(i.udp_send) refers to udp.o(i.udp_sendto) for udp_sendto
+ udp.o(i.udp_sendto) refers to ip.o(i.ip_route) for ip_route
+ udp.o(i.udp_sendto) refers to udp.o(i.udp_sendto_if) for udp_sendto_if
+ udp.o(i.udp_sendto_if) refers to udp.o(i.udp_bind) for udp_bind
+ udp.o(i.udp_sendto_if) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ udp.o(i.udp_sendto_if) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ udp.o(i.udp_sendto_if) refers to pbuf.o(i.pbuf_chain) for pbuf_chain
+ udp.o(i.udp_sendto_if) refers to inet.o(i.htons) for htons
+ udp.o(i.udp_sendto_if) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ udp.o(i.udp_sendto_if) refers to ip.o(i.ip_output_if) for ip_output_if
+ init.o(i.lwip_init) refers to mem.o(i.mem_init) for mem_init
+ init.o(i.lwip_init) refers to memp.o(i.memp_init) for memp_init
+ mem.o(i.mem_calloc) refers to mem.o(i.mem_malloc) for mem_malloc
+ mem.o(i.mem_calloc) refers to rt_memclr.o(.text) for __aeabi_memclr
+ mem.o(i.mem_free) refers to mem.o(i.plug_holes) for plug_holes
+ mem.o(i.mem_free) refers to mem.o(.data) for .data
+ mem.o(i.mem_init) refers to mem.o(.bss) for .bss
+ mem.o(i.mem_init) refers to mem.o(.data) for .data
+ mem.o(i.mem_malloc) refers to mem.o(.data) for .data
+ mem.o(i.mem_realloc) refers to mem.o(.data) for .data
+ mem.o(i.plug_holes) refers to mem.o(.data) for .data
+ memp.o(i.memp_free) refers to memp.o(.bss) for .bss
+ memp.o(i.memp_init) refers to memp.o(.bss) for .bss
+ memp.o(i.memp_init) refers to memp.o(.constdata) for .constdata
+ memp.o(i.memp_malloc) refers to memp.o(.bss) for .bss
+ netif.o(i.netif_add) refers to netif.o(i.netif_set_addr) for netif_set_addr
+ netif.o(i.netif_add) refers to netif.o(.data) for .data
+ netif.o(i.netif_find) refers to netif.o(.data) for .data
+ netif.o(i.netif_remove) refers to netif.o(.data) for .data
+ netif.o(i.netif_set_addr) refers to netif.o(i.netif_set_ipaddr) for netif_set_ipaddr
+ netif.o(i.netif_set_addr) refers to netif.o(i.netif_set_netmask) for netif_set_netmask
+ netif.o(i.netif_set_addr) refers to netif.o(i.netif_set_gw) for netif_set_gw
+ netif.o(i.netif_set_default) refers to netif.o(.data) for .data
+ netif.o(i.netif_set_ipaddr) refers to tcp.o(i.tcp_abandon) for tcp_abandon
+ netif.o(i.netif_set_ipaddr) refers to tcp.o(.data) for tcp_active_pcbs
+ netif.o(i.netif_set_up) refers to etharp.o(i.etharp_request) for etharp_request
+ pbuf.o(i.pbuf_alloc) refers to memp.o(i.memp_malloc) for memp_malloc
+ pbuf.o(i.pbuf_alloc) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ pbuf.o(i.pbuf_alloc) refers to mem.o(i.mem_malloc) for mem_malloc
+ pbuf.o(i.pbuf_chain) refers to pbuf.o(i.pbuf_cat) for pbuf_cat
+ pbuf.o(i.pbuf_chain) refers to pbuf.o(i.pbuf_ref) for pbuf_ref
+ pbuf.o(i.pbuf_coalesce) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ pbuf.o(i.pbuf_coalesce) refers to pbuf.o(i.pbuf_copy) for pbuf_copy
+ pbuf.o(i.pbuf_coalesce) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ pbuf.o(i.pbuf_copy) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ pbuf.o(i.pbuf_copy_partial) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ pbuf.o(i.pbuf_dechain) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ pbuf.o(i.pbuf_free) refers to mem.o(i.mem_free) for mem_free
+ pbuf.o(i.pbuf_free) refers to memp.o(i.memp_free) for memp_free
+ pbuf.o(i.pbuf_realloc) refers to mem.o(i.mem_realloc) for mem_realloc
+ pbuf.o(i.pbuf_realloc) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ pbuf.o(i.pbuf_take) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ raw.o(i.raw_input) refers to inet.o(i.ntohs) for ntohs
+ raw.o(i.raw_input) refers to raw.o(.data) for .data
+ raw.o(i.raw_new) refers to memp.o(i.memp_malloc) for memp_malloc
+ raw.o(i.raw_new) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+ raw.o(i.raw_new) refers to raw.o(.data) for .data
+ raw.o(i.raw_remove) refers to memp.o(i.memp_free) for memp_free
+ raw.o(i.raw_remove) refers to raw.o(.data) for .data
+ raw.o(i.raw_send) refers to raw.o(i.raw_sendto) for raw_sendto
+ raw.o(i.raw_sendto) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ raw.o(i.raw_sendto) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ raw.o(i.raw_sendto) refers to pbuf.o(i.pbuf_chain) for pbuf_chain
+ raw.o(i.raw_sendto) refers to ip.o(i.ip_route) for ip_route
+ raw.o(i.raw_sendto) refers to ip.o(i.ip_output_if) for ip_output_if
+ raw.o(i.raw_sendto) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ icmp.o(i.icmp_dest_unreach) refers to icmp.o(i.icmp_send_response) for icmp_send_response
+ icmp.o(i.icmp_input) refers to inet.o(i.ntohs) for ntohs
+ icmp.o(i.icmp_input) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ icmp.o(i.icmp_input) refers to inet.o(i.ntohl) for ntohl
+ icmp.o(i.icmp_input) refers to ip_addr.o(i.ip_addr_isbroadcast) for ip_addr_isbroadcast
+ icmp.o(i.icmp_input) refers to inet_chksum.o(i.inet_chksum_pbuf) for inet_chksum_pbuf
+ icmp.o(i.icmp_input) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ icmp.o(i.icmp_input) refers to pbuf.o(i.pbuf_copy) for pbuf_copy
+ icmp.o(i.icmp_input) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ icmp.o(i.icmp_input) refers to inet.o(i.htons) for htons
+ icmp.o(i.icmp_input) refers to ip.o(i.ip_output_if) for ip_output_if
+ icmp.o(i.icmp_send_response) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ icmp.o(i.icmp_send_response) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ icmp.o(i.icmp_send_response) refers to inet_chksum.o(i.inet_chksum) for inet_chksum
+ icmp.o(i.icmp_send_response) refers to ip.o(i.ip_output) for ip_output
+ icmp.o(i.icmp_send_response) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ icmp.o(i.icmp_time_exceeded) refers to icmp.o(i.icmp_send_response) for icmp_send_response
+ inet.o(i.inet_addr) refers to inet.o(i.inet_aton) for inet_aton
+ inet.o(i.inet_ntoa) refers to inet.o(.bss) for .bss
+ inet_chksum.o(i.inet_chksum) refers to inet_chksum.o(i.lwip_standard_chksum) for lwip_standard_chksum
+ inet_chksum.o(i.inet_chksum_pbuf) refers to inet_chksum.o(i.lwip_standard_chksum) for lwip_standard_chksum
+ inet_chksum.o(i.inet_chksum_pseudo) refers to inet_chksum.o(i.lwip_standard_chksum) for lwip_standard_chksum
+ inet_chksum.o(i.inet_chksum_pseudo) refers to inet.o(i.htons) for htons
+ inet_chksum.o(i.lwip_standard_chksum) refers to inet.o(i.htons) for htons
+ ip.o(i.ip_current_header) refers to ip.o(.data) for .data
+ ip.o(i.ip_current_netif) refers to ip.o(.data) for .data
+ ip.o(i.ip_input) refers to inet.o(i.ntohs) for ntohs
+ ip.o(i.ip_input) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ ip.o(i.ip_input) refers to pbuf.o(i.pbuf_realloc) for pbuf_realloc
+ ip.o(i.ip_input) refers to netif.o(i.netif_is_up) for netif_is_up
+ ip.o(i.ip_input) refers to ip_addr.o(i.ip_addr_isbroadcast) for ip_addr_isbroadcast
+ ip.o(i.ip_input) refers to inet.o(i.ntohl) for ntohl
+ ip.o(i.ip_input) refers to inet.o(i.htons) for htons
+ ip.o(i.ip_input) refers to ip_frag.o(i.ip_reass) for ip_reass
+ ip.o(i.ip_input) refers to raw.o(i.raw_input) for raw_input
+ ip.o(i.ip_input) refers to udp.o(i.udp_input) for udp_input
+ ip.o(i.ip_input) refers to tcp_in.o(i.tcp_input) for tcp_input
+ ip.o(i.ip_input) refers to icmp.o(i.icmp_input) for icmp_input
+ ip.o(i.ip_input) refers to icmp.o(i.icmp_dest_unreach) for icmp_dest_unreach
+ ip.o(i.ip_input) refers to netif.o(.data) for netif_list
+ ip.o(i.ip_input) refers to ip.o(.data) for .data
+ ip.o(i.ip_output) refers to ip.o(i.ip_route) for ip_route
+ ip.o(i.ip_output) refers to ip.o(i.ip_output_if) for ip_output_if
+ ip.o(i.ip_output_if) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ ip.o(i.ip_output_if) refers to inet.o(i.ntohs) for ntohs
+ ip.o(i.ip_output_if) refers to inet.o(i.htons) for htons
+ ip.o(i.ip_output_if) refers to ip_frag.o(i.ip_frag) for ip_frag
+ ip.o(i.ip_output_if) refers to ip.o(.data) for .data
+ ip.o(i.ip_route) refers to netif.o(i.netif_is_up) for netif_is_up
+ ip.o(i.ip_route) refers to netif.o(.data) for netif_list
+ ip_frag.o(i.ip_frag) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ ip_frag.o(i.ip_frag) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ ip_frag.o(i.ip_frag) refers to inet.o(i.ntohs) for ntohs
+ ip_frag.o(i.ip_frag) refers to pbuf.o(i.pbuf_copy_partial) for pbuf_copy_partial
+ ip_frag.o(i.ip_frag) refers to inet.o(i.htons) for htons
+ ip_frag.o(i.ip_frag) refers to inet_chksum.o(i.inet_chksum) for inet_chksum
+ ip_frag.o(i.ip_frag) refers to pbuf.o(i.pbuf_realloc) for pbuf_realloc
+ ip_frag.o(i.ip_frag) refers to pbuf.o(i.pbuf_chain) for pbuf_chain
+ ip_frag.o(i.ip_frag) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ ip_frag.o(i.ip_frag) refers to ip_frag.o(.bss) for .bss
+ ip_frag.o(i.ip_reass) refers to inet.o(i.ntohs) for ntohs
+ ip_frag.o(i.ip_reass) refers to pbuf.o(i.pbuf_clen) for pbuf_clen
+ ip_frag.o(i.ip_reass) refers to ip_frag.o(i.ip_reass_remove_oldest_datagram) for ip_reass_remove_oldest_datagram
+ ip_frag.o(i.ip_reass) refers to memp.o(i.memp_malloc) for memp_malloc
+ ip_frag.o(i.ip_reass) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
+ ip_frag.o(i.ip_reass) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ ip_frag.o(i.ip_reass) refers to ip_frag.o(i.ip_reass_chain_frag_into_datagram_and_validate) for ip_reass_chain_frag_into_datagram_and_validate
+ ip_frag.o(i.ip_reass) refers to inet.o(i.htons) for htons
+ ip_frag.o(i.ip_reass) refers to inet_chksum.o(i.inet_chksum) for inet_chksum
+ ip_frag.o(i.ip_reass) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ ip_frag.o(i.ip_reass) refers to pbuf.o(i.pbuf_cat) for pbuf_cat
+ ip_frag.o(i.ip_reass) refers to ip_frag.o(i.ip_reass_dequeue_datagram) for ip_reass_dequeue_datagram
+ ip_frag.o(i.ip_reass) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ ip_frag.o(i.ip_reass) refers to ip_frag.o(.data) for .data
+ ip_frag.o(i.ip_reass_chain_frag_into_datagram_and_validate) refers to inet.o(i.ntohs) for ntohs
+ ip_frag.o(i.ip_reass_chain_frag_into_datagram_and_validate) refers to pbuf.o(i.pbuf_clen) for pbuf_clen
+ ip_frag.o(i.ip_reass_chain_frag_into_datagram_and_validate) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ ip_frag.o(i.ip_reass_chain_frag_into_datagram_and_validate) refers to ip_frag.o(.data) for .data
+ ip_frag.o(i.ip_reass_dequeue_datagram) refers to memp.o(i.memp_free) for memp_free
+ ip_frag.o(i.ip_reass_dequeue_datagram) refers to ip_frag.o(.data) for .data
+ ip_frag.o(i.ip_reass_free_complete_datagram) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy
+ ip_frag.o(i.ip_reass_free_complete_datagram) refers to icmp.o(i.icmp_time_exceeded) for icmp_time_exceeded
+ ip_frag.o(i.ip_reass_free_complete_datagram) refers to pbuf.o(i.pbuf_clen) for pbuf_clen
+ ip_frag.o(i.ip_reass_free_complete_datagram) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ ip_frag.o(i.ip_reass_free_complete_datagram) refers to ip_frag.o(i.ip_reass_dequeue_datagram) for ip_reass_dequeue_datagram
+ ip_frag.o(i.ip_reass_free_complete_datagram) refers to ip_frag.o(.data) for .data
+ ip_frag.o(i.ip_reass_remove_oldest_datagram) refers to ip_frag.o(i.ip_reass_free_complete_datagram) for ip_reass_free_complete_datagram
+ ip_frag.o(i.ip_reass_remove_oldest_datagram) refers to ip_frag.o(.data) for .data
+ ip_frag.o(i.ip_reass_tmr) refers to ip_frag.o(i.ip_reass_free_complete_datagram) for ip_reass_free_complete_datagram
+ ip_frag.o(i.ip_reass_tmr) refers to ip_frag.o(.data) for .data
+ etharp.o(i.etharp_arp_input) refers to inet.o(i.htons) for htons
+ etharp.o(i.etharp_arp_input) refers to etharp.o(i.update_arp_entry) for update_arp_entry
+ etharp.o(i.etharp_arp_input) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ etharp.o(i.etharp_find_addr) refers to etharp.o(i.find_entry) for find_entry
+ etharp.o(i.etharp_find_addr) refers to etharp.o(.bss) for .bss
+ etharp.o(i.etharp_ip_input) refers to etharp.o(i.update_arp_entry) for update_arp_entry
+ etharp.o(i.etharp_output) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ etharp.o(i.etharp_output) refers to ip_addr.o(i.ip_addr_isbroadcast) for ip_addr_isbroadcast
+ etharp.o(i.etharp_output) refers to inet.o(i.ntohl) for ntohl
+ etharp.o(i.etharp_output) refers to etharp.o(i.etharp_send_ip) for etharp_send_ip
+ etharp.o(i.etharp_output) refers to etharp.o(i.etharp_query) for etharp_query
+ etharp.o(i.etharp_output) refers to etharp.o(.constdata) for .constdata
+ etharp.o(i.etharp_query) refers to ip_addr.o(i.ip_addr_isbroadcast) for ip_addr_isbroadcast
+ etharp.o(i.etharp_query) refers to inet.o(i.ntohl) for ntohl
+ etharp.o(i.etharp_query) refers to etharp.o(i.find_entry) for find_entry
+ etharp.o(i.etharp_query) refers to etharp.o(i.etharp_request) for etharp_request
+ etharp.o(i.etharp_query) refers to etharp.o(i.etharp_send_ip) for etharp_send_ip
+ etharp.o(i.etharp_query) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ etharp.o(i.etharp_query) refers to pbuf.o(i.pbuf_copy) for pbuf_copy
+ etharp.o(i.etharp_query) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ etharp.o(i.etharp_query) refers to pbuf.o(i.pbuf_ref) for pbuf_ref
+ etharp.o(i.etharp_query) refers to memp.o(i.memp_malloc) for memp_malloc
+ etharp.o(i.etharp_query) refers to etharp.o(.bss) for .bss
+ etharp.o(i.etharp_raw) refers to pbuf.o(i.pbuf_alloc) for pbuf_alloc
+ etharp.o(i.etharp_raw) refers to inet.o(i.htons) for htons
+ etharp.o(i.etharp_raw) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ etharp.o(i.etharp_request) refers to etharp.o(i.etharp_raw) for etharp_raw
+ etharp.o(i.etharp_request) refers to etharp.o(.constdata) for .constdata
+ etharp.o(i.etharp_send_ip) refers to inet.o(i.htons) for htons
+ etharp.o(i.etharp_tmr) refers to etharp.o(i.free_etharp_q) for free_etharp_q
+ etharp.o(i.etharp_tmr) refers to etharp.o(.bss) for .bss
+ etharp.o(i.ethernet_input) refers to inet.o(i.htons) for htons
+ etharp.o(i.ethernet_input) refers to etharp.o(i.etharp_ip_input) for etharp_ip_input
+ etharp.o(i.ethernet_input) refers to pbuf.o(i.pbuf_header) for pbuf_header
+ etharp.o(i.ethernet_input) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ etharp.o(i.ethernet_input) refers to ip.o(i.ip_input) for ip_input
+ etharp.o(i.ethernet_input) refers to etharp.o(i.etharp_arp_input) for etharp_arp_input
+ etharp.o(i.find_entry) refers to etharp.o(i.free_etharp_q) for free_etharp_q
+ etharp.o(i.find_entry) refers to etharp.o(.bss) for .bss
+ etharp.o(i.find_entry) refers to etharp.o(.data) for .data
+ etharp.o(i.free_etharp_q) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ etharp.o(i.free_etharp_q) refers to memp.o(i.memp_free) for memp_free
+ etharp.o(i.update_arp_entry) refers to ip_addr.o(i.ip_addr_isbroadcast) for ip_addr_isbroadcast
+ etharp.o(i.update_arp_entry) refers to inet.o(i.ntohl) for ntohl
+ etharp.o(i.update_arp_entry) refers to etharp.o(i.find_entry) for find_entry
+ etharp.o(i.update_arp_entry) refers to memp.o(i.memp_free) for memp_free
+ etharp.o(i.update_arp_entry) refers to etharp.o(i.etharp_send_ip) for etharp_send_ip
+ etharp.o(i.update_arp_entry) refers to pbuf.o(i.pbuf_free) for pbuf_free
+ etharp.o(i.update_arp_entry) refers to etharp.o(.bss) for .bss
+ system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72
+ startup_stm32f10x_cl.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_cl.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_cl.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_cl.o(RESET) refers to startup_stm32f10x_cl.o(STACK) for __initial_sp
+ startup_stm32f10x_cl.o(RESET) refers to startup_stm32f10x_cl.o(.text) for Reset_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.NMI_Handler) for NMI_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.HardFault_Handler) for HardFault_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.MemManage_Handler) for MemManage_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.BusFault_Handler) for BusFault_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.UsageFault_Handler) for UsageFault_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.SVC_Handler) for SVC_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.DebugMon_Handler) for DebugMon_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.PendSV_Handler) for PendSV_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.SysTick_Handler) for SysTick_Handler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f107.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
+ startup_stm32f10x_cl.o(RESET) refers to sci.o(i.USART1_IRQHandler) for USART1_IRQHandler
+ startup_stm32f10x_cl.o(RESET) refers to sci.o(i.USART2_IRQHandler) for USART2_IRQHandler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.EXTI15_10_IRQHandler) for EXTI15_10_IRQHandler
+ startup_stm32f10x_cl.o(RESET) refers to usart.o(i.UART4_IRQHandler) for UART4_IRQHandler
+ startup_stm32f10x_cl.o(RESET) refers to usart.o(i.UART5_IRQHandler) for UART5_IRQHandler
+ startup_stm32f10x_cl.o(RESET) refers to stm32f10x_it.o(i.ETH_IRQHandler) for ETH_IRQHandler
+ startup_stm32f10x_cl.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
+ startup_stm32f10x_cl.o(.text) refers to __main.o(!!!main) for __main
+ startup_stm32f10x_cl.o(.text) refers to startup_stm32f10x_cl.o(HEAP) for Heap_Mem
+ startup_stm32f10x_cl.o(.text) refers to startup_stm32f10x_cl.o(STACK) for Stack_Mem
+ led.o(i.LED_Init1) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ led.o(i.LED_Init1) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ led.o(i.LED_Init2) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ led.o(i.LED_Init2) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ led.o(i.LED_Init3) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ led.o(i.LED_Init3) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ delay.o(i.delay_ms) refers to delay.o(i.delay_us) for delay_us
+ delay.o(i.delay_s) refers to delay.o(i.delay_ms) for delay_ms
+ usart.o(i.UART4_IRQHandler) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.UART4_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus
+ usart.o(i.UART4_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData
+ usart.o(i.UART4_IRQHandler) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+ usart.o(i.UART5_IRQHandler) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.UART5_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus
+ usart.o(i.UART5_IRQHandler) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData
+ usart.o(i.UART5_IRQHandler) refers to usart.o(i.USART2_printf) for USART2_printf
+ usart.o(i.UART5_IRQHandler) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits
+ usart.o(i.UART5_IRQHandler) refers to tcp_client.o(i.Check_TCP_Connect) for Check_TCP_Connect
+ usart.o(i.UART5_IRQHandler) refers to tcp_client.o(i.TCP_Client_Send_Data) for TCP_Client_Send_Data
+ usart.o(i.UART5_IRQHandler) refers to tcp_client.o(i.Delay_s) for Delay_s
+ usart.o(i.USART1_Init) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART1_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ usart.o(i.USART1_Init) refers to stm32f10x_gpio.o(i.GPIO_PinRemapConfig) for GPIO_PinRemapConfig
+ usart.o(i.USART1_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init
+ usart.o(i.USART1_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig
+ usart.o(i.USART1_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd
+ usart.o(i.USART1_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ usart.o(i.USART1_Init) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig
+ usart.o(i.USART1_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init
+ usart.o(i.USART1_printf) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART1_printf) refers to c89vsnprintf.o(.text) for __c89vsnprintf
+ usart.o(i.USART1_printf) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData
+ usart.o(i.USART1_printf) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus
+ usart.o(i.USART1_printf) refers to strlen.o(.text) for strlen
+ usart.o(i.USART2_Init) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ usart.o(i.USART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd
+ usart.o(i.USART2_Init) refers to stm32f10x_gpio.o(i.GPIO_PinRemapConfig) for GPIO_PinRemapConfig
+ usart.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init
+ usart.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig
+ usart.o(i.USART2_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd
+ usart.o(i.USART2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ usart.o(i.USART2_Init) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig
+ usart.o(i.USART2_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init
+ usart.o(i.USART2_printf) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART2_printf) refers to c89vsnprintf.o(.text) for __c89vsnprintf
+ usart.o(i.USART2_printf) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData
+ usart.o(i.USART2_printf) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus
+ usart.o(i.USART2_printf) refers to strlen.o(.text) for strlen
+ usart.o(i.USART4_Init) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART4_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ usart.o(i.USART4_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd
+ usart.o(i.USART4_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init
+ usart.o(i.USART4_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig
+ usart.o(i.USART4_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd
+ usart.o(i.USART4_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ usart.o(i.USART4_Init) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig
+ usart.o(i.USART4_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init
+ usart.o(i.USART4_printf) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART4_printf) refers to c89vsnprintf.o(.text) for __c89vsnprintf
+ usart.o(i.USART4_printf) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData
+ usart.o(i.USART4_printf) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus
+ usart.o(i.USART4_printf) refers to strlen.o(.text) for strlen
+ usart.o(i.USART5_Init) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART5_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd
+ usart.o(i.USART5_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd
+ usart.o(i.USART5_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init
+ usart.o(i.USART5_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig
+ usart.o(i.USART5_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd
+ usart.o(i.USART5_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init
+ usart.o(i.USART5_Init) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig
+ usart.o(i.USART5_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init
+ usart.o(i.USART5_printf) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.USART5_printf) refers to c89vsnprintf.o(.text) for __c89vsnprintf
+ usart.o(i.USART5_printf) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData
+ usart.o(i.USART5_printf) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus
+ usart.o(i.USART5_printf) refers to strlen.o(.text) for strlen
+ usart.o(i._sys_exit) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(i.fputc) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.bss) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.bss) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.bss) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.bss) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ usart.o(.data) refers (Special) to use_no_semi_2.o(.text) for __use_no_semihosting
+ use_no_semi_2.o(.text) refers (Special) to use_no_semi.o(.text) for __use_no_semihosting_swi
+ c89vsnprintf.o(.text) refers (Special) to _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) for _printf_a
+ c89vsnprintf.o(.text) refers (Special) to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c
+ c89vsnprintf.o(.text) refers (Special) to _printf_charcount.o(.text) for _printf_charcount
+ c89vsnprintf.o(.text) refers (Special) to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d
+ c89vsnprintf.o(.text) refers (Special) to _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) for _printf_e
+ c89vsnprintf.o(.text) refers (Special) to _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) for _printf_f
+ c89vsnprintf.o(.text) refers (Special) to printf1.o(x$fpl$printf1) for _printf_fp_dec
+ c89vsnprintf.o(.text) refers (Special) to _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) for _printf_g
+ c89vsnprintf.o(.text) refers (Special) to _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) for _printf_i
+ c89vsnprintf.o(.text) refers (Special) to _printf_dec.o(.text) for _printf_int_dec
+ c89vsnprintf.o(.text) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l
+ c89vsnprintf.o(.text) refers (Special) to _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) for _printf_lc
+ c89vsnprintf.o(.text) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll
+ c89vsnprintf.o(.text) refers (Special) to _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) for _printf_lld
+ c89vsnprintf.o(.text) refers (Special) to _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) for _printf_lli
+ c89vsnprintf.o(.text) refers (Special) to _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) for _printf_llo
+ c89vsnprintf.o(.text) refers (Special) to _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) for _printf_llu
+ c89vsnprintf.o(.text) refers (Special) to _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) for _printf_llx
+ c89vsnprintf.o(.text) refers (Special) to _printf_longlong_dec.o(.text) for _printf_longlong_dec
+ c89vsnprintf.o(.text) refers (Special) to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex
+ c89vsnprintf.o(.text) refers (Special) to _printf_oct_int_ll.o(.text) for _printf_longlong_oct
+ c89vsnprintf.o(.text) refers (Special) to _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) for _printf_ls
+ c89vsnprintf.o(.text) refers (Special) to _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) for _printf_n
+ c89vsnprintf.o(.text) refers (Special) to _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) for _printf_o
+ c89vsnprintf.o(.text) refers (Special) to _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) for _printf_p
+ c89vsnprintf.o(.text) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ c89vsnprintf.o(.text) refers (Special) to _printf_pad.o(.text) for _printf_post_padding
+ c89vsnprintf.o(.text) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s
+ c89vsnprintf.o(.text) refers (Special) to _printf_str.o(.text) for _printf_str
+ c89vsnprintf.o(.text) refers (Special) to _printf_truncate.o(.text) for _printf_truncate_signed
+ c89vsnprintf.o(.text) refers (Special) to _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) for _printf_u
+ c89vsnprintf.o(.text) refers (Special) to _printf_wctomb.o(.text) for _printf_wctomb
+ c89vsnprintf.o(.text) refers (Special) to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x
+ c89vsnprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common
+ c89vsnprintf.o(.text) refers to _sputc.o(.text) for _sputc
+ c89vsnprintf.o(.text) refers to _snputc.o(.text) for _snputc
+ __2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
+ __2printf.o(.text) refers to usart.o(.data) for __stdout
+ __2sprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common
+ __2sprintf.o(.text) refers to _sputc.o(.text) for _sputc
+ noretval__2printf.o(.text) refers to _printf_char_file.o(.text) for _printf_char_file
+ noretval__2printf.o(.text) refers to usart.o(.data) for __stdout
+ noretval__2sprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common
+ noretval__2sprintf.o(.text) refers to _sputc.o(.text) for _sputc
+ __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_signed
+ _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned
+ _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata
+ __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata
+ __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+ __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+ __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata
+ __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+ __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit
+ __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent
+ __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata
+ _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec
+ _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end
+ rt_memcpy_v6.o(.text) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4
+ rt_memclr.o(.text) refers to rt_memclr_w.o(.text) for _memset_w
+ strncpy.o(.text) refers to rt_memclr.o(.text) for __aeabi_memclr
+ __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1
+ __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh
+ _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common
+ _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+ _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+ _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+ _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+ _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+ _printf_char_common.o(.text) refers to __printf_flags_ss_wp.o(.text) for __printf
+ _printf_char_file.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common
+ _printf_char_file.o(.text) refers to ferror.o(.text) for ferror
+ _printf_char_file.o(.text) refers to usart.o(i.fputc) for fputc
+ _printf_wctomb.o(.text) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common
+ _printf_wctomb.o(.text) refers to _wcrtomb.o(.text) for _wcrtomb
+ _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+ _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+ _printf_wctomb.o(.text) refers to _printf_wctomb.o(.constdata) for .constdata
+ _printf_wctomb.o(.constdata) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common
+ _printf_longlong_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10
+ _printf_longlong_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_oct_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_oct_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned
+ _printf_oct_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_oct_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_oct_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned
+ _printf_hex_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_hex_ll.o(.text) refers to _printf_hex_ll.o(.constdata) for .constdata
+ _printf_hex_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned
+ _printf_hex_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_hex_int.o(.text) refers to _printf_hex_int.o(.constdata) for .constdata
+ _printf_hex_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_hex_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned
+ _printf_hex_int_ll.o(.text) refers to _printf_hex_int_ll.o(.constdata) for .constdata
+ _printf_hex_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_hex_ptr.o(.text) refers to _printf_hex_ptr.o(.constdata) for .constdata
+ _printf_hex_int_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_hex_int_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned
+ _printf_hex_int_ptr.o(.text) refers to _printf_hex_int_ptr.o(.constdata) for .constdata
+ _printf_hex_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_hex_ll_ptr.o(.text) refers to _printf_hex_ll_ptr.o(.constdata) for .constdata
+ _printf_hex_int_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common
+ _printf_hex_int_ll_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned
+ _printf_hex_int_ll_ptr.o(.text) refers to _printf_hex_int_ll_ptr.o(.constdata) for .constdata
+ _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) refers (Weak) to _printf_char.o(.text) for _printf_char
+ _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string
+ _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) refers (Weak) to _printf_charcount.o(.text) for _printf_charcount
+ _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_int_hex
+ _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_hex_ptr
+ _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_int_oct
+ _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec
+ _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec
+ _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec
+ _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec
+ _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec
+ _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll
+ _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec
+ _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll
+ _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec
+ _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll
+ _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec
+ _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l
+ _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Weak) to _printf_wchar.o(.text) for _printf_wchar
+ _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l
+ _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Weak) to _printf_wchar.o(.text) for _printf_wstring
+ _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll
+ _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_ll_oct
+ _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll
+ _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_ll_hex
+ printf1.o(x$fpl$printf1) refers to _printf_fp_dec.o(.text) for _printf_fp_dec_real
+ __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main
+ __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B
+ __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D
+ __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap
+ __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004
+ _printf_fp_dec.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ _printf_fp_dec.o(.text) refers (Special) to lc_numeric_c.o(locale$$code) for _get_lc_numeric
+ _printf_fp_dec.o(.text) refers to bigflt0.o(.text) for _btod_etento
+ _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_d2e) for _btod_d2e
+ _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_ediv) for _btod_ediv
+ _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_emul) for _btod_emul
+ _printf_fp_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10
+ _printf_fp_dec.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify
+ _printf_fp_dec.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan
+ _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+ _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+ _printf_fp_dec.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale
+ _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+ _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str
+ _printf_wchar.o(.text) refers (Weak) to _printf_wctomb.o(.text) for _printf_wctomb
+ _wcrtomb.o(.text) refers to rt_ctype_table.o(.text) for __rt_ctype_table
+ sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace
+ sys_stackheap_outer.o(.text) refers to startup_stm32f10x_cl.o(.text) for __user_initial_stackheap
+ rt_ctype_table.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale
+ rt_ctype_table.o(.text) refers to lc_ctype_c.o(locale$$code) for _get_lc_ctype
+ rt_locale.o(.text) refers to rt_locale.o(.bss) for __rt_locale_data
+ rt_locale_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start
+ _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding
+ _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding
+ bigflt0.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ bigflt0.o(.text) refers to btod.o(CL$$btod_emul) for _btod_emul
+ bigflt0.o(.text) refers to btod.o(CL$$btod_ediv) for _btod_ediv
+ bigflt0.o(.text) refers to bigflt0.o(.constdata) for .constdata
+ bigflt0.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_d2e) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_d2e) refers to btod.o(CL$$btod_d2e_norm_op1) for _d2e_norm_op1
+ btod.o(CL$$btod_d2e_norm_op1) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_d2e_norm_op1) refers to btod.o(CL$$btod_d2e_denorm_low) for _d2e_denorm_low
+ btod.o(CL$$btod_d2e_denorm_low) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_emul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_emul) refers to btod.o(CL$$btod_mult_common) for __btod_mult_common
+ btod.o(CL$$btod_emul) refers to btod.o(CL$$btod_e2e) for _e2e
+ btod.o(CL$$btod_ediv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_ediv) refers to btod.o(CL$$btod_div_common) for __btod_div_common
+ btod.o(CL$$btod_ediv) refers to btod.o(CL$$btod_e2e) for _e2e
+ btod.o(CL$$btod_emuld) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_emuld) refers to btod.o(CL$$btod_mult_common) for __btod_mult_common
+ btod.o(CL$$btod_emuld) refers to btod.o(CL$$btod_e2d) for _e2d
+ btod.o(CL$$btod_edivd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_edivd) refers to btod.o(CL$$btod_div_common) for __btod_div_common
+ btod.o(CL$$btod_edivd) refers to btod.o(CL$$btod_e2d) for _e2d
+ btod.o(CL$$btod_e2e) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_e2d) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_e2d) refers to btod.o(CL$$btod_e2e) for _e2e
+ btod.o(CL$$btod_mult_common) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ btod.o(CL$$btod_div_common) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ lc_numeric_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000016) for __rt_lib_init_lc_numeric_2
+ lc_numeric_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000016) for __rt_lib_init_lc_numeric_2
+ lc_numeric_c.o(locale$$code) refers to strcmpv7m.o(.text) for strcmp
+ lc_numeric_c.o(locale$$code) refers to lc_numeric_c.o(locale$$data) for __lcnum_c_name
+ exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1
+ libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1
+ istatus.o(x$fpl$ieeestatus) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ fpclassify.o(i.__ARM_fpclassify) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp
+ libspace.o(.text) refers to libspace.o(.bss) for __libspace_start
+ rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+ rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+ rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+ rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
+ rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
+ rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
+ rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000
+ lc_ctype_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000012) for __rt_lib_init_lc_ctype_2
+ lc_ctype_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000012) for __rt_lib_init_lc_ctype_2
+ lc_ctype_c.o(locale$$code) refers to strcmpv7m.o(.text) for strcmp
+ lc_ctype_c.o(locale$$code) refers to lc_ctype_c.o(locale$$data) for __lcctype_c_name
+ libinit2.o(.ARM.Collect$$libinit$$0000000F) refers (Weak) to rt_locale_intlibspace.o(.text) for __rt_locale
+ libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000012) refers (Weak) to lc_ctype_c.o(locale$$code) for _get_lc_ctype
+ libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000016) refers (Weak) to lc_numeric_c.o(locale$$code) for _get_lc_numeric
+ libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
+ libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+ libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer
+ rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown
+ rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to usart.o(i._sys_exit) for _sys_exit
+ rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001
+ rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003
+ rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004
+ argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv
+ _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard
+ _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM
+ _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1
+ libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1
+ sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+ sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+ defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+ defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
+ defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
+ rt_raise.o(.text) refers to __raise.o(.text) for __raise
+ rt_raise.o(.text) refers to usart.o(i._sys_exit) for _sys_exit
+ defsig_exit.o(.text) refers to usart.o(i._sys_exit) for _sys_exit
+ defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler
+ defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch
+ sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
+ sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
+ defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
+ defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+ defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display
+
+
+==============================================================================
+
+Removing Unused input sections from the image.
+
+ Removing main.o(i.Delay), (20 bytes).
+ Removing stm32f107.o(i.TIM_Configuration), (80 bytes).
+ Removing netconf.o(.data), (4 bytes).
+ Removing netconf.o(.data), (4 bytes).
+ Removing netconf.o(.data), (1 bytes).
+ Removing netconf.o(.data), (1 bytes).
+ Removing tcp_client.o(.bss), (800 bytes).
+ Removing hx711.o(i.HX711_Read), (104 bytes).
+ Removing hx711.o(i.Init_HX711pin), (72 bytes).
+ Removing stm32f10x_usart.o(i.USART_ClearFlag), (6 bytes).
+ Removing stm32f10x_usart.o(i.USART_ClockInit), (30 bytes).
+ Removing stm32f10x_usart.o(i.USART_ClockStructInit), (12 bytes).
+ Removing stm32f10x_usart.o(i.USART_DMACmd), (16 bytes).
+ Removing stm32f10x_usart.o(i.USART_DeInit), (116 bytes).
+ Removing stm32f10x_usart.o(i.USART_HalfDuplexCmd), (20 bytes).
+ Removing stm32f10x_usart.o(i.USART_IrDACmd), (20 bytes).
+ Removing stm32f10x_usart.o(i.USART_IrDAConfig), (16 bytes).
+ Removing stm32f10x_usart.o(i.USART_LINBreakDetectLengthConfig), (16 bytes).
+ Removing stm32f10x_usart.o(i.USART_LINCmd), (20 bytes).
+ Removing stm32f10x_usart.o(i.USART_ReceiverWakeUpCmd), (20 bytes).
+ Removing stm32f10x_usart.o(i.USART_SendBreak), (10 bytes).
+ Removing stm32f10x_usart.o(i.USART_SetAddress), (16 bytes).
+ Removing stm32f10x_usart.o(i.USART_SetGuardTime), (16 bytes).
+ Removing stm32f10x_usart.o(i.USART_SetPrescaler), (16 bytes).
+ Removing stm32f10x_usart.o(i.USART_SmartCardCmd), (20 bytes).
+ Removing stm32f10x_usart.o(i.USART_SmartCardNACKCmd), (20 bytes).
+ Removing stm32f10x_usart.o(i.USART_StructInit), (22 bytes).
+ Removing stm32f10x_usart.o(i.USART_WakeUpConfig), (16 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (22 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_DeInit), (180 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (40 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (28 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (16 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (6 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_ReadInputDataBit), (14 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (6 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (14 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes).
+ Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_ADCCLKConfig), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd), (24 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd), (24 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_BackupResetCmd), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (16 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_DeInit), (76 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_HCLKConfig), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_HSEConfig), (52 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_I2S2CLKConfig), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_I2S3CLKConfig), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_ITConfig), (24 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_LSEConfig), (32 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_OTGFSCLKConfig), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PCLK1Config), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PCLK2Config), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PLL2Cmd), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PLL2Config), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PLLCmd), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PLLConfig), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PREDIV1Config), (28 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_PREDIV2Config), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_RTCCLKCmd), (12 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_RTCCLKConfig), (16 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_SYSCLKConfig), (20 bytes).
+ Removing stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp), (44 bytes).
+ Removing stm32f10x_spi.o(i.I2S_Cmd), (20 bytes).
+ Removing stm32f10x_spi.o(i.I2S_Init), (228 bytes).
+ Removing stm32f10x_spi.o(i.I2S_StructInit), (18 bytes).
+ Removing stm32f10x_spi.o(i.SPI_BiDirectionalLineConfig), (22 bytes).
+ Removing stm32f10x_spi.o(i.SPI_CalculateCRC), (20 bytes).
+ Removing stm32f10x_spi.o(i.SPI_Cmd), (20 bytes).
+ Removing stm32f10x_spi.o(i.SPI_DataSizeConfig), (16 bytes).
+ Removing stm32f10x_spi.o(i.SPI_GetCRC), (12 bytes).
+ Removing stm32f10x_spi.o(i.SPI_GetCRCPolynomial), (4 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_ClearFlag), (6 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_ClearITPendingBit), (14 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_DMACmd), (16 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_DeInit), (84 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus), (14 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_GetITStatus), (44 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_ITConfig), (24 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_ReceiveData), (4 bytes).
+ Removing stm32f10x_spi.o(i.SPI_I2S_SendData), (4 bytes).
+ Removing stm32f10x_spi.o(i.SPI_Init), (56 bytes).
+ Removing stm32f10x_spi.o(i.SPI_NSSInternalSoftwareConfig), (24 bytes).
+ Removing stm32f10x_spi.o(i.SPI_SSOutputCmd), (20 bytes).
+ Removing stm32f10x_spi.o(i.SPI_StructInit), (24 bytes).
+ Removing stm32f10x_spi.o(i.SPI_TransmitCRC), (10 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_ClearFlag), (12 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_ClearITPendingBit), (12 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_DeInit), (36 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_GenerateSWInterrupt), (16 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_GetFlagStatus), (20 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_GetITStatus), (32 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_Init), (112 bytes).
+ Removing stm32f10x_exti.o(i.EXTI_StructInit), (14 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_ClearFlag), (12 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_EnableWriteProtection), (168 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_EraseAllPages), (60 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_EraseOptionBytes), (116 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_ErasePage), (64 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_GetFlagStatus), (32 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_GetPrefetchBufferStatus), (20 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_GetReadOutProtectionStatus), (20 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_GetStatus), (40 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_GetUserOptionByte), (12 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_GetWriteProtectionOptionByte), (12 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_HalfCycleAccessCmd), (24 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_ITConfig), (24 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_Lock), (16 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_PrefetchBufferCmd), (24 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_ProgramHalfWord), (56 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_ProgramOptionByteData), (72 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_ProgramWord), (76 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_ReadOutProtection), (136 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_SetLatency), (20 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_Unlock), (24 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_UserOptionByteConfig), (88 bytes).
+ Removing stm32f10x_flash.o(i.FLASH_WaitForLastOperation), (46 bytes).
+ Removing misc.o(i.NVIC_SystemLPConfig), (24 bytes).
+ Removing misc.o(i.SysTick_CLKSourceConfig), (24 bytes).
+ Removing stm32f10x_adc.o(i.ADC_AnalogWatchdogCmd), (16 bytes).
+ Removing stm32f10x_adc.o(i.ADC_AnalogWatchdogSingleChannelConfig), (12 bytes).
+ Removing stm32f10x_adc.o(i.ADC_AnalogWatchdogThresholdsConfig), (6 bytes).
+ Removing stm32f10x_adc.o(i.ADC_AutoInjectedConvCmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_ClearFlag), (6 bytes).
+ Removing stm32f10x_adc.o(i.ADC_ClearITPendingBit), (8 bytes).
+ Removing stm32f10x_adc.o(i.ADC_Cmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_DMACmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_DeInit), (68 bytes).
+ Removing stm32f10x_adc.o(i.ADC_DiscModeChannelCountConfig), (16 bytes).
+ Removing stm32f10x_adc.o(i.ADC_DiscModeCmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_ExternalTrigConvCmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_ExternalTrigInjectedConvCmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_ExternalTrigInjectedConvConfig), (12 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetCalibrationStatus), (14 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetConversionValue), (6 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetDualModeConversionValue), (12 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetFlagStatus), (14 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetITStatus), (28 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetInjectedConversionValue), (14 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetResetCalibrationStatus), (14 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetSoftwareStartConvStatus), (14 bytes).
+ Removing stm32f10x_adc.o(i.ADC_GetSoftwareStartInjectedConvCmdStatus), (14 bytes).
+ Removing stm32f10x_adc.o(i.ADC_ITConfig), (18 bytes).
+ Removing stm32f10x_adc.o(i.ADC_Init), (72 bytes).
+ Removing stm32f10x_adc.o(i.ADC_InjectedChannelConfig), (74 bytes).
+ Removing stm32f10x_adc.o(i.ADC_InjectedDiscModeCmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_InjectedSequencerLengthConfig), (16 bytes).
+ Removing stm32f10x_adc.o(i.ADC_RegularChannelConfig), (116 bytes).
+ Removing stm32f10x_adc.o(i.ADC_ResetCalibration), (10 bytes).
+ Removing stm32f10x_adc.o(i.ADC_SetInjectedOffset), (10 bytes).
+ Removing stm32f10x_adc.o(i.ADC_SoftwareStartConvCmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_SoftwareStartInjectedConvCmd), (20 bytes).
+ Removing stm32f10x_adc.o(i.ADC_StartCalibration), (10 bytes).
+ Removing stm32f10x_adc.o(i.ADC_StructInit), (18 bytes).
+ Removing stm32f10x_adc.o(i.ADC_TempSensorVrefintCmd), (28 bytes).
+ Removing stm32f10x_tim.o(i.TI1_Config), (46 bytes).
+ Removing stm32f10x_tim.o(i.TI2_Config), (54 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ARRPreloadConfig), (22 bytes).
+ Removing stm32f10x_tim.o(i.TIM_BDTRConfig), (34 bytes).
+ Removing stm32f10x_tim.o(i.TIM_BDTRStructInit), (18 bytes).
+ Removing stm32f10x_tim.o(i.TIM_CCPreloadControl), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_CCxCmd), (22 bytes).
+ Removing stm32f10x_tim.o(i.TIM_CCxNCmd), (22 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ClearFlag), (6 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ClearOC1Ref), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ClearOC2Ref), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ClearOC3Ref), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ClearOC4Ref), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_Cmd), (22 bytes).
+ Removing stm32f10x_tim.o(i.TIM_CounterModeConfig), (14 bytes).
+ Removing stm32f10x_tim.o(i.TIM_CtrlPWMOutputs), (22 bytes).
+ Removing stm32f10x_tim.o(i.TIM_DMACmd), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_DMAConfig), (8 bytes).
+ Removing stm32f10x_tim.o(i.TIM_DeInit), (200 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ETRClockMode1Config), (18 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ETRClockMode2Config), (18 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ETRConfig), (24 bytes).
+ Removing stm32f10x_tim.o(i.TIM_EncoderInterfaceConfig), (50 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ForcedOC1Config), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ForcedOC2Config), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ForcedOC3Config), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ForcedOC4Config), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GenerateEvent), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GetCapture1), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GetCapture2), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GetCapture3), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GetCapture4), (6 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GetCounter), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GetFlagStatus), (14 bytes).
+ Removing stm32f10x_tim.o(i.TIM_GetPrescaler), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ICInit), (172 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ICStructInit), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ITConfig), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig), (18 bytes).
+ Removing stm32f10x_tim.o(i.TIM_InternalClockConfig), (10 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC1FastConfig), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC1Init), (96 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC1NPolarityConfig), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC1PolarityConfig), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC1PreloadConfig), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC2FastConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC2Init), (128 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC2NPolarityConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC2PolarityConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC2PreloadConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC3FastConfig), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC3Init), (124 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC3NPolarityConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC3PolarityConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC3PreloadConfig), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC4FastConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC4Init), (100 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC4PolarityConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OC4PreloadConfig), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_OCStructInit), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_PWMIConfig), (108 bytes).
+ Removing stm32f10x_tim.o(i.TIM_PrescalerConfig), (6 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectCCDMA), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectCOM), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectHallSensor), (20 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectInputTrigger), (12 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectMasterSlaveMode), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectOCxM), (74 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectOnePulseMode), (18 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectOutputTrigger), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SelectSlaveMode), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetAutoreload), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetClockDivision), (14 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetCompare1), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetCompare2), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetCompare3), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetCompare4), (6 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetCounter), (4 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetIC1Prescaler), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetIC2Prescaler), (24 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetIC3Prescaler), (16 bytes).
+ Removing stm32f10x_tim.o(i.TIM_SetIC4Prescaler), (24 bytes).
+ Removing stm32f10x_tim.o(i.TIM_TIxExternalClockConfig), (46 bytes).
+ Removing stm32f10x_tim.o(i.TIM_TimeBaseInit), (60 bytes).
+ Removing stm32f10x_tim.o(i.TIM_TimeBaseStructInit), (18 bytes).
+ Removing stm32f10x_tim.o(i.TIM_UpdateDisableConfig), (22 bytes).
+ Removing stm32f10x_tim.o(i.TIM_UpdateRequestConfig), (22 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_ARPCmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_AcknowledgeConfig), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_CalculatePEC), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_CheckEvent), (24 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_ClearFlag), (6 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_ClearITPendingBit), (6 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_Cmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_DMACmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_DMALastTransferCmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_DeInit), (44 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_DualAddressCmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_FastModeDutyCycleConfig), (22 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_GeneralCallCmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_GenerateSTART), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_GenerateSTOP), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_GetFlagStatus), (42 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_GetITStatus), (36 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_GetLastEvent), (14 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_GetPEC), (6 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_ITConfig), (16 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_Init), (188 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_OwnAddress2Config), (16 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_PECPositionConfig), (22 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_ReadRegister), (10 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_ReceiveData), (6 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_SMBusAlertConfig), (22 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_Send7bitAddress), (16 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_SendData), (4 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_SoftwareResetCmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_StretchClockCmd), (20 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_StructInit), (28 bytes).
+ Removing stm32f10x_i2c.o(i.I2C_TransmitPEC), (20 bytes).
+ Removing stm32_eth.o(i.ETH_BackPressureActivationCmd), (28 bytes).
+ Removing stm32_eth.o(i.ETH_DMAClearFlag), (12 bytes).
+ Removing stm32_eth.o(i.ETH_DMAPTPRxDescChainInit), (108 bytes).
+ Removing stm32_eth.o(i.ETH_DMAPTPTxDescChainInit), (100 bytes).
+ Removing stm32_eth.o(i.ETH_DMARxDescEndOfRingCmd), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DMARxDescRingInit), (84 bytes).
+ Removing stm32_eth.o(i.ETH_DMARxDescSecondAddressChainedCmd), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescBufferSizeConfig), (12 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescCRCCmd), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescEndOfRingCmd), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescFrameSegmentConfig), (8 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescRingInit), (68 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescSecondAddressChainedCmd), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescShortFramePaddingCmd), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescTimeStampCmd), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DMATxDescTransmitITConfig), (18 bytes).
+ Removing stm32_eth.o(i.ETH_DropRxPkt), (52 bytes).
+ Removing stm32_eth.o(i.ETH_EnablePTPTimeStampAddend), (16 bytes).
+ Removing stm32_eth.o(i.ETH_EnablePTPTimeStampInterruptTrigger), (16 bytes).
+ Removing stm32_eth.o(i.ETH_EnablePTPTimeStampUpdate), (16 bytes).
+ Removing stm32_eth.o(i.ETH_GetBufferUnavailableMissedFrameCounter), (12 bytes).
+ Removing stm32_eth.o(i.ETH_GetCurrentRxBufferAddress), (12 bytes).
+ Removing stm32_eth.o(i.ETH_GetCurrentRxDescStartAddress), (12 bytes).
+ Removing stm32_eth.o(i.ETH_GetCurrentTxBufferAddress), (12 bytes).
+ Removing stm32_eth.o(i.ETH_GetCurrentTxDescStartAddress), (12 bytes).
+ Removing stm32_eth.o(i.ETH_GetDMAFlagStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetDMAITStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetDMAOverflowStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetDMARxDescBufferSize), (16 bytes).
+ Removing stm32_eth.o(i.ETH_GetDMARxDescFlagStatus), (14 bytes).
+ Removing stm32_eth.o(i.ETH_GetDMATxDescCollisionCount), (8 bytes).
+ Removing stm32_eth.o(i.ETH_GetDMATxDescFlagStatus), (14 bytes).
+ Removing stm32_eth.o(i.ETH_GetFlowControlBusyStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetFlushTransmitFIFOStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetMACAddress), (36 bytes).
+ Removing stm32_eth.o(i.ETH_GetMACFlagStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetMACITStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetMMCITStatus), (40 bytes).
+ Removing stm32_eth.o(i.ETH_GetMMCRegister), (12 bytes).
+ Removing stm32_eth.o(i.ETH_GetPMTFlagStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetPTPFlagStatus), (20 bytes).
+ Removing stm32_eth.o(i.ETH_GetPTPRegister), (12 bytes).
+ Removing stm32_eth.o(i.ETH_GetReceiveProcessState), (16 bytes).
+ Removing stm32_eth.o(i.ETH_GetRxOverflowMissedFrameCounter), (16 bytes).
+ Removing stm32_eth.o(i.ETH_GetTransmitProcessState), (16 bytes).
+ Removing stm32_eth.o(i.ETH_GlobalUnicastWakeUpCmd), (28 bytes).
+ Removing stm32_eth.o(i.ETH_HandlePTPRxPkt), (152 bytes).
+ Removing stm32_eth.o(i.ETH_HandlePTPTxPkt), (184 bytes).
+ Removing stm32_eth.o(i.ETH_HandleRxPkt), (120 bytes).
+ Removing stm32_eth.o(i.ETH_HandleTxPkt), (108 bytes).
+ Removing stm32_eth.o(i.ETH_InitializePTPTimeStamp), (16 bytes).
+ Removing stm32_eth.o(i.ETH_InitiatePauseControlFrame), (16 bytes).
+ Removing stm32_eth.o(i.ETH_MACAddressFilterConfig), (28 bytes).
+ Removing stm32_eth.o(i.ETH_MACAddressMaskBytesFilterConfig), (24 bytes).
+ Removing stm32_eth.o(i.ETH_MACAddressPerfectFilterCmd), (28 bytes).
+ Removing stm32_eth.o(i.ETH_MACITConfig), (24 bytes).
+ Removing stm32_eth.o(i.ETH_MMCCounterFreezeCmd), (32 bytes).
+ Removing stm32_eth.o(i.ETH_MMCCounterRolloverCmd), (32 bytes).
+ Removing stm32_eth.o(i.ETH_MMCCountersReset), (20 bytes).
+ Removing stm32_eth.o(i.ETH_MMCITConfig), (56 bytes).
+ Removing stm32_eth.o(i.ETH_MMCResetOnReadCmd), (32 bytes).
+ Removing stm32_eth.o(i.ETH_MagicPacketDetectionCmd), (28 bytes).
+ Removing stm32_eth.o(i.ETH_PHYLoopBackCmd), (40 bytes).
+ Removing stm32_eth.o(i.ETH_PTPTimeStampCmd), (28 bytes).
+ Removing stm32_eth.o(i.ETH_PTPUpdateMethodConfig), (28 bytes).
+ Removing stm32_eth.o(i.ETH_PowerDownCmd), (28 bytes).
+ Removing stm32_eth.o(i.ETH_ResetWakeUpFrameFilterRegisterPointer), (16 bytes).
+ Removing stm32_eth.o(i.ETH_ResumeDMAReception), (12 bytes).
+ Removing stm32_eth.o(i.ETH_ResumeDMATransmission), (12 bytes).
+ Removing stm32_eth.o(i.ETH_SetDMARxDescOwnBit), (10 bytes).
+ Removing stm32_eth.o(i.ETH_SetDMATxDescOwnBit), (10 bytes).
+ Removing stm32_eth.o(i.ETH_SetPTPSubSecondIncrement), (12 bytes).
+ Removing stm32_eth.o(i.ETH_SetPTPTargetTime), (16 bytes).
+ Removing stm32_eth.o(i.ETH_SetPTPTimeStampAddend), (12 bytes).
+ Removing stm32_eth.o(i.ETH_SetPTPTimeStampUpdate), (16 bytes).
+ Removing stm32_eth.o(i.ETH_SetWakeUpFrameFilterRegister), (24 bytes).
+ Removing stm32_eth.o(i.ETH_WakeUpFrameDetectionCmd), (28 bytes).
+ Removing ethernetif.o(.data), (4 bytes).
+ Removing ethernetif.o(.data), (4 bytes).
+ Removing ethernetif.o(.data), (4 bytes).
+ Removing tcp.o(i.tcp_accept), (4 bytes).
+ Removing tcp.o(i.tcp_accept_null), (6 bytes).
+ Removing tcp.o(i.tcp_arg), (4 bytes).
+ Removing tcp.o(i.tcp_err), (6 bytes).
+ Removing tcp.o(i.tcp_listen_with_backlog), (132 bytes).
+ Removing tcp.o(i.tcp_poll), (10 bytes).
+ Removing tcp.o(i.tcp_sent), (6 bytes).
+ Removing tcp.o(i.tcp_setprio), (4 bytes).
+ Removing udp.o(i.udp_bind), (92 bytes).
+ Removing udp.o(i.udp_connect), (76 bytes).
+ Removing udp.o(i.udp_disconnect), (24 bytes).
+ Removing udp.o(i.udp_new), (26 bytes).
+ Removing udp.o(i.udp_recv), (6 bytes).
+ Removing udp.o(i.udp_remove), (44 bytes).
+ Removing udp.o(i.udp_send), (8 bytes).
+ Removing udp.o(i.udp_sendto), (40 bytes).
+ Removing udp.o(i.udp_sendto_if), (176 bytes).
+ Removing init.o(i.lwip_init), (14 bytes).
+ Removing mem.o(i.mem_calloc), (26 bytes).
+ Removing netif.o(i.netif_find), (64 bytes).
+ Removing netif.o(i.netif_remove), (56 bytes).
+ Removing netif.o(i.netif_set_down), (18 bytes).
+ Removing pbuf.o(i.pbuf_coalesce), (44 bytes).
+ Removing pbuf.o(i.pbuf_dechain), (38 bytes).
+ Removing pbuf.o(i.pbuf_take), (78 bytes).
+ Removing raw.o(i.raw_bind), (10 bytes).
+ Removing raw.o(i.raw_connect), (10 bytes).
+ Removing raw.o(i.raw_new), (44 bytes).
+ Removing raw.o(i.raw_recv), (6 bytes).
+ Removing raw.o(i.raw_remove), (44 bytes).
+ Removing raw.o(i.raw_send), (6 bytes).
+ Removing raw.o(i.raw_sendto), (138 bytes).
+ Removing inet.o(i.inet_addr), (20 bytes).
+ Removing inet.o(i.inet_aton), (238 bytes).
+ Removing inet.o(i.inet_ntoa), (88 bytes).
+ Removing inet.o(.bss), (16 bytes).
+ Removing inet_chksum.o(i.inet_chksum_pseudo), (134 bytes).
+ Removing ip.o(i.ip_current_header), (12 bytes).
+ Removing ip.o(i.ip_current_netif), (12 bytes).
+ Removing ip_addr.o(.constdata), (4 bytes).
+ Removing ip_frag.o(i.ip_reass_tmr), (44 bytes).
+ Removing etharp.o(i.etharp_find_addr), (56 bytes).
+ Removing system_stm32f10x.o(.constdata), (4 bytes).
+ Removing system_stm32f10x.o(.constdata), (4 bytes).
+ Removing system_stm32f10x.o(.constdata), (4 bytes).
+ Removing system_stm32f10x.o(.constdata), (4 bytes).
+ Removing system_stm32f10x.o(.constdata), (4 bytes).
+ Removing core_cm3.o(.emb_text), (32 bytes).
+ Removing delay.o(i.delay_s), (24 bytes).
+ Removing usart.o(i.USART5_printf), (76 bytes).
+ Removing usart.o(.bss), (200 bytes).
+ Removing usart.o(.bss), (200 bytes).
+ Removing usart.o(.bss), (200 bytes).
+ Removing usart.o(.bss), (200 bytes).
+ Removing usart.o(.data), (2 bytes).
+ Removing usart.o(.data), (2 bytes).
+ Removing usart.o(.data), (2 bytes).
+ Removing usart.o(.data), (2 bytes).
+
+422 unused section(s) (total 13902 bytes) removed from the image.
+
+==============================================================================
+
+Image Symbol Table
+
+ Local Symbols
+
+ Symbol Name Value Ov Type Size Object(Section)
+
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE
+ ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE
+ ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE
+ ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE
+ ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE
+ ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE
+ ../clib/angel/rt.s 0x00000000 Number 0 rt_locale_intlibspace.o ABSOLUTE
+ ../clib/angel/rt.s 0x00000000 Number 0 rt_ctype_table.o ABSOLUTE
+ ../clib/angel/rt.s 0x00000000 Number 0 rt_locale.o ABSOLUTE
+ ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE
+ ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi_2.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE
+ ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE
+ ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE
+ ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE
+ ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE
+ ../clib/bigflt.c 0x00000000 Number 0 bigflt0.o ABSOLUTE
+ ../clib/btod.s 0x00000000 Number 0 btod.o ABSOLUTE
+ ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE
+ ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE
+ ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE
+ ../clib/locale.c 0x00000000 Number 0 _wcrtomb.o ABSOLUTE
+ ../clib/locale.s 0x00000000 Number 0 lc_numeric_c.o ABSOLUTE
+ ../clib/locale.s 0x00000000 Number 0 lc_ctype_c.o ABSOLUTE
+ ../clib/longlong.s 0x00000000 Number 0 lludiv10.o ABSOLUTE
+ ../clib/memcpset.s 0x00000000 Number 0 strncpy.o ABSOLUTE
+ ../clib/memcpset.s 0x00000000 Number 0 strcmpv7m.o ABSOLUTE
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+ i.tcp_slowtmr 0x080069d4 Section 0 tcp.o(i.tcp_slowtmr)
+ i.tcp_tmr 0x08006be4 Section 0 tcp.o(i.tcp_tmr)
+ i.tcp_update_rcv_ann_wnd 0x08006c04 Section 0 tcp.o(i.tcp_update_rcv_ann_wnd)
+ i.tcp_write 0x08006c2e Section 0 tcp_out.o(i.tcp_write)
+ i.tcp_zero_window_probe 0x08006c5c Section 0 tcp_out.o(i.tcp_zero_window_probe)
+ i.udp_input 0x08006cb0 Section 0 udp.o(i.udp_input)
+ i.update_arp_entry 0x08006dec Section 0 etharp.o(i.update_arp_entry)
+ update_arp_entry 0x08006ded Thumb Code 162 etharp.o(i.update_arp_entry)
+ locale$$code 0x08006e94 Section 44 lc_numeric_c.o(locale$$code)
+ locale$$code 0x08006ec0 Section 44 lc_ctype_c.o(locale$$code)
+ x$fpl$printf1 0x08006eec Section 4 printf1.o(x$fpl$printf1)
+ .constdata 0x08006ef0 Section 4 main.o(.constdata)
+ x$fpl$usenofp 0x08006ef0 Section 0 usenofp.o(x$fpl$usenofp)
+ .constdata 0x08006ef4 Section 20 tcp.o(.constdata)
+ .constdata 0x08006f08 Section 36 memp.o(.constdata)
+ memp_sizes 0x08006f08 Data 18 memp.o(.constdata)
+ memp_num 0x08006f1a Data 18 memp.o(.constdata)
+ .constdata 0x08006f2c Section 4 ip_addr.o(.constdata)
+ .constdata 0x08006f30 Section 12 etharp.o(.constdata)
+ .constdata 0x08006f3c Section 17 __printf_flags_ss_wp.o(.constdata)
+ maptable 0x08006f3c Data 17 __printf_flags_ss_wp.o(.constdata)
+ .constdata 0x08006f50 Section 8 _printf_wctomb.o(.constdata)
+ initial_mbstate 0x08006f50 Data 8 _printf_wctomb.o(.constdata)
+ .constdata 0x08006f58 Section 40 _printf_hex_int_ll_ptr.o(.constdata)
+ uc_hextab 0x08006f58 Data 20 _printf_hex_int_ll_ptr.o(.constdata)
+ lc_hextab 0x08006f6c Data 20 _printf_hex_int_ll_ptr.o(.constdata)
+ .constdata 0x08006f80 Section 148 bigflt0.o(.constdata)
+ tenpwrs_x 0x08006f80 Data 60 bigflt0.o(.constdata)
+ tenpwrs_i 0x08006fbc Data 64 bigflt0.o(.constdata)
+ locale$$data 0x08007034 Section 28 lc_numeric_c.o(locale$$data)
+ __lcnum_c_name 0x08007038 Data 2 lc_numeric_c.o(locale$$data)
+ __lcnum_c_start 0x08007040 Data 0 lc_numeric_c.o(locale$$data)
+ __lcnum_c_point 0x0800704c Data 0 lc_numeric_c.o(locale$$data)
+ __lcnum_c_thousands 0x0800704e Data 0 lc_numeric_c.o(locale$$data)
+ __lcnum_c_grouping 0x0800704f Data 0 lc_numeric_c.o(locale$$data)
+ locale$$data 0x08007050 Section 272 lc_ctype_c.o(locale$$data)
+ __lcnum_c_end 0x08007050 Data 0 lc_numeric_c.o(locale$$data)
+ __lcctype_c_name 0x08007054 Data 2 lc_ctype_c.o(locale$$data)
+ __lcctype_c_start 0x0800705c Data 0 lc_ctype_c.o(locale$$data)
+ __lcctype_c_end 0x08007160 Data 0 lc_ctype_c.o(locale$$data)
+ .data 0x20000000 Section 16 main.o(.data)
+ i 0x20000008 Data 4 main.o(.data)
+ .data 0x20000010 Section 16 netconf.o(.data)
+ IPaddress 0x20000018 Data 4 netconf.o(.data)
+ .data 0x20000020 Section 16 tcp_client.o(.data)
+ i 0x20000024 Data 4 tcp_client.o(.data)
+ .data 0x20000030 Section 20 stm32f10x_rcc.o(.data)
+ ADCPrescTable 0x20000030 Data 4 stm32f10x_rcc.o(.data)
+ APBAHBPrescTable 0x20000034 Data 16 stm32f10x_rcc.o(.data)
+ .data 0x20000044 Section 16 stm32_eth.o(.data)
+ .data 0x20000054 Section 6 ethernetif.o(.data)
+ .data 0x2000005c Section 32 tcp.o(.data)
+ tcp_timer 0x2000005c Data 1 tcp.o(.data)
+ port 0x2000005e Data 2 tcp.o(.data)
+ iss 0x20000060 Data 4 tcp.o(.data)
+ .data 0x2000007c Section 28 tcp_in.o(.data)
+ flags 0x2000007c Data 1 tcp_in.o(.data)
+ recv_flags 0x2000007d Data 1 tcp_in.o(.data)
+ tcplen 0x2000007e Data 2 tcp_in.o(.data)
+ tcphdr 0x20000080 Data 4 tcp_in.o(.data)
+ iphdr 0x20000084 Data 4 tcp_in.o(.data)
+ seqno 0x20000088 Data 4 tcp_in.o(.data)
+ ackno 0x2000008c Data 4 tcp_in.o(.data)
+ recv_data 0x20000090 Data 4 tcp_in.o(.data)
+ .data 0x20000098 Section 4 udp.o(.data)
+ .data 0x2000009c Section 16 mem.o(.data)
+ mem_sem 0x2000009c Data 1 mem.o(.data)
+ ram 0x200000a0 Data 4 mem.o(.data)
+ ram_end 0x200000a4 Data 4 mem.o(.data)
+ lfree 0x200000a8 Data 4 mem.o(.data)
+ .data 0x200000ac Section 12 netif.o(.data)
+ netifnum 0x200000ac Data 1 netif.o(.data)
+ .data 0x200000b8 Section 4 raw.o(.data)
+ raw_pcbs 0x200000b8 Data 4 raw.o(.data)
+ .data 0x200000bc Section 12 ip.o(.data)
+ ip_id 0x200000bc Data 2 ip.o(.data)
+ current_netif 0x200000c0 Data 4 ip.o(.data)
+ current_header 0x200000c4 Data 4 ip.o(.data)
+ .data 0x200000c8 Section 8 ip_frag.o(.data)
+ ip_reass_pbufcount 0x200000c8 Data 2 ip_frag.o(.data)
+ reassdatagrams 0x200000cc Data 4 ip_frag.o(.data)
+ .data 0x200000d0 Section 1 etharp.o(.data)
+ etharp_cached_entry 0x200000d0 Data 1 etharp.o(.data)
+ .data 0x200000d4 Section 4 usart.o(.data)
+ .bss 0x200000d8 Section 48 netconf.o(.bss)
+ .bss 0x20000108 Section 900 tcp_client.o(.bss)
+ .bss 0x2000048c Section 9216 ethernetif.o(.bss)
+ .bss 0x2000288c Section 20 tcp_in.o(.bss)
+ inseg 0x2000288c Data 20 tcp_in.o(.bss)
+ .bss 0x200028a0 Section 8212 mem.o(.bss)
+ ram_heap 0x200028a0 Data 8212 mem.o(.bss)
+ .bss 0x200048b4 Section 18095 memp.o(.bss)
+ memp_tab 0x200048b4 Data 36 memp.o(.bss)
+ memp_memory 0x200048d8 Data 18059 memp.o(.bss)
+ .bss 0x20008f63 Section 1504 ip_frag.o(.bss)
+ buf 0x20008f63 Data 1504 ip_frag.o(.bss)
+ .bss 0x20009544 Section 200 etharp.o(.bss)
+ arp_table 0x20009544 Data 200 etharp.o(.bss)
+ .bss 0x2000960c Section 96 libspace.o(.bss)
+ HEAP 0x20009670 Section 512 startup_stm32f10x_cl.o(HEAP)
+ Heap_Mem 0x20009670 Data 512 startup_stm32f10x_cl.o(HEAP)
+ STACK 0x20009870 Section 1024 startup_stm32f10x_cl.o(STACK)
+ Stack_Mem 0x20009870 Data 1024 startup_stm32f10x_cl.o(STACK)
+ __initial_sp 0x20009c70 Data 0 startup_stm32f10x_cl.o(STACK)
+
+ Global Symbols
+
+ Symbol Name Value Ov Type Size Object(Section)
+
+ BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEJ$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
+ __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE
+ _printf_flags 0x00000000 Number 0 printf_stubs.o ABSOLUTE
+ _printf_return_value 0x00000000 Number 0 printf_stubs.o ABSOLUTE
+ _printf_sizespec 0x00000000 Number 0 printf_stubs.o ABSOLUTE
+ _printf_widthprec 0x00000000 Number 0 printf_stubs.o ABSOLUTE
+ __ARM_exceptions_init - Undefined Weak Reference
+ __alloca_initialize - Undefined Weak Reference
+ __arm_preinit_ - Undefined Weak Reference
+ __cpp_initialize__aeabi_ - Undefined Weak Reference
+ __cxa_finalize - Undefined Weak Reference
+ __sigvec_lookup - Undefined Weak Reference
+ _atexit_init - Undefined Weak Reference
+ _call_atexit_fns - Undefined Weak Reference
+ _clock_init - Undefined Weak Reference
+ _fp_trap_init - Undefined Weak Reference
+ _fp_trap_shutdown - Undefined Weak Reference
+ _get_lc_collate - Undefined Weak Reference
+ _get_lc_monetary - Undefined Weak Reference
+ _get_lc_time - Undefined Weak Reference
+ _getenv_init - Undefined Weak Reference
+ _handle_redirection - Undefined Weak Reference
+ _init_alloc - Undefined Weak Reference
+ _init_user_alloc - Undefined Weak Reference
+ _initio - Undefined Weak Reference
+ _mutex_acquire - Undefined Weak Reference
+ _mutex_release - Undefined Weak Reference
+ _printf_fp_hex - Undefined Weak Reference
+ _printf_mbtowc - Undefined Weak Reference
+ _printf_wc - Undefined Weak Reference
+ _rand_init - Undefined Weak Reference
+ _signal_finish - Undefined Weak Reference
+ _signal_init - Undefined Weak Reference
+ _terminate_alloc - Undefined Weak Reference
+ _terminate_user_alloc - Undefined Weak Reference
+ _terminateio - Undefined Weak Reference
+ __Vectors_Size 0x00000150 Number 0 startup_stm32f10x_cl.o ABSOLUTE
+ __Vectors 0x08000000 Data 4 startup_stm32f10x_cl.o(RESET)
+ __Vectors_End 0x08000150 Data 0 startup_stm32f10x_cl.o(RESET)
+ __main 0x08000151 Thumb Code 8 __main.o(!!!main)
+ __scatterload 0x08000159 Thumb Code 0 __scatter.o(!!!scatter)
+ __scatterload_rt2 0x08000159 Thumb Code 44 __scatter.o(!!!scatter)
+ __scatterload_rt2_thumb_only 0x08000159 Thumb Code 0 __scatter.o(!!!scatter)
+ __scatterload_null 0x08000167 Thumb Code 0 __scatter.o(!!!scatter)
+ __scatterload_copy 0x0800018d Thumb Code 26 __scatter_copy.o(!!handler_copy)
+ __scatterload_zeroinit 0x080001a9 Thumb Code 28 __scatter_zi.o(!!handler_zi)
+ _printf_n 0x080001c5 Thumb Code 0 _printf_n.o(.ARM.Collect$$_printf_percent$$00000001)
+ _printf_percent 0x080001c5 Thumb Code 0 _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000)
+ _printf_p 0x080001cb Thumb Code 0 _printf_p.o(.ARM.Collect$$_printf_percent$$00000002)
+ _printf_f 0x080001d1 Thumb Code 0 _printf_f.o(.ARM.Collect$$_printf_percent$$00000003)
+ _printf_e 0x080001d7 Thumb Code 0 _printf_e.o(.ARM.Collect$$_printf_percent$$00000004)
+ _printf_g 0x080001dd Thumb Code 0 _printf_g.o(.ARM.Collect$$_printf_percent$$00000005)
+ _printf_a 0x080001e3 Thumb Code 0 _printf_a.o(.ARM.Collect$$_printf_percent$$00000006)
+ _printf_ll 0x080001e9 Thumb Code 0 _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007)
+ _printf_i 0x080001f3 Thumb Code 0 _printf_i.o(.ARM.Collect$$_printf_percent$$00000008)
+ _printf_d 0x080001f9 Thumb Code 0 _printf_d.o(.ARM.Collect$$_printf_percent$$00000009)
+ _printf_u 0x080001ff Thumb Code 0 _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A)
+ _printf_o 0x08000205 Thumb Code 0 _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B)
+ _printf_x 0x0800020b Thumb Code 0 _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C)
+ _printf_lli 0x08000211 Thumb Code 0 _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D)
+ _printf_lld 0x08000217 Thumb Code 0 _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E)
+ _printf_llu 0x0800021d Thumb Code 0 _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F)
+ _printf_llo 0x08000223 Thumb Code 0 _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010)
+ _printf_llx 0x08000229 Thumb Code 0 _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011)
+ _printf_l 0x0800022f Thumb Code 0 _printf_l.o(.ARM.Collect$$_printf_percent$$00000012)
+ _printf_c 0x08000239 Thumb Code 0 _printf_c.o(.ARM.Collect$$_printf_percent$$00000013)
+ _printf_s 0x0800023f Thumb Code 0 _printf_s.o(.ARM.Collect$$_printf_percent$$00000014)
+ _printf_lc 0x08000245 Thumb Code 0 _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015)
+ _printf_ls 0x0800024b Thumb Code 0 _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016)
+ _printf_percent_end 0x08000251 Thumb Code 0 _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017)
+ __rt_lib_init 0x08000255 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000)
+ __rt_lib_init_fp_1 0x08000257 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002)
+ __rt_lib_init_heap_1 0x08000257 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A)
+ __rt_lib_init_lc_common 0x08000257 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000F)
+ __rt_lib_init_preinit_1 0x08000257 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004)
+ __rt_lib_init_rand_1 0x08000257 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E)
+ __rt_lib_init_user_alloc_1 0x08000257 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C)
+ __rt_lib_init_lc_collate_1 0x0800025d Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011)
+ __rt_lib_init_lc_ctype_2 0x0800025d Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000012)
+ __rt_lib_init_lc_ctype_1 0x08000269 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013)
+ __rt_lib_init_lc_monetary_1 0x08000269 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015)
+ __rt_lib_init_lc_numeric_2 0x08000269 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000016)
+ __rt_lib_init_alloca_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E)
+ __rt_lib_init_argv_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C)
+ __rt_lib_init_atexit_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B)
+ __rt_lib_init_clock_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021)
+ __rt_lib_init_cpp_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032)
+ __rt_lib_init_exceptions_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030)
+ __rt_lib_init_fp_trap_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F)
+ __rt_lib_init_getenv_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023)
+ __rt_lib_init_lc_numeric_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017)
+ __rt_lib_init_lc_time_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019)
+ __rt_lib_init_return 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033)
+ __rt_lib_init_signal_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D)
+ __rt_lib_init_stdio_1 0x08000273 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025)
+ __rt_lib_shutdown 0x08000275 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
+ __rt_lib_shutdown_cpp_1 0x08000277 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
+ __rt_lib_shutdown_fp_trap_1 0x08000277 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
+ __rt_lib_shutdown_heap_1 0x08000277 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
+ __rt_lib_shutdown_return 0x08000277 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
+ __rt_lib_shutdown_signal_1 0x08000277 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
+ __rt_lib_shutdown_stdio_1 0x08000277 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
+ __rt_lib_shutdown_user_alloc_1 0x08000277 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
+ __rt_entry 0x08000279 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000)
+ __rt_entry_presh_1 0x08000279 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
+ __rt_entry_sh 0x08000279 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
+ __rt_entry_li 0x0800027f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
+ __rt_entry_postsh_1 0x0800027f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
+ __rt_entry_main 0x08000283 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
+ __rt_entry_postli_1 0x08000283 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
+ __rt_exit 0x0800028b Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000)
+ __rt_exit_ls 0x0800028d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003)
+ __rt_exit_prels_1 0x0800028d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002)
+ __rt_exit_exit 0x08000291 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004)
+ Reset_Handler 0x08000299 Thumb Code 4 startup_stm32f10x_cl.o(.text)
+ ADC1_2_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN1_RX0_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN1_RX1_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN1_SCE_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN1_TX_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN2_RX0_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN2_RX1_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN2_SCE_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ CAN2_TX_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA1_Channel1_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA1_Channel2_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA1_Channel3_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA1_Channel4_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA1_Channel5_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA1_Channel6_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA1_Channel7_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA2_Channel1_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA2_Channel2_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA2_Channel3_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA2_Channel4_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ DMA2_Channel5_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ ETH_WKUP_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ EXTI0_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ EXTI1_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ EXTI2_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ EXTI3_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ EXTI4_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ EXTI9_5_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ FLASH_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ I2C1_ER_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ I2C1_EV_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ I2C2_ER_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ I2C2_EV_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ OTG_FS_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ OTG_FS_WKUP_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ PVD_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ RCC_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ RTCAlarm_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ RTC_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ SPI1_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ SPI2_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ SPI3_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TAMPER_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM1_BRK_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM1_CC_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM1_TRG_COM_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM1_UP_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM3_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM4_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM5_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM6_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ TIM7_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ USART3_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ WWDG_IRQHandler 0x080002af Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ __user_initial_stackheap 0x080002b1 Thumb Code 0 startup_stm32f10x_cl.o(.text)
+ __use_no_semihosting 0x080002d1 Thumb Code 2 use_no_semi_2.o(.text)
+ __c89vsnprintf 0x080002d5 Thumb Code 48 c89vsnprintf.o(.text)
+ __2printf 0x08000309 Thumb Code 20 __2printf.o(.text)
+ __2sprintf 0x08000321 Thumb Code 38 __2sprintf.o(.text)
+ _printf_int_dec 0x0800034d Thumb Code 104 _printf_dec.o(.text)
+ __printf 0x080003c5 Thumb Code 388 __printf_flags_ss_wp.o(.text)
+ strlen 0x0800054d Thumb Code 62 strlen.o(.text)
+ strncmp 0x0800058b Thumb Code 150 strncmp.o(.text)
+ __aeabi_memcpy 0x08000621 Thumb Code 0 rt_memcpy_v6.o(.text)
+ __rt_memcpy 0x08000621 Thumb Code 138 rt_memcpy_v6.o(.text)
+ _memcpy_lastbytes 0x08000687 Thumb Code 0 rt_memcpy_v6.o(.text)
+ __aeabi_memclr 0x080006ab Thumb Code 0 rt_memclr.o(.text)
+ __rt_memclr 0x080006ab Thumb Code 68 rt_memclr.o(.text)
+ _memset 0x080006af Thumb Code 0 rt_memclr.o(.text)
+ __aeabi_memclr4 0x080006ef Thumb Code 0 rt_memclr_w.o(.text)
+ __aeabi_memclr8 0x080006ef Thumb Code 0 rt_memclr_w.o(.text)
+ __rt_memclr_w 0x080006ef Thumb Code 78 rt_memclr_w.o(.text)
+ _memset_w 0x080006f3 Thumb Code 0 rt_memclr_w.o(.text)
+ strncpy 0x0800073d Thumb Code 86 strncpy.o(.text)
+ __use_two_region_memory 0x08000793 Thumb Code 2 heapauxi.o(.text)
+ __rt_heap_escrow$2region 0x08000795 Thumb Code 2 heapauxi.o(.text)
+ __rt_heap_expand$2region 0x08000797 Thumb Code 2 heapauxi.o(.text)
+ __I$use$semihosting 0x08000799 Thumb Code 0 use_no_semi.o(.text)
+ __use_no_semihosting_swi 0x08000799 Thumb Code 2 use_no_semi.o(.text)
+ _printf_pre_padding 0x0800079b Thumb Code 44 _printf_pad.o(.text)
+ _printf_post_padding 0x080007c7 Thumb Code 34 _printf_pad.o(.text)
+ _printf_truncate_signed 0x080007e9 Thumb Code 18 _printf_truncate.o(.text)
+ _printf_truncate_unsigned 0x080007fb Thumb Code 18 _printf_truncate.o(.text)
+ _printf_str 0x0800080d Thumb Code 82 _printf_str.o(.text)
+ _printf_int_common 0x0800085f Thumb Code 178 _printf_intcommon.o(.text)
+ _printf_charcount 0x08000911 Thumb Code 40 _printf_charcount.o(.text)
+ _printf_char_common 0x08000943 Thumb Code 32 _printf_char_common.o(.text)
+ _sputc 0x08000969 Thumb Code 10 _sputc.o(.text)
+ _snputc 0x08000973 Thumb Code 16 _snputc.o(.text)
+ _printf_char_file 0x08000985 Thumb Code 32 _printf_char_file.o(.text)
+ _printf_wctomb 0x080009a9 Thumb Code 182 _printf_wctomb.o(.text)
+ _printf_longlong_dec 0x08000a65 Thumb Code 108 _printf_longlong_dec.o(.text)
+ _printf_longlong_oct 0x08000ae1 Thumb Code 66 _printf_oct_int_ll.o(.text)
+ _printf_int_oct 0x08000b23 Thumb Code 24 _printf_oct_int_ll.o(.text)
+ _printf_ll_oct 0x08000b3b Thumb Code 12 _printf_oct_int_ll.o(.text)
+ _printf_longlong_hex 0x08000b51 Thumb Code 86 _printf_hex_int_ll_ptr.o(.text)
+ _printf_int_hex 0x08000ba7 Thumb Code 28 _printf_hex_int_ll_ptr.o(.text)
+ _printf_ll_hex 0x08000bc3 Thumb Code 12 _printf_hex_int_ll_ptr.o(.text)
+ _printf_hex_ptr 0x08000bcf Thumb Code 18 _printf_hex_int_ll_ptr.o(.text)
+ __aeabi_memcpy4 0x08000be5 Thumb Code 0 rt_memcpy_w.o(.text)
+ __aeabi_memcpy8 0x08000be5 Thumb Code 0 rt_memcpy_w.o(.text)
+ __rt_memcpy_w 0x08000be5 Thumb Code 100 rt_memcpy_w.o(.text)
+ _memcpy_lastbytes_aligned 0x08000c2d Thumb Code 0 rt_memcpy_w.o(.text)
+ _ll_udiv10 0x08000c49 Thumb Code 138 lludiv10.o(.text)
+ __lib_sel_fp_printf 0x08000cd3 Thumb Code 2 _printf_fp_dec.o(.text)
+ _printf_fp_dec_real 0x08000e85 Thumb Code 620 _printf_fp_dec.o(.text)
+ _printf_cs_common 0x080010f1 Thumb Code 20 _printf_char.o(.text)
+ _printf_char 0x08001105 Thumb Code 16 _printf_char.o(.text)
+ _printf_string 0x08001115 Thumb Code 8 _printf_char.o(.text)
+ _printf_lcs_common 0x0800111d Thumb Code 20 _printf_wchar.o(.text)
+ _printf_wchar 0x08001131 Thumb Code 16 _printf_wchar.o(.text)
+ _printf_wstring 0x08001141 Thumb Code 8 _printf_wchar.o(.text)
+ ferror 0x08001149 Thumb Code 8 ferror.o(.text)
+ _wcrtomb 0x08001151 Thumb Code 64 _wcrtomb.o(.text)
+ __user_setup_stackheap 0x08001191 Thumb Code 74 sys_stackheap_outer.o(.text)
+ __rt_ctype_table 0x080011dd Thumb Code 16 rt_ctype_table.o(.text)
+ __rt_locale 0x080011ed Thumb Code 8 rt_locale_intlibspace.o(.text)
+ _printf_fp_infnan 0x080011f5 Thumb Code 112 _printf_fp_infnan.o(.text)
+ _btod_etento 0x08001275 Thumb Code 224 bigflt0.o(.text)
+ exit 0x08001359 Thumb Code 18 exit.o(.text)
+ __user_libspace 0x0800136d Thumb Code 8 libspace.o(.text)
+ __user_perproc_libspace 0x0800136d Thumb Code 0 libspace.o(.text)
+ __user_perthread_libspace 0x0800136d Thumb Code 0 libspace.o(.text)
+ strcmp 0x08001375 Thumb Code 128 strcmpv7m.o(.text)
+ _btod_d2e 0x080013f5 Thumb Code 62 btod.o(CL$$btod_d2e)
+ _d2e_denorm_low 0x08001433 Thumb Code 70 btod.o(CL$$btod_d2e_denorm_low)
+ _d2e_norm_op1 0x08001479 Thumb Code 96 btod.o(CL$$btod_d2e_norm_op1)
+ __btod_div_common 0x080014d9 Thumb Code 696 btod.o(CL$$btod_div_common)
+ _e2e 0x08001811 Thumb Code 220 btod.o(CL$$btod_e2e)
+ _btod_ediv 0x080018ed Thumb Code 42 btod.o(CL$$btod_ediv)
+ _btod_emul 0x08001917 Thumb Code 42 btod.o(CL$$btod_emul)
+ __btod_mult_common 0x08001941 Thumb Code 580 btod.o(CL$$btod_mult_common)
+ BusFault_Handler 0x08001b85 Thumb Code 2 stm32f10x_it.o(i.BusFault_Handler)
+ Check_TCP_Connect 0x08001b89 Thumb Code 60 tcp_client.o(i.Check_TCP_Connect)
+ DebugMon_Handler 0x08001bcd Thumb Code 2 stm32f10x_it.o(i.DebugMon_Handler)
+ Delay_s 0x08001bcf Thumb Code 6 tcp_client.o(i.Delay_s)
+ Display_Periodic_Handle 0x08001bd5 Thumb Code 86 netconf.o(i.Display_Periodic_Handle)
+ ETH_DMAClearITPendingBit 0x08001c49 Thumb Code 6 stm32_eth.o(i.ETH_DMAClearITPendingBit)
+ ETH_DMAITConfig 0x08001c55 Thumb Code 18 stm32_eth.o(i.ETH_DMAITConfig)
+ ETH_DMAReceptionCmd 0x08001c6d Thumb Code 22 stm32_eth.o(i.ETH_DMAReceptionCmd)
+ ETH_DMARxDescChainInit 0x08001c89 Thumb Code 68 stm32_eth.o(i.ETH_DMARxDescChainInit)
+ ETH_DMARxDescReceiveITConfig 0x08001cd5 Thumb Code 18 stm32_eth.o(i.ETH_DMARxDescReceiveITConfig)
+ ETH_DMATransmissionCmd 0x08001ce9 Thumb Code 22 stm32_eth.o(i.ETH_DMATransmissionCmd)
+ ETH_DMATxDescChainInit 0x08001d05 Thumb Code 62 stm32_eth.o(i.ETH_DMATxDescChainInit)
+ ETH_DMATxDescChecksumInsertionConfig 0x08001d4d Thumb Code 8 stm32_eth.o(i.ETH_DMATxDescChecksumInsertionConfig)
+ ETH_DeInit 0x08001d55 Thumb Code 24 stm32_eth.o(i.ETH_DeInit)
+ ETH_FlushTransmitFIFO 0x08001d81 Thumb Code 12 stm32_eth.o(i.ETH_FlushTransmitFIFO)
+ ETH_GetCurrentTxBuffer 0x08001d91 Thumb Code 8 ethernetif.o(i.ETH_GetCurrentTxBuffer)
+ ETH_GetDMARxDescFrameLength 0x08001d9d Thumb Code 8 stm32_eth.o(i.ETH_GetDMARxDescFrameLength)
+ ETH_GetRxPktSize 0x08001da5 Thumb Code 30 stm32_eth.o(i.ETH_GetRxPktSize)
+ ETH_GetSoftwareResetStatus 0x08001dc9 Thumb Code 14 stm32_eth.o(i.ETH_GetSoftwareResetStatus)
+ ETH_IRQHandler 0x08001ddd Thumb Code 34 stm32f10x_it.o(i.ETH_IRQHandler)
+ ETH_Init 0x08001e01 Thumb Code 480 stm32_eth.o(i.ETH_Init)
+ ETH_MACAddressConfig 0x08002009 Thumb Code 22 stm32_eth.o(i.ETH_MACAddressConfig)
+ ETH_MACReceptionCmd 0x08002025 Thumb Code 22 stm32_eth.o(i.ETH_MACReceptionCmd)
+ ETH_MACTransmissionCmd 0x08002041 Thumb Code 22 stm32_eth.o(i.ETH_MACTransmissionCmd)
+ ETH_ReadPHYRegister 0x0800205d Thumb Code 80 stm32_eth.o(i.ETH_ReadPHYRegister)
+ ETH_RxPkt_ChainMode 0x080020b5 Thumb Code 72 ethernetif.o(i.ETH_RxPkt_ChainMode)
+ ETH_SoftwareReset 0x08002105 Thumb Code 12 stm32_eth.o(i.ETH_SoftwareReset)
+ ETH_Start 0x08002115 Thumb Code 34 stm32_eth.o(i.ETH_Start)
+ ETH_StructInit 0x08002137 Thumb Code 124 stm32_eth.o(i.ETH_StructInit)
+ ETH_TxPkt_ChainMode 0x080021b5 Thumb Code 50 ethernetif.o(i.ETH_TxPkt_ChainMode)
+ ETH_WritePHYRegister 0x080021f1 Thumb Code 76 stm32_eth.o(i.ETH_WritePHYRegister)
+ EXTI15_10_IRQHandler 0x08002245 Thumb Code 2 stm32f10x_it.o(i.EXTI15_10_IRQHandler)
+ Ethernet_Configuration 0x08002249 Thumb Code 144 stm32f107.o(i.Ethernet_Configuration)
+ GPIO_Configuration 0x080022dd Thumb Code 232 stm32f107.o(i.GPIO_Configuration)
+ GPIO_ETH_MediaInterfaceConfig 0x080023d5 Thumb Code 8 stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig)
+ GPIO_Init 0x080023e1 Thumb Code 156 stm32f10x_gpio.o(i.GPIO_Init)
+ GPIO_PinRemapConfig 0x0800247d Thumb Code 66 stm32f10x_gpio.o(i.GPIO_PinRemapConfig)
+ GPIO_ResetBits 0x080024c5 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_ResetBits)
+ GPIO_SetBits 0x080024c9 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_SetBits)
+ HardFault_Handler 0x080024cd Thumb Code 2 stm32f10x_it.o(i.HardFault_Handler)
+ LED_Init1 0x080024d1 Thumb Code 40 led.o(i.LED_Init1)
+ LED_Init2 0x080024fd Thumb Code 38 led.o(i.LED_Init2)
+ LED_Init3 0x08002529 Thumb Code 38 led.o(i.LED_Init3)
+ LwIP_Init 0x08002555 Thumb Code 114 netconf.o(i.LwIP_Init)
+ LwIP_Periodic_Handle 0x080025dd Thumb Code 48 netconf.o(i.LwIP_Periodic_Handle)
+ LwIP_Pkt_Handle 0x08002611 Thumb Code 6 netconf.o(i.LwIP_Pkt_Handle)
+ MemManage_Handler 0x0800261d Thumb Code 2 stm32f10x_it.o(i.MemManage_Handler)
+ My_IP4_ADDR 0x0800261f Thumb Code 26 netconf.o(i.My_IP4_ADDR)
+ NMI_Handler 0x08002639 Thumb Code 2 stm32f10x_it.o(i.NMI_Handler)
+ NVIC_Configuration 0x0800263b Thumb Code 176 stm32f107.o(i.NVIC_Configuration)
+ NVIC_Init 0x080026ed Thumb Code 94 misc.o(i.NVIC_Init)
+ NVIC_PriorityGroupConfig 0x08002751 Thumb Code 10 misc.o(i.NVIC_PriorityGroupConfig)
+ NVIC_SetVectorTable 0x08002785 Thumb Code 12 misc.o(i.NVIC_SetVectorTable)
+ PendSV_Handler 0x08002799 Thumb Code 2 stm32f10x_it.o(i.PendSV_Handler)
+ RCC_AHBPeriphClockCmd 0x0800279d Thumb Code 18 stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd)
+ RCC_AHBPeriphResetCmd 0x080027b5 Thumb Code 18 stm32f10x_rcc.o(i.RCC_AHBPeriphResetCmd)
+ RCC_APB1PeriphClockCmd 0x080027cd Thumb Code 18 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd)
+ RCC_APB2PeriphClockCmd 0x080027e5 Thumb Code 18 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)
+ RCC_GetClocksFreq 0x080027fd Thumb Code 180 stm32f10x_rcc.o(i.RCC_GetClocksFreq)
+ RCC_GetFlagStatus 0x080028c5 Thumb Code 42 stm32f10x_rcc.o(i.RCC_GetFlagStatus)
+ RCC_MCOConfig 0x080028f5 Thumb Code 6 stm32f10x_rcc.o(i.RCC_MCOConfig)
+ RCC_PLL3Cmd 0x08002901 Thumb Code 6 stm32f10x_rcc.o(i.RCC_PLL3Cmd)
+ RCC_PLL3Config 0x0800290d Thumb Code 14 stm32f10x_rcc.o(i.RCC_PLL3Config)
+ SVC_Handler 0x08002921 Thumb Code 2 stm32f10x_it.o(i.SVC_Handler)
+ Set_MAC_Address 0x080029f5 Thumb Code 34 ethernetif.o(i.Set_MAC_Address)
+ SysTick_Handler 0x08002a1d Thumb Code 4 stm32f10x_it.o(i.SysTick_Handler)
+ SystemInit 0x08002a21 Thumb Code 64 system_stm32f10x.o(i.SystemInit)
+ System_Periodic_Handle 0x08002a6d Thumb Code 20 main.o(i.System_Periodic_Handle)
+ System_Setup 0x08002a85 Thumb Code 116 stm32f107.o(i.System_Setup)
+ TCP_Client_Init 0x08002af9 Thumb Code 70 tcp_client.o(i.TCP_Client_Init)
+ TCP_Client_Recv 0x08002b4d Thumb Code 314 tcp_client.o(i.TCP_Client_Recv)
+ TCP_Client_Send_Data 0x08002cd5 Thumb Code 24 tcp_client.o(i.TCP_Client_Send_Data)
+ TCP_Connected 0x08002ced Thumb Code 4 tcp_client.o(i.TCP_Connected)
+ TIM2_IRQHandler 0x08002cf1 Thumb Code 30 stm32f107.o(i.TIM2_IRQHandler)
+ TIM_ClearITPendingBit 0x08002d0f Thumb Code 6 stm32f10x_tim.o(i.TIM_ClearITPendingBit)
+ TIM_GetITStatus 0x08002d15 Thumb Code 24 stm32f10x_tim.o(i.TIM_GetITStatus)
+ Time_Update 0x08002d2d Thumb Code 10 main.o(i.Time_Update)
+ UART4_IRQHandler 0x08002d3d Thumb Code 60 usart.o(i.UART4_IRQHandler)
+ UART5_IRQHandler 0x08002d81 Thumb Code 158 usart.o(i.UART5_IRQHandler)
+ USART1_IRQHandler 0x08002e49 Thumb Code 56 sci.o(i.USART1_IRQHandler)
+ USART1_Init 0x08002e85 Thumb Code 170 usart.o(i.USART1_Init)
+ USART1_printf 0x08002f39 Thumb Code 72 usart.o(i.USART1_printf)
+ USART2_IRQHandler 0x08002f85 Thumb Code 62 sci.o(i.USART2_IRQHandler)
+ USART2_Init 0x08002fc9 Thumb Code 176 usart.o(i.USART2_Init)
+ USART2_printf 0x08003081 Thumb Code 72 usart.o(i.USART2_printf)
+ USART4_Init 0x080030cd Thumb Code 168 usart.o(i.USART4_Init)
+ USART4_printf 0x0800317d Thumb Code 72 usart.o(i.USART4_printf)
+ USART5_Init 0x080031c9 Thumb Code 166 usart.o(i.USART5_Init)
+ USART_ClearITPendingBit 0x0800327d Thumb Code 12 stm32f10x_usart.o(i.USART_ClearITPendingBit)
+ USART_Cmd 0x08003289 Thumb Code 20 stm32f10x_usart.o(i.USART_Cmd)
+ USART_Configuration 0x0800329d Thumb Code 302 sci.o(i.USART_Configuration)
+ USART_GetFlagStatus 0x080033dd Thumb Code 14 stm32f10x_usart.o(i.USART_GetFlagStatus)
+ USART_GetITStatus 0x080033eb Thumb Code 62 stm32f10x_usart.o(i.USART_GetITStatus)
+ USART_ITConfig 0x08003429 Thumb Code 48 stm32f10x_usart.o(i.USART_ITConfig)
+ USART_Init 0x08003459 Thumb Code 134 stm32f10x_usart.o(i.USART_Init)
+ USART_ReceiveData 0x080034e5 Thumb Code 8 stm32f10x_usart.o(i.USART_ReceiveData)
+ USART_SendData 0x080034ed Thumb Code 8 stm32f10x_usart.o(i.USART_SendData)
+ UsageFault_Handler 0x080034f5 Thumb Code 2 stm32f10x_it.o(i.UsageFault_Handler)
+ __ARM_fpclassify 0x080034f7 Thumb Code 40 fpclassify.o(i.__ARM_fpclassify)
+ _is_digit 0x0800351f Thumb Code 14 __printf_wp.o(i._is_digit)
+ _sys_exit 0x0800352d Thumb Code 2 usart.o(i._sys_exit)
+ delay_ms 0x0800352f Thumb Code 24 delay.o(i.delay_ms)
+ delay_us 0x08003547 Thumb Code 32 delay.o(i.delay_us)
+ etharp_arp_input 0x08003567 Thumb Code 202 etharp.o(i.etharp_arp_input)
+ etharp_ip_input 0x08003631 Thumb Code 40 etharp.o(i.etharp_ip_input)
+ etharp_output 0x08003659 Thumb Code 178 etharp.o(i.etharp_output)
+ etharp_query 0x08003711 Thumb Code 256 etharp.o(i.etharp_query)
+ etharp_request 0x080038b5 Thumb Code 32 etharp.o(i.etharp_request)
+ etharp_tmr 0x08003911 Thumb Code 78 etharp.o(i.etharp_tmr)
+ ethernet_input 0x08003965 Thumb Code 84 etharp.o(i.ethernet_input)
+ ethernetif_init 0x080039b9 Thumb Code 56 ethernetif.o(i.ethernetif_init)
+ ethernetif_input 0x080039f9 Thumb Code 116 ethernetif.o(i.ethernetif_input)
+ fputc 0x08003bad Thumb Code 14 usart.o(i.fputc)
+ htonl 0x08003bdf Thumb Code 4 inet.o(i.htonl)
+ htons 0x08003be3 Thumb Code 4 inet.o(i.htons)
+ icmp_dest_unreach 0x08003be7 Thumb Code 8 icmp.o(i.icmp_dest_unreach)
+ icmp_input 0x08003bef Thumb Code 276 icmp.o(i.icmp_input)
+ icmp_time_exceeded 0x08003d69 Thumb Code 8 icmp.o(i.icmp_time_exceeded)
+ inet_chksum 0x08003d71 Thumb Code 12 inet_chksum.o(i.inet_chksum)
+ inet_chksum_pbuf 0x08003d7d Thumb Code 72 inet_chksum.o(i.inet_chksum_pbuf)
+ ip_addr_isbroadcast 0x08003dc5 Thumb Code 48 ip_addr.o(i.ip_addr_isbroadcast)
+ ip_frag 0x08003df5 Thumb Code 298 ip_frag.o(i.ip_frag)
+ ip_input 0x08003f25 Thumb Code 348 ip.o(i.ip_input)
+ ip_output 0x08004089 Thumb Code 52 ip.o(i.ip_output)
+ ip_output_if 0x080040bd Thumb Code 200 ip.o(i.ip_output_if)
+ ip_reass 0x08004189 Thumb Code 428 ip_frag.o(i.ip_reass)
+ ip_route 0x08004531 Thumb Code 62 ip.o(i.ip_route)
+ main 0x08004669 Thumb Code 488 main.o(i.main)
+ mem_free 0x080048a5 Thumb Code 40 mem.o(i.mem_free)
+ mem_init 0x080048d1 Thumb Code 44 mem.o(i.mem_init)
+ mem_malloc 0x08004905 Thumb Code 162 mem.o(i.mem_malloc)
+ mem_realloc 0x080049ad Thumb Code 190 mem.o(i.mem_realloc)
+ memp_free 0x08004a71 Thumb Code 18 memp.o(i.memp_free)
+ memp_init 0x08004a89 Thumb Code 78 memp.o(i.memp_init)
+ memp_malloc 0x08004ae1 Thumb Code 28 memp.o(i.memp_malloc)
+ netif_add 0x08004b01 Thumb Code 68 netif.o(i.netif_add)
+ netif_is_up 0x08004b49 Thumb Code 10 netif.o(i.netif_is_up)
+ netif_set_addr 0x08004b53 Thumb Code 32 netif.o(i.netif_set_addr)
+ netif_set_default 0x08004b75 Thumb Code 6 netif.o(i.netif_set_default)
+ netif_set_gw 0x08004b81 Thumb Code 8 netif.o(i.netif_set_gw)
+ netif_set_ipaddr 0x08004b89 Thumb Code 96 netif.o(i.netif_set_ipaddr)
+ netif_set_netmask 0x08004bf1 Thumb Code 8 netif.o(i.netif_set_netmask)
+ netif_set_up 0x08004bf9 Thumb Code 28 netif.o(i.netif_set_up)
+ ntohl 0x08004c15 Thumb Code 4 inet.o(i.ntohl)
+ ntohs 0x08004c19 Thumb Code 4 inet.o(i.ntohs)
+ pbuf_alloc 0x08004c1d Thumb Code 268 pbuf.o(i.pbuf_alloc)
+ pbuf_cat 0x08004d29 Thumb Code 40 pbuf.o(i.pbuf_cat)
+ pbuf_chain 0x08004d51 Thumb Code 18 pbuf.o(i.pbuf_chain)
+ pbuf_clen 0x08004d63 Thumb Code 18 pbuf.o(i.pbuf_clen)
+ pbuf_copy 0x08004d75 Thumb Code 144 pbuf.o(i.pbuf_copy)
+ pbuf_copy_partial 0x08004e05 Thumb Code 104 pbuf.o(i.pbuf_copy_partial)
+ pbuf_free 0x08004e6d Thumb Code 68 pbuf.o(i.pbuf_free)
+ pbuf_header 0x08004eb1 Thumb Code 96 pbuf.o(i.pbuf_header)
+ pbuf_realloc 0x08004f11 Thumb Code 78 pbuf.o(i.pbuf_realloc)
+ pbuf_ref 0x08004f5f Thumb Code 12 pbuf.o(i.pbuf_ref)
+ raw_input 0x08004fc1 Thumb Code 100 raw.o(i.raw_input)
+ tcp_abandon 0x08005029 Thumb Code 142 tcp.o(i.tcp_abandon)
+ tcp_alloc 0x080050bd Thumb Code 248 tcp.o(i.tcp_alloc)
+ tcp_bind 0x080051c1 Thumb Code 182 tcp.o(i.tcp_bind)
+ tcp_close 0x0800527d Thumb Code 156 tcp.o(i.tcp_close)
+ tcp_connect 0x0800531d Thumb Code 190 tcp.o(i.tcp_connect)
+ tcp_eff_send_mss 0x080053e1 Thumb Code 32 tcp.o(i.tcp_eff_send_mss)
+ tcp_enqueue 0x08005401 Thumb Code 752 tcp_out.o(i.tcp_enqueue)
+ tcp_fasttmr 0x080056f1 Thumb Code 84 tcp.o(i.tcp_fasttmr)
+ tcp_input 0x08005749 Thumb Code 776 tcp_in.o(i.tcp_input)
+ tcp_keepalive 0x08005a65 Thumb Code 70 tcp_out.o(i.tcp_keepalive)
+ tcp_new 0x08005b95 Thumb Code 6 tcp.o(i.tcp_new)
+ tcp_next_iss 0x08005bfd Thumb Code 12 tcp.o(i.tcp_next_iss)
+ tcp_output 0x08005c0d Thumb Code 532 tcp_out.o(i.tcp_output)
+ tcp_pcb_purge 0x08005fcd Thumb Code 48 tcp.o(i.tcp_pcb_purge)
+ tcp_pcb_remove 0x08005ffd Thumb Code 90 tcp.o(i.tcp_pcb_remove)
+ tcp_recv 0x0800680b Thumb Code 6 tcp.o(i.tcp_recv)
+ tcp_recved 0x0800682d Thumb Code 60 tcp.o(i.tcp_recved)
+ tcp_rexmit 0x08006869 Thumb Code 84 tcp_out.o(i.tcp_rexmit)
+ tcp_rexmit_rto 0x080068bd Thumb Code 46 tcp_out.o(i.tcp_rexmit_rto)
+ tcp_rst 0x080068eb Thumb Code 152 tcp_out.o(i.tcp_rst)
+ tcp_seg_free 0x08006983 Thumb Code 32 tcp.o(i.tcp_seg_free)
+ tcp_segs_free 0x080069a3 Thumb Code 26 tcp.o(i.tcp_segs_free)
+ tcp_send_ctrl 0x080069bd Thumb Code 22 tcp_out.o(i.tcp_send_ctrl)
+ tcp_slowtmr 0x080069d5 Thumb Code 512 tcp.o(i.tcp_slowtmr)
+ tcp_tmr 0x08006be5 Thumb Code 28 tcp.o(i.tcp_tmr)
+ tcp_update_rcv_ann_wnd 0x08006c05 Thumb Code 42 tcp.o(i.tcp_update_rcv_ann_wnd)
+ tcp_write 0x08006c2f Thumb Code 46 tcp_out.o(i.tcp_write)
+ tcp_zero_window_probe 0x08006c5d Thumb Code 82 tcp_out.o(i.tcp_zero_window_probe)
+ udp_input 0x08006cb1 Thumb Code 312 udp.o(i.udp_input)
+ _get_lc_numeric 0x08006e95 Thumb Code 44 lc_numeric_c.o(locale$$code)
+ _get_lc_ctype 0x08006ec1 Thumb Code 44 lc_ctype_c.o(locale$$code)
+ _printf_fp_dec 0x08006eed Thumb Code 4 printf1.o(x$fpl$printf1)
+ __I$use$fp 0x08006ef0 Number 0 usenofp.o(x$fpl$usenofp)
+ tcp_persist_backoff 0x08006ef4 Data 7 tcp.o(.constdata)
+ tcp_backoff 0x08006efb Data 13 tcp.o(.constdata)
+ ip_addr_any 0x08006f2c Data 4 ip_addr.o(.constdata)
+ ethbroadcast 0x08006f30 Data 6 etharp.o(.constdata)
+ ethzero 0x08006f36 Data 6 etharp.o(.constdata)
+ Region$$Table$$Base 0x08007014 Number 0 anon$$obj.o(Region$$Table)
+ Region$$Table$$Limit 0x08007034 Number 0 anon$$obj.o(Region$$Table)
+ __ctype 0x0800705d Data 0 lc_ctype_c.o(locale$$data)
+ a 0x20000000 Data 1 main.o(.data)
+ LocalTime 0x20000004 Data 4 main.o(.data)
+ timingdelay 0x2000000c Data 4 main.o(.data)
+ TCPTimer 0x20000010 Data 4 netconf.o(.data)
+ ARPTimer 0x20000014 Data 4 netconf.o(.data)
+ DisplayTimer 0x2000001c Data 4 netconf.o(.data)
+ connect_flag 0x20000020 Data 1 tcp_client.o(.data)
+ C 0x20000028 Data 8 tcp_client.o(.data)
+ DMATxDescToSet 0x20000044 Data 4 stm32_eth.o(.data)
+ DMARxDescToGet 0x20000048 Data 4 stm32_eth.o(.data)
+ DMAPTPTxDescToSet 0x2000004c Data 4 stm32_eth.o(.data)
+ DMAPTPRxDescToGet 0x20000050 Data 4 stm32_eth.o(.data)
+ MACaddr 0x20000054 Data 6 ethernetif.o(.data)
+ tcp_ticks 0x20000064 Data 4 tcp.o(.data)
+ tcp_bound_pcbs 0x20000068 Data 4 tcp.o(.data)
+ tcp_listen_pcbs 0x2000006c Data 4 tcp.o(.data)
+ tcp_active_pcbs 0x20000070 Data 4 tcp.o(.data)
+ tcp_tw_pcbs 0x20000074 Data 4 tcp.o(.data)
+ tcp_tmp_pcb 0x20000078 Data 4 tcp.o(.data)
+ tcp_input_pcb 0x20000094 Data 4 tcp_in.o(.data)
+ udp_pcbs 0x20000098 Data 4 udp.o(.data)
+ netif_list 0x200000b0 Data 4 netif.o(.data)
+ netif_default 0x200000b4 Data 4 netif.o(.data)
+ __stdout 0x200000d4 Data 4 usart.o(.data)
+ netif 0x200000d8 Data 48 netconf.o(.bss)
+ member 0x20000108 Data 900 tcp_client.o(.bss)
+ DMARxDscrTab 0x2000048c Data 64 ethernetif.o(.bss)
+ DMATxDscrTab 0x200004cc Data 32 ethernetif.o(.bss)
+ Rx_Buff 0x200004ec Data 6080 ethernetif.o(.bss)
+ Tx_Buff 0x20001cac Data 3040 ethernetif.o(.bss)
+ __libspace_start 0x2000960c Data 96 libspace.o(.bss)
+ __temporary_stack_top$libspace 0x2000966c Data 0 libspace.o(.bss)
+
+
+
+==============================================================================
+
+Memory Map of the image
+
+ Image Entry point : 0x08000151
+
+ Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00007238, Max: 0x00040000, ABSOLUTE)
+
+ Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x00007160, Max: 0x00040000, ABSOLUTE)
+
+ Exec Addr Load Addr Size Type Attr Idx E Section Name Object
+
+ 0x08000000 0x08000000 0x00000150 Data RO 4178 RESET startup_stm32f10x_cl.o
+ 0x08000150 0x08000150 0x00000008 Code RO 4385 * !!!main c_w.l(__main.o)
+ 0x08000158 0x08000158 0x00000034 Code RO 4679 !!!scatter c_w.l(__scatter.o)
+ 0x0800018c 0x0800018c 0x0000001a Code RO 4681 !!handler_copy c_w.l(__scatter_copy.o)
+ 0x080001a6 0x080001a6 0x00000002 PAD
+ 0x080001a8 0x080001a8 0x0000001c Code RO 4683 !!handler_zi c_w.l(__scatter_zi.o)
+ 0x080001c4 0x080001c4 0x00000000 Code RO 4370 .ARM.Collect$$_printf_percent$$00000000 c_w.l(_printf_percent.o)
+ 0x080001c4 0x080001c4 0x00000006 Code RO 4442 .ARM.Collect$$_printf_percent$$00000001 c_w.l(_printf_n.o)
+ 0x080001ca 0x080001ca 0x00000006 Code RO 4444 .ARM.Collect$$_printf_percent$$00000002 c_w.l(_printf_p.o)
+ 0x080001d0 0x080001d0 0x00000006 Code RO 4448 .ARM.Collect$$_printf_percent$$00000003 c_w.l(_printf_f.o)
+ 0x080001d6 0x080001d6 0x00000006 Code RO 4449 .ARM.Collect$$_printf_percent$$00000004 c_w.l(_printf_e.o)
+ 0x080001dc 0x080001dc 0x00000006 Code RO 4450 .ARM.Collect$$_printf_percent$$00000005 c_w.l(_printf_g.o)
+ 0x080001e2 0x080001e2 0x00000006 Code RO 4451 .ARM.Collect$$_printf_percent$$00000006 c_w.l(_printf_a.o)
+ 0x080001e8 0x080001e8 0x0000000a Code RO 4456 .ARM.Collect$$_printf_percent$$00000007 c_w.l(_printf_ll.o)
+ 0x080001f2 0x080001f2 0x00000006 Code RO 4446 .ARM.Collect$$_printf_percent$$00000008 c_w.l(_printf_i.o)
+ 0x080001f8 0x080001f8 0x00000006 Code RO 4369 .ARM.Collect$$_printf_percent$$00000009 c_w.l(_printf_d.o)
+ 0x080001fe 0x080001fe 0x00000006 Code RO 4447 .ARM.Collect$$_printf_percent$$0000000A c_w.l(_printf_u.o)
+ 0x08000204 0x08000204 0x00000006 Code RO 4445 .ARM.Collect$$_printf_percent$$0000000B c_w.l(_printf_o.o)
+ 0x0800020a 0x0800020a 0x00000006 Code RO 4443 .ARM.Collect$$_printf_percent$$0000000C c_w.l(_printf_x.o)
+ 0x08000210 0x08000210 0x00000006 Code RO 4453 .ARM.Collect$$_printf_percent$$0000000D c_w.l(_printf_lli.o)
+ 0x08000216 0x08000216 0x00000006 Code RO 4454 .ARM.Collect$$_printf_percent$$0000000E c_w.l(_printf_lld.o)
+ 0x0800021c 0x0800021c 0x00000006 Code RO 4455 .ARM.Collect$$_printf_percent$$0000000F c_w.l(_printf_llu.o)
+ 0x08000222 0x08000222 0x00000006 Code RO 4460 .ARM.Collect$$_printf_percent$$00000010 c_w.l(_printf_llo.o)
+ 0x08000228 0x08000228 0x00000006 Code RO 4461 .ARM.Collect$$_printf_percent$$00000011 c_w.l(_printf_llx.o)
+ 0x0800022e 0x0800022e 0x0000000a Code RO 4457 .ARM.Collect$$_printf_percent$$00000012 c_w.l(_printf_l.o)
+ 0x08000238 0x08000238 0x00000006 Code RO 4440 .ARM.Collect$$_printf_percent$$00000013 c_w.l(_printf_c.o)
+ 0x0800023e 0x0800023e 0x00000006 Code RO 4441 .ARM.Collect$$_printf_percent$$00000014 c_w.l(_printf_s.o)
+ 0x08000244 0x08000244 0x00000006 Code RO 4458 .ARM.Collect$$_printf_percent$$00000015 c_w.l(_printf_lc.o)
+ 0x0800024a 0x0800024a 0x00000006 Code RO 4459 .ARM.Collect$$_printf_percent$$00000016 c_w.l(_printf_ls.o)
+ 0x08000250 0x08000250 0x00000004 Code RO 4452 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o)
+ 0x08000254 0x08000254 0x00000002 Code RO 4543 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o)
+ 0x08000256 0x08000256 0x00000000 Code RO 4560 .ARM.Collect$$libinit$$00000002 c_w.l(libinit2.o)
+ 0x08000256 0x08000256 0x00000000 Code RO 4562 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o)
+ 0x08000256 0x08000256 0x00000000 Code RO 4565 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o)
+ 0x08000256 0x08000256 0x00000000 Code RO 4567 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o)
+ 0x08000256 0x08000256 0x00000000 Code RO 4569 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o)
+ 0x08000256 0x08000256 0x00000006 Code RO 4570 .ARM.Collect$$libinit$$0000000F c_w.l(libinit2.o)
+ 0x0800025c 0x0800025c 0x00000000 Code RO 4572 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o)
+ 0x0800025c 0x0800025c 0x0000000c Code RO 4573 .ARM.Collect$$libinit$$00000012 c_w.l(libinit2.o)
+ 0x08000268 0x08000268 0x00000000 Code RO 4574 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o)
+ 0x08000268 0x08000268 0x00000000 Code RO 4576 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o)
+ 0x08000268 0x08000268 0x0000000a Code RO 4577 .ARM.Collect$$libinit$$00000016 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4578 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4580 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4582 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4584 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4586 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4588 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4590 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4592 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4596 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4598 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4600 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000000 Code RO 4602 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o)
+ 0x08000272 0x08000272 0x00000002 Code RO 4603 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o)
+ 0x08000274 0x08000274 0x00000002 Code RO 4621 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o)
+ 0x08000276 0x08000276 0x00000000 Code RO 4631 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o)
+ 0x08000276 0x08000276 0x00000000 Code RO 4633 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o)
+ 0x08000276 0x08000276 0x00000000 Code RO 4636 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o)
+ 0x08000276 0x08000276 0x00000000 Code RO 4639 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o)
+ 0x08000276 0x08000276 0x00000000 Code RO 4641 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o)
+ 0x08000276 0x08000276 0x00000000 Code RO 4644 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o)
+ 0x08000276 0x08000276 0x00000002 Code RO 4645 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o)
+ 0x08000278 0x08000278 0x00000000 Code RO 4389 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o)
+ 0x08000278 0x08000278 0x00000000 Code RO 4467 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o)
+ 0x08000278 0x08000278 0x00000006 Code RO 4479 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o)
+ 0x0800027e 0x0800027e 0x00000000 Code RO 4469 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o)
+ 0x0800027e 0x0800027e 0x00000004 Code RO 4470 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o)
+ 0x08000282 0x08000282 0x00000000 Code RO 4472 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o)
+ 0x08000282 0x08000282 0x00000008 Code RO 4473 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o)
+ 0x0800028a 0x0800028a 0x00000002 Code RO 4552 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o)
+ 0x0800028c 0x0800028c 0x00000000 Code RO 4605 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o)
+ 0x0800028c 0x0800028c 0x00000004 Code RO 4606 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o)
+ 0x08000290 0x08000290 0x00000006 Code RO 4607 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o)
+ 0x08000296 0x08000296 0x00000002 PAD
+ 0x08000298 0x08000298 0x00000038 Code RO 4179 .text startup_stm32f10x_cl.o
+ 0x080002d0 0x080002d0 0x00000002 Code RO 4333 .text c_w.l(use_no_semi_2.o)
+ 0x080002d2 0x080002d2 0x00000002 PAD
+ 0x080002d4 0x080002d4 0x00000034 Code RO 4335 .text c_w.l(c89vsnprintf.o)
+ 0x08000308 0x08000308 0x00000018 Code RO 4337 .text c_w.l(__2printf.o)
+ 0x08000320 0x08000320 0x0000002c Code RO 4339 .text c_w.l(__2sprintf.o)
+ 0x0800034c 0x0800034c 0x00000078 Code RO 4347 .text c_w.l(_printf_dec.o)
+ 0x080003c4 0x080003c4 0x00000188 Code RO 4366 .text c_w.l(__printf_flags_ss_wp.o)
+ 0x0800054c 0x0800054c 0x0000003e Code RO 4371 .text c_w.l(strlen.o)
+ 0x0800058a 0x0800058a 0x00000096 Code RO 4373 .text c_w.l(strncmp.o)
+ 0x08000620 0x08000620 0x0000008a Code RO 4375 .text c_w.l(rt_memcpy_v6.o)
+ 0x080006aa 0x080006aa 0x00000044 Code RO 4377 .text c_w.l(rt_memclr.o)
+ 0x080006ee 0x080006ee 0x0000004e Code RO 4379 .text c_w.l(rt_memclr_w.o)
+ 0x0800073c 0x0800073c 0x00000056 Code RO 4381 .text c_w.l(strncpy.o)
+ 0x08000792 0x08000792 0x00000006 Code RO 4383 .text c_w.l(heapauxi.o)
+ 0x08000798 0x08000798 0x00000002 Code RO 4387 .text c_w.l(use_no_semi.o)
+ 0x0800079a 0x0800079a 0x0000004e Code RO 4390 .text c_w.l(_printf_pad.o)
+ 0x080007e8 0x080007e8 0x00000024 Code RO 4392 .text c_w.l(_printf_truncate.o)
+ 0x0800080c 0x0800080c 0x00000052 Code RO 4394 .text c_w.l(_printf_str.o)
+ 0x0800085e 0x0800085e 0x000000b2 Code RO 4396 .text c_w.l(_printf_intcommon.o)
+ 0x08000910 0x08000910 0x00000028 Code RO 4398 .text c_w.l(_printf_charcount.o)
+ 0x08000938 0x08000938 0x00000030 Code RO 4400 .text c_w.l(_printf_char_common.o)
+ 0x08000968 0x08000968 0x0000000a Code RO 4402 .text c_w.l(_sputc.o)
+ 0x08000972 0x08000972 0x00000010 Code RO 4404 .text c_w.l(_snputc.o)
+ 0x08000982 0x08000982 0x00000002 PAD
+ 0x08000984 0x08000984 0x00000024 Code RO 4406 .text c_w.l(_printf_char_file.o)
+ 0x080009a8 0x080009a8 0x000000bc Code RO 4408 .text c_w.l(_printf_wctomb.o)
+ 0x08000a64 0x08000a64 0x0000007c Code RO 4411 .text c_w.l(_printf_longlong_dec.o)
+ 0x08000ae0 0x08000ae0 0x00000070 Code RO 4417 .text c_w.l(_printf_oct_int_ll.o)
+ 0x08000b50 0x08000b50 0x00000094 Code RO 4437 .text c_w.l(_printf_hex_int_ll_ptr.o)
+ 0x08000be4 0x08000be4 0x00000064 Code RO 4462 .text c_w.l(rt_memcpy_w.o)
+ 0x08000c48 0x08000c48 0x0000008a Code RO 4481 .text c_w.l(lludiv10.o)
+ 0x08000cd2 0x08000cd2 0x0000041e Code RO 4483 .text c_w.l(_printf_fp_dec.o)
+ 0x080010f0 0x080010f0 0x0000002c Code RO 4487 .text c_w.l(_printf_char.o)
+ 0x0800111c 0x0800111c 0x0000002c Code RO 4489 .text c_w.l(_printf_wchar.o)
+ 0x08001148 0x08001148 0x00000008 Code RO 4491 .text c_w.l(ferror.o)
+ 0x08001150 0x08001150 0x00000040 Code RO 4495 .text c_w.l(_wcrtomb.o)
+ 0x08001190 0x08001190 0x0000004a Code RO 4497 .text c_w.l(sys_stackheap_outer.o)
+ 0x080011da 0x080011da 0x00000002 PAD
+ 0x080011dc 0x080011dc 0x00000010 Code RO 4499 .text c_w.l(rt_ctype_table.o)
+ 0x080011ec 0x080011ec 0x00000008 Code RO 4504 .text c_w.l(rt_locale_intlibspace.o)
+ 0x080011f4 0x080011f4 0x00000080 Code RO 4506 .text c_w.l(_printf_fp_infnan.o)
+ 0x08001274 0x08001274 0x000000e4 Code RO 4508 .text c_w.l(bigflt0.o)
+ 0x08001358 0x08001358 0x00000012 Code RO 4536 .text c_w.l(exit.o)
+ 0x0800136a 0x0800136a 0x00000002 PAD
+ 0x0800136c 0x0800136c 0x00000008 Code RO 4549 .text c_w.l(libspace.o)
+ 0x08001374 0x08001374 0x00000080 Code RO 4557 .text c_w.l(strcmpv7m.o)
+ 0x080013f4 0x080013f4 0x0000003e Code RO 4511 CL$$btod_d2e c_w.l(btod.o)
+ 0x08001432 0x08001432 0x00000046 Code RO 4513 CL$$btod_d2e_denorm_low c_w.l(btod.o)
+ 0x08001478 0x08001478 0x00000060 Code RO 4512 CL$$btod_d2e_norm_op1 c_w.l(btod.o)
+ 0x080014d8 0x080014d8 0x00000338 Code RO 4521 CL$$btod_div_common c_w.l(btod.o)
+ 0x08001810 0x08001810 0x000000dc Code RO 4518 CL$$btod_e2e c_w.l(btod.o)
+ 0x080018ec 0x080018ec 0x0000002a Code RO 4515 CL$$btod_ediv c_w.l(btod.o)
+ 0x08001916 0x08001916 0x0000002a Code RO 4514 CL$$btod_emul c_w.l(btod.o)
+ 0x08001940 0x08001940 0x00000244 Code RO 4520 CL$$btod_mult_common c_w.l(btod.o)
+ 0x08001b84 0x08001b84 0x00000002 Code RO 1 i.BusFault_Handler stm32f10x_it.o
+ 0x08001b86 0x08001b86 0x00000002 PAD
+ 0x08001b88 0x08001b88 0x00000044 Code RO 403 i.Check_TCP_Connect tcp_client.o
+ 0x08001bcc 0x08001bcc 0x00000002 Code RO 2 i.DebugMon_Handler stm32f10x_it.o
+ 0x08001bce 0x08001bce 0x00000006 Code RO 404 i.Delay_s tcp_client.o
+ 0x08001bd4 0x08001bd4 0x00000074 Code RO 335 i.Display_Periodic_Handle netconf.o
+ 0x08001c48 0x08001c48 0x0000000c Code RO 2380 i.ETH_DMAClearITPendingBit stm32_eth.o
+ 0x08001c54 0x08001c54 0x00000018 Code RO 2381 i.ETH_DMAITConfig stm32_eth.o
+ 0x08001c6c 0x08001c6c 0x0000001c Code RO 2384 i.ETH_DMAReceptionCmd stm32_eth.o
+ 0x08001c88 0x08001c88 0x0000004c Code RO 2385 i.ETH_DMARxDescChainInit stm32_eth.o
+ 0x08001cd4 0x08001cd4 0x00000012 Code RO 2387 i.ETH_DMARxDescReceiveITConfig stm32_eth.o
+ 0x08001ce6 0x08001ce6 0x00000002 PAD
+ 0x08001ce8 0x08001ce8 0x0000001c Code RO 2390 i.ETH_DMATransmissionCmd stm32_eth.o
+ 0x08001d04 0x08001d04 0x00000048 Code RO 2393 i.ETH_DMATxDescChainInit stm32_eth.o
+ 0x08001d4c 0x08001d4c 0x00000008 Code RO 2394 i.ETH_DMATxDescChecksumInsertionConfig stm32_eth.o
+ 0x08001d54 0x08001d54 0x00000018 Code RO 2402 i.ETH_DeInit stm32_eth.o
+ 0x08001d6c 0x08001d6c 0x00000012 Code RO 2403 i.ETH_Delay stm32_eth.o
+ 0x08001d7e 0x08001d7e 0x00000002 PAD
+ 0x08001d80 0x08001d80 0x00000010 Code RO 2408 i.ETH_FlushTransmitFIFO stm32_eth.o
+ 0x08001d90 0x08001d90 0x0000000c Code RO 2981 i.ETH_GetCurrentTxBuffer ethernetif.o
+ 0x08001d9c 0x08001d9c 0x00000008 Code RO 2419 i.ETH_GetDMARxDescFrameLength stm32_eth.o
+ 0x08001da4 0x08001da4 0x00000024 Code RO 2434 i.ETH_GetRxPktSize stm32_eth.o
+ 0x08001dc8 0x08001dc8 0x00000014 Code RO 2435 i.ETH_GetSoftwareResetStatus stm32_eth.o
+ 0x08001ddc 0x08001ddc 0x00000022 Code RO 3 i.ETH_IRQHandler stm32f10x_it.o
+ 0x08001dfe 0x08001dfe 0x00000002 PAD
+ 0x08001e00 0x08001e00 0x00000208 Code RO 2442 i.ETH_Init stm32_eth.o
+ 0x08002008 0x08002008 0x0000001c Code RO 2445 i.ETH_MACAddressConfig stm32_eth.o
+ 0x08002024 0x08002024 0x0000001c Code RO 2450 i.ETH_MACReceptionCmd stm32_eth.o
+ 0x08002040 0x08002040 0x0000001c Code RO 2451 i.ETH_MACTransmissionCmd stm32_eth.o
+ 0x0800205c 0x0800205c 0x00000058 Code RO 2462 i.ETH_ReadPHYRegister stm32_eth.o
+ 0x080020b4 0x080020b4 0x00000050 Code RO 2982 i.ETH_RxPkt_ChainMode ethernetif.o
+ 0x08002104 0x08002104 0x00000010 Code RO 2473 i.ETH_SoftwareReset stm32_eth.o
+ 0x08002114 0x08002114 0x00000022 Code RO 2474 i.ETH_Start stm32_eth.o
+ 0x08002136 0x08002136 0x0000007c Code RO 2475 i.ETH_StructInit stm32_eth.o
+ 0x080021b2 0x080021b2 0x00000002 PAD
+ 0x080021b4 0x080021b4 0x0000003c Code RO 2983 i.ETH_TxPkt_ChainMode ethernetif.o
+ 0x080021f0 0x080021f0 0x00000054 Code RO 2477 i.ETH_WritePHYRegister stm32_eth.o
+ 0x08002244 0x08002244 0x00000002 Code RO 4 i.EXTI15_10_IRQHandler stm32f10x_it.o
+ 0x08002246 0x08002246 0x00000002 PAD
+ 0x08002248 0x08002248 0x00000094 Code RO 285 i.Ethernet_Configuration stm32f107.o
+ 0x080022dc 0x080022dc 0x000000f8 Code RO 286 i.GPIO_Configuration stm32f107.o
+ 0x080023d4 0x080023d4 0x0000000c Code RO 681 i.GPIO_ETH_MediaInterfaceConfig stm32f10x_gpio.o
+ 0x080023e0 0x080023e0 0x0000009c Code RO 685 i.GPIO_Init stm32f10x_gpio.o
+ 0x0800247c 0x0800247c 0x00000048 Code RO 687 i.GPIO_PinRemapConfig stm32f10x_gpio.o
+ 0x080024c4 0x080024c4 0x00000004 Code RO 692 i.GPIO_ResetBits stm32f10x_gpio.o
+ 0x080024c8 0x080024c8 0x00000004 Code RO 693 i.GPIO_SetBits stm32f10x_gpio.o
+ 0x080024cc 0x080024cc 0x00000002 Code RO 5 i.HardFault_Handler stm32f10x_it.o
+ 0x080024ce 0x080024ce 0x00000002 PAD
+ 0x080024d0 0x080024d0 0x0000002c Code RO 4183 i.LED_Init1 led.o
+ 0x080024fc 0x080024fc 0x0000002c Code RO 4184 i.LED_Init2 led.o
+ 0x08002528 0x08002528 0x0000002c Code RO 4185 i.LED_Init3 led.o
+ 0x08002554 0x08002554 0x00000088 Code RO 336 i.LwIP_Init netconf.o
+ 0x080025dc 0x080025dc 0x00000034 Code RO 337 i.LwIP_Periodic_Handle netconf.o
+ 0x08002610 0x08002610 0x0000000c Code RO 338 i.LwIP_Pkt_Handle netconf.o
+ 0x0800261c 0x0800261c 0x00000002 Code RO 6 i.MemManage_Handler stm32f10x_it.o
+ 0x0800261e 0x0800261e 0x0000001a Code RO 339 i.My_IP4_ADDR netconf.o
+ 0x08002638 0x08002638 0x00000002 Code RO 7 i.NMI_Handler stm32f10x_it.o
+ 0x0800263a 0x0800263a 0x000000b0 Code RO 287 i.NVIC_Configuration stm32f107.o
+ 0x080026ea 0x080026ea 0x00000002 PAD
+ 0x080026ec 0x080026ec 0x00000064 Code RO 1389 i.NVIC_Init misc.o
+ 0x08002750 0x08002750 0x00000014 Code RO 1390 i.NVIC_PriorityGroupConfig misc.o
+ 0x08002764 0x08002764 0x00000020 Code RO 288 i.NVIC_SetPriority stm32f107.o
+ 0x08002784 0x08002784 0x00000014 Code RO 1391 i.NVIC_SetVectorTable misc.o
+ 0x08002798 0x08002798 0x00000002 Code RO 8 i.PendSV_Handler stm32f10x_it.o
+ 0x0800279a 0x0800279a 0x00000002 PAD
+ 0x0800279c 0x0800279c 0x00000018 Code RO 794 i.RCC_AHBPeriphClockCmd stm32f10x_rcc.o
+ 0x080027b4 0x080027b4 0x00000018 Code RO 795 i.RCC_AHBPeriphResetCmd stm32f10x_rcc.o
+ 0x080027cc 0x080027cc 0x00000018 Code RO 796 i.RCC_APB1PeriphClockCmd stm32f10x_rcc.o
+ 0x080027e4 0x080027e4 0x00000018 Code RO 798 i.RCC_APB2PeriphClockCmd stm32f10x_rcc.o
+ 0x080027fc 0x080027fc 0x000000c8 Code RO 806 i.RCC_GetClocksFreq stm32f10x_rcc.o
+ 0x080028c4 0x080028c4 0x00000030 Code RO 807 i.RCC_GetFlagStatus stm32f10x_rcc.o
+ 0x080028f4 0x080028f4 0x0000000c Code RO 818 i.RCC_MCOConfig stm32f10x_rcc.o
+ 0x08002900 0x08002900 0x0000000c Code RO 824 i.RCC_PLL3Cmd stm32f10x_rcc.o
+ 0x0800290c 0x0800290c 0x00000014 Code RO 825 i.RCC_PLL3Config stm32f10x_rcc.o
+ 0x08002920 0x08002920 0x00000002 Code RO 9 i.SVC_Handler stm32f10x_it.o
+ 0x08002922 0x08002922 0x00000002 PAD
+ 0x08002924 0x08002924 0x000000d0 Code RO 4138 i.SetSysClockTo72 system_stm32f10x.o
+ 0x080029f4 0x080029f4 0x00000028 Code RO 2984 i.Set_MAC_Address ethernetif.o
+ 0x08002a1c 0x08002a1c 0x00000004 Code RO 10 i.SysTick_Handler stm32f10x_it.o
+ 0x08002a20 0x08002a20 0x0000004c Code RO 4139 i.SystemInit system_stm32f10x.o
+ 0x08002a6c 0x08002a6c 0x00000018 Code RO 223 i.System_Periodic_Handle main.o
+ 0x08002a84 0x08002a84 0x00000074 Code RO 289 i.System_Setup stm32f107.o
+ 0x08002af8 0x08002af8 0x00000054 Code RO 405 i.TCP_Client_Init tcp_client.o
+ 0x08002b4c 0x08002b4c 0x00000188 Code RO 406 i.TCP_Client_Recv tcp_client.o
+ 0x08002cd4 0x08002cd4 0x00000018 Code RO 407 i.TCP_Client_Send_Data tcp_client.o
+ 0x08002cec 0x08002cec 0x00000004 Code RO 408 i.TCP_Connected tcp_client.o
+ 0x08002cf0 0x08002cf0 0x0000001e Code RO 290 i.TIM2_IRQHandler stm32f107.o
+ 0x08002d0e 0x08002d0e 0x00000006 Code RO 1656 i.TIM_ClearITPendingBit stm32f10x_tim.o
+ 0x08002d14 0x08002d14 0x00000018 Code RO 1682 i.TIM_GetITStatus stm32f10x_tim.o
+ 0x08002d2c 0x08002d2c 0x00000010 Code RO 224 i.Time_Update main.o
+ 0x08002d3c 0x08002d3c 0x00000044 Code RO 4230 i.UART4_IRQHandler usart.o
+ 0x08002d80 0x08002d80 0x000000c8 Code RO 4231 i.UART5_IRQHandler usart.o
+ 0x08002e48 0x08002e48 0x0000003c Code RO 484 i.USART1_IRQHandler sci.o
+ 0x08002e84 0x08002e84 0x000000b4 Code RO 4232 i.USART1_Init usart.o
+ 0x08002f38 0x08002f38 0x0000004c Code RO 4233 i.USART1_printf usart.o
+ 0x08002f84 0x08002f84 0x00000044 Code RO 485 i.USART2_IRQHandler sci.o
+ 0x08002fc8 0x08002fc8 0x000000b8 Code RO 4234 i.USART2_Init usart.o
+ 0x08003080 0x08003080 0x0000004c Code RO 4235 i.USART2_printf usart.o
+ 0x080030cc 0x080030cc 0x000000b0 Code RO 4236 i.USART4_Init usart.o
+ 0x0800317c 0x0800317c 0x0000004c Code RO 4237 i.USART4_printf usart.o
+ 0x080031c8 0x080031c8 0x000000b4 Code RO 4238 i.USART5_Init usart.o
+ 0x0800327c 0x0800327c 0x0000000c Code RO 512 i.USART_ClearITPendingBit stm32f10x_usart.o
+ 0x08003288 0x08003288 0x00000014 Code RO 515 i.USART_Cmd stm32f10x_usart.o
+ 0x0800329c 0x0800329c 0x00000140 Code RO 486 i.USART_Configuration sci.o
+ 0x080033dc 0x080033dc 0x0000000e Code RO 518 i.USART_GetFlagStatus stm32f10x_usart.o
+ 0x080033ea 0x080033ea 0x0000003e Code RO 519 i.USART_GetITStatus stm32f10x_usart.o
+ 0x08003428 0x08003428 0x00000030 Code RO 521 i.USART_ITConfig stm32f10x_usart.o
+ 0x08003458 0x08003458 0x0000008c Code RO 522 i.USART_Init stm32f10x_usart.o
+ 0x080034e4 0x080034e4 0x00000008 Code RO 527 i.USART_ReceiveData stm32f10x_usart.o
+ 0x080034ec 0x080034ec 0x00000008 Code RO 530 i.USART_SendData stm32f10x_usart.o
+ 0x080034f4 0x080034f4 0x00000002 Code RO 11 i.UsageFault_Handler stm32f10x_it.o
+ 0x080034f6 0x080034f6 0x00000028 Code RO 4547 i.__ARM_fpclassify m_ws.l(fpclassify.o)
+ 0x0800351e 0x0800351e 0x0000000e Code RO 4359 i._is_digit c_w.l(__printf_wp.o)
+ 0x0800352c 0x0800352c 0x00000002 Code RO 4240 i._sys_exit usart.o
+ 0x0800352e 0x0800352e 0x00000018 Code RO 4207 i.delay_ms delay.o
+ 0x08003546 0x08003546 0x00000020 Code RO 4209 i.delay_us delay.o
+ 0x08003566 0x08003566 0x000000ca Code RO 4052 i.etharp_arp_input etharp.o
+ 0x08003630 0x08003630 0x00000028 Code RO 4054 i.etharp_ip_input etharp.o
+ 0x08003658 0x08003658 0x000000b8 Code RO 4055 i.etharp_output etharp.o
+ 0x08003710 0x08003710 0x00000104 Code RO 4056 i.etharp_query etharp.o
+ 0x08003814 0x08003814 0x0000009e Code RO 4057 i.etharp_raw etharp.o
+ 0x080038b2 0x080038b2 0x00000002 PAD
+ 0x080038b4 0x080038b4 0x00000024 Code RO 4058 i.etharp_request etharp.o
+ 0x080038d8 0x080038d8 0x00000036 Code RO 4059 i.etharp_send_ip etharp.o
+ 0x0800390e 0x0800390e 0x00000002 PAD
+ 0x08003910 0x08003910 0x00000054 Code RO 4060 i.etharp_tmr etharp.o
+ 0x08003964 0x08003964 0x00000054 Code RO 4061 i.ethernet_input etharp.o
+ 0x080039b8 0x080039b8 0x00000040 Code RO 2985 i.ethernetif_init ethernetif.o
+ 0x080039f8 0x080039f8 0x00000078 Code RO 2986 i.ethernetif_input ethernetif.o
+ 0x08003a70 0x08003a70 0x0000013c Code RO 4062 i.find_entry etharp.o
+ 0x08003bac 0x08003bac 0x00000014 Code RO 4241 i.fputc usart.o
+ 0x08003bc0 0x08003bc0 0x0000001e Code RO 4063 i.free_etharp_q etharp.o
+ 0x08003bde 0x08003bde 0x00000004 Code RO 3854 i.htonl inet.o
+ 0x08003be2 0x08003be2 0x00000004 Code RO 3855 i.htons inet.o
+ 0x08003be6 0x08003be6 0x00000008 Code RO 3819 i.icmp_dest_unreach icmp.o
+ 0x08003bee 0x08003bee 0x00000114 Code RO 3820 i.icmp_input icmp.o
+ 0x08003d02 0x08003d02 0x00000066 Code RO 3821 i.icmp_send_response icmp.o
+ 0x08003d68 0x08003d68 0x00000008 Code RO 3822 i.icmp_time_exceeded icmp.o
+ 0x08003d70 0x08003d70 0x0000000c Code RO 3902 i.inet_chksum inet_chksum.o
+ 0x08003d7c 0x08003d7c 0x00000048 Code RO 3903 i.inet_chksum_pbuf inet_chksum.o
+ 0x08003dc4 0x08003dc4 0x00000030 Code RO 3982 i.ip_addr_isbroadcast ip_addr.o
+ 0x08003df4 0x08003df4 0x00000130 Code RO 4005 i.ip_frag ip_frag.o
+ 0x08003f24 0x08003f24 0x00000164 Code RO 3940 i.ip_input ip.o
+ 0x08004088 0x08004088 0x00000034 Code RO 3941 i.ip_output ip.o
+ 0x080040bc 0x080040bc 0x000000cc Code RO 3942 i.ip_output_if ip.o
+ 0x08004188 0x08004188 0x000001b0 Code RO 4006 i.ip_reass ip_frag.o
+ 0x08004338 0x08004338 0x000000f0 Code RO 4007 i.ip_reass_chain_frag_into_datagram_and_validate ip_frag.o
+ 0x08004428 0x08004428 0x00000024 Code RO 4008 i.ip_reass_dequeue_datagram ip_frag.o
+ 0x0800444c 0x0800444c 0x00000070 Code RO 4009 i.ip_reass_free_complete_datagram ip_frag.o
+ 0x080044bc 0x080044bc 0x00000074 Code RO 4010 i.ip_reass_remove_oldest_datagram ip_frag.o
+ 0x08004530 0x08004530 0x00000048 Code RO 3943 i.ip_route ip.o
+ 0x08004578 0x08004578 0x00000088 Code RO 2987 i.low_level_init ethernetif.o
+ 0x08004600 0x08004600 0x0000002c Code RO 2988 i.low_level_output ethernetif.o
+ 0x0800462c 0x0800462c 0x0000003c Code RO 3905 i.lwip_standard_chksum inet_chksum.o
+ 0x08004668 0x08004668 0x0000023c Code RO 225 i.main main.o
+ 0x080048a4 0x080048a4 0x0000002c Code RO 3513 i.mem_free mem.o
+ 0x080048d0 0x080048d0 0x00000034 Code RO 3514 i.mem_init mem.o
+ 0x08004904 0x08004904 0x000000a8 Code RO 3515 i.mem_malloc mem.o
+ 0x080049ac 0x080049ac 0x000000c4 Code RO 3516 i.mem_realloc mem.o
+ 0x08004a70 0x08004a70 0x00000018 Code RO 3556 i.memp_free memp.o
+ 0x08004a88 0x08004a88 0x00000058 Code RO 3557 i.memp_init memp.o
+ 0x08004ae0 0x08004ae0 0x00000020 Code RO 3558 i.memp_malloc memp.o
+ 0x08004b00 0x08004b00 0x00000048 Code RO 3598 i.netif_add netif.o
+ 0x08004b48 0x08004b48 0x0000000a Code RO 3600 i.netif_is_up netif.o
+ 0x08004b52 0x08004b52 0x00000020 Code RO 3602 i.netif_set_addr netif.o
+ 0x08004b72 0x08004b72 0x00000002 PAD
+ 0x08004b74 0x08004b74 0x0000000c Code RO 3603 i.netif_set_default netif.o
+ 0x08004b80 0x08004b80 0x00000008 Code RO 3605 i.netif_set_gw netif.o
+ 0x08004b88 0x08004b88 0x00000068 Code RO 3606 i.netif_set_ipaddr netif.o
+ 0x08004bf0 0x08004bf0 0x00000008 Code RO 3607 i.netif_set_netmask netif.o
+ 0x08004bf8 0x08004bf8 0x0000001c Code RO 3608 i.netif_set_up netif.o
+ 0x08004c14 0x08004c14 0x00000004 Code RO 3859 i.ntohl inet.o
+ 0x08004c18 0x08004c18 0x00000004 Code RO 3860 i.ntohs inet.o
+ 0x08004c1c 0x08004c1c 0x0000010c Code RO 3673 i.pbuf_alloc pbuf.o
+ 0x08004d28 0x08004d28 0x00000028 Code RO 3674 i.pbuf_cat pbuf.o
+ 0x08004d50 0x08004d50 0x00000012 Code RO 3675 i.pbuf_chain pbuf.o
+ 0x08004d62 0x08004d62 0x00000012 Code RO 3676 i.pbuf_clen pbuf.o
+ 0x08004d74 0x08004d74 0x00000090 Code RO 3678 i.pbuf_copy pbuf.o
+ 0x08004e04 0x08004e04 0x00000068 Code RO 3679 i.pbuf_copy_partial pbuf.o
+ 0x08004e6c 0x08004e6c 0x00000044 Code RO 3681 i.pbuf_free pbuf.o
+ 0x08004eb0 0x08004eb0 0x00000060 Code RO 3682 i.pbuf_header pbuf.o
+ 0x08004f10 0x08004f10 0x0000004e Code RO 3683 i.pbuf_realloc pbuf.o
+ 0x08004f5e 0x08004f5e 0x0000000c Code RO 3684 i.pbuf_ref pbuf.o
+ 0x08004f6a 0x08004f6a 0x00000002 PAD
+ 0x08004f6c 0x08004f6c 0x00000054 Code RO 3517 i.plug_holes mem.o
+ 0x08004fc0 0x08004fc0 0x00000068 Code RO 3759 i.raw_input raw.o
+ 0x08005028 0x08005028 0x00000094 Code RO 3106 i.tcp_abandon tcp.o
+ 0x080050bc 0x080050bc 0x00000104 Code RO 3109 i.tcp_alloc tcp.o
+ 0x080051c0 0x080051c0 0x000000bc Code RO 3111 i.tcp_bind tcp.o
+ 0x0800527c 0x0800527c 0x000000a0 Code RO 3112 i.tcp_close tcp.o
+ 0x0800531c 0x0800531c 0x000000c4 Code RO 3113 i.tcp_connect tcp.o
+ 0x080053e0 0x080053e0 0x00000020 Code RO 3114 i.tcp_eff_send_mss tcp.o
+ 0x08005400 0x08005400 0x000002f0 Code RO 3328 i.tcp_enqueue tcp_out.o
+ 0x080056f0 0x080056f0 0x00000058 Code RO 3116 i.tcp_fasttmr tcp.o
+ 0x08005748 0x08005748 0x0000031c Code RO 3282 i.tcp_input tcp_in.o
+ 0x08005a64 0x08005a64 0x00000046 Code RO 3329 i.tcp_keepalive tcp_out.o
+ 0x08005aaa 0x08005aaa 0x00000002 PAD
+ 0x08005aac 0x08005aac 0x000000e8 Code RO 3283 i.tcp_listen_input tcp_in.o
+ 0x08005b94 0x08005b94 0x00000006 Code RO 3118 i.tcp_new tcp.o
+ 0x08005b9a 0x08005b9a 0x00000002 PAD
+ 0x08005b9c 0x08005b9c 0x00000060 Code RO 3119 i.tcp_new_port tcp.o
+ 0x08005bfc 0x08005bfc 0x00000010 Code RO 3120 i.tcp_next_iss tcp.o
+ 0x08005c0c 0x08005c0c 0x00000218 Code RO 3330 i.tcp_output tcp_out.o
+ 0x08005e24 0x08005e24 0x000000b0 Code RO 3331 i.tcp_output_segment tcp_out.o
+ 0x08005ed4 0x08005ed4 0x00000078 Code RO 3332 i.tcp_output_set_header tcp_out.o
+ 0x08005f4c 0x08005f4c 0x00000080 Code RO 3284 i.tcp_parseopt tcp_in.o
+ 0x08005fcc 0x08005fcc 0x00000030 Code RO 3121 i.tcp_pcb_purge tcp.o
+ 0x08005ffc 0x08005ffc 0x00000060 Code RO 3122 i.tcp_pcb_remove tcp.o
+ 0x0800605c 0x0800605c 0x00000344 Code RO 3285 i.tcp_process tcp_in.o
+ 0x080063a0 0x080063a0 0x0000046a Code RO 3286 i.tcp_receive tcp_in.o
+ 0x0800680a 0x0800680a 0x00000006 Code RO 3124 i.tcp_recv tcp.o
+ 0x08006810 0x08006810 0x0000001c Code RO 3125 i.tcp_recv_null tcp.o
+ 0x0800682c 0x0800682c 0x0000003c Code RO 3126 i.tcp_recved tcp.o
+ 0x08006868 0x08006868 0x00000054 Code RO 3333 i.tcp_rexmit tcp_out.o
+ 0x080068bc 0x080068bc 0x0000002e Code RO 3334 i.tcp_rexmit_rto tcp_out.o
+ 0x080068ea 0x080068ea 0x00000098 Code RO 3335 i.tcp_rst tcp_out.o
+ 0x08006982 0x08006982 0x00000020 Code RO 3127 i.tcp_seg_free tcp.o
+ 0x080069a2 0x080069a2 0x0000001a Code RO 3128 i.tcp_segs_free tcp.o
+ 0x080069bc 0x080069bc 0x00000016 Code RO 3336 i.tcp_send_ctrl tcp_out.o
+ 0x080069d2 0x080069d2 0x00000002 PAD
+ 0x080069d4 0x080069d4 0x00000210 Code RO 3131 i.tcp_slowtmr tcp.o
+ 0x08006be4 0x08006be4 0x00000020 Code RO 3132 i.tcp_tmr tcp.o
+ 0x08006c04 0x08006c04 0x0000002a Code RO 3133 i.tcp_update_rcv_ann_wnd tcp.o
+ 0x08006c2e 0x08006c2e 0x0000002e Code RO 3337 i.tcp_write tcp_out.o
+ 0x08006c5c 0x08006c5c 0x00000052 Code RO 3338 i.tcp_zero_window_probe tcp_out.o
+ 0x08006cae 0x08006cae 0x00000002 PAD
+ 0x08006cb0 0x08006cb0 0x0000013c Code RO 3401 i.udp_input udp.o
+ 0x08006dec 0x08006dec 0x000000a8 Code RO 4064 i.update_arp_entry etharp.o
+ 0x08006e94 0x08006e94 0x0000002c Code RO 4534 locale$$code c_w.l(lc_numeric_c.o)
+ 0x08006ec0 0x08006ec0 0x0000002c Code RO 4555 locale$$code c_w.l(lc_ctype_c.o)
+ 0x08006eec 0x08006eec 0x00000004 Code RO 4464 x$fpl$printf1 fz_ws.l(printf1.o)
+ 0x08006ef0 0x08006ef0 0x00000000 Code RO 4546 x$fpl$usenofp fz_ws.l(usenofp.o)
+ 0x08006ef0 0x08006ef0 0x00000004 Data RO 226 .constdata main.o
+ 0x08006ef4 0x08006ef4 0x00000014 Data RO 3134 .constdata tcp.o
+ 0x08006f08 0x08006f08 0x00000024 Data RO 3560 .constdata memp.o
+ 0x08006f2c 0x08006f2c 0x00000004 Data RO 3983 .constdata ip_addr.o
+ 0x08006f30 0x08006f30 0x0000000c Data RO 4066 .constdata etharp.o
+ 0x08006f3c 0x08006f3c 0x00000011 Data RO 4367 .constdata c_w.l(__printf_flags_ss_wp.o)
+ 0x08006f4d 0x08006f4d 0x00000003 PAD
+ 0x08006f50 0x08006f50 0x00000008 Data RO 4409 .constdata c_w.l(_printf_wctomb.o)
+ 0x08006f58 0x08006f58 0x00000028 Data RO 4438 .constdata c_w.l(_printf_hex_int_ll_ptr.o)
+ 0x08006f80 0x08006f80 0x00000094 Data RO 4509 .constdata c_w.l(bigflt0.o)
+ 0x08007014 0x08007014 0x00000020 Data RO 4677 Region$$Table anon$$obj.o
+ 0x08007034 0x08007034 0x0000001c Data RO 4533 locale$$data c_w.l(lc_numeric_c.o)
+ 0x08007050 0x08007050 0x00000110 Data RO 4554 locale$$data c_w.l(lc_ctype_c.o)
+
+
+ Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x08007160, Size: 0x00009c70, Max: 0x00010000, ABSOLUTE)
+
+ Exec Addr Load Addr Size Type Attr Idx E Section Name Object
+
+ 0x20000000 0x08007160 0x00000010 Data RW 227 .data main.o
+ 0x20000010 0x08007170 0x00000010 Data RW 341 .data netconf.o
+ 0x20000020 0x08007180 0x00000010 Data RW 411 .data tcp_client.o
+ 0x20000030 0x08007190 0x00000014 Data RW 834 .data stm32f10x_rcc.o
+ 0x20000044 0x080071a4 0x00000010 Data RW 2478 .data stm32_eth.o
+ 0x20000054 0x080071b4 0x00000006 Data RW 2993 .data ethernetif.o
+ 0x2000005a 0x080071ba 0x00000002 PAD
+ 0x2000005c 0x080071bc 0x00000020 Data RW 3135 .data tcp.o
+ 0x2000007c 0x080071dc 0x0000001c Data RW 3288 .data tcp_in.o
+ 0x20000098 0x080071f8 0x00000004 Data RW 3408 .data udp.o
+ 0x2000009c 0x080071fc 0x00000010 Data RW 3519 .data mem.o
+ 0x200000ac 0x0800720c 0x0000000c Data RW 3609 .data netif.o
+ 0x200000b8 0x08007218 0x00000004 Data RW 3765 .data raw.o
+ 0x200000bc 0x0800721c 0x0000000c Data RW 3944 .data ip.o
+ 0x200000c8 0x08007228 0x00000008 Data RW 4013 .data ip_frag.o
+ 0x200000d0 0x08007230 0x00000001 Data RW 4067 .data etharp.o
+ 0x200000d1 0x08007231 0x00000003 PAD
+ 0x200000d4 0x08007234 0x00000004 Data RW 4250 .data usart.o
+ 0x200000d8 - 0x00000030 Zero RW 340 .bss netconf.o
+ 0x20000108 - 0x00000384 Zero RW 410 .bss tcp_client.o
+ 0x2000048c - 0x00002400 Zero RW 2989 .bss ethernetif.o
+ 0x2000288c - 0x00000014 Zero RW 3287 .bss tcp_in.o
+ 0x200028a0 - 0x00002014 Zero RW 3518 .bss mem.o
+ 0x200048b4 - 0x000046af Zero RW 3559 .bss memp.o
+ 0x20008f63 - 0x000005e0 Zero RW 4012 .bss ip_frag.o
+ 0x20009543 0x08007238 0x00000001 PAD
+ 0x20009544 - 0x000000c8 Zero RW 4065 .bss etharp.o
+ 0x2000960c - 0x00000060 Zero RW 4550 .bss c_w.l(libspace.o)
+ 0x2000966c 0x08007238 0x00000004 PAD
+ 0x20009670 - 0x00000200 Zero RW 4177 HEAP startup_stm32f10x_cl.o
+ 0x20009870 - 0x00000400 Zero RW 4176 STACK startup_stm32f10x_cl.o
+
+
+==============================================================================
+
+Image component sizes
+
+
+ Code (inc. data) RO Data RW Data ZI Data Debug Object Name
+
+ 0 0 0 0 0 32 core_cm3.o
+ 56 0 0 0 0 1332 delay.o
+ 1616 34 12 1 200 13464 etharp.o
+ 556 52 0 6 9216 7494 ethernetif.o
+ 394 0 0 0 0 3566 icmp.o
+ 16 0 0 0 0 2978 inet.o
+ 144 0 0 0 0 5709 inet_chksum.o
+ 0 0 0 0 0 692 init.o
+ 684 22 0 12 0 4913 ip.o
+ 48 0 4 0 0 5501 ip_addr.o
+ 1240 34 0 8 1504 7701 ip_frag.o
+ 132 16 0 0 0 1500 led.o
+ 612 94 4 16 0 2917 main.o
+ 544 30 0 16 8212 5053 mem.o
+ 144 20 36 0 18095 3918 memp.o
+ 140 24 0 0 0 2329 misc.o
+ 342 62 0 16 48 5966 netconf.o
+ 274 18 0 12 0 7177 netif.o
+ 846 0 0 0 0 8545 pbuf.o
+ 104 4 0 4 0 1700 raw.o
+ 448 28 0 0 0 6634 sci.o
+ 56 22 336 0 1536 868 startup_stm32f10x_cl.o
+ 1338 136 0 16 0 16124 stm32_eth.o
+ 750 20 0 0 0 8320 stm32f107.o
+ 248 10 0 0 0 4810 stm32f10x_gpio.o
+ 56 0 0 0 0 323379 stm32f10x_it.o
+ 388 68 0 20 0 9401 stm32f10x_rcc.o
+ 30 0 0 0 0 5361 stm32f10x_tim.o
+ 312 6 0 0 0 7291 stm32f10x_usart.o
+ 284 30 0 0 0 1665 system_stm32f10x.o
+ 2088 80 20 32 0 23191 tcp.o
+ 578 100 0 16 900 5099 tcp_client.o
+ 3122 76 0 28 20 14728 tcp_in.o
+ 2086 12 0 0 0 10803 tcp_out.o
+ 316 4 0 4 0 3404 udp.o
+ 1238 108 0 4 0 10357 usart.o
+
+ ----------------------------------------------------------------------
+ 21266 1110 444 216 39732 543922 Object Totals
+ 0 0 32 0 0 0 (incl. Generated)
+ 36 0 0 5 1 0 (incl. Padding)
+
+ ----------------------------------------------------------------------
+
+ Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
+
+ 24 4 0 0 0 84 __2printf.o
+ 44 6 0 0 0 84 __2sprintf.o
+ 8 0 0 0 0 68 __main.o
+ 392 4 17 0 0 92 __printf_flags_ss_wp.o
+ 14 0 0 0 0 68 __printf_wp.o
+ 0 0 0 0 0 0 __rtentry.o
+ 12 0 0 0 0 0 __rtentry2.o
+ 6 0 0 0 0 0 __rtentry4.o
+ 52 8 0 0 0 0 __scatter.o
+ 26 0 0 0 0 0 __scatter_copy.o
+ 28 0 0 0 0 0 __scatter_zi.o
+ 6 0 0 0 0 0 _printf_a.o
+ 6 0 0 0 0 0 _printf_c.o
+ 44 0 0 0 0 108 _printf_char.o
+ 48 6 0 0 0 96 _printf_char_common.o
+ 36 4 0 0 0 80 _printf_char_file.o
+ 40 0 0 0 0 68 _printf_charcount.o
+ 6 0 0 0 0 0 _printf_d.o
+ 120 16 0 0 0 92 _printf_dec.o
+ 6 0 0 0 0 0 _printf_e.o
+ 6 0 0 0 0 0 _printf_f.o
+ 1054 0 0 0 0 216 _printf_fp_dec.o
+ 128 16 0 0 0 84 _printf_fp_infnan.o
+ 6 0 0 0 0 0 _printf_g.o
+ 148 4 40 0 0 160 _printf_hex_int_ll_ptr.o
+ 6 0 0 0 0 0 _printf_i.o
+ 178 0 0 0 0 88 _printf_intcommon.o
+ 10 0 0 0 0 0 _printf_l.o
+ 6 0 0 0 0 0 _printf_lc.o
+ 10 0 0 0 0 0 _printf_ll.o
+ 6 0 0 0 0 0 _printf_lld.o
+ 6 0 0 0 0 0 _printf_lli.o
+ 6 0 0 0 0 0 _printf_llo.o
+ 6 0 0 0 0 0 _printf_llu.o
+ 6 0 0 0 0 0 _printf_llx.o
+ 124 16 0 0 0 92 _printf_longlong_dec.o
+ 6 0 0 0 0 0 _printf_ls.o
+ 6 0 0 0 0 0 _printf_n.o
+ 6 0 0 0 0 0 _printf_o.o
+ 112 10 0 0 0 124 _printf_oct_int_ll.o
+ 6 0 0 0 0 0 _printf_p.o
+ 78 0 0 0 0 108 _printf_pad.o
+ 0 0 0 0 0 0 _printf_percent.o
+ 4 0 0 0 0 0 _printf_percent_end.o
+ 6 0 0 0 0 0 _printf_s.o
+ 82 0 0 0 0 80 _printf_str.o
+ 36 0 0 0 0 84 _printf_truncate.o
+ 6 0 0 0 0 0 _printf_u.o
+ 44 0 0 0 0 108 _printf_wchar.o
+ 188 6 8 0 0 92 _printf_wctomb.o
+ 6 0 0 0 0 0 _printf_x.o
+ 16 0 0 0 0 68 _snputc.o
+ 10 0 0 0 0 68 _sputc.o
+ 64 0 0 0 0 92 _wcrtomb.o
+ 228 4 148 0 0 96 bigflt0.o
+ 1936 128 0 0 0 672 btod.o
+ 52 4 0 0 0 80 c89vsnprintf.o
+ 18 0 0 0 0 80 exit.o
+ 8 0 0 0 0 68 ferror.o
+ 6 0 0 0 0 152 heapauxi.o
+ 44 10 272 0 0 76 lc_ctype_c.o
+ 44 10 28 0 0 76 lc_numeric_c.o
+ 2 0 0 0 0 0 libinit.o
+ 30 0 0 0 0 0 libinit2.o
+ 2 0 0 0 0 0 libshutdown.o
+ 2 0 0 0 0 0 libshutdown2.o
+ 8 4 0 0 96 68 libspace.o
+ 138 0 0 0 0 80 lludiv10.o
+ 16 4 0 0 0 76 rt_ctype_table.o
+ 8 4 0 0 0 68 rt_locale_intlibspace.o
+ 68 0 0 0 0 68 rt_memclr.o
+ 78 0 0 0 0 80 rt_memclr_w.o
+ 138 0 0 0 0 68 rt_memcpy_v6.o
+ 100 0 0 0 0 80 rt_memcpy_w.o
+ 2 0 0 0 0 0 rtexit.o
+ 10 0 0 0 0 0 rtexit2.o
+ 128 0 0 0 0 68 strcmpv7m.o
+ 62 0 0 0 0 76 strlen.o
+ 150 0 0 0 0 80 strncmp.o
+ 86 0 0 0 0 76 strncpy.o
+ 74 0 0 0 0 80 sys_stackheap_outer.o
+ 2 0 0 0 0 68 use_no_semi.o
+ 2 0 0 0 0 68 use_no_semi_2.o
+ 4 0 0 0 0 68 printf1.o
+ 0 0 0 0 0 0 usenofp.o
+ 40 0 0 0 0 68 fpclassify.o
+
+ ----------------------------------------------------------------------
+ 6798 268 516 0 100 4844 Library Totals
+ 12 0 3 0 4 0 (incl. Padding)
+
+ ----------------------------------------------------------------------
+
+ Code (inc. data) RO Data RW Data ZI Data Debug Library Name
+
+ 6742 268 513 0 96 4708 c_w.l
+ 4 0 0 0 0 68 fz_ws.l
+ 40 0 0 0 0 68 m_ws.l
+
+ ----------------------------------------------------------------------
+ 6798 268 516 0 100 4844 Library Totals
+
+ ----------------------------------------------------------------------
+
+==============================================================================
+
+
+ Code (inc. data) RO Data RW Data ZI Data Debug
+
+ 28064 1378 960 216 39832 535502 Grand Totals
+ 28064 1378 960 216 39832 535502 ELF Image Totals
+ 28064 1378 960 216 0 0 ROM Totals
+
+==============================================================================
+
+ Total RO Size (Code + RO Data) 29024 ( 28.34kB)
+ Total RW Size (RW Data + ZI Data) 40048 ( 39.11kB)
+ Total ROM Size (Code + RO Data + RW Data) 29240 ( 28.55kB)
+
+==============================================================================
+
diff --git a/F107/Project/RVMDK/List/startup_stm32f10x_cl.lst b/F107/Project/RVMDK/List/startup_stm32f10x_cl.lst
new file mode 100644
index 0000000..0d51572
--- /dev/null
+++ b/F107/Project/RVMDK/List/startup_stm32f10x_cl.lst
@@ -0,0 +1,1730 @@
+
+
+
+ARM Macro Assembler Page 1
+
+
+ 1 00000000 ;******************** (C) COPYRIGHT 2009 STMicroelectron
+ ics ********************
+ 2 00000000 ;* File Name : startup_stm32f10x_cl.s
+ 3 00000000 ;* Author : MCD Application Team
+ 4 00000000 ;* Version : V3.1.2
+ 5 00000000 ;* Date : 09/28/2009
+ 6 00000000 ;* Description : STM32F10x Connectivity line devi
+ ces vector table for RVMDK
+ 7 00000000 ;* toolchain.
+ 8 00000000 ;* This module performs:
+ 9 00000000 ;* - Set the initial SP
+ 10 00000000 ;* - Set the initial PC == Reset_Ha
+ ndler
+ 11 00000000 ;* - Set the vector table entries w
+ ith the exceptions ISR address
+ 12 00000000 ;* - Branches to __main in the C li
+ brary (which eventually
+ 13 00000000 ;* calls main()).
+ 14 00000000 ;* After Reset the CortexM3 process
+ or is in Thread mode,
+ 15 00000000 ;* priority is Privileged, and the
+ Stack is set to Main.
+ 16 00000000 ;* <<< Use Configuration Wizard in Context Menu >>>
+ 17 00000000 ;*******************************************************
+ ************************
+ 18 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A
+ T PROVIDING CUSTOMERS
+ 19 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR
+ DER FOR THEM TO SAVE TIME.
+ 20 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB
+ LE FOR ANY DIRECT,
+ 21 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
+ CLAIMS ARISING FROM THE
+ 22 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM
+ ERS OF THE CODING
+ 23 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR
+ PRODUCTS.
+ 24 00000000 ;*******************************************************
+ ************************
+ 25 00000000
+ 26 00000000 ; Amount of memory (in bytes) allocated for Stack
+ 27 00000000 ; Tailor this value to your application needs
+ 28 00000000 ; Stack Configuration
+ 29 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+ 30 00000000 ;
+ 31 00000000
+ 32 00000000 00000400
+ Stack_Size
+ EQU 0x00000400
+ 33 00000000
+ 34 00000000 AREA STACK, NOINIT, READWRITE, ALIGN
+=3
+ 35 00000000 Stack_Mem
+ SPACE Stack_Size
+ 36 00000400 __initial_sp
+ 37 00000400
+ 38 00000400
+ 39 00000400 ; Heap Configuration
+ 40 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+
+
+ARM Macro Assembler Page 2
+
+
+ 41 00000400 ;
+ 42 00000400
+ 43 00000400 00000200
+ Heap_Size
+ EQU 0x00000200
+ 44 00000400
+ 45 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=
+3
+ 46 00000000 __heap_base
+ 47 00000000 Heap_Mem
+ SPACE Heap_Size
+ 48 00000200 __heap_limit
+ 49 00000200
+ 50 00000200 PRESERVE8
+ 51 00000200 THUMB
+ 52 00000200
+ 53 00000200
+ 54 00000200 ; Vector Table Mapped to Address 0 at Reset
+ 55 00000200 AREA RESET, DATA, READONLY
+ 56 00000000 EXPORT __Vectors
+ 57 00000000 EXPORT __Vectors_End
+ 58 00000000 EXPORT __Vectors_Size
+ 59 00000000
+ 60 00000000 00000000
+ __Vectors
+ DCD __initial_sp ; Top of Stack
+ 61 00000004 00000000 DCD Reset_Handler ; Reset Handler
+ 62 00000008 00000000 DCD NMI_Handler ; NMI Handler
+ 63 0000000C 00000000 DCD HardFault_Handler ; Hard Fault
+ Handler
+ 64 00000010 00000000 DCD MemManage_Handler
+ ; MPU Fault Handler
+
+ 65 00000014 00000000 DCD BusFault_Handler
+ ; Bus Fault Handler
+
+ 66 00000018 00000000 DCD UsageFault_Handler ; Usage Faul
+ t Handler
+ 67 0000001C 00000000 DCD 0 ; Reserved
+ 68 00000020 00000000 DCD 0 ; Reserved
+ 69 00000024 00000000 DCD 0 ; Reserved
+ 70 00000028 00000000 DCD 0 ; Reserved
+ 71 0000002C 00000000 DCD SVC_Handler ; SVCall Handler
+ 72 00000030 00000000 DCD DebugMon_Handler ; Debug Monito
+ r Handler
+ 73 00000034 00000000 DCD 0 ; Reserved
+ 74 00000038 00000000 DCD PendSV_Handler ; PendSV Handler
+
+ 75 0000003C 00000000 DCD SysTick_Handler
+ ; SysTick Handler
+ 76 00000040
+ 77 00000040 ; External Interrupts
+ 78 00000040 00000000 DCD WWDG_IRQHandler
+ ; Window Watchdog
+ 79 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX
+ TI Line detect
+ 80 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper
+ 81 0000004C 00000000 DCD RTC_IRQHandler ; RTC
+ 82 00000050 00000000 DCD FLASH_IRQHandler ; Flash
+
+
+
+ARM Macro Assembler Page 3
+
+
+ 83 00000054 00000000 DCD RCC_IRQHandler ; RCC
+ 84 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0
+ 85 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1
+ 86 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2
+ 87 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3
+ 88 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4
+ 89 0000006C 00000000 DCD DMA1_Channel1_IRQHandler
+ ; DMA1 Channel 1
+ 90 00000070 00000000 DCD DMA1_Channel2_IRQHandler
+ ; DMA1 Channel 2
+ 91 00000074 00000000 DCD DMA1_Channel3_IRQHandler
+ ; DMA1 Channel 3
+ 92 00000078 00000000 DCD DMA1_Channel4_IRQHandler
+ ; DMA1 Channel 4
+ 93 0000007C 00000000 DCD DMA1_Channel5_IRQHandler
+ ; DMA1 Channel 5
+ 94 00000080 00000000 DCD DMA1_Channel6_IRQHandler
+ ; DMA1 Channel 6
+ 95 00000084 00000000 DCD DMA1_Channel7_IRQHandler
+ ; DMA1 Channel 7
+ 96 00000088 00000000 DCD ADC1_2_IRQHandler
+ ; ADC1 and ADC2
+ 97 0000008C 00000000 DCD CAN1_TX_IRQHandler ; CAN1 TX
+ 98 00000090 00000000 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
+ 99 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
+ 100 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
+ 101 0000009C 00000000 DCD EXTI9_5_IRQHandler
+ ; EXTI Line 9..5
+ 102 000000A0 00000000 DCD TIM1_BRK_IRQHandler
+ ; TIM1 Break
+ 103 000000A4 00000000 DCD TIM1_UP_IRQHandler
+ ; TIM1 Update
+ 104 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1
+ Trigger and Commuta
+ tion
+ 105 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu
+ re Compare
+ 106 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2
+ 107 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3
+ 108 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4
+ 109 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event
+
+ 110 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error
+
+ 111 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event
+
+ 112 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C1 Error
+
+ 113 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1
+ 114 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2
+ 115 000000D4 00000000 DCD USART1_IRQHandler ; USART1
+ 116 000000D8 00000000 DCD USART2_IRQHandler ; USART2
+ 117 000000DC 00000000 DCD USART3_IRQHandler ; USART3
+ 118 000000E0 00000000 DCD EXTI15_10_IRQHandler
+ ; EXTI Line 15..10
+ 119 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC alarm
+ through EXTI line
+ 120 000000E8 00000000 DCD OTG_FS_WKUP_IRQHandler ; USB OT
+ G FS Wakeup through
+
+
+
+ARM Macro Assembler Page 4
+
+
+ EXTI line
+ 121 000000EC 00000000 DCD 0 ; Reserved
+ 122 000000F0 00000000 DCD 0 ; Reserved
+ 123 000000F4 00000000 DCD 0 ; Reserved
+ 124 000000F8 00000000 DCD 0 ; Reserved
+ 125 000000FC 00000000 DCD 0 ; Reserved
+ 126 00000100 00000000 DCD 0 ; Reserved
+ 127 00000104 00000000 DCD 0 ; Reserved
+ 128 00000108 00000000 DCD TIM5_IRQHandler ; TIM5
+ 129 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3
+ 130 00000110 00000000 DCD UART4_IRQHandler ; UART4
+ 131 00000114 00000000 DCD UART5_IRQHandler ; UART5
+ 132 00000118 00000000 DCD TIM6_IRQHandler ; TIM6
+ 133 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7
+ 134 00000120 00000000 DCD DMA2_Channel1_IRQHandler
+ ; DMA2 Channel1
+ 135 00000124 00000000 DCD DMA2_Channel2_IRQHandler
+ ; DMA2 Channel2
+ 136 00000128 00000000 DCD DMA2_Channel3_IRQHandler
+ ; DMA2 Channel3
+ 137 0000012C 00000000 DCD DMA2_Channel4_IRQHandler
+ ; DMA2 Channel4
+ 138 00000130 00000000 DCD DMA2_Channel5_IRQHandler
+ ; DMA2 Channel5
+ 139 00000134 00000000 DCD ETH_IRQHandler ; Ethernet
+ 140 00000138 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet
+ Wakeup through EXTI
+ line
+ 141 0000013C 00000000 DCD CAN2_TX_IRQHandler ; CAN2 TX
+ 142 00000140 00000000 DCD CAN2_RX0_IRQHandler ; CAN2 RX0
+ 143 00000144 00000000 DCD CAN2_RX1_IRQHandler ; CAN2 RX1
+ 144 00000148 00000000 DCD CAN2_SCE_IRQHandler ; CAN2 SCE
+ 145 0000014C 00000000 DCD OTG_FS_IRQHandler ; USB OTG FS
+ 146 00000150 __Vectors_End
+ 147 00000150
+ 148 00000150 00000150
+ __Vectors_Size
+ EQU __Vectors_End - __Vectors
+ 149 00000150
+ 150 00000150 AREA |.text|, CODE, READONLY
+ 151 00000000
+ 152 00000000 ; Reset handler routine
+ 153 00000000 Reset_Handler
+ PROC
+ 154 00000000 EXPORT Reset_Handler [WEAK
+]
+ 155 00000000 IMPORT __main
+ 156 00000000 4808 LDR R0, =__main
+ 157 00000002 4700 BX R0
+ 158 00000004 ENDP
+ 159 00000004
+ 160 00000004 ; Dummy Exception Handlers (infinite loops which can be
+ modified)
+ 161 00000004
+ 162 00000004 NMI_Handler
+ PROC
+ 163 00000004 EXPORT NMI_Handler [WEA
+K]
+ 164 00000004 E7FE B .
+
+
+
+ARM Macro Assembler Page 5
+
+
+ 165 00000006 ENDP
+ 167 00000006 HardFault_Handler
+ PROC
+ 168 00000006 EXPORT HardFault_Handler [WEA
+K]
+ 169 00000006 E7FE B .
+ 170 00000008 ENDP
+ 172 00000008 MemManage_Handler
+ PROC
+ 173 00000008 EXPORT MemManage_Handler [WEA
+K]
+ 174 00000008 E7FE B .
+ 175 0000000A ENDP
+ 177 0000000A BusFault_Handler
+ PROC
+ 178 0000000A EXPORT BusFault_Handler [WEA
+K]
+ 179 0000000A E7FE B .
+ 180 0000000C ENDP
+ 182 0000000C UsageFault_Handler
+ PROC
+ 183 0000000C EXPORT UsageFault_Handler [WEA
+K]
+ 184 0000000C E7FE B .
+ 185 0000000E ENDP
+ 186 0000000E SVC_Handler
+ PROC
+ 187 0000000E EXPORT SVC_Handler [WEA
+K]
+ 188 0000000E E7FE B .
+ 189 00000010 ENDP
+ 191 00000010 DebugMon_Handler
+ PROC
+ 192 00000010 EXPORT DebugMon_Handler [WEA
+K]
+ 193 00000010 E7FE B .
+ 194 00000012 ENDP
+ 195 00000012 PendSV_Handler
+ PROC
+ 196 00000012 EXPORT PendSV_Handler [WEA
+K]
+ 197 00000012 E7FE B .
+ 198 00000014 ENDP
+ 199 00000014 SysTick_Handler
+ PROC
+ 200 00000014 EXPORT SysTick_Handler [WEA
+K]
+ 201 00000014 E7FE B .
+ 202 00000016 ENDP
+ 203 00000016
+ 204 00000016 Default_Handler
+ PROC
+ 205 00000016
+ 206 00000016 EXPORT WWDG_IRQHandler [WEA
+K]
+ 207 00000016 EXPORT PVD_IRQHandler [WEA
+K]
+ 208 00000016 EXPORT TAMPER_IRQHandler [WEA
+K]
+
+
+
+ARM Macro Assembler Page 6
+
+
+ 209 00000016 EXPORT RTC_IRQHandler [WEA
+K]
+ 210 00000016 EXPORT FLASH_IRQHandler [WEA
+K]
+ 211 00000016 EXPORT RCC_IRQHandler [WEA
+K]
+ 212 00000016 EXPORT EXTI0_IRQHandler [WEA
+K]
+ 213 00000016 EXPORT EXTI1_IRQHandler [WEA
+K]
+ 214 00000016 EXPORT EXTI2_IRQHandler [WEA
+K]
+ 215 00000016 EXPORT EXTI3_IRQHandler [WEA
+K]
+ 216 00000016 EXPORT EXTI4_IRQHandler [WEA
+K]
+ 217 00000016 EXPORT DMA1_Channel1_IRQHandler [WEA
+K]
+ 218 00000016 EXPORT DMA1_Channel2_IRQHandler [WEA
+K]
+ 219 00000016 EXPORT DMA1_Channel3_IRQHandler [WEA
+K]
+ 220 00000016 EXPORT DMA1_Channel4_IRQHandler [WEA
+K]
+ 221 00000016 EXPORT DMA1_Channel5_IRQHandler [WEA
+K]
+ 222 00000016 EXPORT DMA1_Channel6_IRQHandler [WEA
+K]
+ 223 00000016 EXPORT DMA1_Channel7_IRQHandler [WEA
+K]
+ 224 00000016 EXPORT ADC1_2_IRQHandler [WEA
+K]
+ 225 00000016 EXPORT CAN1_TX_IRQHandler [WEA
+K]
+ 226 00000016 EXPORT CAN1_RX0_IRQHandler [WEA
+K]
+ 227 00000016 EXPORT CAN1_RX1_IRQHandler [WEA
+K]
+ 228 00000016 EXPORT CAN1_SCE_IRQHandler [WEA
+K]
+ 229 00000016 EXPORT EXTI9_5_IRQHandler [WEA
+K]
+ 230 00000016 EXPORT TIM1_BRK_IRQHandler [WEA
+K]
+ 231 00000016 EXPORT TIM1_UP_IRQHandler [WEA
+K]
+ 232 00000016 EXPORT TIM1_TRG_COM_IRQHandler [WEA
+K]
+ 233 00000016 EXPORT TIM1_CC_IRQHandler [WEA
+K]
+ 234 00000016 EXPORT TIM2_IRQHandler [WEA
+K]
+ 235 00000016 EXPORT TIM3_IRQHandler [WEA
+K]
+ 236 00000016 EXPORT TIM4_IRQHandler [WEA
+K]
+ 237 00000016 EXPORT I2C1_EV_IRQHandler [WEA
+K]
+ 238 00000016 EXPORT I2C1_ER_IRQHandler [WEA
+
+
+
+ARM Macro Assembler Page 7
+
+
+K]
+ 239 00000016 EXPORT I2C2_EV_IRQHandler [WEA
+K]
+ 240 00000016 EXPORT I2C2_ER_IRQHandler [WEA
+K]
+ 241 00000016 EXPORT SPI1_IRQHandler [WEA
+K]
+ 242 00000016 EXPORT SPI2_IRQHandler [WEA
+K]
+ 243 00000016 EXPORT USART1_IRQHandler [WEA
+K]
+ 244 00000016 EXPORT USART2_IRQHandler [WEA
+K]
+ 245 00000016 EXPORT USART3_IRQHandler [WEA
+K]
+ 246 00000016 EXPORT EXTI15_10_IRQHandler [WEA
+K]
+ 247 00000016 EXPORT RTCAlarm_IRQHandler [WEA
+K]
+ 248 00000016 EXPORT OTG_FS_WKUP_IRQHandler [WEA
+K]
+ 249 00000016 EXPORT TIM5_IRQHandler [WEA
+K]
+ 250 00000016 EXPORT SPI3_IRQHandler [WEA
+K]
+ 251 00000016 EXPORT UART4_IRQHandler [WEA
+K]
+ 252 00000016 EXPORT UART5_IRQHandler [WEA
+K]
+ 253 00000016 EXPORT TIM6_IRQHandler [WEA
+K]
+ 254 00000016 EXPORT TIM7_IRQHandler [WEA
+K]
+ 255 00000016 EXPORT DMA2_Channel1_IRQHandler [WEA
+K]
+ 256 00000016 EXPORT DMA2_Channel2_IRQHandler [WEA
+K]
+ 257 00000016 EXPORT DMA2_Channel3_IRQHandler [WEA
+K]
+ 258 00000016 EXPORT DMA2_Channel4_IRQHandler [WEA
+K]
+ 259 00000016 EXPORT DMA2_Channel5_IRQHandler [WEA
+K]
+ 260 00000016 EXPORT ETH_IRQHandler [WEA
+K]
+ 261 00000016 EXPORT ETH_WKUP_IRQHandler [WEA
+K]
+ 262 00000016 EXPORT CAN2_TX_IRQHandler [WEA
+K]
+ 263 00000016 EXPORT CAN2_RX0_IRQHandler [WEA
+K]
+ 264 00000016 EXPORT CAN2_RX1_IRQHandler [WEA
+K]
+ 265 00000016 EXPORT CAN2_SCE_IRQHandler [WEA
+K]
+ 266 00000016 EXPORT OTG_FS_IRQHandler [WEA
+K]
+ 267 00000016
+ 268 00000016 WWDG_IRQHandler
+
+
+
+ARM Macro Assembler Page 8
+
+
+ 269 00000016 PVD_IRQHandler
+ 270 00000016 TAMPER_IRQHandler
+ 271 00000016 RTC_IRQHandler
+ 272 00000016 FLASH_IRQHandler
+ 273 00000016 RCC_IRQHandler
+ 274 00000016 EXTI0_IRQHandler
+ 275 00000016 EXTI1_IRQHandler
+ 276 00000016 EXTI2_IRQHandler
+ 277 00000016 EXTI3_IRQHandler
+ 278 00000016 EXTI4_IRQHandler
+ 279 00000016 DMA1_Channel1_IRQHandler
+ 280 00000016 DMA1_Channel2_IRQHandler
+ 281 00000016 DMA1_Channel3_IRQHandler
+ 282 00000016 DMA1_Channel4_IRQHandler
+ 283 00000016 DMA1_Channel5_IRQHandler
+ 284 00000016 DMA1_Channel6_IRQHandler
+ 285 00000016 DMA1_Channel7_IRQHandler
+ 286 00000016 ADC1_2_IRQHandler
+ 287 00000016 CAN1_TX_IRQHandler
+ 288 00000016 CAN1_RX0_IRQHandler
+ 289 00000016 CAN1_RX1_IRQHandler
+ 290 00000016 CAN1_SCE_IRQHandler
+ 291 00000016 EXTI9_5_IRQHandler
+ 292 00000016 TIM1_BRK_IRQHandler
+ 293 00000016 TIM1_UP_IRQHandler
+ 294 00000016 TIM1_TRG_COM_IRQHandler
+ 295 00000016 TIM1_CC_IRQHandler
+ 296 00000016 TIM2_IRQHandler
+ 297 00000016 TIM3_IRQHandler
+ 298 00000016 TIM4_IRQHandler
+ 299 00000016 I2C1_EV_IRQHandler
+ 300 00000016 I2C1_ER_IRQHandler
+ 301 00000016 I2C2_EV_IRQHandler
+ 302 00000016 I2C2_ER_IRQHandler
+ 303 00000016 SPI1_IRQHandler
+ 304 00000016 SPI2_IRQHandler
+ 305 00000016 USART1_IRQHandler
+ 306 00000016 USART2_IRQHandler
+ 307 00000016 USART3_IRQHandler
+ 308 00000016 EXTI15_10_IRQHandler
+ 309 00000016 RTCAlarm_IRQHandler
+ 310 00000016 OTG_FS_WKUP_IRQHandler
+ 311 00000016 TIM5_IRQHandler
+ 312 00000016 SPI3_IRQHandler
+ 313 00000016 UART4_IRQHandler
+ 314 00000016 UART5_IRQHandler
+ 315 00000016 TIM6_IRQHandler
+ 316 00000016 TIM7_IRQHandler
+ 317 00000016 DMA2_Channel1_IRQHandler
+ 318 00000016 DMA2_Channel2_IRQHandler
+ 319 00000016 DMA2_Channel3_IRQHandler
+ 320 00000016 DMA2_Channel4_IRQHandler
+ 321 00000016 DMA2_Channel5_IRQHandler
+ 322 00000016 ETH_IRQHandler
+ 323 00000016 ETH_WKUP_IRQHandler
+ 324 00000016 CAN2_TX_IRQHandler
+ 325 00000016 CAN2_RX0_IRQHandler
+ 326 00000016 CAN2_RX1_IRQHandler
+ 327 00000016 CAN2_SCE_IRQHandler
+
+
+
+ARM Macro Assembler Page 9
+
+
+ 328 00000016 OTG_FS_IRQHandler
+ 329 00000016
+ 330 00000016 E7FE B .
+ 331 00000018
+ 332 00000018 ENDP
+ 333 00000018
+ 334 00000018 ALIGN
+ 335 00000018
+ 336 00000018 ;*******************************************************
+ ************************
+ 337 00000018 ; User Stack and Heap initialization
+ 338 00000018 ;*******************************************************
+ ************************
+ 339 00000018 IF :DEF:__MICROLIB
+ 346 00000018
+ 347 00000018 IMPORT __use_two_region_memory
+ 348 00000018 EXPORT __user_initial_stackheap
+ 349 00000018
+ 350 00000018 __user_initial_stackheap
+ 351 00000018
+ 352 00000018 4803 LDR R0, = Heap_Mem
+ 353 0000001A 4904 LDR R1, =(Stack_Mem + Stack_Size)
+ 354 0000001C 4A04 LDR R2, = (Heap_Mem + Heap_Size)
+ 355 0000001E 4B05 LDR R3, = Stack_Mem
+ 356 00000020 4770 BX LR
+ 357 00000022
+ 358 00000022 00 00 ALIGN
+ 359 00000024
+ 360 00000024 ENDIF
+ 361 00000024
+ 362 00000024 END
+ 00000000
+ 00000000
+ 00000400
+ 00000200
+ 00000000
+Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw
+ork --depend=.\obj\startup_stm32f10x_cl.d -o.\obj\startup_stm32f10x_cl.o -IG:\K
+eil_v5\ARM\RV31\INC -IG:\Keil_v5\ARM\CMSIS\Include -IG:\Keil_v5\ARM\INC\ST\STM3
+2F10x --predefine="__UVISION_VERSION SETA 525" --list=.\list\startup_stm32f10x_
+cl.lst ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+STACK 00000000
+
+Symbol: STACK
+ Definitions
+ At line 34 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ None
+Comment: STACK unused
+Stack_Mem 00000000
+
+Symbol: Stack_Mem
+ Definitions
+ At line 35 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ At line 353 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 355 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+__initial_sp 00000400
+
+Symbol: __initial_sp
+ Definitions
+ At line 36 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ At line 60 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+Comment: __initial_sp used once
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+HEAP 00000000
+
+Symbol: HEAP
+ Definitions
+ At line 45 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ None
+Comment: HEAP unused
+Heap_Mem 00000000
+
+Symbol: Heap_Mem
+ Definitions
+ At line 47 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ At line 352 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 354 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+__heap_base 00000000
+
+Symbol: __heap_base
+ Definitions
+ At line 46 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ None
+Comment: __heap_base unused
+__heap_limit 00000200
+
+Symbol: __heap_limit
+ Definitions
+ At line 48 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ None
+Comment: __heap_limit unused
+4 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+RESET 00000000
+
+Symbol: RESET
+ Definitions
+ At line 55 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ None
+Comment: RESET unused
+__Vectors 00000000
+
+Symbol: __Vectors
+ Definitions
+ At line 60 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ At line 56 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 148 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+__Vectors_End 00000150
+
+Symbol: __Vectors_End
+ Definitions
+ At line 146 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 57 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 148 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Relocatable symbols
+
+.text 00000000
+
+Symbol: .text
+ Definitions
+ At line 150 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ None
+Comment: .text unused
+ADC1_2_IRQHandler 00000016
+
+Symbol: ADC1_2_IRQHandler
+ Definitions
+ At line 286 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 96 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 224 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+BusFault_Handler 0000000A
+
+Symbol: BusFault_Handler
+ Definitions
+ At line 177 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 65 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 178 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN1_RX0_IRQHandler 00000016
+
+Symbol: CAN1_RX0_IRQHandler
+ Definitions
+ At line 288 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 98 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 226 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN1_RX1_IRQHandler 00000016
+
+Symbol: CAN1_RX1_IRQHandler
+ Definitions
+ At line 289 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 99 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 227 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN1_SCE_IRQHandler 00000016
+
+
+
+
+ARM Macro Assembler Page 2 Alphabetic symbol ordering
+Relocatable symbols
+
+Symbol: CAN1_SCE_IRQHandler
+ Definitions
+ At line 290 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 100 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 228 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN1_TX_IRQHandler 00000016
+
+Symbol: CAN1_TX_IRQHandler
+ Definitions
+ At line 287 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 97 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 225 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN2_RX0_IRQHandler 00000016
+
+Symbol: CAN2_RX0_IRQHandler
+ Definitions
+ At line 325 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 142 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 263 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN2_RX1_IRQHandler 00000016
+
+Symbol: CAN2_RX1_IRQHandler
+ Definitions
+ At line 326 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 143 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 264 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN2_SCE_IRQHandler 00000016
+
+Symbol: CAN2_SCE_IRQHandler
+ Definitions
+ At line 327 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 144 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 265 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+CAN2_TX_IRQHandler 00000016
+
+
+
+ARM Macro Assembler Page 3 Alphabetic symbol ordering
+Relocatable symbols
+
+
+Symbol: CAN2_TX_IRQHandler
+ Definitions
+ At line 324 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 141 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 262 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA1_Channel1_IRQHandler 00000016
+
+Symbol: DMA1_Channel1_IRQHandler
+ Definitions
+ At line 279 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 89 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 217 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA1_Channel2_IRQHandler 00000016
+
+Symbol: DMA1_Channel2_IRQHandler
+ Definitions
+ At line 280 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 90 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 218 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA1_Channel3_IRQHandler 00000016
+
+Symbol: DMA1_Channel3_IRQHandler
+ Definitions
+ At line 281 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 91 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 219 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA1_Channel4_IRQHandler 00000016
+
+Symbol: DMA1_Channel4_IRQHandler
+ Definitions
+ At line 282 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 92 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 220 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+
+
+
+ARM Macro Assembler Page 4 Alphabetic symbol ordering
+Relocatable symbols
+
+DMA1_Channel5_IRQHandler 00000016
+
+Symbol: DMA1_Channel5_IRQHandler
+ Definitions
+ At line 283 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 93 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 221 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA1_Channel6_IRQHandler 00000016
+
+Symbol: DMA1_Channel6_IRQHandler
+ Definitions
+ At line 284 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 94 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 222 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA1_Channel7_IRQHandler 00000016
+
+Symbol: DMA1_Channel7_IRQHandler
+ Definitions
+ At line 285 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 95 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 223 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA2_Channel1_IRQHandler 00000016
+
+Symbol: DMA2_Channel1_IRQHandler
+ Definitions
+ At line 317 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 134 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 255 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA2_Channel2_IRQHandler 00000016
+
+Symbol: DMA2_Channel2_IRQHandler
+ Definitions
+ At line 318 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 135 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 256 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+
+
+ARM Macro Assembler Page 5 Alphabetic symbol ordering
+Relocatable symbols
+
+
+DMA2_Channel3_IRQHandler 00000016
+
+Symbol: DMA2_Channel3_IRQHandler
+ Definitions
+ At line 319 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 136 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 257 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA2_Channel4_IRQHandler 00000016
+
+Symbol: DMA2_Channel4_IRQHandler
+ Definitions
+ At line 320 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 137 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 258 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DMA2_Channel5_IRQHandler 00000016
+
+Symbol: DMA2_Channel5_IRQHandler
+ Definitions
+ At line 321 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 138 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 259 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+DebugMon_Handler 00000010
+
+Symbol: DebugMon_Handler
+ Definitions
+ At line 191 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 72 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 192 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+Default_Handler 00000016
+
+Symbol: Default_Handler
+ Definitions
+ At line 204 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ None
+Comment: Default_Handler unused
+ETH_IRQHandler 00000016
+
+
+
+ARM Macro Assembler Page 6 Alphabetic symbol ordering
+Relocatable symbols
+
+
+Symbol: ETH_IRQHandler
+ Definitions
+ At line 322 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 139 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 260 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+ETH_WKUP_IRQHandler 00000016
+
+Symbol: ETH_WKUP_IRQHandler
+ Definitions
+ At line 323 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 140 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 261 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+EXTI0_IRQHandler 00000016
+
+Symbol: EXTI0_IRQHandler
+ Definitions
+ At line 274 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 84 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 212 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+EXTI15_10_IRQHandler 00000016
+
+Symbol: EXTI15_10_IRQHandler
+ Definitions
+ At line 308 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 118 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 246 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+EXTI1_IRQHandler 00000016
+
+Symbol: EXTI1_IRQHandler
+ Definitions
+ At line 275 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 85 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 213 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+
+
+
+ARM Macro Assembler Page 7 Alphabetic symbol ordering
+Relocatable symbols
+
+EXTI2_IRQHandler 00000016
+
+Symbol: EXTI2_IRQHandler
+ Definitions
+ At line 276 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 86 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 214 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+EXTI3_IRQHandler 00000016
+
+Symbol: EXTI3_IRQHandler
+ Definitions
+ At line 277 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 87 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 215 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+EXTI4_IRQHandler 00000016
+
+Symbol: EXTI4_IRQHandler
+ Definitions
+ At line 278 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 88 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 216 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+EXTI9_5_IRQHandler 00000016
+
+Symbol: EXTI9_5_IRQHandler
+ Definitions
+ At line 291 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 101 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 229 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+FLASH_IRQHandler 00000016
+
+Symbol: FLASH_IRQHandler
+ Definitions
+ At line 272 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 82 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 210 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+
+
+ARM Macro Assembler Page 8 Alphabetic symbol ordering
+Relocatable symbols
+
+
+HardFault_Handler 00000006
+
+Symbol: HardFault_Handler
+ Definitions
+ At line 167 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 63 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 168 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+I2C1_ER_IRQHandler 00000016
+
+Symbol: I2C1_ER_IRQHandler
+ Definitions
+ At line 300 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 110 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 238 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+I2C1_EV_IRQHandler 00000016
+
+Symbol: I2C1_EV_IRQHandler
+ Definitions
+ At line 299 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 109 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 237 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+I2C2_ER_IRQHandler 00000016
+
+Symbol: I2C2_ER_IRQHandler
+ Definitions
+ At line 302 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 112 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 240 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+I2C2_EV_IRQHandler 00000016
+
+Symbol: I2C2_EV_IRQHandler
+ Definitions
+ At line 301 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 111 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 239 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+
+
+
+ARM Macro Assembler Page 9 Alphabetic symbol ordering
+Relocatable symbols
+
+m32f10x_cl.s
+
+MemManage_Handler 00000008
+
+Symbol: MemManage_Handler
+ Definitions
+ At line 172 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 64 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 173 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+NMI_Handler 00000004
+
+Symbol: NMI_Handler
+ Definitions
+ At line 162 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 62 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 163 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+OTG_FS_IRQHandler 00000016
+
+Symbol: OTG_FS_IRQHandler
+ Definitions
+ At line 328 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 145 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 266 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+OTG_FS_WKUP_IRQHandler 00000016
+
+Symbol: OTG_FS_WKUP_IRQHandler
+ Definitions
+ At line 310 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 120 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 248 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+PVD_IRQHandler 00000016
+
+Symbol: PVD_IRQHandler
+ Definitions
+ At line 269 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 79 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+
+
+
+ARM Macro Assembler Page 10 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 207 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+PendSV_Handler 00000012
+
+Symbol: PendSV_Handler
+ Definitions
+ At line 195 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 74 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 196 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+RCC_IRQHandler 00000016
+
+Symbol: RCC_IRQHandler
+ Definitions
+ At line 273 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 83 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 211 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+RTCAlarm_IRQHandler 00000016
+
+Symbol: RTCAlarm_IRQHandler
+ Definitions
+ At line 309 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 119 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 247 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+RTC_IRQHandler 00000016
+
+Symbol: RTC_IRQHandler
+ Definitions
+ At line 271 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 81 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 209 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+Reset_Handler 00000000
+
+Symbol: Reset_Handler
+ Definitions
+ At line 153 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 61 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+
+
+
+ARM Macro Assembler Page 11 Alphabetic symbol ordering
+Relocatable symbols
+
+32f10x_cl.s
+ At line 154 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+SPI1_IRQHandler 00000016
+
+Symbol: SPI1_IRQHandler
+ Definitions
+ At line 303 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 113 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 241 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+SPI2_IRQHandler 00000016
+
+Symbol: SPI2_IRQHandler
+ Definitions
+ At line 304 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 114 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 242 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+SPI3_IRQHandler 00000016
+
+Symbol: SPI3_IRQHandler
+ Definitions
+ At line 312 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 129 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 250 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+SVC_Handler 0000000E
+
+Symbol: SVC_Handler
+ Definitions
+ At line 186 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 71 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 187 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+SysTick_Handler 00000014
+
+Symbol: SysTick_Handler
+ Definitions
+ At line 199 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+
+
+
+ARM Macro Assembler Page 12 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 75 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 200 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TAMPER_IRQHandler 00000016
+
+Symbol: TAMPER_IRQHandler
+ Definitions
+ At line 270 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 80 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 208 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM1_BRK_IRQHandler 00000016
+
+Symbol: TIM1_BRK_IRQHandler
+ Definitions
+ At line 292 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 102 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 230 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM1_CC_IRQHandler 00000016
+
+Symbol: TIM1_CC_IRQHandler
+ Definitions
+ At line 295 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 105 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 233 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM1_TRG_COM_IRQHandler 00000016
+
+Symbol: TIM1_TRG_COM_IRQHandler
+ Definitions
+ At line 294 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 104 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 232 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM1_UP_IRQHandler 00000016
+
+Symbol: TIM1_UP_IRQHandler
+ Definitions
+ At line 293 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+
+
+ARM Macro Assembler Page 13 Alphabetic symbol ordering
+Relocatable symbols
+
+ Uses
+ At line 103 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 231 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM2_IRQHandler 00000016
+
+Symbol: TIM2_IRQHandler
+ Definitions
+ At line 296 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 106 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 234 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM3_IRQHandler 00000016
+
+Symbol: TIM3_IRQHandler
+ Definitions
+ At line 297 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 107 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 235 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM4_IRQHandler 00000016
+
+Symbol: TIM4_IRQHandler
+ Definitions
+ At line 298 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 108 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 236 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM5_IRQHandler 00000016
+
+Symbol: TIM5_IRQHandler
+ Definitions
+ At line 311 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 128 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 249 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM6_IRQHandler 00000016
+
+Symbol: TIM6_IRQHandler
+ Definitions
+ At line 315 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+
+
+
+ARM Macro Assembler Page 14 Alphabetic symbol ordering
+Relocatable symbols
+
+m32f10x_cl.s
+ Uses
+ At line 132 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 253 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+TIM7_IRQHandler 00000016
+
+Symbol: TIM7_IRQHandler
+ Definitions
+ At line 316 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 133 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 254 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+UART4_IRQHandler 00000016
+
+Symbol: UART4_IRQHandler
+ Definitions
+ At line 313 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 130 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 251 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+UART5_IRQHandler 00000016
+
+Symbol: UART5_IRQHandler
+ Definitions
+ At line 314 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 131 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 252 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+USART1_IRQHandler 00000016
+
+Symbol: USART1_IRQHandler
+ Definitions
+ At line 305 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 115 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 243 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+USART2_IRQHandler 00000016
+
+Symbol: USART2_IRQHandler
+ Definitions
+
+
+
+ARM Macro Assembler Page 15 Alphabetic symbol ordering
+Relocatable symbols
+
+ At line 306 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 116 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 244 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+USART3_IRQHandler 00000016
+
+Symbol: USART3_IRQHandler
+ Definitions
+ At line 307 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 117 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ At line 245 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+UsageFault_Handler 0000000C
+
+Symbol: UsageFault_Handler
+ Definitions
+ At line 182 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 66 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 183 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+WWDG_IRQHandler 00000016
+
+Symbol: WWDG_IRQHandler
+ Definitions
+ At line 268 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 78 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 206 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+__user_initial_stackheap 00000018
+
+Symbol: __user_initial_stackheap
+ Definitions
+ At line 350 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 348 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+Comment: __user_initial_stackheap used once
+74 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+Absolute symbols
+
+Heap_Size 00000200
+
+Symbol: Heap_Size
+ Definitions
+ At line 43 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ At line 47 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 354 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+Stack_Size 00000400
+
+Symbol: Stack_Size
+ Definitions
+ At line 32 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ Uses
+ At line 35 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+ At line 353 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+
+__Vectors_Size 00000150
+
+Symbol: __Vectors_Size
+ Definitions
+ At line 148 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 58 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm
+32f10x_cl.s
+Comment: __Vectors_Size used once
+3 symbols
+
+
+
+ARM Macro Assembler Page 1 Alphabetic symbol ordering
+External symbols
+
+__main 00000000
+
+Symbol: __main
+ Definitions
+ At line 155 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ At line 156 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+Comment: __main used once
+__use_two_region_memory 00000000
+
+Symbol: __use_two_region_memory
+ Definitions
+ At line 347 in file ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_st
+m32f10x_cl.s
+ Uses
+ None
+Comment: __use_two_region_memory unused
+2 symbols
+424 symbols in table
diff --git a/F107/Project/RVMDK/Obj/ExtDll.iex b/F107/Project/RVMDK/Obj/ExtDll.iex
new file mode 100644
index 0000000..6c0896e
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ExtDll.iex
@@ -0,0 +1,2 @@
+[EXTDLL]
+Count=0
diff --git a/F107/Project/RVMDK/Obj/Project_STM32107VCT6.dep b/F107/Project/RVMDK/Obj/Project_STM32107VCT6.dep
new file mode 100644
index 0000000..3880663
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/Project_STM32107VCT6.dep
@@ -0,0 +1,1082 @@
+Dependencies for Project 'Project', Target 'STM32107VCT6': (DO NOT MODIFY !)
+F (..\src\stm32f10x_it.c)(0x51FBBCC4)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_it.o --omf_browse .\obj\stm32f10x_it.crf --depend .\obj\stm32f10x_it.d)
+I (..\inc\stm32f10x_it.h)(0x4B065C40)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\inc\main.h)(0x5CAF3FE6)
+I (..\inc\stm32f107.h)(0x4B065C40)
+I (..\..\Utilities\STM32_EVAL\stm32_eval.h)(0x4B065C44)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h)(0x5131B922)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h)(0x4B065C44)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h)(0x4B065C44)
+I (..\inc\netconf.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\helloworld.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\httpd.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\port\fsdata.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\tftpserver.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h)(0x4B065C42)
+I (..\src\TCP_CLIENT.h)(0x5CAC40E6)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\main.o --omf_browse .\obj\main.crf --depend .\obj\main.d)
+I (..\inc\main.h)(0x5CAF3FE6)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
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+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
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+I (..\inc\stm32f107.h)(0x4B065C40)
+I (..\..\Utilities\STM32_EVAL\stm32_eval.h)(0x4B065C44)
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+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\inc\netconf.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\helloworld.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\httpd.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\fsdata.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\tftpserver.h)(0x4B065C40)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
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+I (..\src\TCP_CLIENT.h)(0x5CAC40E6)
+I (..\..\Basic\usart\usart.h)(0x5CAC40C0)
+I (G:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x599ECD2A)
+I (G:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x599ECD2C)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
+I (G:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x599ECD2C)
+I (..\..\Basic\delay\delay.h)(0x5C73E09C)
+I (..\..\Hardware\LED\led.h)(0x5C74C77E)
+I (..\src\HX711.h)(0x5330264C)
+I (..\src\sys.h)(0x5CA17C8C)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f107.o --omf_browse .\obj\stm32f107.crf --depend .\obj\stm32f107.d)
+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
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+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+I (..\inc\stm32f107.h)(0x4B065C40)
+I (..\..\Utilities\STM32_EVAL\stm32_eval.h)(0x4B065C44)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\netconf.o --omf_browse .\obj\netconf.crf --depend .\obj\netconf.d)
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+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h)(0x4B065C42)
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+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
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+I (..\inc\stm32f107.h)(0x4B065C40)
+I (..\..\Utilities\STM32_EVAL\stm32_eval.h)(0x4B065C44)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h)(0x5131B922)
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+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h)(0x4B065C44)
+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\inc\netconf.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\helloworld.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\httpd.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\fsdata.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\tftpserver.h)(0x4B065C40)
+I (..\src\TCP_CLIENT.h)(0x5CAC40E6)
+I (G:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x599ECD2C)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\tcp_client.o --omf_browse .\obj\tcp_client.crf --depend .\obj\tcp_client.d)
+I (..\inc\main.h)(0x5CAF3FE6)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+I (..\inc\stm32f107.h)(0x4B065C40)
+I (..\..\Utilities\STM32_EVAL\stm32_eval.h)(0x4B065C44)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h)(0x5131B922)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h)(0x4B065C44)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h)(0x4B065C44)
+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\inc\netconf.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\helloworld.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\httpd.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\fsdata.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\tftpserver.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h)(0x4B065C42)
+I (..\src\TCP_CLIENT.h)(0x5CAC40E6)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
+I (..\..\Basic\usart\usart.h)(0x5CAC40C0)
+I (G:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x599ECD2A)
+I (G:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x599ECD2C)
+I (G:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x599ECD2C)
+I (..\src\HX711.h)(0x5330264C)
+I (..\src\sys.h)(0x5CA17C8C)
+I (..\..\Basic\delay\delay.h)(0x5C73E09C)
+F (..\src\HX711.c)(0x5330266A)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\hx711.o --omf_browse .\obj\hx711.crf --depend .\obj\hx711.d)
+I (..\src\HX711.h)(0x5330264C)
+I (..\src\sys.h)(0x5CA17C8C)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+I (..\..\Basic\delay\delay.h)(0x5C73E09C)
+F (..\src\sys.c)(0x5CA6B74C)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\sys.o --omf_browse .\obj\sys.crf --depend .\obj\sys.d)
+I (..\src\sys.h)(0x5CA17C8C)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\src\SCI.c)(0x53064232)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\sci.o --omf_browse .\obj\sci.crf --depend .\obj\sci.d)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c)(0x4B065C40)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_usart.o --omf_browse .\obj\stm32f10x_usart.crf --depend .\obj\stm32f10x_usart.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_gpio.o --omf_browse .\obj\stm32f10x_gpio.crf --depend .\obj\stm32f10x_gpio.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_rcc.o --omf_browse .\obj\stm32f10x_rcc.crf --depend .\obj\stm32f10x_rcc.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_spi.o --omf_browse .\obj\stm32f10x_spi.crf --depend .\obj\stm32f10x_spi.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_exti.o --omf_browse .\obj\stm32f10x_exti.crf --depend .\obj\stm32f10x_exti.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_flash.o --omf_browse .\obj\stm32f10x_flash.crf --depend .\obj\stm32f10x_flash.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\misc.o --omf_browse .\obj\misc.crf --depend .\obj\misc.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_adc.o --omf_browse .\obj\stm32f10x_adc.crf --depend .\obj\stm32f10x_adc.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c)(0x4B065C40)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_tim.o --omf_browse .\obj\stm32f10x_tim.crf --depend .\obj\stm32f10x_tim.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32f10x_i2c.o --omf_browse .\obj\stm32f10x_i2c.crf --depend .\obj\stm32f10x_i2c.d)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\STM32_ETH_Driver\src\stm32_eth.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\stm32_eth.o --omf_browse .\obj\stm32_eth.crf --depend .\obj\stm32_eth.d)
+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\ethernetif.o --omf_browse .\obj\ethernetif.crf --depend .\obj\ethernetif.d)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\tcpip.o --omf_browse .\obj\tcpip.crf --depend .\obj\tcpip.d)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\api_lib.o --omf_browse .\obj\api_lib.crf --depend .\obj\api_lib.d)
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\netbuf.o --omf_browse .\obj\netbuf.crf --depend .\obj\netbuf.d)
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\netdb.o --omf_browse .\obj\netdb.crf --depend .\obj\netdb.d)
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\api_msg.o --omf_browse .\obj\api_msg.crf --depend .\obj\api_msg.d)
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\err.o --omf_browse .\obj\err.crf --depend .\obj\err.d)
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-o .\obj\stats.o --omf_browse .\obj\stats.crf --depend .\obj\stats.d)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+F (..\..\Utilities\lwip-1.3.1\src\core\sys.c)(0x4B065C42)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\sys_1.o --omf_browse .\obj\sys_1.crf --depend .\obj\sys_1.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\tcp.o --omf_browse .\obj\tcp.crf --depend .\obj\tcp.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h)(0x4B065C42)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\tcp_in.o --omf_browse .\obj\tcp_in.crf --depend .\obj\tcp_in.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/perf.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\tcp_out.o --omf_browse .\obj\tcp_out.crf --depend .\obj\tcp_out.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h)(0x4B065C42)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\udp.o --omf_browse .\obj\udp.crf --depend .\obj\udp.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/perf.h)(0x4B065C40)
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+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\dhcp.o --omf_browse .\obj\dhcp.crf --depend .\obj\dhcp.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\init.o --omf_browse .\obj\init.crf --depend .\obj\init.d)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sockets.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/raw.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp_msg.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp_structs.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/autoip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/igmp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/dns.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h)(0x4B065C42)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\mem.o --omf_browse .\obj\mem.crf --depend .\obj\mem.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h)(0x4B065C42)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\memp.o --omf_browse .\obj\memp.crf --depend .\obj\memp.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\netif.o --omf_browse .\obj\netif.crf --depend .\obj\netif.d)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\pbuf.o --omf_browse .\obj\pbuf.crf --depend .\obj\pbuf.d)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\raw.o --omf_browse .\obj\raw.crf --depend .\obj\raw.d)
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\autoip.o --omf_browse .\obj\autoip.crf --depend .\obj\autoip.d)
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+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h)(0x4B065C42)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\igmp.o --omf_browse .\obj\igmp.crf --depend .\obj\igmp.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\inet.o --omf_browse .\obj\inet.crf --depend .\obj\inet.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\inet_chksum.o --omf_browse .\obj\inet_chksum.crf --depend .\obj\inet_chksum.d)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\ip.o --omf_browse .\obj\ip.crf --depend .\obj\ip.d)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\ip_addr.o --omf_browse .\obj\ip_addr.crf --depend .\obj\ip_addr.d)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\ip_frag.o --omf_browse .\obj\ip_frag.crf --depend .\obj\ip_frag.d)
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+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
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-IG:\Keil_v5\ARM\RV31\INC
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-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\etharp.o --omf_browse .\obj\etharp.crf --depend .\obj\etharp.d)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h)(0x4B065C42)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
+F (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\system_stm32f10x.o --omf_browse .\obj\system_stm32f10x.crf --depend .\obj\system_stm32f10x.d)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Libraries\CMSIS\Core\CM3\core_cm3.c)(0x4B065C3E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\core_cm3.o --omf_browse .\obj\core_cm3.crf --depend .\obj\core_cm3.d)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+F (..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s)(0x4B065C3E)(--cpu Cortex-M3 -g --apcs=interwork
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
--pd "__UVISION_VERSION SETA 525"
--list .\list\startup_stm32f10x_cl.lst --xref -o .\obj\startup_stm32f10x_cl.o --depend .\obj\startup_stm32f10x_cl.d)
+F (..\..\Hardware\LED\led.c)(0x5C74C77E)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\led.o --omf_browse .\obj\led.crf --depend .\obj\led.d)
+I (..\..\Hardware\LED\led.h)(0x5C74C77E)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Basic\delay\delay.c)(0x5A414364)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\delay.o --omf_browse .\obj\delay.crf --depend .\obj\delay.d)
+I (..\..\Basic\delay\delay.h)(0x5C73E09C)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+F (..\..\Basic\usart\usart.c)(0x5CC465AA)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
-IG:\Keil_v5\ARM\RV31\INC
-IG:\Keil_v5\ARM\CMSIS\Include
-IG:\Keil_v5\ARM\INC\ST\STM32F10x
-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
-o .\obj\usart.o --omf_browse .\obj\usart.crf --depend .\obj\usart.d)
+I (..\inc\main.h)(0x5CAF3FE6)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (G:\Keil_v5\ARM\ARMCC\include\stdint.h)(0x599ECD2E)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+I (..\inc\stm32f107.h)(0x4B065C40)
+I (..\..\Utilities\STM32_EVAL\stm32_eval.h)(0x4B065C44)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h)(0x5131B922)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h)(0x4B065C44)
+I (..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h)(0x4B065C44)
+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\inc\netconf.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\helloworld.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\httpd.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\arch/cpu.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\fsdata.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\tftpserver.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h)(0x4B065C42)
+I (..\src\TCP_CLIENT.h)(0x5CAC40E6)
+I (..\..\Basic\usart\usart.h)(0x5CAC40C0)
+I (G:\Keil_v5\ARM\ARMCC\include\stdarg.h)(0x599ECD2A)
+I (G:\Keil_v5\ARM\ARMCC\include\stdlib.h)(0x599ECD2C)
+I (G:\Keil_v5\ARM\ARMCC\include\string.h)(0x599ECD2C)
+I (G:\Keil_v5\ARM\ARMCC\include\stdio.h)(0x599ECD2C)
+I (..\..\Basic\delay\delay.h)(0x5C73E09C)
+I (..\..\Hardware\LED\led.h)(0x5C74C77E)
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.axf b/F107/Project/RVMDK/Obj/STM3210C-EVAL.axf
new file mode 100644
index 0000000..ac5e5b0
Binary files /dev/null and b/F107/Project/RVMDK/Obj/STM3210C-EVAL.axf differ
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.build_log.htm b/F107/Project/RVMDK/Obj/STM3210C-EVAL.build_log.htm
new file mode 100644
index 0000000..14e218a
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL.build_log.htm
@@ -0,0 +1,34 @@
+
+
+
+礦ision Build Log
+Tool Versions:
+IDE-Version: μVision V5.25.2.0
+Copyright (C) 2018 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: 4 3, 2, LIC=NQQGK-Z22ZT-KNUAC-7S80V-KIDF3-7Z5ME
+
+Tool Versions:
+Toolchain: MDK-ARM Plus Version: 5.25.2.0
+Toolchain Path: G:\Keil_v5\ARM\ARMCC\Bin
+C Compiler: Armcc.exe V5.06 update 6 (build 750)
+Assembler: Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator: ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter: FromElf.exe V5.06 update 6 (build 750)
+CPU DLL: SARMCM3.DLL V5.25.2.0
+Dialog DLL: DARMSTM.DLL V1.68.0.0
+Target DLL: Segger\JL2CM3.dll V2.99.29.0
+Dialog DLL: TARMSTM.DLL V1.66.0.0
+
+Project:
+D:\项目\compile\基于IOT的无人快递站点\Two\F107\Project\RVMDK\Project.uvproj
+Project File Date: 05/16/2019
+
+Output:
+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'G:\Keil_v5\ARM\ARMCC\Bin'
+Build target 'STM32107VCT6'
+".\Obj\STM3210C-EVAL.axf" - 0 Error(s), 0 Warning(s).
+Build Time Elapsed: 00:00:01
+
+
+
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.hex b/F107/Project/RVMDK/Obj/STM3210C-EVAL.hex
new file mode 100644
index 0000000..3a5e8c4
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL.hex
@@ -0,0 +1,1831 @@
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diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.htm b/F107/Project/RVMDK/Obj/STM3210C-EVAL.htm
new file mode 100644
index 0000000..6001d22
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL.htm
@@ -0,0 +1,3087 @@
+
+
+Static Call Graph - [.\Obj\STM3210C-EVAL.axf]
+
+Static Call Graph for image .\Obj\STM3210C-EVAL.axf
+
#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Thu May 16 14:08:13 2019
+
+
Maximum Stack Usage = 644 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)
+Call chain for Maximum Stack Depth:
+__rt_entry_main ⇒ main ⇒ LwIP_Init ⇒ netif_add ⇒ netif_set_addr ⇒ netif_set_ipaddr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
+Functions with no stack information
+
+
+
+
+Mutually Recursive functions
+
ADC1_2_IRQHandler ⇒ ADC1_2_IRQHandler
+ BusFault_Handler ⇒ BusFault_Handler
+ HardFault_Handler ⇒ HardFault_Handler
+ MemManage_Handler ⇒ MemManage_Handler
+ Delay_s ⇒ Delay_s
+ UsageFault_Handler ⇒ UsageFault_Handler
+
+
+
+Function Pointers
+
+ - ADC1_2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- BusFault_Handler from stm32f10x_it.o(i.BusFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN1_RX0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN1_RX1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN1_SCE_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN1_TX_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN2_RX0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN2_RX1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN2_SCE_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- CAN2_TX_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA1_Channel1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA1_Channel2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA1_Channel3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA1_Channel4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA1_Channel5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA1_Channel6_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA1_Channel7_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA2_Channel1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA2_Channel2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA2_Channel3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA2_Channel4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DMA2_Channel5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- DebugMon_Handler from stm32f10x_it.o(i.DebugMon_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- ETH_IRQHandler from stm32f10x_it.o(i.ETH_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
+
- ETH_WKUP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- EXTI0_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- EXTI15_10_IRQHandler from stm32f10x_it.o(i.EXTI15_10_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
+
- EXTI1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- EXTI2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- EXTI3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- EXTI4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- EXTI9_5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- FLASH_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- HardFault_Handler from stm32f10x_it.o(i.HardFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- I2C1_ER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- I2C1_EV_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- I2C2_ER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- I2C2_EV_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- MemManage_Handler from stm32f10x_it.o(i.MemManage_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- NMI_Handler from stm32f10x_it.o(i.NMI_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- OTG_FS_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- OTG_FS_WKUP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- PVD_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- PendSV_Handler from stm32f10x_it.o(i.PendSV_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- RCC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- RTCAlarm_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- RTC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- Reset_Handler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- SPI1_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- SPI2_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- SPI3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- SVC_Handler from stm32f10x_it.o(i.SVC_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- SysTick_Handler from stm32f10x_it.o(i.SysTick_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- TAMPER_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TCP_Client_Recv from tcp_client.o(i.TCP_Client_Recv) referenced from tcp_client.o(i.TCP_Client_Init)
+
- TCP_Connected from tcp_client.o(i.TCP_Connected) referenced from tcp_client.o(i.TCP_Client_Init)
+
- TIM1_BRK_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM1_CC_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM1_TRG_COM_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM1_UP_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM2_IRQHandler from stm32f107.o(i.TIM2_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM4_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM5_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM6_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- TIM7_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- UART4_IRQHandler from usart.o(i.UART4_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
+
- UART5_IRQHandler from usart.o(i.UART5_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
+
- USART1_IRQHandler from sci.o(i.USART1_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
+
- USART2_IRQHandler from sci.o(i.USART2_IRQHandler) referenced from startup_stm32f10x_cl.o(RESET)
+
- USART3_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- UsageFault_Handler from stm32f10x_it.o(i.UsageFault_Handler) referenced from startup_stm32f10x_cl.o(RESET)
+
- WWDG_IRQHandler from startup_stm32f10x_cl.o(.text) referenced from startup_stm32f10x_cl.o(RESET)
+
- __main from __main.o(!!!main) referenced from startup_stm32f10x_cl.o(.text)
+
- _get_lc_ctype from lc_ctype_c.o(locale$$code) referenced from rt_ctype_table.o(.text)
+
- _printf_input_char from _printf_char_common.o(.text) referenced from _printf_char_common.o(.text)
+
- _snputc from _snputc.o(.text) referenced from c89vsnprintf.o(.text)
+
- _sputc from _sputc.o(.text) referenced from __2sprintf.o(.text)
+
- etharp_output from etharp.o(i.etharp_output) referenced from ethernetif.o(i.ethernetif_init)
+
- ethernet_input from etharp.o(i.ethernet_input) referenced from netconf.o(i.LwIP_Init)
+
- ethernetif_init from ethernetif.o(i.ethernetif_init) referenced from netconf.o(i.LwIP_Init)
+
- fputc from usart.o(i.fputc) referenced from _printf_char_file.o(.text)
+
- low_level_output from ethernetif.o(i.low_level_output) referenced from ethernetif.o(i.ethernetif_init)
+
- tcp_recv_null from tcp.o(i.tcp_recv_null) referenced from tcp.o(i.tcp_alloc)
+
+
+
+Global Symbols
+
+__main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main))
+
[Calls]
- >> __rt_entry
+
- >> __scatterload
+
+
+__scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter))
+
[Called By]
+
+__scatterload_rt2 (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
[Calls]
+
+__scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
+
__scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+
+
__scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
+
[Calls]
+
[Called By]
+
+__scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
+
+
_printf_n (Thumb, 0 bytes, Stack size unknown bytes, _printf_n.o(.ARM.Collect$$_printf_percent$$00000001))
+
[Calls]
+
+_printf_percent (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000))
+
[Called By]
+
+_printf_p (Thumb, 0 bytes, Stack size unknown bytes, _printf_p.o(.ARM.Collect$$_printf_percent$$00000002))
+
[Stack]
- Max Depth = 64 + Unknown Stack Size
+
- Call Chain = _printf_p ⇒ _printf_hex_ptr ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_f (Thumb, 0 bytes, Stack size unknown bytes, _printf_f.o(.ARM.Collect$$_printf_percent$$00000003))
+
[Stack]
- Max Depth = 324 + Unknown Stack Size
+
- Call Chain = _printf_f ⇒ _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
+
+
[Calls]
+
+_printf_e (Thumb, 0 bytes, Stack size unknown bytes, _printf_e.o(.ARM.Collect$$_printf_percent$$00000004))
+
[Stack]
- Max Depth = 324 + Unknown Stack Size
+
- Call Chain = _printf_e ⇒ _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
+
+
[Calls]
+
+_printf_g (Thumb, 0 bytes, Stack size unknown bytes, _printf_g.o(.ARM.Collect$$_printf_percent$$00000005))
+
[Stack]
- Max Depth = 324 + Unknown Stack Size
+
- Call Chain = _printf_g ⇒ _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
+
+
[Calls]
+
+_printf_a (Thumb, 0 bytes, Stack size unknown bytes, _printf_a.o(.ARM.Collect$$_printf_percent$$00000006))
+
+
_printf_ll (Thumb, 0 bytes, Stack size unknown bytes, _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007))
+
+
_printf_i (Thumb, 0 bytes, Stack size unknown bytes, _printf_i.o(.ARM.Collect$$_printf_percent$$00000008))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = _printf_i ⇒ _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_d (Thumb, 0 bytes, Stack size unknown bytes, _printf_d.o(.ARM.Collect$$_printf_percent$$00000009))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = _printf_d ⇒ _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_u (Thumb, 0 bytes, Stack size unknown bytes, _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = _printf_u ⇒ _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_o (Thumb, 0 bytes, Stack size unknown bytes, _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B))
+
[Stack]
- Max Depth = 64 + Unknown Stack Size
+
- Call Chain = _printf_o ⇒ _printf_int_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_x (Thumb, 0 bytes, Stack size unknown bytes, _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C))
+
[Stack]
- Max Depth = 80 + Unknown Stack Size
+
- Call Chain = _printf_x ⇒ _printf_int_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_lli (Thumb, 0 bytes, Stack size unknown bytes, _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = _printf_lli ⇒ _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_dec
+
+
+_printf_lld (Thumb, 0 bytes, Stack size unknown bytes, _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = _printf_lld ⇒ _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_dec
+
+
+_printf_llu (Thumb, 0 bytes, Stack size unknown bytes, _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F))
+
[Stack]
- Max Depth = 72 + Unknown Stack Size
+
- Call Chain = _printf_llu ⇒ _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_dec
+
+
+_printf_llo (Thumb, 0 bytes, Stack size unknown bytes, _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010))
+
[Stack]
- Max Depth = 56 + Unknown Stack Size
+
- Call Chain = _printf_llo ⇒ _printf_ll_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_llx (Thumb, 0 bytes, Stack size unknown bytes, _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011))
+
[Stack]
- Max Depth = 64 + Unknown Stack Size
+
- Call Chain = _printf_llx ⇒ _printf_ll_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_l (Thumb, 0 bytes, Stack size unknown bytes, _printf_l.o(.ARM.Collect$$_printf_percent$$00000012))
+
+
_printf_c (Thumb, 0 bytes, Stack size unknown bytes, _printf_c.o(.ARM.Collect$$_printf_percent$$00000013))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = _printf_c ⇒ _printf_char ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_s (Thumb, 0 bytes, Stack size unknown bytes, _printf_s.o(.ARM.Collect$$_printf_percent$$00000014))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = _printf_s ⇒ _printf_string ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding
+
+
[Calls]
+
+_printf_lc (Thumb, 0 bytes, Stack size unknown bytes, _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015))
+
[Stack]
- Max Depth = 88 + Unknown Stack Size
+
- Call Chain = _printf_lc ⇒ _printf_wchar ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table
+
+
[Calls]
+
+_printf_ls (Thumb, 0 bytes, Stack size unknown bytes, _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016))
+
[Stack]
- Max Depth = 88 + Unknown Stack Size
+
- Call Chain = _printf_ls ⇒ _printf_wstring ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table
+
+
[Calls]
+
+_printf_percent_end (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017))
+
+
__rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
+
[Called By]
+
+__rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002))
+
+
__rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
+
+
__rt_lib_init_lc_common (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000F))
+
[Calls]
+
+__rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
+
+
__rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
+
+
__rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
+
+
__rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
+
+
__rt_lib_init_lc_ctype_2 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000012))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __rt_lib_init_lc_ctype_2 ⇒ _get_lc_ctype
+
+
[Calls]
+
+__rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
+
+
__rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
+
+
__rt_lib_init_lc_numeric_2 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000016))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __rt_lib_init_lc_numeric_2 ⇒ _get_lc_numeric
+
+
[Calls]
+
+__rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
+
+
__rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
+
+
__rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
+
+
__rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
+
+
__rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
+
+
__rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
+
+
__rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
+
+
__rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
+
+
__rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
+
+
__rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
+
+
__rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033))
+
+
__rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
+
+
__rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
+
+
__rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
+
[Called By]
+
+__rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
+
+
__rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007))
+
+
__rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F))
+
+
__rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010))
+
+
__rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A))
+
+
__rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
+
+
__rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
+
+
__rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000))
+
[Called By]
- >> __main
+
- >> __scatterload_rt2
+
+
+__rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
+
+
__rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap
+
+
[Calls]- >> __user_setup_stackheap
+
+
+__rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A))
+
[Calls]
+
+__rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
+
+
__rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
+
[Stack]
- Max Depth = 644 + Unknown Stack Size
+
- Call Chain = __rt_entry_main ⇒ main ⇒ LwIP_Init ⇒ netif_add ⇒ netif_set_addr ⇒ netif_set_ipaddr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
+__rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
+
+
__rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
+
[Called By]
+
+__rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003))
+
[Calls]
+
+__rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
+
+
__rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
+
[Calls]
+
+Reset_Handler (Thumb, 4 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+CAN1_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+CAN2_RX0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+CAN2_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+CAN2_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+CAN2_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA2_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+DMA2_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+OTG_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+OTG_FS_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_cl.o(.text))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+__user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f10x_cl.o(.text))
+
[Called By]
- >> __user_setup_stackheap
+
+
+__use_no_semihosting (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi_2.o(.text), UNUSED)
+
+
__c89vsnprintf (Thumb, 48 bytes, Stack size 24 bytes, c89vsnprintf.o(.text))
+
[Stack]
- Max Depth = 128 + Unknown Stack Size
+
- Call Chain = __c89vsnprintf ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]- >> _sputc
+
- >> _printf_char_common
+
+
[Called By]- >> USART4_printf
+
- >> USART1_printf
+
- >> USART2_printf
+
+
+__2printf (Thumb, 20 bytes, Stack size 24 bytes, __2printf.o(.text))
+
[Stack]
- Max Depth = 144 + Unknown Stack Size
+
- Call Chain = __2printf ⇒ _printf_char_file ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]
+
[Called By]
+
+__2sprintf (Thumb, 38 bytes, Stack size 32 bytes, __2sprintf.o(.text))
+
[Stack]
- Max Depth = 136 + Unknown Stack Size
+
- Call Chain = __2sprintf ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]- >> _sputc
+
- >> _printf_char_common
+
+
[Called By]- >> Display_Periodic_Handle
+
+
+_printf_int_dec (Thumb, 104 bytes, Stack size 24 bytes, _printf_dec.o(.text))
+
[Stack]
- Max Depth = 72
- Call Chain = _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_int_common
+
- >> _printf_truncate_unsigned
+
- >> _printf_truncate_signed
+
+
[Called By]- >> _printf_u
+
- >> _printf_i
+
- >> _printf_d
+
+
+__printf (Thumb, 388 bytes, Stack size 40 bytes, __printf_flags_ss_wp.o(.text))
+
[Stack]
- Max Depth = 40 + Unknown Stack Size
+
- Call Chain = __printf
+
+
[Calls]- >> _printf_percent
+
- >> _is_digit
+
+
[Called By]
+
+strlen (Thumb, 62 bytes, Stack size 8 bytes, strlen.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = strlen
+
+
[Called By]- >> USART4_printf
+
- >> USART1_printf
+
- >> USART2_printf
+
+
+strncmp (Thumb, 150 bytes, Stack size 16 bytes, strncmp.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = strncmp
+
+
[Called By]
+
+__aeabi_memcpy (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text))
+
[Called By]
- >> ethernetif_input
+
- >> ip_reass_free_complete_datagram
+
- >> ip_reass
+
- >> ip_frag
+
- >> icmp_send_response
+
- >> pbuf_copy_partial
+
- >> pbuf_copy
+
- >> tcp_enqueue
+
- >> low_level_output
+
+
+__rt_memcpy (Thumb, 138 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text), UNUSED)
+
[Calls]
+
+_memcpy_lastbytes (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_v6.o(.text), UNUSED)
+
+
__aeabi_memclr (Thumb, 0 bytes, Stack size 0 bytes, rt_memclr.o(.text))
+
[Called By]
+
+__rt_memclr (Thumb, 68 bytes, Stack size 0 bytes, rt_memclr.o(.text), UNUSED)
+
[Calls]
+
+_memset (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text), UNUSED)
+
+
__aeabi_memclr4 (Thumb, 0 bytes, Stack size 4 bytes, rt_memclr_w.o(.text))
+
[Stack]
- Max Depth = 4
- Call Chain = __aeabi_memclr4
+
+
[Called By]- >> main
+
- >> ip_reass
+
- >> tcp_alloc
+
+
+__aeabi_memclr8 (Thumb, 0 bytes, Stack size 4 bytes, rt_memclr_w.o(.text), UNUSED)
+
+
__rt_memclr_w (Thumb, 78 bytes, Stack size 4 bytes, rt_memclr_w.o(.text), UNUSED)
+
+
_memset_w (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED)
+
[Called By]
+
+strncpy (Thumb, 86 bytes, Stack size 8 bytes, strncpy.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = strncpy
+
+
[Calls]
+
[Called By]
+
+__use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+
+
__I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+
+
__use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+
+
_printf_pre_padding (Thumb, 44 bytes, Stack size 16 bytes, _printf_pad.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = _printf_pre_padding
+
+
[Called By]- >> _printf_fp_infnan
+
- >> _printf_fp_dec_real
+
- >> _printf_wctomb
+
- >> _printf_int_common
+
- >> _printf_str
+
+
+_printf_post_padding (Thumb, 34 bytes, Stack size 16 bytes, _printf_pad.o(.text))
+
[Stack]
- Max Depth = 16
- Call Chain = _printf_post_padding
+
+
[Called By]- >> _printf_fp_infnan
+
- >> _printf_fp_dec_real
+
- >> _printf_wctomb
+
- >> _printf_int_common
+
- >> _printf_str
+
+
+_printf_truncate_signed (Thumb, 18 bytes, Stack size 0 bytes, _printf_truncate.o(.text))
+
[Called By]
+
+_printf_truncate_unsigned (Thumb, 18 bytes, Stack size 0 bytes, _printf_truncate.o(.text))
+
[Called By]
- >> _printf_int_hex
+
- >> _printf_int_oct
+
- >> _printf_int_dec
+
+
+_printf_str (Thumb, 82 bytes, Stack size 16 bytes, _printf_str.o(.text))
+
[Stack]
- Max Depth = 32
- Call Chain = _printf_str ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_post_padding
+
- >> _printf_pre_padding
+
+
[Called By]
+
+_printf_int_common (Thumb, 178 bytes, Stack size 32 bytes, _printf_intcommon.o(.text))
+
[Stack]
- Max Depth = 48
- Call Chain = _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_post_padding
+
- >> _printf_pre_padding
+
+
[Called By]- >> _printf_longlong_hex
+
- >> _printf_longlong_oct
+
- >> _printf_longlong_dec
+
- >> _printf_int_dec
+
+
+_printf_charcount (Thumb, 40 bytes, Stack size 0 bytes, _printf_charcount.o(.text))
+
[Called By]
+
+_printf_char_common (Thumb, 32 bytes, Stack size 64 bytes, _printf_char_common.o(.text))
+
[Stack]
- Max Depth = 104 + Unknown Stack Size
+
- Call Chain = _printf_char_common ⇒ __printf
+
+
[Calls]
+
[Called By]- >> _printf_char_file
+
- >> __2sprintf
+
- >> __c89vsnprintf
+
+
+_sputc (Thumb, 10 bytes, Stack size 0 bytes, _sputc.o(.text))
+
[Called By]
- >> __2sprintf
+
- >> __c89vsnprintf
+
+
[Address Reference Count : 1]
+_snputc (Thumb, 16 bytes, Stack size 0 bytes, _snputc.o(.text))
+
[Address Reference Count : 1]
+_printf_char_file (Thumb, 32 bytes, Stack size 16 bytes, _printf_char_file.o(.text))
+
[Stack]
- Max Depth = 120 + Unknown Stack Size
+
- Call Chain = _printf_char_file ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]- >> ferror
+
- >> _printf_char_common
+
+
[Called By]
+
+_printf_wctomb (Thumb, 182 bytes, Stack size 56 bytes, _printf_wctomb.o(.text))
+
[Stack]
- Max Depth = 80
- Call Chain = _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table
+
+
[Calls]- >> _wcrtomb
+
- >> _printf_post_padding
+
- >> _printf_pre_padding
+
+
[Called By]
+
+_printf_longlong_dec (Thumb, 108 bytes, Stack size 24 bytes, _printf_longlong_dec.o(.text))
+
[Stack]
- Max Depth = 72
- Call Chain = _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _ll_udiv10
+
- >> _printf_int_common
+
+
[Called By]- >> _printf_llu
+
- >> _printf_lld
+
- >> _printf_lli
+
+
+_printf_longlong_oct (Thumb, 66 bytes, Stack size 8 bytes, _printf_oct_int_ll.o(.text))
+
[Stack]
- Max Depth = 56
- Call Chain = _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
[Called By]- >> _printf_ll_oct
+
- >> _printf_int_oct
+
+
+_printf_int_oct (Thumb, 24 bytes, Stack size 8 bytes, _printf_oct_int_ll.o(.text))
+
[Stack]
- Max Depth = 64
- Call Chain = _printf_int_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_oct
+
- >> _printf_truncate_unsigned
+
+
[Called By]
+
+_printf_ll_oct (Thumb, 12 bytes, Stack size 0 bytes, _printf_oct_int_ll.o(.text))
+
[Stack]
- Max Depth = 56
- Call Chain = _printf_ll_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_oct
+
+
[Called By]
+
+_printf_longlong_hex (Thumb, 86 bytes, Stack size 16 bytes, _printf_hex_int_ll_ptr.o(.text))
+
[Stack]
- Max Depth = 64
- Call Chain = _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]
+
[Called By]- >> _printf_hex_ptr
+
- >> _printf_ll_hex
+
- >> _printf_int_hex
+
+
+_printf_int_hex (Thumb, 28 bytes, Stack size 16 bytes, _printf_hex_int_ll_ptr.o(.text))
+
[Stack]
- Max Depth = 80
- Call Chain = _printf_int_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_hex
+
- >> _printf_truncate_unsigned
+
+
[Called By]
+
+_printf_ll_hex (Thumb, 12 bytes, Stack size 0 bytes, _printf_hex_int_ll_ptr.o(.text))
+
[Stack]
- Max Depth = 64
- Call Chain = _printf_ll_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_hex
+
+
[Called By]
+
+_printf_hex_ptr (Thumb, 18 bytes, Stack size 0 bytes, _printf_hex_int_ll_ptr.o(.text))
+
[Stack]
- Max Depth = 64
- Call Chain = _printf_hex_ptr ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_longlong_hex
+
+
[Called By]
+
+__aeabi_memcpy4 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
+
[Called By]
+
+__aeabi_memcpy8 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
+
+
__rt_memcpy_w (Thumb, 100 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
+
+
_memcpy_lastbytes_aligned (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_w.o(.text), UNUSED)
+
+
_ll_udiv10 (Thumb, 138 bytes, Stack size 12 bytes, lludiv10.o(.text))
+
[Stack]
- Max Depth = 12
- Call Chain = _ll_udiv10
+
+
[Called By]- >> _fp_digits
+
- >> _printf_longlong_dec
+
+
+__lib_sel_fp_printf (Thumb, 2 bytes, Stack size 0 bytes, _printf_fp_dec.o(.text), UNUSED)
+
+
_printf_fp_dec_real (Thumb, 620 bytes, Stack size 104 bytes, _printf_fp_dec.o(.text))
+
[Stack]
- Max Depth = 324
- Call Chain = _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
+
+
[Calls]- >> __ARM_fpclassify
+
- >> _printf_fp_infnan
+
- >> __rt_locale
+
- >> _fp_digits
+
- >> _printf_post_padding
+
- >> _printf_pre_padding
+
+
[Called By]
+
+_printf_cs_common (Thumb, 20 bytes, Stack size 8 bytes, _printf_char.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding
+
+
[Calls]
+
[Called By]- >> _printf_string
+
- >> _printf_char
+
+
+_printf_char (Thumb, 16 bytes, Stack size 0 bytes, _printf_char.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = _printf_char ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding
+
+
[Calls]
+
[Called By]
+
+_printf_string (Thumb, 8 bytes, Stack size 0 bytes, _printf_char.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = _printf_string ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding
+
+
[Calls]
+
[Called By]
+
+_printf_lcs_common (Thumb, 20 bytes, Stack size 8 bytes, _printf_wchar.o(.text))
+
[Stack]
- Max Depth = 88
- Call Chain = _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table
+
+
[Calls]
+
[Called By]- >> _printf_wstring
+
- >> _printf_wchar
+
+
+_printf_wchar (Thumb, 16 bytes, Stack size 0 bytes, _printf_wchar.o(.text))
+
[Stack]
- Max Depth = 88
- Call Chain = _printf_wchar ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table
+
+
[Calls]
+
[Called By]
+
+_printf_wstring (Thumb, 8 bytes, Stack size 0 bytes, _printf_wchar.o(.text))
+
[Stack]
- Max Depth = 88
- Call Chain = _printf_wstring ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table
+
+
[Calls]
+
[Called By]
+
+ferror (Thumb, 8 bytes, Stack size 0 bytes, ferror.o(.text))
+
[Called By]
+
+_wcrtomb (Thumb, 64 bytes, Stack size 16 bytes, _wcrtomb.o(.text))
+
[Stack]
- Max Depth = 24
- Call Chain = _wcrtomb ⇒ __rt_ctype_table
+
+
[Calls]
+
[Called By]
+
+__user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = __user_setup_stackheap
+
+
[Calls]- >> __user_perproc_libspace
+
- >> __user_initial_stackheap
+
+
[Called By]
+
+__rt_ctype_table (Thumb, 16 bytes, Stack size 8 bytes, rt_ctype_table.o(.text))
+
[Stack]
- Max Depth = 8
- Call Chain = __rt_ctype_table
+
+
[Calls]
+
[Called By]
+
+__rt_locale (Thumb, 8 bytes, Stack size 0 bytes, rt_locale_intlibspace.o(.text))
+
[Called By]
- >> __rt_ctype_table
+
- >> _printf_fp_dec_real
+
- >> __rt_lib_init_lc_common
+
+
+_printf_fp_infnan (Thumb, 112 bytes, Stack size 24 bytes, _printf_fp_infnan.o(.text))
+
[Stack]
- Max Depth = 40
- Call Chain = _printf_fp_infnan ⇒ _printf_post_padding
+
+
[Calls]- >> _printf_post_padding
+
- >> _printf_pre_padding
+
+
[Called By]
+
+_btod_etento (Thumb, 224 bytes, Stack size 72 bytes, bigflt0.o(.text))
+
[Stack]
- Max Depth = 124
- Call Chain = _btod_etento ⇒ _btod_emul ⇒ _e2e
+
+
[Calls]- >> _btod_emul
+
- >> _btod_ediv
+
+
[Called By]
+
+exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text))
+
[Stack]
- Max Depth = 8 + Unknown Stack Size
+
- Call Chain = exit
+
+
[Calls]
+
[Called By]
+
+__user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+
+
__user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
+
[Called By]
- >> __user_setup_stackheap
+
+
+__user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+
+
strcmp (Thumb, 128 bytes, Stack size 0 bytes, strcmpv7m.o(.text))
+
[Called By]
- >> _get_lc_ctype
+
- >> _get_lc_numeric
+
+
+_btod_d2e (Thumb, 62 bytes, Stack size 0 bytes, btod.o(CL$$btod_d2e))
+
[Calls]
+
[Called By]
+
+_d2e_denorm_low (Thumb, 70 bytes, Stack size 0 bytes, btod.o(CL$$btod_d2e_denorm_low))
+
[Called By]
+
+_d2e_norm_op1 (Thumb, 96 bytes, Stack size 0 bytes, btod.o(CL$$btod_d2e_norm_op1))
+
[Calls]
+
[Called By]
+
+__btod_div_common (Thumb, 696 bytes, Stack size 24 bytes, btod.o(CL$$btod_div_common))
+
[Stack]
- Max Depth = 24
- Call Chain = __btod_div_common
+
+
[Called By]
+
+_e2e (Thumb, 220 bytes, Stack size 24 bytes, btod.o(CL$$btod_e2e))
+
[Stack]
- Max Depth = 24
- Call Chain = _e2e
+
+
[Called By]- >> _btod_emul
+
- >> _btod_ediv
+
+
+_btod_ediv (Thumb, 42 bytes, Stack size 28 bytes, btod.o(CL$$btod_ediv))
+
[Stack]
- Max Depth = 52
- Call Chain = _btod_ediv ⇒ _e2e
+
+
[Calls]- >> _e2e
+
- >> __btod_div_common
+
+
[Called By]- >> _btod_etento
+
- >> _fp_digits
+
+
+_btod_emul (Thumb, 42 bytes, Stack size 28 bytes, btod.o(CL$$btod_emul))
+
[Stack]
- Max Depth = 52
- Call Chain = _btod_emul ⇒ _e2e
+
+
[Calls]- >> __btod_mult_common
+
- >> _e2e
+
+
[Called By]- >> _btod_etento
+
- >> _fp_digits
+
+
+__btod_mult_common (Thumb, 580 bytes, Stack size 16 bytes, btod.o(CL$$btod_mult_common))
+
[Stack]
- Max Depth = 16
- Call Chain = __btod_mult_common
+
+
[Called By]
+
+BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.BusFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+Check_TCP_Connect (Thumb, 60 bytes, Stack size 16 bytes, tcp_client.o(i.Check_TCP_Connect))
+
[Stack]
- Max Depth = 404
- Call Chain = Check_TCP_Connect ⇒ TCP_Client_Init ⇒ tcp_new ⇒ tcp_alloc ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> main
+
- >> UART5_IRQHandler
+
+
+DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.DebugMon_Handler))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+Delay_s (Thumb, 6 bytes, Stack size 0 bytes, tcp_client.o(i.Delay_s))
+
[Calls]
+
[Called By]- >> Delay_s
+
- >> main
+
- >> UART5_IRQHandler
+
+
+Display_Periodic_Handle (Thumb, 86 bytes, Stack size 40 bytes, netconf.o(i.Display_Periodic_Handle))
+
[Stack]
- Max Depth = 176 + Unknown Stack Size
+
- Call Chain = Display_Periodic_Handle ⇒ __2sprintf ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]
+
[Called By]- >> System_Periodic_Handle
+
+
+ETH_DMAClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_DMAClearITPendingBit))
+
[Called By]
+
+ETH_DMAITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_DMAITConfig))
+
[Called By]
- >> Ethernet_Configuration
+
+
+ETH_DMAReceptionCmd (Thumb, 22 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_DMAReceptionCmd))
+
[Called By]
+
+ETH_DMARxDescChainInit (Thumb, 68 bytes, Stack size 20 bytes, stm32_eth.o(i.ETH_DMARxDescChainInit))
+
[Stack]
- Max Depth = 20
- Call Chain = ETH_DMARxDescChainInit
+
+
[Called By]
+
+ETH_DMARxDescReceiveITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_DMARxDescReceiveITConfig))
+
[Called By]
+
+ETH_DMATransmissionCmd (Thumb, 22 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_DMATransmissionCmd))
+
[Called By]
+
+ETH_DMATxDescChainInit (Thumb, 62 bytes, Stack size 20 bytes, stm32_eth.o(i.ETH_DMATxDescChainInit))
+
[Stack]
- Max Depth = 20
- Call Chain = ETH_DMATxDescChainInit
+
+
[Called By]
+
+ETH_DMATxDescChecksumInsertionConfig (Thumb, 8 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_DMATxDescChecksumInsertionConfig))
+
[Called By]
+
+ETH_DeInit (Thumb, 24 bytes, Stack size 8 bytes, stm32_eth.o(i.ETH_DeInit))
+
[Stack]
- Max Depth = 8
- Call Chain = ETH_DeInit
+
+
[Calls]- >> RCC_AHBPeriphResetCmd
+
+
[Called By]- >> Ethernet_Configuration
+
+
+ETH_FlushTransmitFIFO (Thumb, 12 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_FlushTransmitFIFO))
+
[Called By]
+
+ETH_GetCurrentTxBuffer (Thumb, 8 bytes, Stack size 0 bytes, ethernetif.o(i.ETH_GetCurrentTxBuffer))
+
[Called By]
+
+ETH_GetDMARxDescFrameLength (Thumb, 8 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_GetDMARxDescFrameLength))
+
[Called By]
+
+ETH_GetRxPktSize (Thumb, 30 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_GetRxPktSize))
+
[Calls]
- >> ETH_GetDMARxDescFrameLength
+
+
[Called By]
+
+ETH_GetSoftwareResetStatus (Thumb, 14 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_GetSoftwareResetStatus))
+
[Called By]
- >> Ethernet_Configuration
+
+
+ETH_IRQHandler (Thumb, 34 bytes, Stack size 8 bytes, stm32f10x_it.o(i.ETH_IRQHandler))
+
[Stack]
- Max Depth = 108
- Call Chain = ETH_IRQHandler ⇒ LwIP_Pkt_Handle ⇒ ethernetif_input ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> LwIP_Pkt_Handle
+
- >> ETH_GetRxPktSize
+
- >> ETH_DMAClearITPendingBit
+
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+ETH_Init (Thumb, 480 bytes, Stack size 56 bytes, stm32_eth.o(i.ETH_Init))
+
[Stack]
- Max Depth = 76
- Call Chain = ETH_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> RCC_GetClocksFreq
+
- >> ETH_WritePHYRegister
+
- >> ETH_ReadPHYRegister
+
- >> ETH_Delay
+
+
[Called By]- >> Ethernet_Configuration
+
+
+ETH_MACAddressConfig (Thumb, 22 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_MACAddressConfig))
+
[Called By]
+
+ETH_MACReceptionCmd (Thumb, 22 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_MACReceptionCmd))
+
[Called By]
+
+ETH_MACTransmissionCmd (Thumb, 22 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_MACTransmissionCmd))
+
[Called By]
+
+ETH_ReadPHYRegister (Thumb, 80 bytes, Stack size 12 bytes, stm32_eth.o(i.ETH_ReadPHYRegister))
+
[Stack]
- Max Depth = 12
- Call Chain = ETH_ReadPHYRegister
+
+
[Called By]
+
+ETH_RxPkt_ChainMode (Thumb, 72 bytes, Stack size 16 bytes, ethernetif.o(i.ETH_RxPkt_ChainMode))
+
[Stack]
- Max Depth = 16
- Call Chain = ETH_RxPkt_ChainMode
+
+
[Called By]
+
+ETH_SoftwareReset (Thumb, 12 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_SoftwareReset))
+
[Called By]
- >> Ethernet_Configuration
+
+
+ETH_Start (Thumb, 34 bytes, Stack size 4 bytes, stm32_eth.o(i.ETH_Start))
+
[Stack]
- Max Depth = 4
- Call Chain = ETH_Start
+
+
[Calls]- >> ETH_MACTransmissionCmd
+
- >> ETH_MACReceptionCmd
+
- >> ETH_FlushTransmitFIFO
+
- >> ETH_DMATransmissionCmd
+
- >> ETH_DMAReceptionCmd
+
+
[Called By]
+
+ETH_StructInit (Thumb, 124 bytes, Stack size 0 bytes, stm32_eth.o(i.ETH_StructInit))
+
[Called By]
- >> Ethernet_Configuration
+
+
+ETH_TxPkt_ChainMode (Thumb, 50 bytes, Stack size 0 bytes, ethernetif.o(i.ETH_TxPkt_ChainMode))
+
[Called By]
+
+ETH_WritePHYRegister (Thumb, 76 bytes, Stack size 16 bytes, stm32_eth.o(i.ETH_WritePHYRegister))
+
[Stack]
- Max Depth = 16
- Call Chain = ETH_WritePHYRegister
+
+
[Called By]
+
+EXTI15_10_IRQHandler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.EXTI15_10_IRQHandler))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+Ethernet_Configuration (Thumb, 144 bytes, Stack size 192 bytes, stm32f107.o(i.Ethernet_Configuration))
+
[Stack]
- Max Depth = 268
- Call Chain = Ethernet_Configuration ⇒ ETH_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> RCC_PLL3Config
+
- >> RCC_PLL3Cmd
+
- >> RCC_MCOConfig
+
- >> RCC_GetFlagStatus
+
- >> GPIO_ETH_MediaInterfaceConfig
+
- >> ETH_StructInit
+
- >> ETH_SoftwareReset
+
- >> ETH_Init
+
- >> ETH_GetSoftwareResetStatus
+
- >> ETH_DeInit
+
- >> ETH_DMAITConfig
+
+
[Called By]
+
+GPIO_Configuration (Thumb, 232 bytes, Stack size 32 bytes, stm32f107.o(i.GPIO_Configuration))
+
[Stack]
- Max Depth = 52
- Call Chain = GPIO_Configuration ⇒ GPIO_PinRemapConfig
+
+
[Calls]- >> GPIO_PinRemapConfig
+
- >> GPIO_Init
+
+
[Called By]
+
+GPIO_ETH_MediaInterfaceConfig (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig))
+
[Called By]
- >> Ethernet_Configuration
+
+
+GPIO_Init (Thumb, 156 bytes, Stack size 20 bytes, stm32f10x_gpio.o(i.GPIO_Init))
+
[Stack]
- Max Depth = 20
- Call Chain = GPIO_Init
+
+
[Called By]- >> USART_Configuration
+
- >> GPIO_Configuration
+
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_Init
+
- >> LED_Init3
+
- >> LED_Init2
+
- >> LED_Init1
+
+
+GPIO_PinRemapConfig (Thumb, 66 bytes, Stack size 20 bytes, stm32f10x_gpio.o(i.GPIO_PinRemapConfig))
+
[Stack]
- Max Depth = 20
- Call Chain = GPIO_PinRemapConfig
+
+
[Called By]- >> USART_Configuration
+
- >> GPIO_Configuration
+
- >> USART2_Init
+
- >> USART1_Init
+
+
+GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ResetBits))
+
[Called By]
+
+GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_SetBits))
+
[Called By]
- >> main
+
- >> UART5_IRQHandler
+
- >> UART4_IRQHandler
+
+
+HardFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.HardFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+LED_Init1 (Thumb, 40 bytes, Stack size 8 bytes, led.o(i.LED_Init1))
+
[Stack]
- Max Depth = 28
- Call Chain = LED_Init1 ⇒ GPIO_Init
+
+
[Calls]- >> RCC_APB2PeriphClockCmd
+
- >> GPIO_Init
+
+
[Called By]
+
+LED_Init2 (Thumb, 38 bytes, Stack size 8 bytes, led.o(i.LED_Init2))
+
[Stack]
- Max Depth = 28
- Call Chain = LED_Init2 ⇒ GPIO_Init
+
+
[Calls]- >> RCC_APB2PeriphClockCmd
+
- >> GPIO_Init
+
+
[Called By]
+
+LED_Init3 (Thumb, 38 bytes, Stack size 8 bytes, led.o(i.LED_Init3))
+
[Stack]
- Max Depth = 28
- Call Chain = LED_Init3 ⇒ GPIO_Init
+
+
[Calls]- >> RCC_APB2PeriphClockCmd
+
- >> GPIO_Init
+
+
[Called By]
+
+LwIP_Init (Thumb, 114 bytes, Stack size 40 bytes, netconf.o(i.LwIP_Init))
+
[Stack]
- Max Depth = 436
- Call Chain = LwIP_Init ⇒ netif_add ⇒ netif_set_addr ⇒ netif_set_ipaddr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> netif_set_up
+
- >> netif_set_default
+
- >> netif_add
+
- >> memp_init
+
- >> mem_init
+
- >> Set_MAC_Address
+
- >> My_IP4_ADDR
+
+
[Called By]
+
+LwIP_Periodic_Handle (Thumb, 48 bytes, Stack size 16 bytes, netconf.o(i.LwIP_Periodic_Handle))
+
[Stack]
- Max Depth = 396
- Call Chain = LwIP_Periodic_Handle ⇒ tcp_tmr ⇒ tcp_slowtmr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_tmr
+
- >> etharp_tmr
+
+
[Called By]- >> System_Periodic_Handle
+
+
+LwIP_Pkt_Handle (Thumb, 6 bytes, Stack size 0 bytes, netconf.o(i.LwIP_Pkt_Handle))
+
[Stack]
- Max Depth = 100
- Call Chain = LwIP_Pkt_Handle ⇒ ethernetif_input ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.MemManage_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+My_IP4_ADDR (Thumb, 26 bytes, Stack size 16 bytes, netconf.o(i.My_IP4_ADDR))
+
[Stack]
- Max Depth = 16
- Call Chain = My_IP4_ADDR
+
+
[Calls]
+
[Called By]
+
+NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.NMI_Handler))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+NVIC_Configuration (Thumb, 176 bytes, Stack size 16 bytes, stm32f107.o(i.NVIC_Configuration))
+
[Stack]
- Max Depth = 28
- Call Chain = NVIC_Configuration ⇒ NVIC_Init
+
+
[Calls]- >> NVIC_SetVectorTable
+
- >> NVIC_PriorityGroupConfig
+
- >> NVIC_Init
+
+
[Called By]- >> System_Setup
+
- >> main
+
+
+NVIC_Init (Thumb, 94 bytes, Stack size 12 bytes, misc.o(i.NVIC_Init))
+
[Stack]
- Max Depth = 12
- Call Chain = NVIC_Init
+
+
[Called By]- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_Init
+
- >> NVIC_Configuration
+
+
+NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig))
+
[Called By]
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_Init
+
- >> NVIC_Configuration
+
+
+NVIC_SetVectorTable (Thumb, 12 bytes, Stack size 0 bytes, misc.o(i.NVIC_SetVectorTable))
+
[Called By]
+
+PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.PendSV_Handler))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+RCC_AHBPeriphClockCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd))
+
[Called By]
+
+RCC_AHBPeriphResetCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_AHBPeriphResetCmd))
+
[Called By]
+
+RCC_APB1PeriphClockCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd))
+
[Called By]
- >> USART_Configuration
+
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> System_Setup
+
+
+RCC_APB2PeriphClockCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd))
+
[Called By]
- >> USART_Configuration
+
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_Init
+
- >> System_Setup
+
- >> LED_Init3
+
- >> LED_Init2
+
- >> LED_Init1
+
+
+RCC_GetClocksFreq (Thumb, 180 bytes, Stack size 20 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq))
+
[Stack]
- Max Depth = 20
- Call Chain = RCC_GetClocksFreq
+
+
[Called By]- >> USART_Init
+
- >> ETH_Init
+
- >> System_Setup
+
+
+RCC_GetFlagStatus (Thumb, 42 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_GetFlagStatus))
+
[Called By]
- >> Ethernet_Configuration
+
+
+RCC_MCOConfig (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_MCOConfig))
+
[Called By]
- >> Ethernet_Configuration
+
+
+RCC_PLL3Cmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PLL3Cmd))
+
[Called By]
- >> Ethernet_Configuration
+
+
+RCC_PLL3Config (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_PLL3Config))
+
[Called By]
- >> Ethernet_Configuration
+
+
+SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SVC_Handler))
+
[Address Reference Count : 1]
- startup_stm32f10x_cl.o(RESET)
+
+Set_MAC_Address (Thumb, 34 bytes, Stack size 0 bytes, ethernetif.o(i.Set_MAC_Address))
+
[Calls]
- >> ETH_MACAddressConfig
+
+
[Called By]
+
+SysTick_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SysTick_Handler))
+
[Calls]
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+SystemInit (Thumb, 64 bytes, Stack size 0 bytes, system_stm32f10x.o(i.SystemInit))
+
[Stack]
- Max Depth = 12
- Call Chain = SystemInit ⇒ SetSysClockTo72
+
+
[Calls]
+
[Called By]
+
+System_Periodic_Handle (Thumb, 20 bytes, Stack size 8 bytes, main.o(i.System_Periodic_Handle))
+
[Stack]
- Max Depth = 404 + Unknown Stack Size
+
- Call Chain = System_Periodic_Handle ⇒ LwIP_Periodic_Handle ⇒ tcp_tmr ⇒ tcp_slowtmr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> LwIP_Periodic_Handle
+
- >> Display_Periodic_Handle
+
+
[Called By]
+
+System_Setup (Thumb, 116 bytes, Stack size 32 bytes, stm32f107.o(i.System_Setup))
+
[Stack]
- Max Depth = 300
- Call Chain = System_Setup ⇒ Ethernet_Configuration ⇒ ETH_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> USART_Configuration
+
- >> SystemInit
+
- >> RCC_GetClocksFreq
+
- >> RCC_APB2PeriphClockCmd
+
- >> RCC_APB1PeriphClockCmd
+
- >> RCC_AHBPeriphClockCmd
+
- >> GPIO_Configuration
+
- >> Ethernet_Configuration
+
- >> NVIC_SetPriority
+
- >> NVIC_Configuration
+
+
[Called By]
+
+TCP_Client_Init (Thumb, 70 bytes, Stack size 24 bytes, tcp_client.o(i.TCP_Client_Init))
+
[Stack]
- Max Depth = 388
- Call Chain = TCP_Client_Init ⇒ tcp_new ⇒ tcp_alloc ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_recv
+
- >> tcp_new
+
- >> tcp_connect
+
- >> tcp_bind
+
- >> htonl
+
+
[Called By]- >> Check_TCP_Connect
+
- >> main
+
+
+TCP_Client_Recv (Thumb, 314 bytes, Stack size 32 bytes, tcp_client.o(i.TCP_Client_Recv))
+
[Stack]
- Max Depth = 400 + Unknown Stack Size
+
- Call Chain = TCP_Client_Recv ⇒ USART4_printf ⇒ __c89vsnprintf ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]- >> tcp_recved
+
- >> tcp_close
+
- >> pbuf_free
+
- >> USART4_printf
+
- >> delay_ms
+
- >> strncpy
+
+
[Address Reference Count : 1]- tcp_client.o(i.TCP_Client_Init)
+
+TCP_Client_Send_Data (Thumb, 24 bytes, Stack size 16 bytes, tcp_client.o(i.TCP_Client_Send_Data))
+
[Stack]
- Max Depth = 284
- Call Chain = TCP_Client_Send_Data ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_write
+
- >> tcp_output
+
+
[Called By]- >> main
+
- >> UART5_IRQHandler
+
+
+TCP_Connected (Thumb, 4 bytes, Stack size 0 bytes, tcp_client.o(i.TCP_Connected))
+
[Address Reference Count : 1]
- tcp_client.o(i.TCP_Client_Init)
+
+TIM2_IRQHandler (Thumb, 30 bytes, Stack size 8 bytes, stm32f107.o(i.TIM2_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = TIM2_IRQHandler
+
+
[Calls]- >> TIM_GetITStatus
+
- >> TIM_ClearITPendingBit
+
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+TIM_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ClearITPendingBit))
+
[Called By]
+
+TIM_GetITStatus (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_GetITStatus))
+
[Called By]
+
+Time_Update (Thumb, 10 bytes, Stack size 0 bytes, main.o(i.Time_Update))
+
[Called By]
+
+UART4_IRQHandler (Thumb, 60 bytes, Stack size 8 bytes, usart.o(i.UART4_IRQHandler))
+
[Stack]
- Max Depth = 8
- Call Chain = UART4_IRQHandler
+
+
[Calls]- >> USART_ReceiveData
+
- >> USART_GetFlagStatus
+
- >> GPIO_SetBits
+
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+UART5_IRQHandler (Thumb, 158 bytes, Stack size 16 bytes, usart.o(i.UART5_IRQHandler))
+
[Stack]
- Max Depth = 420 + Unknown Stack Size
+
- Call Chain = UART5_IRQHandler ⇒ Check_TCP_Connect ⇒ TCP_Client_Init ⇒ tcp_new ⇒ tcp_alloc ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> USART_ReceiveData
+
- >> USART_GetFlagStatus
+
- >> TCP_Client_Send_Data
+
- >> GPIO_SetBits
+
- >> Delay_s
+
- >> Check_TCP_Connect
+
- >> USART2_printf
+
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+USART1_IRQHandler (Thumb, 56 bytes, Stack size 16 bytes, sci.o(i.USART1_IRQHandler))
+
[Stack]
- Max Depth = 32
- Call Chain = USART1_IRQHandler ⇒ USART_GetITStatus
+
+
[Calls]- >> USART_GetITStatus
+
- >> USART_ClearITPendingBit
+
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+USART1_Init (Thumb, 170 bytes, Stack size 40 bytes, usart.o(i.USART1_Init))
+
[Stack]
- Max Depth = 92
- Call Chain = USART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> USART_Init
+
- >> USART_ITConfig
+
- >> USART_Cmd
+
- >> RCC_APB2PeriphClockCmd
+
- >> NVIC_PriorityGroupConfig
+
- >> NVIC_Init
+
- >> GPIO_PinRemapConfig
+
- >> GPIO_Init
+
+
[Called By]
+
+USART1_printf (Thumb, 72 bytes, Stack size 240 bytes, usart.o(i.USART1_printf))
+
[Stack]
- Max Depth = 368 + Unknown Stack Size
+
- Call Chain = USART1_printf ⇒ __c89vsnprintf ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]- >> USART_SendData
+
- >> USART_GetFlagStatus
+
- >> strlen
+
- >> __c89vsnprintf
+
+
[Called By]
+
+USART2_IRQHandler (Thumb, 62 bytes, Stack size 16 bytes, sci.o(i.USART2_IRQHandler))
+
[Stack]
- Max Depth = 32
- Call Chain = USART2_IRQHandler ⇒ USART_GetITStatus
+
+
[Calls]- >> USART_GetITStatus
+
- >> USART_ClearITPendingBit
+
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+USART2_Init (Thumb, 176 bytes, Stack size 40 bytes, usart.o(i.USART2_Init))
+
[Stack]
- Max Depth = 92
- Call Chain = USART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> USART_Init
+
- >> USART_ITConfig
+
- >> USART_Cmd
+
- >> RCC_APB2PeriphClockCmd
+
- >> RCC_APB1PeriphClockCmd
+
- >> NVIC_PriorityGroupConfig
+
- >> NVIC_Init
+
- >> GPIO_PinRemapConfig
+
- >> GPIO_Init
+
+
[Called By]
+
+USART2_printf (Thumb, 72 bytes, Stack size 240 bytes, usart.o(i.USART2_printf))
+
[Stack]
- Max Depth = 368 + Unknown Stack Size
+
- Call Chain = USART2_printf ⇒ __c89vsnprintf ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]- >> USART_SendData
+
- >> USART_GetFlagStatus
+
- >> strlen
+
- >> __c89vsnprintf
+
+
[Called By]
+
+USART4_Init (Thumb, 168 bytes, Stack size 40 bytes, usart.o(i.USART4_Init))
+
[Stack]
- Max Depth = 92
- Call Chain = USART4_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> USART_Init
+
- >> USART_ITConfig
+
- >> USART_Cmd
+
- >> RCC_APB2PeriphClockCmd
+
- >> RCC_APB1PeriphClockCmd
+
- >> NVIC_PriorityGroupConfig
+
- >> NVIC_Init
+
- >> GPIO_Init
+
+
[Called By]
+
+USART4_printf (Thumb, 72 bytes, Stack size 240 bytes, usart.o(i.USART4_printf))
+
[Stack]
- Max Depth = 368 + Unknown Stack Size
+
- Call Chain = USART4_printf ⇒ __c89vsnprintf ⇒ _printf_char_common ⇒ __printf
+
+
[Calls]- >> USART_SendData
+
- >> USART_GetFlagStatus
+
- >> strlen
+
- >> __c89vsnprintf
+
+
[Called By]
+
+USART5_Init (Thumb, 166 bytes, Stack size 40 bytes, usart.o(i.USART5_Init))
+
[Stack]
- Max Depth = 92
- Call Chain = USART5_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> USART_Init
+
- >> USART_ITConfig
+
- >> USART_Cmd
+
- >> RCC_APB2PeriphClockCmd
+
- >> RCC_APB1PeriphClockCmd
+
- >> NVIC_PriorityGroupConfig
+
- >> NVIC_Init
+
- >> GPIO_Init
+
+
[Called By]
+
+USART_ClearITPendingBit (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ClearITPendingBit))
+
[Called By]
- >> USART2_IRQHandler
+
- >> USART1_IRQHandler
+
- >> USART_Configuration
+
+
+USART_Cmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_Cmd))
+
[Called By]
- >> USART_Configuration
+
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_Init
+
+
+USART_Configuration (Thumb, 302 bytes, Stack size 56 bytes, sci.o(i.USART_Configuration))
+
[Stack]
- Max Depth = 108
- Call Chain = USART_Configuration ⇒ USART_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]- >> USART_Init
+
- >> USART_ITConfig
+
- >> USART_Cmd
+
- >> USART_ClearITPendingBit
+
- >> RCC_APB2PeriphClockCmd
+
- >> RCC_APB1PeriphClockCmd
+
- >> GPIO_PinRemapConfig
+
- >> GPIO_Init
+
+
[Called By]
+
+USART_GetFlagStatus (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_GetFlagStatus))
+
[Called By]
- >> USART4_printf
+
- >> USART1_printf
+
- >> main
+
- >> USART2_printf
+
- >> UART5_IRQHandler
+
- >> UART4_IRQHandler
+
+
+USART_GetITStatus (Thumb, 62 bytes, Stack size 16 bytes, stm32f10x_usart.o(i.USART_GetITStatus))
+
[Stack]
- Max Depth = 16
- Call Chain = USART_GetITStatus
+
+
[Called By]- >> USART2_IRQHandler
+
- >> USART1_IRQHandler
+
+
+USART_ITConfig (Thumb, 48 bytes, Stack size 8 bytes, stm32f10x_usart.o(i.USART_ITConfig))
+
[Stack]
- Max Depth = 8
- Call Chain = USART_ITConfig
+
+
[Called By]- >> USART_Configuration
+
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_Init
+
+
+USART_Init (Thumb, 134 bytes, Stack size 32 bytes, stm32f10x_usart.o(i.USART_Init))
+
[Stack]
- Max Depth = 52
- Call Chain = USART_Init ⇒ RCC_GetClocksFreq
+
+
[Calls]
+
[Called By]- >> USART_Configuration
+
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_Init
+
+
+USART_ReceiveData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ReceiveData))
+
[Called By]
- >> main
+
- >> UART5_IRQHandler
+
- >> UART4_IRQHandler
+
+
+USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_SendData))
+
[Called By]
- >> USART4_printf
+
- >> USART1_printf
+
- >> USART2_printf
+
+
+UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.UsageFault_Handler))
+
[Calls]
+
[Called By]
+
[Address Reference Count : 1]- startup_stm32f10x_cl.o(RESET)
+
+__ARM_fpclassify (Thumb, 40 bytes, Stack size 0 bytes, fpclassify.o(i.__ARM_fpclassify))
+
[Called By]
+
+_is_digit (Thumb, 14 bytes, Stack size 0 bytes, __printf_wp.o(i._is_digit))
+
[Called By]
+
+_sys_exit (Thumb, 2 bytes, Stack size 0 bytes, usart.o(i._sys_exit))
+
[Called By]
+
+delay_ms (Thumb, 24 bytes, Stack size 4 bytes, delay.o(i.delay_ms))
+
[Stack]
- Max Depth = 4
- Call Chain = delay_ms
+
+
[Calls]
+
[Called By]- >> TCP_Client_Recv
+
- >> main
+
+
+delay_us (Thumb, 32 bytes, Stack size 0 bytes, delay.o(i.delay_us))
+
[Called By]
+
+etharp_arp_input (Thumb, 202 bytes, Stack size 32 bytes, etharp.o(i.etharp_arp_input))
+
[Stack]
- Max Depth = 156
- Call Chain = etharp_arp_input ⇒ update_arp_entry ⇒ find_entry ⇒ free_etharp_q ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> htons
+
- >> update_arp_entry
+
+
[Called By]
+
+etharp_ip_input (Thumb, 40 bytes, Stack size 8 bytes, etharp.o(i.etharp_ip_input))
+
[Stack]
- Max Depth = 132
- Call Chain = etharp_ip_input ⇒ update_arp_entry ⇒ find_entry ⇒ free_etharp_q ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+etharp_output (Thumb, 178 bytes, Stack size 32 bytes, etharp.o(i.etharp_output))
+
[Stack]
- Max Depth = 196
- Call Chain = etharp_output ⇒ etharp_query ⇒ etharp_request ⇒ etharp_raw ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_header
+
- >> ntohl
+
- >> ip_addr_isbroadcast
+
- >> etharp_query
+
- >> etharp_send_ip
+
+
[Address Reference Count : 1]- ethernetif.o(i.ethernetif_init)
+
+etharp_query (Thumb, 256 bytes, Stack size 40 bytes, etharp.o(i.etharp_query))
+
[Stack]
- Max Depth = 164
- Call Chain = etharp_query ⇒ etharp_request ⇒ etharp_raw ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> pbuf_ref
+
- >> pbuf_copy
+
- >> etharp_request
+
- >> ntohl
+
- >> ip_addr_isbroadcast
+
- >> memp_malloc
+
- >> pbuf_alloc
+
- >> find_entry
+
- >> etharp_send_ip
+
+
[Called By]
+
+etharp_request (Thumb, 32 bytes, Stack size 24 bytes, etharp.o(i.etharp_request))
+
[Stack]
- Max Depth = 124
- Call Chain = etharp_request ⇒ etharp_raw ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> netif_set_up
+
- >> etharp_query
+
+
+etharp_tmr (Thumb, 78 bytes, Stack size 24 bytes, etharp.o(i.etharp_tmr))
+
[Stack]
- Max Depth = 68
- Call Chain = etharp_tmr ⇒ free_etharp_q ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> LwIP_Periodic_Handle
+
+
+ethernet_input (Thumb, 84 bytes, Stack size 16 bytes, etharp.o(i.ethernet_input))
+
[Stack]
- Max Depth = 476
- Call Chain = ethernet_input ⇒ ip_input ⇒ tcp_input ⇒ tcp_process ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> ip_input
+
- >> pbuf_header
+
- >> htons
+
- >> etharp_ip_input
+
- >> etharp_arp_input
+
+
[Address Reference Count : 1]
+ethernetif_init (Thumb, 56 bytes, Stack size 8 bytes, ethernetif.o(i.ethernetif_init))
+
[Stack]
- Max Depth = 44
- Call Chain = ethernetif_init ⇒ low_level_init ⇒ ETH_DMATxDescChainInit
+
+
[Calls]- >> mem_malloc
+
- >> low_level_init
+
+
[Address Reference Count : 1]
+ethernetif_input (Thumb, 116 bytes, Stack size 40 bytes, ethernetif.o(i.ethernetif_input))
+
[Stack]
- Max Depth = 100
- Call Chain = ethernetif_input ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> pbuf_alloc
+
- >> ETH_RxPkt_ChainMode
+
- >> __aeabi_memcpy
+
+
[Called By]
+
+fputc (Thumb, 14 bytes, Stack size 0 bytes, usart.o(i.fputc))
+
[Address Reference Count : 1]
- _printf_char_file.o(.text)
+
+htonl (Thumb, 4 bytes, Stack size 0 bytes, inet.o(i.htonl))
+
[Called By]
- >> tcp_output
+
- >> My_IP4_ADDR
+
- >> TCP_Client_Init
+
- >> tcp_output_set_header
+
- >> tcp_output_segment
+
- >> tcp_rst
+
- >> tcp_keepalive
+
- >> tcp_enqueue
+
+
+htons (Thumb, 4 bytes, Stack size 0 bytes, inet.o(i.htons))
+
[Called By]
- >> tcp_output
+
- >> ethernet_input
+
- >> etharp_raw
+
- >> ip_reass
+
- >> ip_frag
+
- >> ip_input
+
- >> lwip_standard_chksum
+
- >> icmp_input
+
- >> ip_output_if
+
- >> tcp_output_set_header
+
- >> tcp_output_segment
+
- >> tcp_receive
+
- >> tcp_rst
+
- >> tcp_enqueue
+
- >> etharp_arp_input
+
- >> etharp_send_ip
+
+
+icmp_dest_unreach (Thumb, 8 bytes, Stack size 0 bytes, icmp.o(i.icmp_dest_unreach))
+
[Stack]
- Max Depth = 244
- Call Chain = icmp_dest_unreach ⇒ icmp_send_response ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> ip_input
+
- >> udp_input
+
+
+icmp_input (Thumb, 276 bytes, Stack size 48 bytes, icmp.o(i.icmp_input))
+
[Stack]
- Max Depth = 212
- Call Chain = icmp_input ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> inet_chksum_pbuf
+
- >> pbuf_copy
+
- >> ip_output_if
+
- >> pbuf_header
+
- >> ntohs
+
- >> ntohl
+
- >> ip_addr_isbroadcast
+
- >> htons
+
- >> pbuf_alloc
+
+
[Called By]
+
+icmp_time_exceeded (Thumb, 8 bytes, Stack size 0 bytes, icmp.o(i.icmp_time_exceeded))
+
[Stack]
- Max Depth = 244
- Call Chain = icmp_time_exceeded ⇒ icmp_send_response ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> ip_reass_free_complete_datagram
+
+
+inet_chksum (Thumb, 12 bytes, Stack size 8 bytes, inet_chksum.o(i.inet_chksum))
+
[Stack]
- Max Depth = 16
- Call Chain = inet_chksum ⇒ lwip_standard_chksum
+
+
[Calls]- >> lwip_standard_chksum
+
+
[Called By]- >> ip_reass
+
- >> ip_frag
+
- >> icmp_send_response
+
+
+inet_chksum_pbuf (Thumb, 72 bytes, Stack size 16 bytes, inet_chksum.o(i.inet_chksum_pbuf))
+
[Stack]
- Max Depth = 24
- Call Chain = inet_chksum_pbuf ⇒ lwip_standard_chksum
+
+
[Calls]- >> lwip_standard_chksum
+
+
[Called By]
+
+ip_addr_isbroadcast (Thumb, 48 bytes, Stack size 0 bytes, ip_addr.o(i.ip_addr_isbroadcast))
+
[Called By]
- >> ip_input
+
- >> icmp_input
+
- >> udp_input
+
- >> tcp_input
+
- >> etharp_output
+
- >> etharp_query
+
- >> update_arp_entry
+
+
+ip_frag (Thumb, 298 bytes, Stack size 64 bytes, ip_frag.o(i.ip_frag))
+
[Stack]
- Max Depth = 124
- Call Chain = ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> inet_chksum
+
- >> pbuf_copy_partial
+
- >> pbuf_chain
+
- >> pbuf_realloc
+
- >> ntohs
+
- >> htons
+
- >> pbuf_alloc
+
- >> __aeabi_memcpy
+
+
[Called By]
+
+ip_input (Thumb, 348 bytes, Stack size 32 bytes, ip.o(i.ip_input))
+
[Stack]
- Max Depth = 460
- Call Chain = ip_input ⇒ tcp_input ⇒ tcp_process ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> ip_reass
+
- >> icmp_input
+
- >> raw_input
+
- >> netif_is_up
+
- >> icmp_dest_unreach
+
- >> udp_input
+
- >> pbuf_realloc
+
- >> ntohs
+
- >> ntohl
+
- >> ip_addr_isbroadcast
+
- >> htons
+
- >> tcp_input
+
+
[Called By]
+
+ip_output (Thumb, 52 bytes, Stack size 40 bytes, ip.o(i.ip_output))
+
[Stack]
- Max Depth = 204
- Call Chain = ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> ip_output_if
+
- >> ip_route
+
+
[Called By]- >> tcp_output
+
- >> icmp_send_response
+
- >> tcp_output_segment
+
- >> tcp_zero_window_probe
+
- >> tcp_rst
+
- >> tcp_keepalive
+
+
+ip_output_if (Thumb, 200 bytes, Stack size 40 bytes, ip.o(i.ip_output_if))
+
[Stack]
- Max Depth = 164
- Call Chain = ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> ip_frag
+
- >> pbuf_header
+
- >> ntohs
+
- >> htons
+
+
[Called By]- >> icmp_input
+
- >> ip_output
+
+
+ip_reass (Thumb, 428 bytes, Stack size 40 bytes, ip_frag.o(i.ip_reass))
+
[Stack]
- Max Depth = 332
- Call Chain = ip_reass ⇒ ip_reass_remove_oldest_datagram ⇒ ip_reass_free_complete_datagram ⇒ icmp_time_exceeded ⇒ icmp_send_response ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> ip_reass_remove_oldest_datagram
+
- >> ip_reass_dequeue_datagram
+
- >> ip_reass_chain_frag_into_datagram_and_validate
+
- >> inet_chksum
+
- >> pbuf_cat
+
- >> pbuf_header
+
- >> pbuf_clen
+
- >> ntohs
+
- >> htons
+
- >> memp_malloc
+
- >> __aeabi_memclr4
+
- >> __aeabi_memcpy
+
+
[Called By]
+
+ip_route (Thumb, 62 bytes, Stack size 16 bytes, ip.o(i.ip_route))
+
[Stack]
- Max Depth = 16
- Call Chain = ip_route
+
+
[Calls]
+
[Called By]- >> ip_output
+
- >> tcp_output_segment
+
- >> tcp_eff_send_mss
+
+
+main (Thumb, 488 bytes, Stack size 208 bytes, main.o(i.main))
+
[Stack]
- Max Depth = 644 + Unknown Stack Size
+
- Call Chain = main ⇒ LwIP_Init ⇒ netif_add ⇒ netif_set_addr ⇒ netif_set_ipaddr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> delay_ms
+
- >> USART_ReceiveData
+
- >> USART_GetFlagStatus
+
- >> USART5_Init
+
- >> USART4_Init
+
- >> USART2_Init
+
- >> USART1_printf
+
- >> USART1_Init
+
- >> TCP_Client_Send_Data
+
- >> TCP_Client_Init
+
- >> System_Setup
+
- >> NVIC_Configuration
+
- >> LwIP_Init
+
- >> LED_Init3
+
- >> LED_Init2
+
- >> LED_Init1
+
- >> GPIO_SetBits
+
- >> GPIO_ResetBits
+
- >> Delay_s
+
- >> Check_TCP_Connect
+
- >> System_Periodic_Handle
+
- >> __aeabi_memclr4
+
- >> strncmp
+
- >> __2printf
+
+
[Called By]
+
+mem_free (Thumb, 40 bytes, Stack size 0 bytes, mem.o(i.mem_free))
+
[Stack]
- Max Depth = 12
- Call Chain = mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+mem_init (Thumb, 44 bytes, Stack size 8 bytes, mem.o(i.mem_init))
+
[Stack]
- Max Depth = 8
- Call Chain = mem_init
+
+
[Called By]
+
+mem_malloc (Thumb, 162 bytes, Stack size 20 bytes, mem.o(i.mem_malloc))
+
[Stack]
- Max Depth = 20
- Call Chain = mem_malloc
+
+
[Called By]- >> ethernetif_init
+
- >> pbuf_alloc
+
+
+mem_realloc (Thumb, 190 bytes, Stack size 36 bytes, mem.o(i.mem_realloc))
+
[Stack]
- Max Depth = 36
- Call Chain = mem_realloc
+
+
[Called By]
+
+memp_free (Thumb, 18 bytes, Stack size 0 bytes, memp.o(i.memp_free))
+
[Called By]
- >> tcp_close
+
- >> pbuf_free
+
- >> ip_reass_dequeue_datagram
+
- >> tcp_input
+
- >> tcp_enqueue
+
- >> tcp_slowtmr
+
- >> tcp_seg_free
+
- >> tcp_abandon
+
- >> update_arp_entry
+
- >> free_etharp_q
+
+
+memp_init (Thumb, 78 bytes, Stack size 20 bytes, memp.o(i.memp_init))
+
[Stack]
- Max Depth = 20
- Call Chain = memp_init
+
+
[Called By]
+
+memp_malloc (Thumb, 28 bytes, Stack size 0 bytes, memp.o(i.memp_malloc))
+
[Called By]
- >> ip_reass
+
- >> tcp_enqueue
+
- >> tcp_alloc
+
- >> pbuf_alloc
+
- >> etharp_query
+
+
+netif_add (Thumb, 68 bytes, Stack size 24 bytes, netif.o(i.netif_add))
+
[Stack]
- Max Depth = 396
- Call Chain = netif_add ⇒ netif_set_addr ⇒ netif_set_ipaddr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+netif_is_up (Thumb, 10 bytes, Stack size 0 bytes, netif.o(i.netif_is_up))
+
[Called By]
- >> ip_input
+
- >> ip_route
+
+
+netif_set_addr (Thumb, 32 bytes, Stack size 16 bytes, netif.o(i.netif_set_addr))
+
[Stack]
- Max Depth = 372
- Call Chain = netif_set_addr ⇒ netif_set_ipaddr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> netif_set_netmask
+
- >> netif_set_ipaddr
+
- >> netif_set_gw
+
+
[Called By]
+
+netif_set_default (Thumb, 6 bytes, Stack size 0 bytes, netif.o(i.netif_set_default))
+
[Called By]
+
+netif_set_gw (Thumb, 8 bytes, Stack size 0 bytes, netif.o(i.netif_set_gw))
+
[Called By]
+
+netif_set_ipaddr (Thumb, 96 bytes, Stack size 16 bytes, netif.o(i.netif_set_ipaddr))
+
[Stack]
- Max Depth = 356
- Call Chain = netif_set_ipaddr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+netif_set_netmask (Thumb, 8 bytes, Stack size 0 bytes, netif.o(i.netif_set_netmask))
+
[Called By]
+
+netif_set_up (Thumb, 28 bytes, Stack size 0 bytes, netif.o(i.netif_set_up))
+
[Stack]
- Max Depth = 124
- Call Chain = netif_set_up ⇒ etharp_request ⇒ etharp_raw ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+ntohl (Thumb, 4 bytes, Stack size 0 bytes, inet.o(i.ntohl))
+
[Called By]
- >> tcp_output
+
- >> ip_input
+
- >> icmp_input
+
- >> udp_input
+
- >> tcp_output_segment
+
- >> tcp_rexmit
+
- >> tcp_input
+
- >> tcp_receive
+
- >> tcp_process
+
- >> etharp_output
+
- >> etharp_query
+
- >> update_arp_entry
+
+
+ntohs (Thumb, 4 bytes, Stack size 0 bytes, inet.o(i.ntohs))
+
[Called By]
- >> tcp_output
+
- >> ip_reass_chain_frag_into_datagram_and_validate
+
- >> ip_reass
+
- >> ip_frag
+
- >> ip_input
+
- >> icmp_input
+
- >> raw_input
+
- >> ip_output_if
+
- >> udp_input
+
- >> tcp_output_set_header
+
- >> tcp_input
+
- >> tcp_receive
+
- >> tcp_parseopt
+
- >> tcp_rst
+
- >> tcp_enqueue
+
+
+pbuf_alloc (Thumb, 268 bytes, Stack size 32 bytes, pbuf.o(i.pbuf_alloc))
+
[Stack]
- Max Depth = 60
- Call Chain = pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> memp_malloc
+
- >> mem_malloc
+
+
[Called By]- >> tcp_output
+
- >> ethernetif_input
+
- >> etharp_raw
+
- >> ip_frag
+
- >> icmp_input
+
- >> icmp_send_response
+
- >> tcp_zero_window_probe
+
- >> tcp_rst
+
- >> tcp_keepalive
+
- >> tcp_enqueue
+
- >> etharp_query
+
+
+pbuf_cat (Thumb, 40 bytes, Stack size 8 bytes, pbuf.o(i.pbuf_cat))
+
[Stack]
- Max Depth = 8
- Call Chain = pbuf_cat
+
+
[Called By]- >> ip_reass
+
- >> pbuf_chain
+
- >> tcp_enqueue
+
+
+pbuf_chain (Thumb, 18 bytes, Stack size 8 bytes, pbuf.o(i.pbuf_chain))
+
[Stack]
- Max Depth = 16
- Call Chain = pbuf_chain ⇒ pbuf_cat
+
+
[Calls]- >> pbuf_ref
+
- >> pbuf_cat
+
+
[Called By]
+
+pbuf_clen (Thumb, 18 bytes, Stack size 0 bytes, pbuf.o(i.pbuf_clen))
+
[Called By]
- >> ip_reass_free_complete_datagram
+
- >> ip_reass_chain_frag_into_datagram_and_validate
+
- >> ip_reass
+
- >> tcp_receive
+
- >> tcp_enqueue
+
+
+pbuf_copy (Thumb, 144 bytes, Stack size 32 bytes, pbuf.o(i.pbuf_copy))
+
[Stack]
- Max Depth = 32
- Call Chain = pbuf_copy
+
+
[Calls]
+
[Called By]- >> icmp_input
+
- >> etharp_query
+
+
+pbuf_copy_partial (Thumb, 104 bytes, Stack size 32 bytes, pbuf.o(i.pbuf_copy_partial))
+
[Stack]
- Max Depth = 32
- Call Chain = pbuf_copy_partial
+
+
[Calls]
+
[Called By]
+
+pbuf_free (Thumb, 68 bytes, Stack size 16 bytes, pbuf.o(i.pbuf_free))
+
[Stack]
- Max Depth = 28
- Call Chain = pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> mem_free
+
- >> memp_free
+
+
[Called By]- >> tcp_output
+
- >> TCP_Client_Recv
+
- >> ethernetif_input
+
- >> ethernet_input
+
- >> etharp_raw
+
- >> ip_reass_free_complete_datagram
+
- >> ip_reass_chain_frag_into_datagram_and_validate
+
- >> ip_reass
+
- >> ip_frag
+
- >> ip_input
+
- >> icmp_input
+
- >> icmp_send_response
+
- >> udp_input
+
- >> pbuf_realloc
+
- >> tcp_input
+
- >> tcp_zero_window_probe
+
- >> tcp_rst
+
- >> tcp_keepalive
+
- >> tcp_enqueue
+
- >> tcp_seg_free
+
- >> tcp_pcb_purge
+
- >> tcp_fasttmr
+
- >> tcp_recv_null
+
- >> pbuf_alloc
+
- >> etharp_query
+
- >> etharp_arp_input
+
- >> update_arp_entry
+
- >> free_etharp_q
+
+
+pbuf_header (Thumb, 96 bytes, Stack size 8 bytes, pbuf.o(i.pbuf_header))
+
[Stack]
- Max Depth = 8
- Call Chain = pbuf_header
+
+
[Called By]- >> ethernet_input
+
- >> ip_reass
+
- >> icmp_input
+
- >> ip_output_if
+
- >> udp_input
+
- >> tcp_input
+
- >> tcp_receive
+
- >> tcp_enqueue
+
- >> etharp_output
+
+
+pbuf_realloc (Thumb, 78 bytes, Stack size 16 bytes, pbuf.o(i.pbuf_realloc))
+
[Stack]
- Max Depth = 52
- Call Chain = pbuf_realloc ⇒ mem_realloc
+
+
[Calls]- >> pbuf_free
+
- >> mem_realloc
+
+
[Called By]- >> ip_frag
+
- >> ip_input
+
- >> tcp_receive
+
+
+pbuf_ref (Thumb, 12 bytes, Stack size 0 bytes, pbuf.o(i.pbuf_ref))
+
[Called By]
- >> pbuf_chain
+
- >> etharp_query
+
+
+raw_input (Thumb, 100 bytes, Stack size 32 bytes, raw.o(i.raw_input))
+
[Stack]
- Max Depth = 32
- Call Chain = raw_input
+
+
[Calls]
+
[Called By]
+
+tcp_abandon (Thumb, 142 bytes, Stack size 56 bytes, tcp.o(i.tcp_abandon))
+
[Stack]
- Max Depth = 340
- Call Chain = tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_rst
+
- >> memp_free
+
- >> tcp_segs_free
+
- >> tcp_pcb_remove
+
+
[Called By]- >> netif_set_ipaddr
+
- >> tcp_process
+
- >> tcp_listen_input
+
- >> tcp_slowtmr
+
- >> tcp_alloc
+
+
+tcp_alloc (Thumb, 248 bytes, Stack size 24 bytes, tcp.o(i.tcp_alloc))
+
[Stack]
- Max Depth = 364
- Call Chain = tcp_alloc ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> memp_malloc
+
- >> tcp_next_iss
+
- >> tcp_abandon
+
- >> __aeabi_memclr4
+
+
[Called By]- >> tcp_new
+
- >> tcp_listen_input
+
+
+tcp_bind (Thumb, 182 bytes, Stack size 24 bytes, tcp.o(i.tcp_bind))
+
[Stack]
- Max Depth = 44
- Call Chain = tcp_bind ⇒ tcp_new_port
+
+
[Calls]
+
[Called By]
+
+tcp_close (Thumb, 156 bytes, Stack size 16 bytes, tcp.o(i.tcp_close))
+
[Stack]
- Max Depth = 300
- Call Chain = tcp_close ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_send_ctrl
+
- >> memp_free
+
- >> tcp_pcb_remove
+
+
[Called By]- >> TCP_Client_Recv
+
- >> tcp_recv_null
+
+
+tcp_connect (Thumb, 190 bytes, Stack size 32 bytes, tcp.o(i.tcp_connect))
+
[Stack]
- Max Depth = 300
- Call Chain = tcp_connect ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_enqueue
+
- >> tcp_next_iss
+
- >> tcp_eff_send_mss
+
- >> tcp_new_port
+
+
[Called By]
+
+tcp_eff_send_mss (Thumb, 32 bytes, Stack size 8 bytes, tcp.o(i.tcp_eff_send_mss))
+
[Stack]
- Max Depth = 24
- Call Chain = tcp_eff_send_mss ⇒ ip_route
+
+
[Calls]
+
[Called By]- >> tcp_connect
+
- >> tcp_process
+
- >> tcp_listen_input
+
+
+tcp_enqueue (Thumb, 752 bytes, Stack size 64 bytes, tcp_out.o(i.tcp_enqueue))
+
[Stack]
- Max Depth = 124
- Call Chain = tcp_enqueue ⇒ tcp_segs_free ⇒ tcp_seg_free ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> htonl
+
- >> pbuf_cat
+
- >> pbuf_header
+
- >> pbuf_clen
+
- >> ntohs
+
- >> htons
+
- >> memp_malloc
+
- >> memp_free
+
- >> tcp_segs_free
+
- >> pbuf_alloc
+
- >> __aeabi_memcpy
+
+
[Called By]- >> tcp_write
+
- >> tcp_connect
+
- >> tcp_listen_input
+
- >> tcp_send_ctrl
+
+
+tcp_fasttmr (Thumb, 84 bytes, Stack size 16 bytes, tcp.o(i.tcp_fasttmr))
+
[Stack]
- Max Depth = 284
- Call Chain = tcp_fasttmr ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> pbuf_free
+
+
[Called By]
+
+tcp_input (Thumb, 776 bytes, Stack size 40 bytes, tcp_in.o(i.tcp_input))
+
[Stack]
- Max Depth = 428
- Call Chain = tcp_input ⇒ tcp_process ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> pbuf_free
+
- >> pbuf_header
+
- >> ntohs
+
- >> ntohl
+
- >> ip_addr_isbroadcast
+
- >> tcp_process
+
- >> tcp_listen_input
+
- >> tcp_rst
+
- >> memp_free
+
- >> tcp_pcb_remove
+
+
[Called By]
+
+tcp_keepalive (Thumb, 70 bytes, Stack size 24 bytes, tcp_out.o(i.tcp_keepalive))
+
[Stack]
- Max Depth = 228
- Call Chain = tcp_keepalive ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> htonl
+
- >> ip_output
+
- >> tcp_output_set_header
+
- >> pbuf_alloc
+
+
[Called By]
+
+tcp_new (Thumb, 6 bytes, Stack size 0 bytes, tcp.o(i.tcp_new))
+
[Stack]
- Max Depth = 364
- Call Chain = tcp_new ⇒ tcp_alloc ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+tcp_next_iss (Thumb, 12 bytes, Stack size 0 bytes, tcp.o(i.tcp_next_iss))
+
[Called By]
- >> tcp_connect
+
- >> tcp_alloc
+
+
+tcp_output (Thumb, 532 bytes, Stack size 40 bytes, tcp_out.o(i.tcp_output))
+
[Stack]
- Max Depth = 268
- Call Chain = tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> htonl
+
- >> ip_output
+
- >> tcp_output_set_header
+
- >> tcp_output_segment
+
- >> ntohs
+
- >> ntohl
+
- >> htons
+
- >> tcp_seg_free
+
- >> pbuf_alloc
+
+
[Called By]- >> tcp_recved
+
- >> tcp_connect
+
- >> tcp_close
+
- >> TCP_Client_Send_Data
+
- >> tcp_rexmit
+
- >> tcp_input
+
- >> tcp_receive
+
- >> tcp_process
+
- >> tcp_listen_input
+
- >> tcp_rexmit_rto
+
- >> tcp_slowtmr
+
- >> tcp_pcb_remove
+
- >> tcp_fasttmr
+
+
+tcp_pcb_purge (Thumb, 48 bytes, Stack size 16 bytes, tcp.o(i.tcp_pcb_purge))
+
[Stack]
- Max Depth = 76
- Call Chain = tcp_pcb_purge ⇒ tcp_segs_free ⇒ tcp_seg_free ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> tcp_segs_free
+
+
[Called By]- >> tcp_process
+
- >> tcp_slowtmr
+
- >> tcp_pcb_remove
+
+
+tcp_pcb_remove (Thumb, 90 bytes, Stack size 16 bytes, tcp.o(i.tcp_pcb_remove))
+
[Stack]
- Max Depth = 284
- Call Chain = tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_pcb_purge
+
+
[Called By]- >> tcp_close
+
- >> tcp_input
+
- >> tcp_abandon
+
+
+tcp_recv (Thumb, 6 bytes, Stack size 0 bytes, tcp.o(i.tcp_recv))
+
[Called By]
+
+tcp_recved (Thumb, 60 bytes, Stack size 8 bytes, tcp.o(i.tcp_recved))
+
[Stack]
- Max Depth = 276
- Call Chain = tcp_recved ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_update_rcv_ann_wnd
+
+
[Called By]
+
+tcp_rexmit (Thumb, 84 bytes, Stack size 24 bytes, tcp_out.o(i.tcp_rexmit))
+
[Stack]
- Max Depth = 292
- Call Chain = tcp_rexmit ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> ntohl
+
+
[Called By]- >> tcp_receive
+
- >> tcp_process
+
+
+tcp_rexmit_rto (Thumb, 46 bytes, Stack size 0 bytes, tcp_out.o(i.tcp_rexmit_rto))
+
[Stack]
- Max Depth = 268
- Call Chain = tcp_rexmit_rto ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+tcp_rst (Thumb, 152 bytes, Stack size 48 bytes, tcp_out.o(i.tcp_rst))
+
[Stack]
- Max Depth = 252
- Call Chain = tcp_rst ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> htonl
+
- >> ip_output
+
- >> ntohs
+
- >> htons
+
- >> pbuf_alloc
+
+
[Called By]- >> tcp_input
+
- >> tcp_process
+
- >> tcp_listen_input
+
- >> tcp_abandon
+
+
+tcp_seg_free (Thumb, 32 bytes, Stack size 16 bytes, tcp.o(i.tcp_seg_free))
+
[Stack]
- Max Depth = 44
- Call Chain = tcp_seg_free ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> memp_free
+
+
[Called By]- >> tcp_output
+
- >> tcp_receive
+
- >> tcp_process
+
- >> tcp_segs_free
+
+
+tcp_segs_free (Thumb, 26 bytes, Stack size 16 bytes, tcp.o(i.tcp_segs_free))
+
[Stack]
- Max Depth = 60
- Call Chain = tcp_segs_free ⇒ tcp_seg_free ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> tcp_enqueue
+
- >> tcp_pcb_purge
+
- >> tcp_abandon
+
+
+tcp_send_ctrl (Thumb, 22 bytes, Stack size 16 bytes, tcp_out.o(i.tcp_send_ctrl))
+
[Stack]
- Max Depth = 140
- Call Chain = tcp_send_ctrl ⇒ tcp_enqueue ⇒ tcp_segs_free ⇒ tcp_seg_free ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]
+
+tcp_slowtmr (Thumb, 512 bytes, Stack size 32 bytes, tcp.o(i.tcp_slowtmr))
+
[Stack]
- Max Depth = 372
- Call Chain = tcp_slowtmr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_zero_window_probe
+
- >> tcp_rexmit_rto
+
- >> tcp_keepalive
+
- >> memp_free
+
- >> tcp_pcb_purge
+
- >> tcp_abandon
+
+
[Called By]
+
+tcp_tmr (Thumb, 28 bytes, Stack size 8 bytes, tcp.o(i.tcp_tmr))
+
[Stack]
- Max Depth = 380
- Call Chain = tcp_tmr ⇒ tcp_slowtmr ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_slowtmr
+
- >> tcp_fasttmr
+
+
[Called By]- >> LwIP_Periodic_Handle
+
+
+tcp_update_rcv_ann_wnd (Thumb, 42 bytes, Stack size 12 bytes, tcp.o(i.tcp_update_rcv_ann_wnd))
+
[Stack]
- Max Depth = 12
- Call Chain = tcp_update_rcv_ann_wnd
+
+
[Called By]- >> tcp_recved
+
- >> tcp_receive
+
+
+tcp_write (Thumb, 46 bytes, Stack size 16 bytes, tcp_out.o(i.tcp_write))
+
[Stack]
- Max Depth = 140
- Call Chain = tcp_write ⇒ tcp_enqueue ⇒ tcp_segs_free ⇒ tcp_seg_free ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> TCP_Client_Send_Data
+
+
+tcp_zero_window_probe (Thumb, 82 bytes, Stack size 24 bytes, tcp_out.o(i.tcp_zero_window_probe))
+
[Stack]
- Max Depth = 228
- Call Chain = tcp_zero_window_probe ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> ip_output
+
- >> tcp_output_set_header
+
- >> pbuf_alloc
+
+
[Called By]
+
+udp_input (Thumb, 312 bytes, Stack size 48 bytes, udp.o(i.udp_input))
+
[Stack]
- Max Depth = 292
- Call Chain = udp_input ⇒ icmp_dest_unreach ⇒ icmp_send_response ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> icmp_dest_unreach
+
- >> pbuf_header
+
- >> ntohs
+
- >> ntohl
+
- >> ip_addr_isbroadcast
+
+
[Called By]
+
+_get_lc_numeric (Thumb, 44 bytes, Stack size 8 bytes, lc_numeric_c.o(locale$$code))
+
[Stack]
- Max Depth = 8
- Call Chain = _get_lc_numeric
+
+
[Calls]
+
[Called By]- >> __rt_lib_init_lc_numeric_2
+
+
+_get_lc_ctype (Thumb, 44 bytes, Stack size 8 bytes, lc_ctype_c.o(locale$$code))
+
[Stack]
- Max Depth = 8
- Call Chain = _get_lc_ctype
+
+
[Calls]
+
[Called By]- >> __rt_lib_init_lc_ctype_2
+
+
[Address Reference Count : 1]- rt_ctype_table.o(.text)
+
+_printf_fp_dec (Thumb, 4 bytes, Stack size 0 bytes, printf1.o(x$fpl$printf1))
+
[Stack]
- Max Depth = 324
- Call Chain = _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
+
+
[Calls]
+
[Called By]- >> _printf_g
+
- >> _printf_e
+
- >> _printf_f
+
+
+
+Local Symbols
+
+NVIC_SetPriority (Thumb, 32 bytes, Stack size 0 bytes, stm32f107.o(i.NVIC_SetPriority))
+
[Called By]
+
+ETH_Delay (Thumb, 18 bytes, Stack size 12 bytes, stm32_eth.o(i.ETH_Delay))
+
[Stack]
- Max Depth = 12
- Call Chain = ETH_Delay
+
+
[Called By]
+
+low_level_init (Thumb, 124 bytes, Stack size 16 bytes, ethernetif.o(i.low_level_init))
+
[Stack]
- Max Depth = 36
- Call Chain = low_level_init ⇒ ETH_DMATxDescChainInit
+
+
[Calls]- >> ETH_Start
+
- >> ETH_DMATxDescChecksumInsertionConfig
+
- >> ETH_DMATxDescChainInit
+
- >> ETH_DMARxDescReceiveITConfig
+
- >> ETH_DMARxDescChainInit
+
+
[Called By]
+
+low_level_output (Thumb, 44 bytes, Stack size 16 bytes, ethernetif.o(i.low_level_output))
+
[Stack]
- Max Depth = 16
- Call Chain = low_level_output
+
+
[Calls]- >> ETH_TxPkt_ChainMode
+
- >> ETH_GetCurrentTxBuffer
+
- >> __aeabi_memcpy
+
+
[Address Reference Count : 1]- ethernetif.o(i.ethernetif_init)
+
+tcp_new_port (Thumb, 92 bytes, Stack size 20 bytes, tcp.o(i.tcp_new_port))
+
[Stack]
- Max Depth = 20
- Call Chain = tcp_new_port
+
+
[Called By]- >> tcp_connect
+
- >> tcp_bind
+
+
+tcp_recv_null (Thumb, 28 bytes, Stack size 8 bytes, tcp.o(i.tcp_recv_null))
+
[Stack]
- Max Depth = 308
- Call Chain = tcp_recv_null ⇒ tcp_close ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_close
+
- >> pbuf_free
+
+
[Address Reference Count : 1]
+tcp_listen_input (Thumb, 222 bytes, Stack size 24 bytes, tcp_in.o(i.tcp_listen_input))
+
[Stack]
- Max Depth = 388
- Call Chain = tcp_listen_input ⇒ tcp_alloc ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_parseopt
+
- >> tcp_rst
+
- >> tcp_enqueue
+
- >> tcp_eff_send_mss
+
- >> tcp_alloc
+
- >> tcp_abandon
+
+
[Called By]
+
+tcp_parseopt (Thumb, 124 bytes, Stack size 16 bytes, tcp_in.o(i.tcp_parseopt))
+
[Stack]
- Max Depth = 16
- Call Chain = tcp_parseopt
+
+
[Calls]
+
[Called By]- >> tcp_process
+
- >> tcp_listen_input
+
+
+tcp_process (Thumb, 814 bytes, Stack size 48 bytes, tcp_in.o(i.tcp_process))
+
[Stack]
- Max Depth = 388
- Call Chain = tcp_process ⇒ tcp_abandon ⇒ tcp_pcb_remove ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_rexmit
+
- >> ntohl
+
- >> tcp_receive
+
- >> tcp_parseopt
+
- >> tcp_rst
+
- >> tcp_seg_free
+
- >> tcp_pcb_purge
+
- >> tcp_eff_send_mss
+
- >> tcp_abandon
+
+
[Called By]
+
+tcp_receive (Thumb, 1130 bytes, Stack size 32 bytes, tcp_in.o(i.tcp_receive))
+
[Stack]
- Max Depth = 324
- Call Chain = tcp_receive ⇒ tcp_rexmit ⇒ tcp_output ⇒ tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> tcp_output
+
- >> tcp_rexmit
+
- >> pbuf_realloc
+
- >> pbuf_header
+
- >> pbuf_clen
+
- >> ntohs
+
- >> ntohl
+
- >> htons
+
- >> tcp_update_rcv_ann_wnd
+
- >> tcp_seg_free
+
+
[Called By]
+
+tcp_output_segment (Thumb, 168 bytes, Stack size 24 bytes, tcp_out.o(i.tcp_output_segment))
+
[Stack]
- Max Depth = 228
- Call Chain = tcp_output_segment ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> htonl
+
- >> ip_output
+
- >> ntohl
+
- >> htons
+
- >> ip_route
+
+
[Called By]
+
+tcp_output_set_header (Thumb, 120 bytes, Stack size 24 bytes, tcp_out.o(i.tcp_output_set_header))
+
[Stack]
- Max Depth = 24
- Call Chain = tcp_output_set_header
+
+
[Calls]- >> htonl
+
- >> ntohs
+
- >> htons
+
+
[Called By]- >> tcp_output
+
- >> tcp_zero_window_probe
+
- >> tcp_keepalive
+
+
+plug_holes (Thumb, 78 bytes, Stack size 12 bytes, mem.o(i.plug_holes))
+
[Stack]
- Max Depth = 12
- Call Chain = plug_holes
+
+
[Called By]
+
+icmp_send_response (Thumb, 102 bytes, Stack size 40 bytes, icmp.o(i.icmp_send_response))
+
[Stack]
- Max Depth = 244
- Call Chain = icmp_send_response ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> inet_chksum
+
- >> ip_output
+
- >> pbuf_alloc
+
- >> __aeabi_memcpy
+
+
[Called By]- >> icmp_time_exceeded
+
- >> icmp_dest_unreach
+
+
+lwip_standard_chksum (Thumb, 60 bytes, Stack size 8 bytes, inet_chksum.o(i.lwip_standard_chksum))
+
[Stack]
- Max Depth = 8
- Call Chain = lwip_standard_chksum
+
+
[Calls]
+
[Called By]- >> inet_chksum_pbuf
+
- >> inet_chksum
+
+
+ip_reass_chain_frag_into_datagram_and_validate (Thumb, 234 bytes, Stack size 32 bytes, ip_frag.o(i.ip_reass_chain_frag_into_datagram_and_validate))
+
[Stack]
- Max Depth = 60
- Call Chain = ip_reass_chain_frag_into_datagram_and_validate ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> pbuf_clen
+
- >> ntohs
+
+
[Called By]
+
+ip_reass_dequeue_datagram (Thumb, 30 bytes, Stack size 8 bytes, ip_frag.o(i.ip_reass_dequeue_datagram))
+
[Stack]
- Max Depth = 8
- Call Chain = ip_reass_dequeue_datagram
+
+
[Calls]
+
[Called By]- >> ip_reass_free_complete_datagram
+
- >> ip_reass
+
+
+ip_reass_free_complete_datagram (Thumb, 106 bytes, Stack size 24 bytes, ip_frag.o(i.ip_reass_free_complete_datagram))
+
[Stack]
- Max Depth = 268
- Call Chain = ip_reass_free_complete_datagram ⇒ icmp_time_exceeded ⇒ icmp_send_response ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> ip_reass_dequeue_datagram
+
- >> icmp_time_exceeded
+
- >> pbuf_clen
+
- >> __aeabi_memcpy
+
+
[Called By]- >> ip_reass_remove_oldest_datagram
+
+
+ip_reass_remove_oldest_datagram (Thumb, 110 bytes, Stack size 24 bytes, ip_frag.o(i.ip_reass_remove_oldest_datagram))
+
[Stack]
- Max Depth = 292
- Call Chain = ip_reass_remove_oldest_datagram ⇒ ip_reass_free_complete_datagram ⇒ icmp_time_exceeded ⇒ icmp_send_response ⇒ ip_output ⇒ ip_output_if ⇒ ip_frag ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> ip_reass_free_complete_datagram
+
+
[Called By]
+
+etharp_raw (Thumb, 158 bytes, Stack size 40 bytes, etharp.o(i.etharp_raw))
+
[Stack]
- Max Depth = 100
- Call Chain = etharp_raw ⇒ pbuf_alloc ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> htons
+
- >> pbuf_alloc
+
+
[Called By]
+
+etharp_send_ip (Thumb, 54 bytes, Stack size 24 bytes, etharp.o(i.etharp_send_ip))
+
[Stack]
- Max Depth = 24
- Call Chain = etharp_send_ip
+
+
[Calls]
+
[Called By]- >> etharp_output
+
- >> etharp_query
+
- >> update_arp_entry
+
+
+find_entry (Thumb, 308 bytes, Stack size 48 bytes, etharp.o(i.find_entry))
+
[Stack]
- Max Depth = 92
- Call Chain = find_entry ⇒ free_etharp_q ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]
+
[Called By]- >> etharp_query
+
- >> update_arp_entry
+
+
+free_etharp_q (Thumb, 30 bytes, Stack size 16 bytes, etharp.o(i.free_etharp_q))
+
[Stack]
- Max Depth = 44
- Call Chain = free_etharp_q ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> memp_free
+
+
[Called By]- >> etharp_tmr
+
- >> find_entry
+
+
+update_arp_entry (Thumb, 162 bytes, Stack size 32 bytes, etharp.o(i.update_arp_entry))
+
[Stack]
- Max Depth = 124
- Call Chain = update_arp_entry ⇒ find_entry ⇒ free_etharp_q ⇒ pbuf_free ⇒ mem_free ⇒ plug_holes
+
+
[Calls]- >> pbuf_free
+
- >> ntohl
+
- >> ip_addr_isbroadcast
+
- >> memp_free
+
- >> find_entry
+
- >> etharp_send_ip
+
+
[Called By]- >> etharp_ip_input
+
- >> etharp_arp_input
+
+
+SetSysClockTo72 (Thumb, 190 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72))
+
[Stack]
- Max Depth = 12
- Call Chain = SetSysClockTo72
+
+
[Called By]
+
+_printf_input_char (Thumb, 10 bytes, Stack size 0 bytes, _printf_char_common.o(.text))
+
[Address Reference Count : 1]
- _printf_char_common.o(.text)
+
+_fp_digits (Thumb, 432 bytes, Stack size 96 bytes, _printf_fp_dec.o(.text))
+
[Stack]
- Max Depth = 220
- Call Chain = _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e
+
+
[Calls]- >> _btod_emul
+
- >> _btod_ediv
+
- >> _btod_d2e
+
- >> _btod_etento
+
- >> _ll_udiv10
+
+
[Called By]
+
+
+Undefined Global Symbols
+
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.lnp b/F107/Project/RVMDK/Obj/STM3210C-EVAL.lnp
new file mode 100644
index 0000000..e23c34d
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL.lnp
@@ -0,0 +1,60 @@
+--cpu Cortex-M3
+".\obj\stm32f10x_it.o"
+".\obj\main.o"
+".\obj\stm32f107.o"
+".\obj\netconf.o"
+".\obj\tcp_client.o"
+".\obj\hx711.o"
+".\obj\sys.o"
+".\obj\sci.o"
+".\obj\stm32f10x_usart.o"
+".\obj\stm32f10x_gpio.o"
+".\obj\stm32f10x_rcc.o"
+".\obj\stm32f10x_spi.o"
+".\obj\stm32f10x_exti.o"
+".\obj\stm32f10x_flash.o"
+".\obj\misc.o"
+".\obj\stm32f10x_adc.o"
+".\obj\stm32f10x_tim.o"
+".\obj\stm32f10x_i2c.o"
+".\obj\stm32_eth.o"
+".\obj\ethernetif.o"
+".\obj\tcpip.o"
+".\obj\api_lib.o"
+".\obj\netbuf.o"
+".\obj\netifapi.o"
+".\obj\netdb.o"
+".\obj\api_msg.o"
+".\obj\err.o"
+".\obj\stats.o"
+".\obj\sys_1.o"
+".\obj\tcp.o"
+".\obj\tcp_in.o"
+".\obj\tcp_out.o"
+".\obj\udp.o"
+".\obj\dhcp.o"
+".\obj\init.o"
+".\obj\mem.o"
+".\obj\memp.o"
+".\obj\netif.o"
+".\obj\pbuf.o"
+".\obj\raw.o"
+".\obj\autoip.o"
+".\obj\icmp.o"
+".\obj\igmp.o"
+".\obj\inet.o"
+".\obj\inet_chksum.o"
+".\obj\ip.o"
+".\obj\ip_addr.o"
+".\obj\ip_frag.o"
+".\obj\etharp.o"
+".\obj\system_stm32f10x.o"
+".\obj\core_cm3.o"
+".\obj\startup_stm32f10x_cl.o"
+".\obj\led.o"
+".\obj\delay.o"
+".\obj\usart.o"
+--strict --scatter ".\Obj\STM3210C-EVAL.sct"
+--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+--list ".\List\STM3210C-EVAL.map" -o .\Obj\STM3210C-EVAL.axf
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.plg b/F107/Project/RVMDK/Obj/STM3210C-EVAL.plg
new file mode 100644
index 0000000..e8133b6
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL.plg
@@ -0,0 +1,52 @@
+
+
+
+礦ision Build Log
+Project:
+E:\老贾办公\板子工程文件\STM32F107VCT6板子\基于自主设计的107程序\高级例程-以太网-TCP客户端收发数据\Project\RVMDK\Project.uvproj
+Project File Date: 12/22/2016
+
+Output:
+Load "E:\\老贾办公\\板子工程文件\\STM32F107VCT6板子\\基于自主设计的107程序\\高级例程-以太网-TCP客户端收发数据\\Project\\RVMDK\\Obj\\STM3210C-EVAL.AXF"
+* JLink Info: Device "STM32F107VC" selected (256 KB flash, 20 KB RAM).
+Set JLink Project File to "E:\老贾办公\板子工程文件\STM32F107VCT6板子\基于自主设计的107程序\高级例程-以太网-TCP客户端收发数据\Project\RVMDK\JLinkSettings.ini"
+
+JLink info:
+------------
+DLL: V4.50j, compiled Jun 26 2012 09:19:07
+Firmware: J-Link ARM V8 compiled Nov 14 2012 22:34:52
+Hardware: V8.00
+S/N : 17935099
+Feature(s) : RDI,FlashDL,FlashBP,JFlash
+
+* JLink Info: TotalIRLen = 9, IRPrint = 0x0011
+* JLink Info: TotalIRLen = 9, IRPrint = 0x0011
+* JLink Info: Found Cortex-M3 r1p1, Little endian.
+* JLink Info: TPIU fitted.
+* JLink Info: ETM fitted.
+* JLink Info: FPUnit: 6 code (BP) slots and 2 literal slots
+ROMTableAddr = 0xE00FF003
+* JLink Info: Found Cortex-M3 r1p1, Little endian.
+* JLink Info: TPIU fitted.
+* JLink Info: ETM fitted.
+* JLink Info: FPUnit: 6 code (BP) slots and 2 literal slots
+
+Target info:
+------------
+Device: STM32F107VC
+VTarget = 3.332V
+State of Pins:
+TCK: 1, TDI: 0, TDO: 1, TMS: 0, TRES: 1, TRST: 1
+Hardware-Breakpoints: 6
+Software-Breakpoints: 8192
+Watchpoints: 4
+JTAG speed: 2000 kHz
+
+Erase Done.
+Programming Done.
+Verify OK.
+* JLink Info: Found Cortex-M3 r1p1, Little endian.
+* JLink Info: TPIU fitted.
+* JLink Info: ETM fitted.
+* JLink Info: FPUnit: 6 code (BP) slots and 2 literal slots
+Application running ...
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.sct b/F107/Project/RVMDK/Obj/STM3210C-EVAL.sct
new file mode 100644
index 0000000..a8c9a15
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000 { ; load region size_region
+ ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL.tra b/F107/Project/RVMDK/Obj/STM3210C-EVAL.tra
new file mode 100644
index 0000000..2c24e15
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL.tra
@@ -0,0 +1,68 @@
+*** Creating Trace Output File '.\Obj\STM3210C-EVAL.tra' Ok.
+### Preparing for ADS-LD.
+### Creating ADS-LD Command Line
+### List of Objects: adding '".\obj\stm32f10x_it.o"'
+### List of Objects: adding '".\obj\main.o"'
+### List of Objects: adding '".\obj\stm32f107.o"'
+### List of Objects: adding '".\obj\netconf.o"'
+### List of Objects: adding '".\obj\sci.o"'
+### List of Objects: adding '".\obj\tcp_client.o"'
+### List of Objects: adding '".\obj\stm32f10x_usart.o"'
+### List of Objects: adding '".\obj\stm32f10x_gpio.o"'
+### List of Objects: adding '".\obj\stm32f10x_rcc.o"'
+### List of Objects: adding '".\obj\stm32f10x_spi.o"'
+### List of Objects: adding '".\obj\stm32f10x_exti.o"'
+### List of Objects: adding '".\obj\stm32f10x_flash.o"'
+### List of Objects: adding '".\obj\misc.o"'
+### List of Objects: adding '".\obj\stm32f10x_adc.o"'
+### List of Objects: adding '".\obj\stm32f10x_tim.o"'
+### List of Objects: adding '".\obj\stm32f10x_i2c.o"'
+### List of Objects: adding '".\obj\stm32_eth.o"'
+### List of Objects: adding '".\obj\ethernetif.o"'
+### List of Objects: adding '".\obj\tcpip.o"'
+### List of Objects: adding '".\obj\api_lib.o"'
+### List of Objects: adding '".\obj\netbuf.o"'
+### List of Objects: adding '".\obj\netifapi.o"'
+### List of Objects: adding '".\obj\netdb.o"'
+### List of Objects: adding '".\obj\api_msg.o"'
+### List of Objects: adding '".\obj\err.o"'
+### List of Objects: adding '".\obj\stats.o"'
+### List of Objects: adding '".\obj\sys.o"'
+### List of Objects: adding '".\obj\tcp.o"'
+### List of Objects: adding '".\obj\tcp_in.o"'
+### List of Objects: adding '".\obj\tcp_out.o"'
+### List of Objects: adding '".\obj\udp.o"'
+### List of Objects: adding '".\obj\dhcp.o"'
+### List of Objects: adding '".\obj\init.o"'
+### List of Objects: adding '".\obj\mem.o"'
+### List of Objects: adding '".\obj\memp.o"'
+### List of Objects: adding '".\obj\netif.o"'
+### List of Objects: adding '".\obj\pbuf.o"'
+### List of Objects: adding '".\obj\raw.o"'
+### List of Objects: adding '".\obj\autoip.o"'
+### List of Objects: adding '".\obj\icmp.o"'
+### List of Objects: adding '".\obj\igmp.o"'
+### List of Objects: adding '".\obj\inet.o"'
+### List of Objects: adding '".\obj\inet_chksum.o"'
+### List of Objects: adding '".\obj\ip.o"'
+### List of Objects: adding '".\obj\ip_addr.o"'
+### List of Objects: adding '".\obj\ip_frag.o"'
+### List of Objects: adding '".\obj\etharp.o"'
+### List of Objects: adding '".\obj\system_stm32f10x.o"'
+### List of Objects: adding '".\obj\core_cm3.o"'
+### List of Objects: adding '".\obj\startup_stm32f10x_cl.o"'
+### ADS-LD Command completed:
+--cpu Cortex-M3 ".\obj\stm32f10x_it.o" ".\obj\main.o" ".\obj\stm32f107.o" ".\obj\netconf.o" ".\obj\sci.o" ".\obj\tcp_client.o" ".\obj\stm32f10x_usart.o" ".\obj\stm32f10x_gpio.o" ".\obj\stm32f10x_rcc.o" ".\obj\stm32f10x_spi.o" ".\obj\stm32f10x_exti.o" ".\obj\stm32f10x_flash.o" ".\obj\misc.o" ".\obj\stm32f10x_adc.o" ".\obj\stm32f10x_tim.o" ".\obj\stm32f10x_i2c.o" ".\obj\stm32_eth.o" ".\obj\ethernetif.o" ".\obj\tcpip.o" ".\obj\api_lib.o" ".\obj\netbuf.o" ".\obj\netifapi.o" ".\obj\netdb.o" ".\obj\api_msg.o" ".\obj\err.o" ".\obj\stats.o" ".\obj\sys.o" ".\obj\tcp.o" ".\obj\tcp_in.o" ".\obj\tcp_out.o" ".\obj\udp.o" ".\obj\dhcp.o" ".\obj\init.o" ".\obj\mem.o" ".\obj\memp.o" ".\obj\netif.o" ".\obj\pbuf.o" ".\obj\raw.o" ".\obj\autoip.o" ".\obj\icmp.o" ".\obj\igmp.o" ".\obj\inet.o" ".\obj\inet_chksum.o" ".\obj\ip.o" ".\obj\ip_addr.o" ".\obj\ip_frag.o" ".\obj\etharp.o" ".\obj\system_stm32f10x.o" ".\obj\core_cm3.o" ".\obj\startup_stm32f10x_cl.o" --strict --scatter ".\Obj\STM3210C-EVAL.sct"
+--summary_stderr --info summarysizes --map --xref --callgraph --symbols
+--info sizes --info totals --info unused --info veneers
+ --list ".\List\STM3210C-EVAL.map" -o .\Obj\STM3210C-EVAL.axf### Preparing Environment (PrepEnvAds)
+### ADS-LD Output File: '.\Obj\STM3210C-EVAL.axf'
+### ADS-LD Command File: '.\Obj\STM3210C-EVAL.lnp'
+### Checking for dirty Components...
+### Creating CmdFile '.\Obj\STM3210C-EVAL.lnp', Handle=0x0000021C
+### Writing '.lnp' file
+### ADS-LD Command file '.\Obj\STM3210C-EVAL.lnp' is ready.
+### ADS-LD: About to start ADS-LD Thread.
+### ADS-LD: executed with 0 errors
+### Updating obj list
+### LDADS_file() completed.
diff --git a/F107/Project/RVMDK/Obj/STM3210C-EVAL_sct.Bak b/F107/Project/RVMDK/Obj/STM3210C-EVAL_sct.Bak
new file mode 100644
index 0000000..4d47c26
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/STM3210C-EVAL_sct.Bak
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08004800 0x0007C000 { ; load region size_region
+ ER_IROM1 0x08004800 0x0007C000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ RW_IRAM1 0x20000000 0x00010000 { ; RW data
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/F107/Project/RVMDK/Obj/api_lib.crf b/F107/Project/RVMDK/Obj/api_lib.crf
new file mode 100644
index 0000000..86be06a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/api_lib.crf differ
diff --git a/F107/Project/RVMDK/Obj/api_lib.d b/F107/Project/RVMDK/Obj/api_lib.d
new file mode 100644
index 0000000..670c024
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/api_lib.d
@@ -0,0 +1,7 @@
+.\obj\api_lib.o: ..\..\Utilities\lwip-1.3.1\src\api\api_lib.c
+.\obj\api_lib.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\api_lib.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\api_lib.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\api_lib.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\api_lib.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\api_lib.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/api_lib.o b/F107/Project/RVMDK/Obj/api_lib.o
new file mode 100644
index 0000000..6a60ee4
Binary files /dev/null and b/F107/Project/RVMDK/Obj/api_lib.o differ
diff --git a/F107/Project/RVMDK/Obj/api_msg.crf b/F107/Project/RVMDK/Obj/api_msg.crf
new file mode 100644
index 0000000..1057a8e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/api_msg.crf differ
diff --git a/F107/Project/RVMDK/Obj/api_msg.d b/F107/Project/RVMDK/Obj/api_msg.d
new file mode 100644
index 0000000..e177613
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/api_msg.d
@@ -0,0 +1,7 @@
+.\obj\api_msg.o: ..\..\Utilities\lwip-1.3.1\src\api\api_msg.c
+.\obj\api_msg.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\api_msg.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\api_msg.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\api_msg.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\api_msg.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\api_msg.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/api_msg.o b/F107/Project/RVMDK/Obj/api_msg.o
new file mode 100644
index 0000000..946b270
Binary files /dev/null and b/F107/Project/RVMDK/Obj/api_msg.o differ
diff --git a/F107/Project/RVMDK/Obj/autoip.crf b/F107/Project/RVMDK/Obj/autoip.crf
new file mode 100644
index 0000000..4b7b3ac
Binary files /dev/null and b/F107/Project/RVMDK/Obj/autoip.crf differ
diff --git a/F107/Project/RVMDK/Obj/autoip.d b/F107/Project/RVMDK/Obj/autoip.d
new file mode 100644
index 0000000..b00623f
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/autoip.d
@@ -0,0 +1,7 @@
+.\obj\autoip.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\autoip.c
+.\obj\autoip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\autoip.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\autoip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\autoip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\autoip.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\autoip.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/autoip.o b/F107/Project/RVMDK/Obj/autoip.o
new file mode 100644
index 0000000..a0c3a36
Binary files /dev/null and b/F107/Project/RVMDK/Obj/autoip.o differ
diff --git a/F107/Project/RVMDK/Obj/client.__i b/F107/Project/RVMDK/Obj/client.__i
new file mode 100644
index 0000000..9e081a1
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/client.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\client.o" --omf_browse ".\Obj\client.crf" --depend ".\Obj\client.d" "..\..\Utilities\lwip-1.3.1\port\client.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/client.crf b/F107/Project/RVMDK/Obj/client.crf
new file mode 100644
index 0000000..b358fb9
Binary files /dev/null and b/F107/Project/RVMDK/Obj/client.crf differ
diff --git a/F107/Project/RVMDK/Obj/client.d b/F107/Project/RVMDK/Obj/client.d
new file mode 100644
index 0000000..272da2e
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/client.d
@@ -0,0 +1,43 @@
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\port\client.c
+.\Obj\client.o: ..\inc\main.h
+.\Obj\client.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\client.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\client.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\client.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\client.o: ..\inc\stm32f10x_conf.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\client.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\client.o: ..\inc\stm32f107.h
+.\Obj\client.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\Obj\client.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\Obj\client.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\Obj\client.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\Obj\client.o: G:\keil\ARM\RV31\INC\string.h
+.\Obj\client.o: G:\keil\ARM\RV31\INC\stdio.h
diff --git a/F107/Project/RVMDK/Obj/client.o b/F107/Project/RVMDK/Obj/client.o
new file mode 100644
index 0000000..56a5f91
Binary files /dev/null and b/F107/Project/RVMDK/Obj/client.o differ
diff --git a/F107/Project/RVMDK/Obj/core_cm3.crf b/F107/Project/RVMDK/Obj/core_cm3.crf
new file mode 100644
index 0000000..01b7efa
Binary files /dev/null and b/F107/Project/RVMDK/Obj/core_cm3.crf differ
diff --git a/F107/Project/RVMDK/Obj/core_cm3.d b/F107/Project/RVMDK/Obj/core_cm3.d
new file mode 100644
index 0000000..665cd16
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/core_cm3.d
@@ -0,0 +1,2 @@
+.\obj\core_cm3.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.c
+.\obj\core_cm3.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
diff --git a/F107/Project/RVMDK/Obj/core_cm3.o b/F107/Project/RVMDK/Obj/core_cm3.o
new file mode 100644
index 0000000..61061f3
Binary files /dev/null and b/F107/Project/RVMDK/Obj/core_cm3.o differ
diff --git a/F107/Project/RVMDK/Obj/delay.crf b/F107/Project/RVMDK/Obj/delay.crf
new file mode 100644
index 0000000..309a6e1
Binary files /dev/null and b/F107/Project/RVMDK/Obj/delay.crf differ
diff --git a/F107/Project/RVMDK/Obj/delay.d b/F107/Project/RVMDK/Obj/delay.d
new file mode 100644
index 0000000..c766685
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/delay.d
@@ -0,0 +1,18 @@
+.\obj\delay.o: ..\..\Basic\delay\delay.c
+.\obj\delay.o: ..\..\Basic\delay\delay.h
+.\obj\delay.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\delay.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\delay.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\delay.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\delay.o: ..\inc\stm32f10x_conf.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\delay.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\delay.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/delay.o b/F107/Project/RVMDK/Obj/delay.o
new file mode 100644
index 0000000..744ab9e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/delay.o differ
diff --git a/F107/Project/RVMDK/Obj/dhcp.crf b/F107/Project/RVMDK/Obj/dhcp.crf
new file mode 100644
index 0000000..7bf6d34
Binary files /dev/null and b/F107/Project/RVMDK/Obj/dhcp.crf differ
diff --git a/F107/Project/RVMDK/Obj/dhcp.d b/F107/Project/RVMDK/Obj/dhcp.d
new file mode 100644
index 0000000..90bc8bb
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/dhcp.d
@@ -0,0 +1,7 @@
+.\obj\dhcp.o: ..\..\Utilities\lwip-1.3.1\src\core\dhcp.c
+.\obj\dhcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\dhcp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\dhcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\dhcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\dhcp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\dhcp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/dhcp.o b/F107/Project/RVMDK/Obj/dhcp.o
new file mode 100644
index 0000000..c5c456e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/dhcp.o differ
diff --git a/F107/Project/RVMDK/Obj/dir.crf b/F107/Project/RVMDK/Obj/dir.crf
new file mode 100644
index 0000000..96d6759
Binary files /dev/null and b/F107/Project/RVMDK/Obj/dir.crf differ
diff --git a/F107/Project/RVMDK/Obj/dir.d b/F107/Project/RVMDK/Obj/dir.d
new file mode 100644
index 0000000..c5d0f21
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/dir.d
@@ -0,0 +1,33 @@
+.\Obj\dir.o: ..\..\Utilities\efsl\source\dir.c
+.\Obj\dir.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\dir.o: ..\..\Utilities\efsl\include\fat.h
diff --git a/F107/Project/RVMDK/Obj/dir.o b/F107/Project/RVMDK/Obj/dir.o
new file mode 100644
index 0000000..364377f
Binary files /dev/null and b/F107/Project/RVMDK/Obj/dir.o differ
diff --git a/F107/Project/RVMDK/Obj/disc.crf b/F107/Project/RVMDK/Obj/disc.crf
new file mode 100644
index 0000000..1653609
Binary files /dev/null and b/F107/Project/RVMDK/Obj/disc.crf differ
diff --git a/F107/Project/RVMDK/Obj/disc.d b/F107/Project/RVMDK/Obj/disc.d
new file mode 100644
index 0000000..5654c23
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/disc.d
@@ -0,0 +1,20 @@
+.\Obj\disc.o: ..\..\Utilities\efsl\source\disc.c
+.\Obj\disc.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\disc.o: ..\..\Utilities\efsl\include\disc.h
diff --git a/F107/Project/RVMDK/Obj/disc.o b/F107/Project/RVMDK/Obj/disc.o
new file mode 100644
index 0000000..ae151d3
Binary files /dev/null and b/F107/Project/RVMDK/Obj/disc.o differ
diff --git a/F107/Project/RVMDK/Obj/efs.crf b/F107/Project/RVMDK/Obj/efs.crf
new file mode 100644
index 0000000..a530f05
Binary files /dev/null and b/F107/Project/RVMDK/Obj/efs.crf differ
diff --git a/F107/Project/RVMDK/Obj/efs.d b/F107/Project/RVMDK/Obj/efs.d
new file mode 100644
index 0000000..a0d2df2
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/efs.d
@@ -0,0 +1,36 @@
+.\Obj\efs.o: ..\..\Utilities\efsl\source\efs.c
+.\Obj\efs.o: ..\..\Utilities\efsl\include\efs.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\ui.h
+.\Obj\efs.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/efs.o b/F107/Project/RVMDK/Obj/efs.o
new file mode 100644
index 0000000..2788821
Binary files /dev/null and b/F107/Project/RVMDK/Obj/efs.o differ
diff --git a/F107/Project/RVMDK/Obj/err.crf b/F107/Project/RVMDK/Obj/err.crf
new file mode 100644
index 0000000..992ee1a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/err.crf differ
diff --git a/F107/Project/RVMDK/Obj/err.d b/F107/Project/RVMDK/Obj/err.d
new file mode 100644
index 0000000..0688a69
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/err.d
@@ -0,0 +1,8 @@
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\src\api\err.c
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\err.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/err.o b/F107/Project/RVMDK/Obj/err.o
new file mode 100644
index 0000000..d14b664
Binary files /dev/null and b/F107/Project/RVMDK/Obj/err.o differ
diff --git a/F107/Project/RVMDK/Obj/etharp.crf b/F107/Project/RVMDK/Obj/etharp.crf
new file mode 100644
index 0000000..00e38fb
Binary files /dev/null and b/F107/Project/RVMDK/Obj/etharp.crf differ
diff --git a/F107/Project/RVMDK/Obj/etharp.d b/F107/Project/RVMDK/Obj/etharp.d
new file mode 100644
index 0000000..f4b33a1
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/etharp.d
@@ -0,0 +1,24 @@
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\netif\etharp.c
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/dhcp.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/autoip.h
+.\obj\etharp.o: ..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h
+.\obj\etharp.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/etharp.o b/F107/Project/RVMDK/Obj/etharp.o
new file mode 100644
index 0000000..25c95e6
Binary files /dev/null and b/F107/Project/RVMDK/Obj/etharp.o differ
diff --git a/F107/Project/RVMDK/Obj/ethernetif.crf b/F107/Project/RVMDK/Obj/ethernetif.crf
new file mode 100644
index 0000000..0d7d64c
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ethernetif.crf differ
diff --git a/F107/Project/RVMDK/Obj/ethernetif.d b/F107/Project/RVMDK/Obj/ethernetif.d
new file mode 100644
index 0000000..9c348c0
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ethernetif.d
@@ -0,0 +1,56 @@
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\ethernetif.c
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\netif/ppp_oe.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\ethernetif.h
+.\obj\ethernetif.o: ..\inc\main.h
+.\obj\ethernetif.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\ethernetif.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\ethernetif.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\ethernetif.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\ethernetif.o: ..\inc\stm32f10x_conf.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\ethernetif.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\ethernetif.o: ..\inc\stm32f107.h
+.\obj\ethernetif.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\obj\ethernetif.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\obj\ethernetif.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\obj\ethernetif.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\obj\ethernetif.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\ethernetif.o: ..\inc\netconf.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\helloworld.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\httpd.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\ethernetif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\ethernetif.o: ..\src\TCP_CLIENT.h
+.\obj\ethernetif.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/ethernetif.o b/F107/Project/RVMDK/Obj/ethernetif.o
new file mode 100644
index 0000000..c7ee8e7
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ethernetif.o differ
diff --git a/F107/Project/RVMDK/Obj/extract.crf b/F107/Project/RVMDK/Obj/extract.crf
new file mode 100644
index 0000000..6263f4a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/extract.crf differ
diff --git a/F107/Project/RVMDK/Obj/extract.d b/F107/Project/RVMDK/Obj/extract.d
new file mode 100644
index 0000000..febf4df
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/extract.d
@@ -0,0 +1,20 @@
+.\Obj\extract.o: ..\..\Utilities\efsl\source\extract.c
+.\Obj\extract.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\extract.o: ..\..\Utilities\efsl\include\extract.h
diff --git a/F107/Project/RVMDK/Obj/extract.o b/F107/Project/RVMDK/Obj/extract.o
new file mode 100644
index 0000000..5281468
Binary files /dev/null and b/F107/Project/RVMDK/Obj/extract.o differ
diff --git a/F107/Project/RVMDK/Obj/fat.crf b/F107/Project/RVMDK/Obj/fat.crf
new file mode 100644
index 0000000..9b444ab
Binary files /dev/null and b/F107/Project/RVMDK/Obj/fat.crf differ
diff --git a/F107/Project/RVMDK/Obj/fat.d b/F107/Project/RVMDK/Obj/fat.d
new file mode 100644
index 0000000..5749ef2
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/fat.d
@@ -0,0 +1,25 @@
+.\Obj\fat.o: ..\..\Utilities\efsl\source\fat.c
+.\Obj\fat.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\fat.o: ..\..\Utilities\efsl\include\time.h
diff --git a/F107/Project/RVMDK/Obj/fat.o b/F107/Project/RVMDK/Obj/fat.o
new file mode 100644
index 0000000..112afc9
Binary files /dev/null and b/F107/Project/RVMDK/Obj/fat.o differ
diff --git a/F107/Project/RVMDK/Obj/file.crf b/F107/Project/RVMDK/Obj/file.crf
new file mode 100644
index 0000000..86974dd
Binary files /dev/null and b/F107/Project/RVMDK/Obj/file.crf differ
diff --git a/F107/Project/RVMDK/Obj/file.d b/F107/Project/RVMDK/Obj/file.d
new file mode 100644
index 0000000..aa61239
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/file.d
@@ -0,0 +1,32 @@
+.\Obj\file.o: ..\..\Utilities\efsl\source\file.c
+.\Obj\file.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\file.o: ..\..\Utilities\efsl\include\file.h
diff --git a/F107/Project/RVMDK/Obj/file.o b/F107/Project/RVMDK/Obj/file.o
new file mode 100644
index 0000000..5e8a89f
Binary files /dev/null and b/F107/Project/RVMDK/Obj/file.o differ
diff --git a/F107/Project/RVMDK/Obj/fs.crf b/F107/Project/RVMDK/Obj/fs.crf
new file mode 100644
index 0000000..7589834
Binary files /dev/null and b/F107/Project/RVMDK/Obj/fs.crf differ
diff --git a/F107/Project/RVMDK/Obj/fs.d b/F107/Project/RVMDK/Obj/fs.d
new file mode 100644
index 0000000..be14606
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/fs.d
@@ -0,0 +1,32 @@
+.\Obj\fs.o: ..\..\Utilities\efsl\source\fs.c
+.\Obj\fs.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\fs.o: ..\..\Utilities\efsl\include\fat.h
diff --git a/F107/Project/RVMDK/Obj/fs.o b/F107/Project/RVMDK/Obj/fs.o
new file mode 100644
index 0000000..80c717c
Binary files /dev/null and b/F107/Project/RVMDK/Obj/fs.o differ
diff --git a/F107/Project/RVMDK/Obj/helloworld.__i b/F107/Project/RVMDK/Obj/helloworld.__i
new file mode 100644
index 0000000..acd07cb
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/helloworld.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\helloworld.o" --omf_browse ".\Obj\helloworld.crf" --depend ".\Obj\helloworld.d" "..\..\Utilities\lwip-1.3.1\port\helloworld.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/helloworld.crf b/F107/Project/RVMDK/Obj/helloworld.crf
new file mode 100644
index 0000000..2c68f13
Binary files /dev/null and b/F107/Project/RVMDK/Obj/helloworld.crf differ
diff --git a/F107/Project/RVMDK/Obj/helloworld.d b/F107/Project/RVMDK/Obj/helloworld.d
new file mode 100644
index 0000000..f890d21
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/helloworld.d
@@ -0,0 +1,37 @@
+.\obj\helloworld.o: ..\src\helloworld.c
+.\obj\helloworld.o: ..\src\helloworld.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\helloworld.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\helloworld.o: d:\Keil_v\ARM\ARMCC\Bin\..\include\string.h
+.\obj\helloworld.o: ..\..\Basic\delay\delay.h
+.\obj\helloworld.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\helloworld.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\helloworld.o: d:\Keil_v\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\helloworld.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\helloworld.o: ..\inc\stm32f10x_conf.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\helloworld.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\helloworld.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/helloworld.o b/F107/Project/RVMDK/Obj/helloworld.o
new file mode 100644
index 0000000..e731882
Binary files /dev/null and b/F107/Project/RVMDK/Obj/helloworld.o differ
diff --git a/F107/Project/RVMDK/Obj/httpd.__i b/F107/Project/RVMDK/Obj/httpd.__i
new file mode 100644
index 0000000..f204bc8
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/httpd.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\httpd.o" --omf_browse ".\Obj\httpd.crf" --depend ".\Obj\httpd.d" "..\..\Utilities\lwip-1.3.1\port\httpd.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/httpd.crf b/F107/Project/RVMDK/Obj/httpd.crf
new file mode 100644
index 0000000..78f26c9
Binary files /dev/null and b/F107/Project/RVMDK/Obj/httpd.crf differ
diff --git a/F107/Project/RVMDK/Obj/httpd.d b/F107/Project/RVMDK/Obj/httpd.d
new file mode 100644
index 0000000..e221d6a
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/httpd.d
@@ -0,0 +1,44 @@
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\port\httpd.c
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\port\httpd.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\Obj\httpd.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.c
+.\Obj\httpd.o: ..\inc\main.h
+.\Obj\httpd.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\httpd.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\httpd.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\httpd.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\httpd.o: ..\inc\stm32f10x_conf.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\httpd.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\httpd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\httpd.o: ..\inc\stm32f107.h
+.\Obj\httpd.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\Obj\httpd.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\Obj\httpd.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\Obj\httpd.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\Obj\httpd.o: G:\keil\ARM\RV31\INC\string.h
diff --git a/F107/Project/RVMDK/Obj/httpd.o b/F107/Project/RVMDK/Obj/httpd.o
new file mode 100644
index 0000000..e43393d
Binary files /dev/null and b/F107/Project/RVMDK/Obj/httpd.o differ
diff --git a/F107/Project/RVMDK/Obj/hx711.crf b/F107/Project/RVMDK/Obj/hx711.crf
new file mode 100644
index 0000000..ded7e69
Binary files /dev/null and b/F107/Project/RVMDK/Obj/hx711.crf differ
diff --git a/F107/Project/RVMDK/Obj/hx711.d b/F107/Project/RVMDK/Obj/hx711.d
new file mode 100644
index 0000000..1faeafc
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/hx711.d
@@ -0,0 +1,20 @@
+.\obj\hx711.o: ..\src\HX711.c
+.\obj\hx711.o: ..\src\HX711.h
+.\obj\hx711.o: ..\src\sys.h
+.\obj\hx711.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\hx711.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\hx711.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\hx711.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\hx711.o: ..\inc\stm32f10x_conf.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\hx711.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\hx711.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\hx711.o: ..\..\Basic\delay\delay.h
diff --git a/F107/Project/RVMDK/Obj/hx711.o b/F107/Project/RVMDK/Obj/hx711.o
new file mode 100644
index 0000000..2e72dc5
Binary files /dev/null and b/F107/Project/RVMDK/Obj/hx711.o differ
diff --git a/F107/Project/RVMDK/Obj/icmp.crf b/F107/Project/RVMDK/Obj/icmp.crf
new file mode 100644
index 0000000..d4ca195
Binary files /dev/null and b/F107/Project/RVMDK/Obj/icmp.crf differ
diff --git a/F107/Project/RVMDK/Obj/icmp.d b/F107/Project/RVMDK/Obj/icmp.d
new file mode 100644
index 0000000..a7d938f
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/icmp.d
@@ -0,0 +1,23 @@
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\icmp.c
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\icmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\icmp.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/icmp.o b/F107/Project/RVMDK/Obj/icmp.o
new file mode 100644
index 0000000..ca86891
Binary files /dev/null and b/F107/Project/RVMDK/Obj/icmp.o differ
diff --git a/F107/Project/RVMDK/Obj/igmp.crf b/F107/Project/RVMDK/Obj/igmp.crf
new file mode 100644
index 0000000..2b3f53e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/igmp.crf differ
diff --git a/F107/Project/RVMDK/Obj/igmp.d b/F107/Project/RVMDK/Obj/igmp.d
new file mode 100644
index 0000000..d3f56ad
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/igmp.d
@@ -0,0 +1,7 @@
+.\obj\igmp.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\igmp.c
+.\obj\igmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\igmp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\igmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\igmp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\igmp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\igmp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/igmp.o b/F107/Project/RVMDK/Obj/igmp.o
new file mode 100644
index 0000000..06e00d1
Binary files /dev/null and b/F107/Project/RVMDK/Obj/igmp.o differ
diff --git a/F107/Project/RVMDK/Obj/inet.crf b/F107/Project/RVMDK/Obj/inet.crf
new file mode 100644
index 0000000..fd7877b
Binary files /dev/null and b/F107/Project/RVMDK/Obj/inet.crf differ
diff --git a/F107/Project/RVMDK/Obj/inet.d b/F107/Project/RVMDK/Obj/inet.d
new file mode 100644
index 0000000..e2598d8
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/inet.d
@@ -0,0 +1,8 @@
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet.c
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\inet.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
diff --git a/F107/Project/RVMDK/Obj/inet.o b/F107/Project/RVMDK/Obj/inet.o
new file mode 100644
index 0000000..402dc05
Binary files /dev/null and b/F107/Project/RVMDK/Obj/inet.o differ
diff --git a/F107/Project/RVMDK/Obj/inet_chksum.crf b/F107/Project/RVMDK/Obj/inet_chksum.crf
new file mode 100644
index 0000000..0ae159d
Binary files /dev/null and b/F107/Project/RVMDK/Obj/inet_chksum.crf differ
diff --git a/F107/Project/RVMDK/Obj/inet_chksum.d b/F107/Project/RVMDK/Obj/inet_chksum.d
new file mode 100644
index 0000000..570ee0d
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/inet_chksum.d
@@ -0,0 +1,13 @@
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet_chksum.c
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\inet_chksum.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\inet_chksum.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stddef.h
diff --git a/F107/Project/RVMDK/Obj/inet_chksum.o b/F107/Project/RVMDK/Obj/inet_chksum.o
new file mode 100644
index 0000000..5bc1f79
Binary files /dev/null and b/F107/Project/RVMDK/Obj/inet_chksum.o differ
diff --git a/F107/Project/RVMDK/Obj/init.crf b/F107/Project/RVMDK/Obj/init.crf
new file mode 100644
index 0000000..7532b43
Binary files /dev/null and b/F107/Project/RVMDK/Obj/init.crf differ
diff --git a/F107/Project/RVMDK/Obj/init.d b/F107/Project/RVMDK/Obj/init.d
new file mode 100644
index 0000000..e8cfab3
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/init.d
@@ -0,0 +1,32 @@
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\core\init.c
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/init.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sockets.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/raw.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp_msg.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp_structs.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/autoip.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/igmp.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/dns.h
+.\obj\init.o: ..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h
diff --git a/F107/Project/RVMDK/Obj/init.o b/F107/Project/RVMDK/Obj/init.o
new file mode 100644
index 0000000..a6ceb95
Binary files /dev/null and b/F107/Project/RVMDK/Obj/init.o differ
diff --git a/F107/Project/RVMDK/Obj/ioman.crf b/F107/Project/RVMDK/Obj/ioman.crf
new file mode 100644
index 0000000..fd74ffd
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ioman.crf differ
diff --git a/F107/Project/RVMDK/Obj/ioman.d b/F107/Project/RVMDK/Obj/ioman.d
new file mode 100644
index 0000000..df8c9dc
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ioman.d
@@ -0,0 +1,15 @@
+.\Obj\ioman.o: ..\..\Utilities\efsl\source\ioman.c
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ioman.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/ioman.o b/F107/Project/RVMDK/Obj/ioman.o
new file mode 100644
index 0000000..ff24175
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ioman.o differ
diff --git a/F107/Project/RVMDK/Obj/ip.crf b/F107/Project/RVMDK/Obj/ip.crf
new file mode 100644
index 0000000..d25f01e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ip.crf differ
diff --git a/F107/Project/RVMDK/Obj/ip.d b/F107/Project/RVMDK/Obj/ip.d
new file mode 100644
index 0000000..f70b70c
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ip.d
@@ -0,0 +1,30 @@
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip.c
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_frag.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/igmp.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/raw.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/dhcp.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\ip.o: ..\..\Utilities\lwip-1.3.1\port\arch/perf.h
+.\obj\ip.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/ip.o b/F107/Project/RVMDK/Obj/ip.o
new file mode 100644
index 0000000..c93938e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ip.o differ
diff --git a/F107/Project/RVMDK/Obj/ip_addr.crf b/F107/Project/RVMDK/Obj/ip_addr.crf
new file mode 100644
index 0000000..88cad7e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ip_addr.crf differ
diff --git a/F107/Project/RVMDK/Obj/ip_addr.d b/F107/Project/RVMDK/Obj/ip_addr.d
new file mode 100644
index 0000000..d4da170
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ip_addr.d
@@ -0,0 +1,12 @@
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_addr.c
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\ip_addr.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
diff --git a/F107/Project/RVMDK/Obj/ip_addr.o b/F107/Project/RVMDK/Obj/ip_addr.o
new file mode 100644
index 0000000..c224912
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ip_addr.o differ
diff --git a/F107/Project/RVMDK/Obj/ip_frag.crf b/F107/Project/RVMDK/Obj/ip_frag.crf
new file mode 100644
index 0000000..0103f68
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ip_frag.crf differ
diff --git a/F107/Project/RVMDK/Obj/ip_frag.d b/F107/Project/RVMDK/Obj/ip_frag.d
new file mode 100644
index 0000000..0b9adec
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ip_frag.d
@@ -0,0 +1,24 @@
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_frag.c
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_frag.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\ip_frag.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\ip_frag.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/ip_frag.o b/F107/Project/RVMDK/Obj/ip_frag.o
new file mode 100644
index 0000000..80e810d
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ip_frag.o differ
diff --git a/F107/Project/RVMDK/Obj/led.crf b/F107/Project/RVMDK/Obj/led.crf
new file mode 100644
index 0000000..e28a457
Binary files /dev/null and b/F107/Project/RVMDK/Obj/led.crf differ
diff --git a/F107/Project/RVMDK/Obj/led.d b/F107/Project/RVMDK/Obj/led.d
new file mode 100644
index 0000000..b95d583
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/led.d
@@ -0,0 +1,18 @@
+.\obj\led.o: ..\..\Hardware\LED\led.c
+.\obj\led.o: ..\..\Hardware\LED\led.h
+.\obj\led.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\led.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\led.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\led.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\led.o: ..\inc\stm32f10x_conf.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\led.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\led.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/led.o b/F107/Project/RVMDK/Obj/led.o
new file mode 100644
index 0000000..375125b
Binary files /dev/null and b/F107/Project/RVMDK/Obj/led.o differ
diff --git a/F107/Project/RVMDK/Obj/ls.crf b/F107/Project/RVMDK/Obj/ls.crf
new file mode 100644
index 0000000..edb1c2c
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ls.crf differ
diff --git a/F107/Project/RVMDK/Obj/ls.d b/F107/Project/RVMDK/Obj/ls.d
new file mode 100644
index 0000000..1d06254
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ls.d
@@ -0,0 +1,35 @@
+.\Obj\ls.o: ..\..\Utilities\efsl\source\ls.c
+.\Obj\ls.o: ..\..\Utilities\efsl\include\ls.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\ls.o: ..\..\Utilities\efsl\include\fat.h
diff --git a/F107/Project/RVMDK/Obj/ls.o b/F107/Project/RVMDK/Obj/ls.o
new file mode 100644
index 0000000..d3f730e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ls.o differ
diff --git a/F107/Project/RVMDK/Obj/main.crf b/F107/Project/RVMDK/Obj/main.crf
new file mode 100644
index 0000000..38a1f29
Binary files /dev/null and b/F107/Project/RVMDK/Obj/main.crf differ
diff --git a/F107/Project/RVMDK/Obj/main.d b/F107/Project/RVMDK/Obj/main.d
new file mode 100644
index 0000000..0e89c91
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/main.d
@@ -0,0 +1,57 @@
+.\obj\main.o: ..\src\main.c
+.\obj\main.o: ..\inc\main.h
+.\obj\main.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\main.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\main.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\main.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\main.o: ..\inc\stm32f10x_conf.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\main.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\main.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\main.o: ..\inc\stm32f107.h
+.\obj\main.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\obj\main.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\obj\main.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\obj\main.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\obj\main.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\main.o: ..\inc\netconf.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\port\helloworld.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\port\httpd.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\main.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\main.o: ..\src\TCP_CLIENT.h
+.\obj\main.o: ..\..\Basic\usart\usart.h
+.\obj\main.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h
+.\obj\main.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
+.\obj\main.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
+.\obj\main.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\main.o: ..\..\Basic\delay\delay.h
+.\obj\main.o: ..\..\Hardware\LED\led.h
+.\obj\main.o: ..\src\HX711.h
+.\obj\main.o: ..\src\sys.h
diff --git a/F107/Project/RVMDK/Obj/main.o b/F107/Project/RVMDK/Obj/main.o
new file mode 100644
index 0000000..68ffe26
Binary files /dev/null and b/F107/Project/RVMDK/Obj/main.o differ
diff --git a/F107/Project/RVMDK/Obj/mem.crf b/F107/Project/RVMDK/Obj/mem.crf
new file mode 100644
index 0000000..b606b82
Binary files /dev/null and b/F107/Project/RVMDK/Obj/mem.crf differ
diff --git a/F107/Project/RVMDK/Obj/mem.d b/F107/Project/RVMDK/Obj/mem.d
new file mode 100644
index 0000000..7117db6
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/mem.d
@@ -0,0 +1,14 @@
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\core\mem.c
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\mem.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\mem.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/mem.o b/F107/Project/RVMDK/Obj/mem.o
new file mode 100644
index 0000000..999496b
Binary files /dev/null and b/F107/Project/RVMDK/Obj/mem.o differ
diff --git a/F107/Project/RVMDK/Obj/memp.crf b/F107/Project/RVMDK/Obj/memp.crf
new file mode 100644
index 0000000..9cc480a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/memp.crf differ
diff --git a/F107/Project/RVMDK/Obj/memp.d b/F107/Project/RVMDK/Obj/memp.d
new file mode 100644
index 0000000..bdf3d12
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/memp.d
@@ -0,0 +1,33 @@
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\core\memp.c
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/raw.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/igmp.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/api.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/api_msg.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcpip.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_frag.h
+.\obj\memp.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\memp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
diff --git a/F107/Project/RVMDK/Obj/memp.o b/F107/Project/RVMDK/Obj/memp.o
new file mode 100644
index 0000000..4e50353
Binary files /dev/null and b/F107/Project/RVMDK/Obj/memp.o differ
diff --git a/F107/Project/RVMDK/Obj/misc.crf b/F107/Project/RVMDK/Obj/misc.crf
new file mode 100644
index 0000000..f1322f8
Binary files /dev/null and b/F107/Project/RVMDK/Obj/misc.crf differ
diff --git a/F107/Project/RVMDK/Obj/misc.d b/F107/Project/RVMDK/Obj/misc.d
new file mode 100644
index 0000000..58fe98e
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/misc.d
@@ -0,0 +1,18 @@
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\misc.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\misc.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\misc.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\misc.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\misc.o: ..\inc\stm32f10x_conf.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\misc.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\misc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/misc.o b/F107/Project/RVMDK/Obj/misc.o
new file mode 100644
index 0000000..c5bf815
Binary files /dev/null and b/F107/Project/RVMDK/Obj/misc.o differ
diff --git a/F107/Project/RVMDK/Obj/mkfs.crf b/F107/Project/RVMDK/Obj/mkfs.crf
new file mode 100644
index 0000000..e0a9ef6
Binary files /dev/null and b/F107/Project/RVMDK/Obj/mkfs.crf differ
diff --git a/F107/Project/RVMDK/Obj/mkfs.d b/F107/Project/RVMDK/Obj/mkfs.d
new file mode 100644
index 0000000..d429cda
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/mkfs.d
@@ -0,0 +1,24 @@
+.\Obj\mkfs.o: ..\..\Utilities\efsl\source\mkfs.c
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\mkfs.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\mkfs.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/mkfs.o b/F107/Project/RVMDK/Obj/mkfs.o
new file mode 100644
index 0000000..85f613b
Binary files /dev/null and b/F107/Project/RVMDK/Obj/mkfs.o differ
diff --git a/F107/Project/RVMDK/Obj/netbuf.crf b/F107/Project/RVMDK/Obj/netbuf.crf
new file mode 100644
index 0000000..21befb9
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netbuf.crf differ
diff --git a/F107/Project/RVMDK/Obj/netbuf.d b/F107/Project/RVMDK/Obj/netbuf.d
new file mode 100644
index 0000000..f1c3cc8
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/netbuf.d
@@ -0,0 +1,7 @@
+.\obj\netbuf.o: ..\..\Utilities\lwip-1.3.1\src\api\netbuf.c
+.\obj\netbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\netbuf.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\netbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\netbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\netbuf.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\netbuf.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/netbuf.o b/F107/Project/RVMDK/Obj/netbuf.o
new file mode 100644
index 0000000..3553beb
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netbuf.o differ
diff --git a/F107/Project/RVMDK/Obj/netconf.crf b/F107/Project/RVMDK/Obj/netconf.crf
new file mode 100644
index 0000000..3832fd3
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netconf.crf differ
diff --git a/F107/Project/RVMDK/Obj/netconf.d b/F107/Project/RVMDK/Obj/netconf.d
new file mode 100644
index 0000000..b5f1cc8
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/netconf.d
@@ -0,0 +1,54 @@
+.\obj\netconf.o: ..\src\netconf.c
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/dhcp.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\ethernetif.h
+.\obj\netconf.o: ..\inc\main.h
+.\obj\netconf.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\netconf.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\netconf.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\netconf.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\netconf.o: ..\inc\stm32f10x_conf.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\netconf.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\netconf.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\netconf.o: ..\inc\stm32f107.h
+.\obj\netconf.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\obj\netconf.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\obj\netconf.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\obj\netconf.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\obj\netconf.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\netconf.o: ..\inc\netconf.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\helloworld.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\httpd.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.h
+.\obj\netconf.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\obj\netconf.o: ..\src\TCP_CLIENT.h
+.\obj\netconf.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
diff --git a/F107/Project/RVMDK/Obj/netconf.o b/F107/Project/RVMDK/Obj/netconf.o
new file mode 100644
index 0000000..ace5707
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netconf.o differ
diff --git a/F107/Project/RVMDK/Obj/netdb.crf b/F107/Project/RVMDK/Obj/netdb.crf
new file mode 100644
index 0000000..6e85d87
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netdb.crf differ
diff --git a/F107/Project/RVMDK/Obj/netdb.d b/F107/Project/RVMDK/Obj/netdb.d
new file mode 100644
index 0000000..98d72d0
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/netdb.d
@@ -0,0 +1,8 @@
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\src\api\netdb.c
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netdb.h
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\netdb.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/netdb.o b/F107/Project/RVMDK/Obj/netdb.o
new file mode 100644
index 0000000..5ac9205
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netdb.o differ
diff --git a/F107/Project/RVMDK/Obj/netif.crf b/F107/Project/RVMDK/Obj/netif.crf
new file mode 100644
index 0000000..5ccf377
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netif.crf differ
diff --git a/F107/Project/RVMDK/Obj/netif.d b/F107/Project/RVMDK/Obj/netif.d
new file mode 100644
index 0000000..f26ceca
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/netif.d
@@ -0,0 +1,22 @@
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\core\netif.c
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/igmp.h
+.\obj\netif.o: ..\..\Utilities\lwip-1.3.1\src\include\netif/etharp.h
diff --git a/F107/Project/RVMDK/Obj/netif.o b/F107/Project/RVMDK/Obj/netif.o
new file mode 100644
index 0000000..a3200c3
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netif.o differ
diff --git a/F107/Project/RVMDK/Obj/netifapi.crf b/F107/Project/RVMDK/Obj/netifapi.crf
new file mode 100644
index 0000000..32d0628
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netifapi.crf differ
diff --git a/F107/Project/RVMDK/Obj/netifapi.d b/F107/Project/RVMDK/Obj/netifapi.d
new file mode 100644
index 0000000..18e4983
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/netifapi.d
@@ -0,0 +1,7 @@
+.\obj\netifapi.o: ..\..\Utilities\lwip-1.3.1\src\api\netifapi.c
+.\obj\netifapi.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\netifapi.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\netifapi.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\netifapi.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\netifapi.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\netifapi.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/netifapi.o b/F107/Project/RVMDK/Obj/netifapi.o
new file mode 100644
index 0000000..d066137
Binary files /dev/null and b/F107/Project/RVMDK/Obj/netifapi.o differ
diff --git a/F107/Project/RVMDK/Obj/partition.crf b/F107/Project/RVMDK/Obj/partition.crf
new file mode 100644
index 0000000..458b8df
Binary files /dev/null and b/F107/Project/RVMDK/Obj/partition.crf differ
diff --git a/F107/Project/RVMDK/Obj/partition.d b/F107/Project/RVMDK/Obj/partition.d
new file mode 100644
index 0000000..638cce7
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/partition.d
@@ -0,0 +1,22 @@
+.\Obj\partition.o: ..\..\Utilities\efsl\source\partition.c
+.\Obj\partition.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\partition.o: ..\..\Utilities\efsl\include\disc.h
diff --git a/F107/Project/RVMDK/Obj/partition.o b/F107/Project/RVMDK/Obj/partition.o
new file mode 100644
index 0000000..bb1db98
Binary files /dev/null and b/F107/Project/RVMDK/Obj/partition.o differ
diff --git a/F107/Project/RVMDK/Obj/pbuf.crf b/F107/Project/RVMDK/Obj/pbuf.crf
new file mode 100644
index 0000000..c4f0b43
Binary files /dev/null and b/F107/Project/RVMDK/Obj/pbuf.crf differ
diff --git a/F107/Project/RVMDK/Obj/pbuf.d b/F107/Project/RVMDK/Obj/pbuf.d
new file mode 100644
index 0000000..2032ff6
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/pbuf.d
@@ -0,0 +1,17 @@
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\core\pbuf.c
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\pbuf.o: ..\..\Utilities\lwip-1.3.1\port\arch/perf.h
+.\obj\pbuf.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/pbuf.o b/F107/Project/RVMDK/Obj/pbuf.o
new file mode 100644
index 0000000..1fdc212
Binary files /dev/null and b/F107/Project/RVMDK/Obj/pbuf.o differ
diff --git a/F107/Project/RVMDK/Obj/plibc.crf b/F107/Project/RVMDK/Obj/plibc.crf
new file mode 100644
index 0000000..cef2c5d
Binary files /dev/null and b/F107/Project/RVMDK/Obj/plibc.crf differ
diff --git a/F107/Project/RVMDK/Obj/plibc.d b/F107/Project/RVMDK/Obj/plibc.d
new file mode 100644
index 0000000..256f60f
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/plibc.d
@@ -0,0 +1,7 @@
+.\Obj\plibc.o: ..\..\Utilities\efsl\source\plibc.c
+.\Obj\plibc.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\plibc.o: ..\..\Utilities\efsl\include\debug.h
+.\Obj\plibc.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\plibc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\plibc.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\plibc.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/plibc.o b/F107/Project/RVMDK/Obj/plibc.o
new file mode 100644
index 0000000..f23ae86
Binary files /dev/null and b/F107/Project/RVMDK/Obj/plibc.o differ
diff --git a/F107/Project/RVMDK/Obj/raw.crf b/F107/Project/RVMDK/Obj/raw.crf
new file mode 100644
index 0000000..92d6347
Binary files /dev/null and b/F107/Project/RVMDK/Obj/raw.crf differ
diff --git a/F107/Project/RVMDK/Obj/raw.d b/F107/Project/RVMDK/Obj/raw.d
new file mode 100644
index 0000000..6e2ed11
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/raw.d
@@ -0,0 +1,23 @@
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\core\raw.c
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/raw.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\raw.o: ..\..\Utilities\lwip-1.3.1\port\arch/perf.h
+.\obj\raw.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/raw.o b/F107/Project/RVMDK/Obj/raw.o
new file mode 100644
index 0000000..605fd96
Binary files /dev/null and b/F107/Project/RVMDK/Obj/raw.o differ
diff --git a/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.__i b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.__i
new file mode 100644
index 0000000..1b8bdf2
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\rs232_485_can_to_tcp.o" --omf_browse ".\Obj\rs232_485_can_to_tcp.crf" --depend ".\Obj\rs232_485_can_to_tcp.d" "..\src\RS232_485_CAN_to_TCP.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.crf b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.crf
new file mode 100644
index 0000000..e23570a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.crf differ
diff --git a/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.d b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.d
new file mode 100644
index 0000000..048f281
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.d
@@ -0,0 +1,36 @@
+.\Obj\rs232_485_can_to_tcp.o: ..\src\RS232_485_CAN_to_TCP.c
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\rs232_485_can_to_tcp.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\rs232_485_can_to_tcp.o: ..\inc\stm32f10x_conf.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\rs232_485_can_to_tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\Obj\rs232_485_can_to_tcp.o: ..\src\RS232_485_CAN_to_TCP.h
diff --git a/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.o b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.o
new file mode 100644
index 0000000..230330b
Binary files /dev/null and b/F107/Project/RVMDK/Obj/rs232_485_can_to_tcp.o differ
diff --git a/F107/Project/RVMDK/Obj/sci.crf b/F107/Project/RVMDK/Obj/sci.crf
new file mode 100644
index 0000000..ffaaa62
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sci.crf differ
diff --git a/F107/Project/RVMDK/Obj/sci.d b/F107/Project/RVMDK/Obj/sci.d
new file mode 100644
index 0000000..75b2ba0
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/sci.d
@@ -0,0 +1,17 @@
+.\obj\sci.o: ..\src\SCI.c
+.\obj\sci.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\sci.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\sci.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\sci.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\sci.o: ..\inc\stm32f10x_conf.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\sci.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\sci.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/sci.o b/F107/Project/RVMDK/Obj/sci.o
new file mode 100644
index 0000000..608dfa3
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sci.o differ
diff --git a/F107/Project/RVMDK/Obj/sd.crf b/F107/Project/RVMDK/Obj/sd.crf
new file mode 100644
index 0000000..c9d84ca
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sd.crf differ
diff --git a/F107/Project/RVMDK/Obj/sd.d b/F107/Project/RVMDK/Obj/sd.d
new file mode 100644
index 0000000..930635c
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/sd.d
@@ -0,0 +1,9 @@
+.\Obj\sd.o: ..\..\Utilities\efsl\source\interface\sd.c
+.\Obj\sd.o: ..\..\Utilities\efsl\include\interface/sd.h
+.\Obj\sd.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\sd.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\sd.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\sd.o: ..\..\Utilities\efsl\include\interface/../debug.h
+.\Obj\sd.o: ..\..\Utilities\efsl\include\interface/../config.h
+.\Obj\sd.o: ..\..\Utilities\efsl\include\interface/sd_stm32.h
+.\Obj\sd.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/sd.o b/F107/Project/RVMDK/Obj/sd.o
new file mode 100644
index 0000000..c7566f8
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sd.o differ
diff --git a/F107/Project/RVMDK/Obj/sd_stm32.crf b/F107/Project/RVMDK/Obj/sd_stm32.crf
new file mode 100644
index 0000000..91555c6
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sd_stm32.crf differ
diff --git a/F107/Project/RVMDK/Obj/sd_stm32.d b/F107/Project/RVMDK/Obj/sd_stm32.d
new file mode 100644
index 0000000..7a5f1d8
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/sd_stm32.d
@@ -0,0 +1,27 @@
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\source\interface\sd_stm32.c
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\sd_stm32.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\sd_stm32.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\sd_stm32.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\sd_stm32.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\sd_stm32.o: ..\inc\stm32f10x_conf.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\sd_stm32.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\sd_stm32.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\interface/sd.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\interface/../debug.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\interface/../config.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\interface/sd_stm32.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\sd_stm32.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/sd_stm32.o b/F107/Project/RVMDK/Obj/sd_stm32.o
new file mode 100644
index 0000000..ba5103d
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sd_stm32.o differ
diff --git a/F107/Project/RVMDK/Obj/server.__i b/F107/Project/RVMDK/Obj/server.__i
new file mode 100644
index 0000000..97e9457
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/server.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\server.o" --omf_browse ".\Obj\server.crf" --depend ".\Obj\server.d" "..\..\Utilities\lwip-1.3.1\port\server.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/server.crf b/F107/Project/RVMDK/Obj/server.crf
new file mode 100644
index 0000000..6e3151b
Binary files /dev/null and b/F107/Project/RVMDK/Obj/server.crf differ
diff --git a/F107/Project/RVMDK/Obj/server.d b/F107/Project/RVMDK/Obj/server.d
new file mode 100644
index 0000000..4cad40a
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/server.d
@@ -0,0 +1,43 @@
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\port\server.c
+.\Obj\server.o: ..\inc\main.h
+.\Obj\server.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\server.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\server.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\server.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\server.o: ..\inc\stm32f10x_conf.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\server.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\server.o: ..\inc\stm32f107.h
+.\Obj\server.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\Obj\server.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\Obj\server.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\Obj\server.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\Obj\server.o: G:\keil\ARM\RV31\INC\string.h
+.\Obj\server.o: G:\keil\ARM\RV31\INC\stdio.h
diff --git a/F107/Project/RVMDK/Obj/server.o b/F107/Project/RVMDK/Obj/server.o
new file mode 100644
index 0000000..34e1b5a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/server.o differ
diff --git a/F107/Project/RVMDK/Obj/startup_stm32f10x_cl.d b/F107/Project/RVMDK/Obj/startup_stm32f10x_cl.d
new file mode 100644
index 0000000..9092e50
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/startup_stm32f10x_cl.d
@@ -0,0 +1 @@
+.\obj\startup_stm32f10x_cl.o: ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s
diff --git a/F107/Project/RVMDK/Obj/startup_stm32f10x_cl.o b/F107/Project/RVMDK/Obj/startup_stm32f10x_cl.o
new file mode 100644
index 0000000..4cc538d
Binary files /dev/null and b/F107/Project/RVMDK/Obj/startup_stm32f10x_cl.o differ
diff --git a/F107/Project/RVMDK/Obj/stats.crf b/F107/Project/RVMDK/Obj/stats.crf
new file mode 100644
index 0000000..858a63e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stats.crf differ
diff --git a/F107/Project/RVMDK/Obj/stats.d b/F107/Project/RVMDK/Obj/stats.d
new file mode 100644
index 0000000..faab862
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stats.d
@@ -0,0 +1,7 @@
+.\obj\stats.o: ..\..\Utilities\lwip-1.3.1\src\core\stats.c
+.\obj\stats.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\stats.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\stats.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\stats.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\stats.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\stats.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/stats.o b/F107/Project/RVMDK/Obj/stats.o
new file mode 100644
index 0000000..e905566
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stats.o differ
diff --git a/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.crf b/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.crf
new file mode 100644
index 0000000..f375c8f
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.d b/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.d
new file mode 100644
index 0000000..b01ad88
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.d
@@ -0,0 +1,18 @@
+.\Obj\stm3210c_eval_ioe.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.c
+.\Obj\stm3210c_eval_ioe.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\stm3210c_eval_ioe.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\stm3210c_eval_ioe.o: ..\inc\stm32f10x_conf.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\stm3210c_eval_ioe.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.o b/F107/Project/RVMDK/Obj/stm3210c_eval_ioe.o
new file mode 100644
index 0000000..de4c071
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diff --git a/F107/Project/RVMDK/Obj/stm3210c_eval_lcd.crf b/F107/Project/RVMDK/Obj/stm3210c_eval_lcd.crf
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diff --git a/F107/Project/RVMDK/Obj/stm3210c_eval_lcd.d b/F107/Project/RVMDK/Obj/stm3210c_eval_lcd.d
new file mode 100644
index 0000000..af009d3
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm3210c_eval_lcd.d
@@ -0,0 +1,19 @@
+.\Obj\stm3210c_eval_lcd.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.c
+.\Obj\stm3210c_eval_lcd.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\stm3210c_eval_lcd.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\stm3210c_eval_lcd.o: ..\inc\stm32f10x_conf.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\stm3210c_eval_lcd.o: ..\..\Utilities\STM32_EVAL\fonts.h
diff --git a/F107/Project/RVMDK/Obj/stm3210c_eval_lcd.o b/F107/Project/RVMDK/Obj/stm3210c_eval_lcd.o
new file mode 100644
index 0000000..095ae48
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diff --git a/F107/Project/RVMDK/Obj/stm32_eth.crf b/F107/Project/RVMDK/Obj/stm32_eth.crf
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index 0000000..ec84e24
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diff --git a/F107/Project/RVMDK/Obj/stm32_eth.d b/F107/Project/RVMDK/Obj/stm32_eth.d
new file mode 100644
index 0000000..fea1e69
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32_eth.d
@@ -0,0 +1,18 @@
+.\obj\stm32_eth.o: ..\..\Libraries\STM32_ETH_Driver\src\stm32_eth.c
+.\obj\stm32_eth.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\stm32_eth.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32_eth.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32_eth.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32_eth.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32_eth.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32_eth.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32_eth.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32_eth.o b/F107/Project/RVMDK/Obj/stm32_eth.o
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index 0000000..0dcbf42
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diff --git a/F107/Project/RVMDK/Obj/stm32_eval.crf b/F107/Project/RVMDK/Obj/stm32_eval.crf
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index 0000000..377c9ac
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diff --git a/F107/Project/RVMDK/Obj/stm32_eval.d b/F107/Project/RVMDK/Obj/stm32_eval.d
new file mode 100644
index 0000000..79063bd
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32_eval.d
@@ -0,0 +1,19 @@
+.\Obj\stm32_eval.o: ..\..\Utilities\STM32_EVAL\stm32_eval.c
+.\Obj\stm32_eval.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\Obj\stm32_eval.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\stm32_eval.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\stm32_eval.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\stm32_eval.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\stm32_eval.o: ..\inc\stm32f10x_conf.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\stm32_eval.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\stm32_eval.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\stm32_eval.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
diff --git a/F107/Project/RVMDK/Obj/stm32_eval.o b/F107/Project/RVMDK/Obj/stm32_eval.o
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index 0000000..f477098
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diff --git a/F107/Project/RVMDK/Obj/stm32f107.crf b/F107/Project/RVMDK/Obj/stm32f107.crf
new file mode 100644
index 0000000..1d19e3c
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diff --git a/F107/Project/RVMDK/Obj/stm32f107.d b/F107/Project/RVMDK/Obj/stm32f107.d
new file mode 100644
index 0000000..855f6e6
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f107.d
@@ -0,0 +1,23 @@
+.\obj\stm32f107.o: ..\src\stm32f107.c
+.\obj\stm32f107.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\stm32f107.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f107.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f107.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f107.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f107.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f107.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f107.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\stm32f107.o: ..\inc\stm32f107.h
+.\obj\stm32f107.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\obj\stm32f107.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\obj\stm32f107.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\obj\stm32f107.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
diff --git a/F107/Project/RVMDK/Obj/stm32f107.o b/F107/Project/RVMDK/Obj/stm32f107.o
new file mode 100644
index 0000000..306d713
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diff --git a/F107/Project/RVMDK/Obj/stm32f10x_adc.crf b/F107/Project/RVMDK/Obj/stm32f10x_adc.crf
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index 0000000..6afbaec
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diff --git a/F107/Project/RVMDK/Obj/stm32f10x_adc.d b/F107/Project/RVMDK/Obj/stm32f10x_adc.d
new file mode 100644
index 0000000..2f5d360
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_adc.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_adc.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_adc.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_adc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_adc.o b/F107/Project/RVMDK/Obj/stm32f10x_adc.o
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index 0000000..3fb51a5
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_adc.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_exti.crf b/F107/Project/RVMDK/Obj/stm32f10x_exti.crf
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index 0000000..7f3cb55
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_exti.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_exti.d b/F107/Project/RVMDK/Obj/stm32f10x_exti.d
new file mode 100644
index 0000000..3c22ea8
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_exti.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_exti.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_exti.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_exti.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_exti.o b/F107/Project/RVMDK/Obj/stm32f10x_exti.o
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index 0000000..492fdc8
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_exti.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_flash.crf b/F107/Project/RVMDK/Obj/stm32f10x_flash.crf
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index 0000000..5e1f692
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_flash.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_flash.d b/F107/Project/RVMDK/Obj/stm32f10x_flash.d
new file mode 100644
index 0000000..df7f152
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_flash.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_flash.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_flash.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_flash.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_flash.o b/F107/Project/RVMDK/Obj/stm32f10x_flash.o
new file mode 100644
index 0000000..998f8ce
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_flash.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_gpio.crf b/F107/Project/RVMDK/Obj/stm32f10x_gpio.crf
new file mode 100644
index 0000000..a8306dc
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_gpio.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_gpio.d b/F107/Project/RVMDK/Obj/stm32f10x_gpio.d
new file mode 100644
index 0000000..fd4b914
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_gpio.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_gpio.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_gpio.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_gpio.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_gpio.o b/F107/Project/RVMDK/Obj/stm32f10x_gpio.o
new file mode 100644
index 0000000..da30a96
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_gpio.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_i2c.crf b/F107/Project/RVMDK/Obj/stm32f10x_i2c.crf
new file mode 100644
index 0000000..4b71cf0
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_i2c.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_i2c.d b/F107/Project/RVMDK/Obj/stm32f10x_i2c.d
new file mode 100644
index 0000000..b194860
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_i2c.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_i2c.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_i2c.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_i2c.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_i2c.o b/F107/Project/RVMDK/Obj/stm32f10x_i2c.o
new file mode 100644
index 0000000..b4573a8
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_i2c.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_it.crf b/F107/Project/RVMDK/Obj/stm32f10x_it.crf
new file mode 100644
index 0000000..373f324
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_it.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_it.d b/F107/Project/RVMDK/Obj/stm32f10x_it.d
new file mode 100644
index 0000000..e953eb6
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_it.d
@@ -0,0 +1,49 @@
+.\obj\stm32f10x_it.o: ..\src\stm32f10x_it.c
+.\obj\stm32f10x_it.o: ..\inc\stm32f10x_it.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_it.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_it.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\stm32f10x_it.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\stm32f10x_it.o: ..\inc\main.h
+.\obj\stm32f10x_it.o: ..\inc\stm32f107.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\obj\stm32f10x_it.o: ..\inc\netconf.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\port\helloworld.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\port\httpd.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\stm32f10x_it.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\stm32f10x_it.o: ..\src\TCP_CLIENT.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_it.o b/F107/Project/RVMDK/Obj/stm32f10x_it.o
new file mode 100644
index 0000000..75b9898
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_it.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_rcc.crf b/F107/Project/RVMDK/Obj/stm32f10x_rcc.crf
new file mode 100644
index 0000000..d3c22b1
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_rcc.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_rcc.d b/F107/Project/RVMDK/Obj/stm32f10x_rcc.d
new file mode 100644
index 0000000..f3765bd
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_rcc.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_rcc.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_rcc.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_rcc.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_rcc.o b/F107/Project/RVMDK/Obj/stm32f10x_rcc.o
new file mode 100644
index 0000000..dcec6ab
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_rcc.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_spi.crf b/F107/Project/RVMDK/Obj/stm32f10x_spi.crf
new file mode 100644
index 0000000..437549a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_spi.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_spi.d b/F107/Project/RVMDK/Obj/stm32f10x_spi.d
new file mode 100644
index 0000000..c252e7a
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_spi.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_spi.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_spi.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_spi.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_spi.o b/F107/Project/RVMDK/Obj/stm32f10x_spi.o
new file mode 100644
index 0000000..31c16da
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_spi.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_tim.crf b/F107/Project/RVMDK/Obj/stm32f10x_tim.crf
new file mode 100644
index 0000000..d67545c
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_tim.crf differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_tim.d b/F107/Project/RVMDK/Obj/stm32f10x_tim.d
new file mode 100644
index 0000000..3a3a34a
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_tim.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_tim.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_tim.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_tim.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_tim.o b/F107/Project/RVMDK/Obj/stm32f10x_tim.o
new file mode 100644
index 0000000..855fb8f
Binary files /dev/null and b/F107/Project/RVMDK/Obj/stm32f10x_tim.o differ
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_usart.crf b/F107/Project/RVMDK/Obj/stm32f10x_usart.crf
new file mode 100644
index 0000000..ad4b68c
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diff --git a/F107/Project/RVMDK/Obj/stm32f10x_usart.d b/F107/Project/RVMDK/Obj/stm32f10x_usart.d
new file mode 100644
index 0000000..b4f924c
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/stm32f10x_usart.d
@@ -0,0 +1,18 @@
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\stm32f10x_usart.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\stm32f10x_usart.o: ..\inc\stm32f10x_conf.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\stm32f10x_usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/stm32f10x_usart.o b/F107/Project/RVMDK/Obj/stm32f10x_usart.o
new file mode 100644
index 0000000..56b42fa
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diff --git a/F107/Project/RVMDK/Obj/sys.crf b/F107/Project/RVMDK/Obj/sys.crf
new file mode 100644
index 0000000..62dc997
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diff --git a/F107/Project/RVMDK/Obj/sys.d b/F107/Project/RVMDK/Obj/sys.d
new file mode 100644
index 0000000..3fe14a8
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/sys.d
@@ -0,0 +1,18 @@
+.\obj\sys.o: ..\src\sys.c
+.\obj\sys.o: ..\src\sys.h
+.\obj\sys.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\sys.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\sys.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\sys.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\sys.o: ..\inc\stm32f10x_conf.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\sys.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\sys.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/sys.o b/F107/Project/RVMDK/Obj/sys.o
new file mode 100644
index 0000000..722b844
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sys.o differ
diff --git a/F107/Project/RVMDK/Obj/sys_1.crf b/F107/Project/RVMDK/Obj/sys_1.crf
new file mode 100644
index 0000000..7e127ec
Binary files /dev/null and b/F107/Project/RVMDK/Obj/sys_1.crf differ
diff --git a/F107/Project/RVMDK/Obj/sys_1.d b/F107/Project/RVMDK/Obj/sys_1.d
new file mode 100644
index 0000000..82b8b03
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/sys_1.d
@@ -0,0 +1,7 @@
+.\obj\sys_1.o: ..\..\Utilities\lwip-1.3.1\src\core\sys.c
+.\obj\sys_1.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\sys_1.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\sys_1.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\sys_1.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\sys_1.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\sys_1.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/sys_1.o b/F107/Project/RVMDK/Obj/sys_1.o
new file mode 100644
index 0000000..f59be9f
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diff --git a/F107/Project/RVMDK/Obj/system_stm32f10x.crf b/F107/Project/RVMDK/Obj/system_stm32f10x.crf
new file mode 100644
index 0000000..47880f8
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diff --git a/F107/Project/RVMDK/Obj/system_stm32f10x.d b/F107/Project/RVMDK/Obj/system_stm32f10x.d
new file mode 100644
index 0000000..e7ad3ba
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/system_stm32f10x.d
@@ -0,0 +1,17 @@
+.\obj\system_stm32f10x.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c
+.\obj\system_stm32f10x.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\system_stm32f10x.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\system_stm32f10x.o: ..\inc\stm32f10x_conf.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\system_stm32f10x.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
diff --git a/F107/Project/RVMDK/Obj/system_stm32f10x.o b/F107/Project/RVMDK/Obj/system_stm32f10x.o
new file mode 100644
index 0000000..6c8f7c2
Binary files /dev/null and b/F107/Project/RVMDK/Obj/system_stm32f10x.o differ
diff --git a/F107/Project/RVMDK/Obj/tcp.crf b/F107/Project/RVMDK/Obj/tcp.crf
new file mode 100644
index 0000000..ea9be95
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diff --git a/F107/Project/RVMDK/Obj/tcp.d b/F107/Project/RVMDK/Obj/tcp.d
new file mode 100644
index 0000000..a8ede10
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp.d
@@ -0,0 +1,23 @@
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\core\tcp.c
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\tcp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\tcp.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/tcp.o b/F107/Project/RVMDK/Obj/tcp.o
new file mode 100644
index 0000000..3017432
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp.o differ
diff --git a/F107/Project/RVMDK/Obj/tcp_client.crf b/F107/Project/RVMDK/Obj/tcp_client.crf
new file mode 100644
index 0000000..4613f65
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diff --git a/F107/Project/RVMDK/Obj/tcp_client.d b/F107/Project/RVMDK/Obj/tcp_client.d
new file mode 100644
index 0000000..b33eaa5
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp_client.d
@@ -0,0 +1,56 @@
+.\obj\tcp_client.o: ..\src\TCP_CLIENT.C
+.\obj\tcp_client.o: ..\inc\main.h
+.\obj\tcp_client.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\tcp_client.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\tcp_client.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\tcp_client.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\tcp_client.o: ..\inc\stm32f10x_conf.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\tcp_client.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\tcp_client.o: ..\inc\stm32f107.h
+.\obj\tcp_client.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\obj\tcp_client.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\obj\tcp_client.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\obj\tcp_client.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\obj\tcp_client.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\tcp_client.o: ..\inc\netconf.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\port\helloworld.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\port\httpd.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\tcp_client.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\tcp_client.o: ..\src\TCP_CLIENT.h
+.\obj\tcp_client.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
+.\obj\tcp_client.o: ..\..\Basic\usart\usart.h
+.\obj\tcp_client.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h
+.\obj\tcp_client.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
+.\obj\tcp_client.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\tcp_client.o: ..\src\HX711.h
+.\obj\tcp_client.o: ..\src\sys.h
+.\obj\tcp_client.o: ..\..\Basic\delay\delay.h
diff --git a/F107/Project/RVMDK/Obj/tcp_client.o b/F107/Project/RVMDK/Obj/tcp_client.o
new file mode 100644
index 0000000..b51657a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_client.o differ
diff --git a/F107/Project/RVMDK/Obj/tcp_in.crf b/F107/Project/RVMDK/Obj/tcp_in.crf
new file mode 100644
index 0000000..2b66b09
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_in.crf differ
diff --git a/F107/Project/RVMDK/Obj/tcp_in.d b/F107/Project/RVMDK/Obj/tcp_in.d
new file mode 100644
index 0000000..bef358a
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp_in.d
@@ -0,0 +1,25 @@
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\core\tcp_in.c
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\tcp_in.o: ..\..\Utilities\lwip-1.3.1\port\arch/perf.h
diff --git a/F107/Project/RVMDK/Obj/tcp_in.o b/F107/Project/RVMDK/Obj/tcp_in.o
new file mode 100644
index 0000000..98e7b16
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_in.o differ
diff --git a/F107/Project/RVMDK/Obj/tcp_out.crf b/F107/Project/RVMDK/Obj/tcp_out.crf
new file mode 100644
index 0000000..d4426dd
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_out.crf differ
diff --git a/F107/Project/RVMDK/Obj/tcp_out.d b/F107/Project/RVMDK/Obj/tcp_out.d
new file mode 100644
index 0000000..58e124e
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp_out.d
@@ -0,0 +1,25 @@
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\core\tcp_out.c
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\tcp_out.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\tcp_out.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/tcp_out.o b/F107/Project/RVMDK/Obj/tcp_out.o
new file mode 100644
index 0000000..a5b1ddd
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_out.o differ
diff --git a/F107/Project/RVMDK/Obj/tcp_server.__i b/F107/Project/RVMDK/Obj/tcp_server.__i
new file mode 100644
index 0000000..d41ad67
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp_server.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\tcp_server.o" --omf_browse ".\Obj\tcp_server.crf" --depend ".\Obj\tcp_server.d" "..\src\TCP_SERVER.C"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/tcp_server.crf b/F107/Project/RVMDK/Obj/tcp_server.crf
new file mode 100644
index 0000000..925e68e
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_server.crf differ
diff --git a/F107/Project/RVMDK/Obj/tcp_server.d b/F107/Project/RVMDK/Obj/tcp_server.d
new file mode 100644
index 0000000..faee74e
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp_server.d
@@ -0,0 +1,36 @@
+.\Obj\tcp_server.o: ..\src\TCP_SERVER.C
+.\Obj\tcp_server.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\Obj\tcp_server.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\tcp_server.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\tcp_server.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\tcp_server.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\tcp_server.o: ..\inc\stm32f10x_conf.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\tcp_server.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\tcp_server.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\tcp_server.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\Obj\tcp_server.o: ..\src\TCP_SERVER.h
diff --git a/F107/Project/RVMDK/Obj/tcp_server.o b/F107/Project/RVMDK/Obj/tcp_server.o
new file mode 100644
index 0000000..5ae5cd8
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_server.o differ
diff --git a/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.__i b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.__i
new file mode 100644
index 0000000..041dfec
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\tcp_to_rs232_485_can.o" --omf_browse ".\Obj\tcp_to_rs232_485_can.crf" --depend ".\Obj\tcp_to_rs232_485_can.d" "..\src\TCP_to_RS232_485_CAN.C"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.crf b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.crf
new file mode 100644
index 0000000..e926c48
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.crf differ
diff --git a/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.d b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.d
new file mode 100644
index 0000000..9e3b727
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.d
@@ -0,0 +1,37 @@
+.\Obj\tcp_to_rs232_485_can.o: ..\src\TCP_to_RS232_485_CAN.C
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\Obj\tcp_to_rs232_485_can.o: G:\keil\ARM\RV31\INC\stdint.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\Obj\tcp_to_rs232_485_can.o: ..\inc\stm32f10x_conf.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\tcp_to_rs232_485_can.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\Obj\tcp_to_rs232_485_can.o: ..\src\TCP_to_RS232_485_CAN.h
+.\Obj\tcp_to_rs232_485_can.o: ..\src\RS232_485_CAN_to_TCP.h
diff --git a/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.o b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.o
new file mode 100644
index 0000000..a576247
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcp_to_rs232_485_can.o differ
diff --git a/F107/Project/RVMDK/Obj/tcpip.crf b/F107/Project/RVMDK/Obj/tcpip.crf
new file mode 100644
index 0000000..a40ea98
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcpip.crf differ
diff --git a/F107/Project/RVMDK/Obj/tcpip.d b/F107/Project/RVMDK/Obj/tcpip.d
new file mode 100644
index 0000000..4b1cf06
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tcpip.d
@@ -0,0 +1,7 @@
+.\obj\tcpip.o: ..\..\Utilities\lwip-1.3.1\src\api\tcpip.c
+.\obj\tcpip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\tcpip.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\tcpip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\tcpip.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\tcpip.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\tcpip.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
diff --git a/F107/Project/RVMDK/Obj/tcpip.o b/F107/Project/RVMDK/Obj/tcpip.o
new file mode 100644
index 0000000..634ba5a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tcpip.o differ
diff --git a/F107/Project/RVMDK/Obj/tftpserver.__i b/F107/Project/RVMDK/Obj/tftpserver.__i
new file mode 100644
index 0000000..584b196
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tftpserver.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\tftpserver.o" --omf_browse ".\Obj\tftpserver.crf" --depend ".\Obj\tftpserver.d" "..\..\Utilities\lwip-1.3.1\port\tftpserver.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/tftpserver.crf b/F107/Project/RVMDK/Obj/tftpserver.crf
new file mode 100644
index 0000000..f4438a5
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tftpserver.crf differ
diff --git a/F107/Project/RVMDK/Obj/tftpserver.d b/F107/Project/RVMDK/Obj/tftpserver.d
new file mode 100644
index 0000000..07fe41c
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tftpserver.d
@@ -0,0 +1,59 @@
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.c
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\Obj\tftpserver.o: ..\..\Utilities\lwip-1.3.1\port\tftputils.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\efs.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\ui.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\ls.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\interface\sd.h
+.\Obj\tftpserver.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\tftpserver.o: G:\keil\ARM\RV31\INC\stdio.h
+.\Obj\tftpserver.o: G:\keil\ARM\RV31\INC\string.h
diff --git a/F107/Project/RVMDK/Obj/tftpserver.o b/F107/Project/RVMDK/Obj/tftpserver.o
new file mode 100644
index 0000000..53aa161
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tftpserver.o differ
diff --git a/F107/Project/RVMDK/Obj/tftputils.__i b/F107/Project/RVMDK/Obj/tftputils.__i
new file mode 100644
index 0000000..b04bf39
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tftputils.__i
@@ -0,0 +1 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface --diag_suppress 236 -I "G:\keil\ARM\INC" -I "G:\keil\ARM\INC\ST\STM32F10x" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\tftputils.o" --omf_browse ".\Obj\tftputils.crf" --depend ".\Obj\tftputils.d" "..\..\Utilities\lwip-1.3.1\port\tftputils.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/tftputils.crf b/F107/Project/RVMDK/Obj/tftputils.crf
new file mode 100644
index 0000000..a2dee42
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tftputils.crf differ
diff --git a/F107/Project/RVMDK/Obj/tftputils.d b/F107/Project/RVMDK/Obj/tftputils.d
new file mode 100644
index 0000000..861368c
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/tftputils.d
@@ -0,0 +1,19 @@
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\port\tftputils.c
+.\Obj\tftputils.o: G:\keil\ARM\RV31\INC\string.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\port\tftputils.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\Obj\tftputils.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
diff --git a/F107/Project/RVMDK/Obj/tftputils.o b/F107/Project/RVMDK/Obj/tftputils.o
new file mode 100644
index 0000000..772ec0a
Binary files /dev/null and b/F107/Project/RVMDK/Obj/tftputils.o differ
diff --git a/F107/Project/RVMDK/Obj/time.crf b/F107/Project/RVMDK/Obj/time.crf
new file mode 100644
index 0000000..40009c4
Binary files /dev/null and b/F107/Project/RVMDK/Obj/time.crf differ
diff --git a/F107/Project/RVMDK/Obj/time.d b/F107/Project/RVMDK/Obj/time.d
new file mode 100644
index 0000000..6e81071
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/time.d
@@ -0,0 +1,4 @@
+.\Obj\time.o: ..\..\Utilities\efsl\source\time.c
+.\Obj\time.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\time.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\time.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/time.o b/F107/Project/RVMDK/Obj/time.o
new file mode 100644
index 0000000..1484597
Binary files /dev/null and b/F107/Project/RVMDK/Obj/time.o differ
diff --git a/F107/Project/RVMDK/Obj/udp.crf b/F107/Project/RVMDK/Obj/udp.crf
new file mode 100644
index 0000000..a63336d
Binary files /dev/null and b/F107/Project/RVMDK/Obj/udp.crf differ
diff --git a/F107/Project/RVMDK/Obj/udp.d b/F107/Project/RVMDK/Obj/udp.d
new file mode 100644
index 0000000..364b964
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/udp.d
@@ -0,0 +1,25 @@
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\core\udp.c
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet_chksum.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/stats.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/snmp.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\port\arch/perf.h
+.\obj\udp.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/dhcp.h
+.\obj\udp.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
diff --git a/F107/Project/RVMDK/Obj/udp.o b/F107/Project/RVMDK/Obj/udp.o
new file mode 100644
index 0000000..a830547
Binary files /dev/null and b/F107/Project/RVMDK/Obj/udp.o differ
diff --git a/F107/Project/RVMDK/Obj/ui.crf b/F107/Project/RVMDK/Obj/ui.crf
new file mode 100644
index 0000000..23cfe21
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ui.crf differ
diff --git a/F107/Project/RVMDK/Obj/ui.d b/F107/Project/RVMDK/Obj/ui.d
new file mode 100644
index 0000000..d37e02e
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/ui.d
@@ -0,0 +1,34 @@
+.\Obj\ui.o: ..\..\Utilities\efsl\source\ui.c
+.\Obj\ui.o: ..\..\Utilities\efsl\include\ui.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\fs.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\error.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\interface.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\types.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\interface\sd_stm32.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\interface\../debug.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\interface\../config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\partition.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\ioman.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\plibc.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\extract.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\disc.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\time.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\file.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\dir.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\fat.h
+.\Obj\ui.o: ..\..\Utilities\efsl\include\config.h
diff --git a/F107/Project/RVMDK/Obj/ui.o b/F107/Project/RVMDK/Obj/ui.o
new file mode 100644
index 0000000..3ec8cc8
Binary files /dev/null and b/F107/Project/RVMDK/Obj/ui.o differ
diff --git a/F107/Project/RVMDK/Obj/usart.__i b/F107/Project/RVMDK/Obj/usart.__i
new file mode 100644
index 0000000..d3a1a6a
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/usart.__i
@@ -0,0 +1,6 @@
+-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I ..\inc -I ..\..\Utilities\STM32_EVAL -I ..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I ..\..\Libraries\STM32_ETH_Driver\inc -I ..\..\Libraries\CMSIS\Core\CM3 -I ..\..\Utilities\lwip-1.3.1\port\ -I ..\..\Utilities\lwip-1.3.1\src\include -I ..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I ..\..\Utilities\lwip-1.3.1\src\include\lwip -I ..\..\Utilities\efsl\include -I ..\..\Utilities\efsl\include\interface -I ..\src -I ..\..\Basic\delay -I ..\..\Hardware\LED -I ..\..\Basic\usart --diag_suppress 236
+-IG:\Keil_v5\ARM\RV31\INC
+-IG:\Keil_v5\ARM\CMSIS\Include
+-IG:\Keil_v5\ARM\INC\ST\STM32F10x
+-D__UVISION_VERSION="525" -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL
+-o .\obj\usart.o --omf_browse .\obj\usart.crf --depend .\obj\usart.d "..\..\Basic\usart\usart.c"
\ No newline at end of file
diff --git a/F107/Project/RVMDK/Obj/usart.crf b/F107/Project/RVMDK/Obj/usart.crf
new file mode 100644
index 0000000..d0826fd
Binary files /dev/null and b/F107/Project/RVMDK/Obj/usart.crf differ
diff --git a/F107/Project/RVMDK/Obj/usart.d b/F107/Project/RVMDK/Obj/usart.d
new file mode 100644
index 0000000..50eece4
--- /dev/null
+++ b/F107/Project/RVMDK/Obj/usart.d
@@ -0,0 +1,55 @@
+.\obj\usart.o: ..\..\Basic\usart\usart.c
+.\obj\usart.o: ..\inc\main.h
+.\obj\usart.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\usart.o: ..\..\Libraries\CMSIS\Core\CM3\core_cm3.h
+.\obj\usart.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h
+.\obj\usart.o: ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h
+.\obj\usart.o: ..\inc\stm32f10x_conf.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h
+.\obj\usart.o: ..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h
+.\obj\usart.o: ..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h
+.\obj\usart.o: ..\inc\stm32f107.h
+.\obj\usart.o: ..\..\Utilities\STM32_EVAL\stm32_eval.h
+.\obj\usart.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval.h
+.\obj\usart.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.h
+.\obj\usart.o: ..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.h
+.\obj\usart.o: ..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h
+.\obj\usart.o: ..\inc\netconf.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\port\helloworld.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\port\httpd.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/arch.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\port\arch/cc.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\port\arch/cpu.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\port\fsdata.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\port\tftpserver.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/mem.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/opt.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\port\lwipopts.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/debug.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/udp.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/pbuf.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/netif.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip_addr.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/inet.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/ip.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h
+.\obj\usart.o: ..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h
+.\obj\usart.o: ..\src\TCP_CLIENT.h
+.\obj\usart.o: ..\..\Basic\usart\usart.h
+.\obj\usart.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h
+.\obj\usart.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdlib.h
+.\obj\usart.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h
+.\obj\usart.o: G:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h
+.\obj\usart.o: ..\..\Basic\delay\delay.h
+.\obj\usart.o: ..\..\Hardware\LED\led.h
diff --git a/F107/Project/RVMDK/Obj/usart.o b/F107/Project/RVMDK/Obj/usart.o
new file mode 100644
index 0000000..22e40ac
Binary files /dev/null and b/F107/Project/RVMDK/Obj/usart.o differ
diff --git a/F107/Project/RVMDK/Project.Uv2.bak b/F107/Project/RVMDK/Project.Uv2.bak
new file mode 100644
index 0000000..c2388f6
--- /dev/null
+++ b/F107/Project/RVMDK/Project.Uv2.bak
@@ -0,0 +1,179 @@
+### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+Target (STM3210C-EVAL), 0x0004 // Tools: 'ARM-ADS'
+
+Group (User)
+Group (STM32F10x_StdPeriph_Driver)
+Group (STM32_ETH_Driver)
+Group (STM32_EVAL)
+Group (LwIP)
+Group (efsl)
+Group (CMSIS)
+Group (RVMDK)
+
+File 1,1,<..\src\stm32f10x_it.c>
+File 1,1,<..\src\main.c>
+File 1,1,<..\src\stm32f107.c>
+File 1,1,<..\src\netconf.c>
+File 1,1,<..\..\Utilities\lwip-1.3.1\port\helloworld.c>
+File 1,1,<..\..\Utilities\lwip-1.3.1\port\httpd.c>
+File 1,1,<..\..\Utilities\lwip-1.3.1\port\tftpserver.c>
+File 1,1,<..\..\Utilities\lwip-1.3.1\port\tftputils.c>
+File 1,1,<..\..\Utilities\lwip-1.3.1\port\client.c>
+File 1,1,<..\..\Utilities\lwip-1.3.1\port\server.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c>
+File 2,1,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c>
+File 3,1,<..\..\Libraries\STM32_ETH_Driver\src\stm32_eth.c>
+File 4,1,<..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.c>
+File 4,1,<..\..\Utilities\STM32_EVAL\stm32_eval.c>
+File 4,1,<..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\port\ethernetif.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\api\tcpip.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\api\api_lib.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\api\netbuf.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\api\netifapi.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\api\netdb.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\api\api_msg.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\api\err.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\stats.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\sys.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\tcp.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\tcp_in.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\tcp_out.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\udp.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\dhcp.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\init.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\mem.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\memp.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\netif.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\pbuf.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\raw.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\autoip.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\icmp.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\igmp.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet_chksum.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_addr.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_frag.c>
+File 5,1,<..\..\Utilities\lwip-1.3.1\src\netif\etharp.c>
+File 6,1,<..\..\Utilities\efsl\source\dir.c>
+File 6,1,<..\..\Utilities\efsl\source\disc.c>
+File 6,1,<..\..\Utilities\efsl\source\efs.c>
+File 6,1,<..\..\Utilities\efsl\source\extract.c>
+File 6,1,<..\..\Utilities\efsl\source\fat.c>
+File 6,1,<..\..\Utilities\efsl\source\file.c>
+File 6,1,<..\..\Utilities\efsl\source\fs.c>
+File 6,1,<..\..\Utilities\efsl\source\ioman.c>
+File 6,1,<..\..\Utilities\efsl\source\ls.c>
+File 6,1,<..\..\Utilities\efsl\source\mkfs.c>
+File 6,1,<..\..\Utilities\efsl\source\partition.c>
+File 6,1,<..\..\Utilities\efsl\source\plibc.c>
+File 6,1,<..\..\Utilities\efsl\source\time.c>
+File 6,1,<..\..\Utilities\efsl\source\ui.c>
+File 6,1,<..\..\Utilities\efsl\source\interface\sd.c>
+File 6,1,<..\..\Utilities\efsl\source\interface\sd_stm32.c>
+File 7,1,<..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c>
+File 7,1,<..\..\Libraries\CMSIS\Core\CM3\core_cm3.c>
+File 8,2,<..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s>
+
+
+Options 1,0,0 // Target 'STM3210C-EVAL'
+ Device (STM32F107xC)
+ Vendor (STMicroelectronics)
+ Cpu (IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3"))
+ FlashUt ()
+ StupF ("STARTUP\ST\STM32F10x.s" ("STM32 Startup Code"))
+ FlashDR (UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_256 -FS08000000 -FL080000))
+ DevID (0)
+ Rgf (stm32f10x_lib.h)
+ Mem ()
+ C ()
+ A ()
+ RL ()
+ OH ()
+ DBC_IFX ()
+ DBC_CMS ()
+ DBC_AMS ()
+ DBC_LMS ()
+ UseEnv=0
+ EnvBin ()
+ EnvInc ()
+ EnvLib ()
+ EnvReg (ST\STM32F10x\)
+ OrgReg (ST\STM32F10x\)
+ TgStat=16
+ OutDir (.\Obj\)
+ OutName (STM3210C-EVAL)
+ GenApp=1
+ GenLib=0
+ GenHex=0
+ Debug=1
+ Browse=1
+ LstDir (.\List\)
+ HexSel=1
+ MG32K=0
+ TGMORE=0
+ RunUsr 0 0 <>
+ RunUsr 1 0 <>
+ BrunUsr 0 0 <>
+ BrunUsr 1 0 <>
+ CrunUsr 0 0 <>
+ CrunUsr 1 0 <>
+ SVCSID <>
+ GLFLAGS=1790
+ ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ACPUTYP ("Cortex-M3")
+ RVDEV ()
+ ADSTFLGA { 0,12,0,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ OCMADSIRAM { 0,0,0,0,32,0,0,1,0 }
+ OCMADSIROM { 1,0,0,0,8,0,0,4,0 }
+ OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
+ OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,8,0,0,4,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,32,0,0,1,0,0,0,0,0,0,0,0,0,0 }
+ RV_STAVEC ()
+ ADSCCFLG { 13,32,0,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSCMISC (--diag_suppress 236)
+ ADSCDEFN (USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL)
+ ADSCUDEF ()
+ ADSCINCD (..\inc;..\..\Utilities\STM32_EVAL;..\..\Utilities\STM32_EVAL\STM3210C_EVAL;..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\Libraries\STM32_ETH_Driver\inc;..\..\Libraries\CMSIS\Core\CM3;..\..\Utilities\lwip-1.3.1\port\;..\..\Utilities\lwip-1.3.1\src\include;..\..\Utilities\lwip-1.3.1\src\include\ipv4;..\..\Utilities\lwip-1.3.1\src\include\lwip;..\..\Utilities\efsl\include;..\..\Utilities\efsl\include\interface)
+ ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSAMISC ()
+ ADSADEFN ()
+ ADSAUDEF ()
+ ADSAINCD ()
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ IncBld=1
+ AlwaysBuild=0
+ GenAsm=0
+ AsmAsm=0
+ PublicsOnly=0
+ StopCode=3
+ CustArgs ()
+ LibMods ()
+ ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
+ ADSLDTA (0x08000000)
+ ADSLDDA (0x20000000)
+ ADSLDSC ()
+ ADSLDIB ()
+ ADSLDIC ()
+ ADSLDMC ()
+ ADSLDIF ()
+ ADSLDDW ()
+ OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F107xCSchedule)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F107xC)
+ OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
+ FLASH1 { 9,0,0,0,1,0,0,0,1,16,0,0,0,0,0,0,0,0,0,0 }
+ FLASH2 (BIN\UL2CM3.DLL)
+ FLASH3 ()
+ FLASH4 ()
+EndOpt
+
diff --git a/F107/Project/RVMDK/Project.opt.bak b/F107/Project/RVMDK/Project.opt.bak
new file mode 100644
index 0000000..745b590
--- /dev/null
+++ b/F107/Project/RVMDK/Project.opt.bak
@@ -0,0 +1,119 @@
+### uVision2 Project, (C) Keil Software
+### Do not modify !
+
+ cExt (*.c)
+ aExt (*.s*; *.src; *.a*)
+ oExt (*.obj)
+ lExt (*.lib)
+ tExt (*.txt; *.h; *.inc)
+ pExt (*.plm)
+ CppX (*.cpp)
+ DaveTm { 0,0,0,0,0,0,0,0 }
+
+Target (STM3210C-EVAL), 0x0004 // Tools: 'ARM-ADS'
+GRPOPT 1,(User),1,0,0
+GRPOPT 2,(STM32F10x_StdPeriph_Driver),0,0,0
+GRPOPT 3,(STM32_ETH_Driver),0,0,0
+GRPOPT 4,(STM32_EVAL),0,0,0
+GRPOPT 5,(LwIP),0,0,0
+GRPOPT 6,(efsl),0,0,0
+GRPOPT 7,(CMSIS),0,0,0
+GRPOPT 8,(RVMDK),0,0,0
+
+OPTFFF 1,1,1,687865856,0,0,0,0,<..\src\stm32f10x_it.c>
+OPTFFF 1,2,1,67108866,0,1,1,0,<..\src\main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,226,255,255,255,66,0,0,0,87,0,0,0,95,3,0,0,195,1,0,0 }
+OPTFFF 1,3,1,469762048,0,0,0,0,<..\src\stm32f107.c>
+OPTFFF 1,4,1,637534208,0,0,0,0,<..\src\netconf.c>
+OPTFFF 1,5,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\port\helloworld.c>
+OPTFFF 1,6,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\port\httpd.c>
+OPTFFF 1,7,1,587202560,0,0,0,0,<..\..\Utilities\lwip-1.3.1\port\tftpserver.c>
+OPTFFF 1,8,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\port\tftputils.c>
+OPTFFF 1,9,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\port\client.c>
+OPTFFF 1,10,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\port\server.c>
+OPTFFF 2,11,1,167772160,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c>
+OPTFFF 2,12,1,0,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c>
+OPTFFF 2,13,1,83886080,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c>
+OPTFFF 2,14,1,0,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c>
+OPTFFF 2,15,1,0,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c>
+OPTFFF 2,16,1,0,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c>
+OPTFFF 2,17,1,83886080,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c>
+OPTFFF 2,18,1,0,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c>
+OPTFFF 2,19,1,0,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c>
+OPTFFF 2,20,1,0,0,0,0,0,<..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c>
+OPTFFF 3,21,1,989855744,0,0,0,0,<..\..\Libraries\STM32_ETH_Driver\src\stm32_eth.c>
+OPTFFF 4,22,1,33554432,0,0,0,0,<..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_ioe.c>
+OPTFFF 4,23,1,150994944,0,0,0,0,<..\..\Utilities\STM32_EVAL\stm32_eval.c>
+OPTFFF 4,24,1,0,0,0,0,0,<..\..\Utilities\STM32_EVAL\STM3210C_EVAL\stm3210c_eval_lcd.c>
+OPTFFF 5,25,1,1895825408,0,0,0,0,<..\..\Utilities\lwip-1.3.1\port\ethernetif.c>
+OPTFFF 5,26,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\api\tcpip.c>
+OPTFFF 5,27,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\api\api_lib.c>
+OPTFFF 5,28,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\api\netbuf.c>
+OPTFFF 5,29,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\api\netifapi.c>
+OPTFFF 5,30,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\api\netdb.c>
+OPTFFF 5,31,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\api\api_msg.c>
+OPTFFF 5,32,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\api\err.c>
+OPTFFF 5,33,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\stats.c>
+OPTFFF 5,34,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\sys.c>
+OPTFFF 5,35,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\tcp.c>
+OPTFFF 5,36,1,1442840576,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\tcp_in.c>
+OPTFFF 5,37,1,150994944,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\tcp_out.c>
+OPTFFF 5,38,1,352321536,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\udp.c>
+OPTFFF 5,39,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\dhcp.c>
+OPTFFF 5,40,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\init.c>
+OPTFFF 5,41,1,402653184,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\mem.c>
+OPTFFF 5,42,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\memp.c>
+OPTFFF 5,43,1,637534208,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\netif.c>
+OPTFFF 5,44,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\pbuf.c>
+OPTFFF 5,45,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\raw.c>
+OPTFFF 5,46,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\autoip.c>
+OPTFFF 5,47,1,369098752,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\icmp.c>
+OPTFFF 5,48,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\igmp.c>
+OPTFFF 5,49,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet.c>
+OPTFFF 5,50,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet_chksum.c>
+OPTFFF 5,51,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip.c>
+OPTFFF 5,52,1,536870912,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_addr.c>
+OPTFFF 5,53,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_frag.c>
+OPTFFF 5,54,1,0,0,0,0,0,<..\..\Utilities\lwip-1.3.1\src\netif\etharp.c>
+OPTFFF 6,55,1,0,0,0,0,0,<..\..\Utilities\efsl\source\dir.c>
+OPTFFF 6,56,1,0,0,0,0,0,<..\..\Utilities\efsl\source\disc.c>
+OPTFFF 6,57,1,0,0,0,0,0,<..\..\Utilities\efsl\source\efs.c>
+OPTFFF 6,58,1,0,0,0,0,0,<..\..\Utilities\efsl\source\extract.c>
+OPTFFF 6,59,1,0,0,0,0,0,<..\..\Utilities\efsl\source\fat.c>
+OPTFFF 6,60,1,0,0,0,0,0,<..\..\Utilities\efsl\source\file.c>
+OPTFFF 6,61,1,0,0,0,0,0,<..\..\Utilities\efsl\source\fs.c>
+OPTFFF 6,62,1,0,0,0,0,0,<..\..\Utilities\efsl\source\ioman.c>
+OPTFFF 6,63,1,0,0,0,0,0,<..\..\Utilities\efsl\source\ls.c>
+OPTFFF 6,64,1,0,0,0,0,0,<..\..\Utilities\efsl\source\mkfs.c>
+OPTFFF 6,65,1,0,0,0,0,0,<..\..\Utilities\efsl\source\partition.c>
+OPTFFF 6,66,1,0,0,0,0,0,<..\..\Utilities\efsl\source\plibc.c>
+OPTFFF 6,67,1,0,0,0,0,0,<..\..\Utilities\efsl\source\time.c>
+OPTFFF 6,68,1,0,0,0,0,0,<..\..\Utilities\efsl\source\ui.c>
+OPTFFF 6,69,1,0,0,0,0,0,<..\..\Utilities\efsl\source\interface\sd.c>
+OPTFFF 6,70,1,0,0,0,0,0,<..\..\Utilities\efsl\source\interface\sd_stm32.c>
+OPTFFF 7,71,1,0,0,0,0,0,<..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c>
+OPTFFF 7,72,1,0,0,0,0,0,<..\..\Libraries\CMSIS\Core\CM3\core_cm3.c>
+OPTFFF 8,73,2,218103808,0,0,0,0,<..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s>
+
+
+TARGOPT 1, (STM3210C-EVAL)
+ ADSCLK=8000000
+ OPTTT 1,1,1,0
+ OPTHX 1,65535,0,0,0
+ OPTLX 79,66,8,<.\List\>
+ OPTOX 16
+ OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
+ OPTXL 1,1,1,1,1,1,1,0,0
+ OPTFL 1,0,1
+ OPTAX 0
+ OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F107xCSchedule)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F107xC)
+ OPTDBG 49150,1,()()()()()()()()()() (BIN\UL2CM3.DLL)()()()
+ OPTKEY 0,(DLGTARM)((1010=77,100,443,650,0)(1007=105,140,282,408,0)(1008=105,727,471,956,0)(1009=120,156,354,697,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(124=-1,-1,-1,-1,0)(125=-1,-1,-1,-1,0)(126=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0))
+ OPTKEY 0,(ARMDBGFLAGS)()
+ OPTKEY 0,(DLGUARM)((105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0))
+ OPTKEY 0,(UL2CM3)(-UM0079A9E -O14 -S0 -C0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000)
+ OPTWA 0,1,(data)
+ OPTDF 0x40000084
+ OPTLE <>
+ OPTLC <>
+EndOpt
+
diff --git a/F107/Project/RVMDK/Project.uvgui.Administrator b/F107/Project/RVMDK/Project.uvgui.Administrator
new file mode 100644
index 0000000..de4cb5e
--- /dev/null
+++ b/F107/Project/RVMDK/Project.uvgui.Administrator
@@ -0,0 +1,1396 @@
+
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new file mode 100644
index 0000000..2d0a5e7
--- /dev/null
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@@ -0,0 +1,1352 @@
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+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_addr.c
+ ip_addr.c
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+
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+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_frag.c
+ ip_frag.c
+ 0
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+
+ 4
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+ 0
+ ..\..\Utilities\lwip-1.3.1\src\netif\etharp.c
+ etharp.c
+ 0
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+
+
+
+
+ CMSIS
+ 1
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+ 5
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+ ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c
+ system_stm32f10x.c
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+
+ 5
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+ ..\..\Libraries\CMSIS\Core\CM3\core_cm3.c
+ core_cm3.c
+ 0
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+
+
+
+
+ RVMDK
+ 0
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+
+ 6
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+ 2
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+ 0
+ ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s
+ startup_stm32f10x_cl.s
+ 0
+ 0
+
+
+
+
+ Hardware
+ 1
+ 0
+ 0
+ 0
+
+ 7
+ 53
+ 1
+ 0
+ 0
+ 0
+ ..\..\Hardware\LED\led.c
+ led.c
+ 0
+ 0
+
+
+
+
+ Basic
+ 1
+ 0
+ 0
+ 0
+
+ 8
+ 54
+ 1
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+ ..\..\Basic\delay\delay.c
+ delay.c
+ 0
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+
+
+ 8
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+ 1
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+ ..\..\Basic\usart\usart.c
+ usart.c
+ 0
+ 0
+
+
+
+
diff --git a/F107/Project/RVMDK/Project.uvproj b/F107/Project/RVMDK/Project.uvproj
new file mode 100644
index 0000000..f563126
--- /dev/null
+++ b/F107/Project/RVMDK/Project.uvproj
@@ -0,0 +1,739 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ STM32107VCT6
+ 0x4
+ ARM-ADS
+ 5060750::V5.06 update 6 (build 750)::ARMCC
+ 0
+
+
+ STM32F107VC
+ STMicroelectronics
+ IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")
+
+ "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")
+ UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000)
+ 4889
+ stm32f10x_lib.h
+
+
+
+
+
+
+
+
+
+ SFD\ST\STM32F107x\STM32F107.sfr
+ 0
+ 0
+
+
+
+ ST\STM32F10x\
+ ST\STM32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Obj\
+ STM3210C-EVAL
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\List\
+ 1
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+ 0
+
+ 0
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+
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+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+ 1
+
+
+ SARMCM3.DLL
+ -REMAP
+ DARMSTM.DLL
+ -pSTM32F107VC
+ SARMCM3.DLL
+
+ TARMSTM.DLL
+ -pSTM32F107VC
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
+ 0
+ 1
+
+ 0
+ 4
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Segger\JL2CM3.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4099
+
+ 0
+ Segger\JL2CM3.dll
+ "" ()
+
+
+
+
+ 0
+
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
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+ 0
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+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
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+ 0
+ 2
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+
+ --diag_suppress 236
+ USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL
+
+ ..\inc;..\..\Utilities\STM32_EVAL;..\..\Utilities\STM32_EVAL\STM3210C_EVAL;..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\Libraries\STM32_ETH_Driver\inc;..\..\Libraries\CMSIS\Core\CM3;..\..\Utilities\lwip-1.3.1\port\;..\..\Utilities\lwip-1.3.1\src\include;..\..\Utilities\lwip-1.3.1\src\include\ipv4;..\..\Utilities\lwip-1.3.1\src\include\lwip;..\..\Utilities\efsl\include;..\..\Utilities\efsl\include\interface;..\src;..\..\Basic\delay;..\..\Hardware\LED;..\..\Basic\usart
+
+
+
+ 1
+ 0
+ 0
+ 0
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+
+
+
+
+
+
+
+ 1
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+ 0
+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+
+ User
+
+
+ stm32f10x_it.c
+ 1
+ ..\src\stm32f10x_it.c
+
+
+ main.c
+ 1
+ ..\src\main.c
+
+
+ stm32f107.c
+ 1
+ ..\src\stm32f107.c
+
+
+ netconf.c
+ 1
+ ..\src\netconf.c
+
+
+ TCP_CLIENT.C
+ 1
+ ..\src\TCP_CLIENT.C
+
+
+ HX711.c
+ 1
+ ..\src\HX711.c
+
+
+ sys.c
+ 1
+ ..\src\sys.c
+
+
+ SCI.c
+ 1
+ ..\src\SCI.c
+
+
+
+
+ STM32F10x_StdPeriph_Driver
+
+
+ stm32f10x_usart.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+
+
+ stm32f10x_gpio.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+
+
+ stm32f10x_rcc.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+
+
+ stm32f10x_spi.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+
+
+ stm32f10x_exti.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c
+
+
+ stm32f10x_flash.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+
+
+ misc.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+
+
+ stm32f10x_adc.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c
+
+
+ stm32f10x_tim.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+
+
+ stm32f10x_i2c.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c
+
+
+
+
+ STM32_ETH_Driver
+
+
+ stm32_eth.c
+ 1
+ ..\..\Libraries\STM32_ETH_Driver\src\stm32_eth.c
+
+
+
+
+ LwIP
+
+
+ ethernetif.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\port\ethernetif.c
+
+
+ tcpip.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\tcpip.c
+
+
+ api_lib.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\api_lib.c
+
+
+ netbuf.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\netbuf.c
+
+
+ netifapi.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\netifapi.c
+
+
+ netdb.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\netdb.c
+
+
+ api_msg.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\api_msg.c
+
+
+ err.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\err.c
+
+
+ stats.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\stats.c
+
+
+ sys.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\sys.c
+
+
+ tcp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\tcp.c
+
+
+ tcp_in.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\tcp_in.c
+
+
+ tcp_out.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\tcp_out.c
+
+
+ udp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\udp.c
+
+
+ dhcp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\dhcp.c
+
+
+ init.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\init.c
+
+
+ mem.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\mem.c
+
+
+ memp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\memp.c
+
+
+ netif.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\netif.c
+
+
+ pbuf.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\pbuf.c
+
+
+ raw.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\raw.c
+
+
+ autoip.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\autoip.c
+
+
+ icmp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\icmp.c
+
+
+ igmp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\igmp.c
+
+
+ inet.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet.c
+
+
+ inet_chksum.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet_chksum.c
+
+
+ ip.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip.c
+
+
+ ip_addr.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_addr.c
+
+
+ ip_frag.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_frag.c
+
+
+ etharp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\netif\etharp.c
+
+
+
+
+ CMSIS
+
+
+ system_stm32f10x.c
+ 1
+ ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c
+
+
+ core_cm3.c
+ 1
+ ..\..\Libraries\CMSIS\Core\CM3\core_cm3.c
+
+
+
+
+ RVMDK
+
+
+ startup_stm32f10x_cl.s
+ 2
+ ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s
+
+
+
+
+ Hardware
+
+
+ led.c
+ 1
+ ..\..\Hardware\LED\led.c
+
+
+
+
+ Basic
+
+
+ delay.c
+ 1
+ ..\..\Basic\delay\delay.c
+
+
+ usart.c
+ 1
+ ..\..\Basic\usart\usart.c
+
+
+
+
+
+
+
+
diff --git a/F107/Project/RVMDK/Project_STM32107VCT6.dep b/F107/Project/RVMDK/Project_STM32107VCT6.dep
new file mode 100644
index 0000000..64c7da3
--- /dev/null
+++ b/F107/Project/RVMDK/Project_STM32107VCT6.dep
@@ -0,0 +1,941 @@
+Dependencies for Project 'Project', Target 'STM32107VCT6': (DO NOT MODIFY !)
+F (..\src\stm32f10x_it.c)(0x51FBBCC4)(-c --cpu Cortex-M3 -g -O2 --apcs=interwork --split_sections -I..\inc -I..\..\Utilities\STM32_EVAL -I..\..\Utilities\STM32_EVAL\STM3210C_EVAL -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Libraries\STM32_ETH_Driver\inc -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Utilities\lwip-1.3.1\port\ -I..\..\Utilities\lwip-1.3.1\src\include -I..\..\Utilities\lwip-1.3.1\src\include\ipv4 -I..\..\Utilities\lwip-1.3.1\src\include\lwip -I..\..\Utilities\efsl\include -I..\..\Utilities\efsl\include\interface -I..\src --diag_suppress 236 -I D:\Keil\ARM\RV31\Inc -I D:\Keil\ARM\CMSIS\Include -I D:\Keil\ARM\Inc\ST\STM32F10x -DUSE_STDPERIPH_DRIVER -DSTM32F10X_CL -DUSE_STM3210C_EVAL -o ".\Obj\stm32f10x_it.o" --omf_browse ".\Obj\stm32f10x_it.crf" --depend ".\Obj\stm32f10x_it.d")
+I (..\inc\stm32f10x_it.h)(0x4B065C40)
+I (..\..\Libraries\CMSIS\Core\CM3\stm32f10x.h)(0x5182792A)
+I (..\..\Libraries\CMSIS\Core\CM3\core_cm3.h)(0x4B065C3E)
+I (D:\Keil\ARM\RV31\Inc\stdint.h)(0x4F58357C)
+I (..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.h)(0x4B065C3E)
+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_adc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_exti.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_flash.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_gpio.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_i2c.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_rcc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\misc.h)(0x4B065C3E)
+I (..\..\Libraries\STM32_ETH_Driver\inc\stm32_eth.h)(0x4B065C3E)
+I (..\inc\main.h)(0x5732E09E)
+I (..\inc\stm32f107.h)(0x4B065C40)
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+I (..\..\Utilities\lwip-1.3.1\port\helloworld.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\httpd.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/def.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\port\tftpserver.h)(0x4B065C40)
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+I (..\..\Utilities\lwip-1.3.1\src\include\ipv4\lwip/icmp.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
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+I (..\src\TCP_CLIENT.h)(0x585B3E58)
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+I (D:\Keil\ARM\RV31\Inc\stdint.h)(0x4F58357C)
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+I (..\inc\stm32f10x_conf.h)(0x4B065C40)
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+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_tim.h)(0x4B065C3E)
+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_usart.h)(0x4B065C3E)
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+I (..\inc\stm32f107.h)(0x4B065C40)
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+I (..\..\Utilities\lwip-1.3.1\port\lwipopts.h)(0x51FBA104)
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+I (..\..\Utilities\lwip-1.3.1\port\arch/cc.h)(0x4B065C40)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/memp_std.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/tcp.h)(0x4B065C42)
+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/sys.h)(0x4B065C42)
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+I (..\..\Utilities\lwip-1.3.1\src\include\lwip/err.h)(0x4B065C42)
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+I (..\..\Libraries\STM32F10x_StdPeriph_Driver\inc\stm32f10x_spi.h)(0x4B065C3E)
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+I (..\..\Utilities\lwip-1.3.1\port\helloworld.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\httpd.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\fsdata.h)(0x4B065C40)
+I (..\..\Utilities\lwip-1.3.1\port\tftpserver.h)(0x4B065C40)
+I (..\src\TCP_CLIENT.h)(0x585B3E58)
+I (D:\Keil\ARM\RV31\Inc\stdio.h)(0x4F58357C)
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+ autoip.c
+
+
+ 4
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+ 1
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+ 0
+ 0
+ 0
+ 0
+ 0
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+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\icmp.c
+ icmp.c
+
+
+ 4
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+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\igmp.c
+ igmp.c
+
+
+ 4
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+ 1
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+ 0
+ 0
+ 0
+ 0
+ 0
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+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet.c
+ inet.c
+
+
+ 4
+ 43
+ 1
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+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet_chksum.c
+ inet_chksum.c
+
+
+ 4
+ 44
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip.c
+ ip.c
+
+
+ 4
+ 45
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_addr.c
+ ip_addr.c
+
+
+ 4
+ 46
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_frag.c
+ ip_frag.c
+
+
+ 4
+ 47
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Utilities\lwip-1.3.1\src\netif\etharp.c
+ etharp.c
+
+
+
+
+ CMSIS
+ 1
+ 0
+ 0
+
+ 5
+ 48
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c
+ system_stm32f10x.c
+
+
+ 5
+ 49
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Libraries\CMSIS\Core\CM3\core_cm3.c
+ core_cm3.c
+
+
+
+
+ RVMDK
+ 0
+ 0
+ 0
+
+ 6
+ 50
+ 2
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s
+ startup_stm32f10x_cl.s
+
+
+
+
diff --git a/F107/Project/RVMDK/Project_uvproj.bak b/F107/Project/RVMDK/Project_uvproj.bak
new file mode 100644
index 0000000..2bea4a7
--- /dev/null
+++ b/F107/Project/RVMDK/Project_uvproj.bak
@@ -0,0 +1,679 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ STM32107VCT6
+ 0x4
+ ARM-ADS
+
+
+ STM32F107VC
+ STMicroelectronics
+ IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")
+
+ "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code")
+ UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000)
+ 4889
+ stm32f10x_lib.h
+
+
+
+
+
+
+
+
+
+ SFD\ST\STM32F107x\STM32F107.sfr
+ 0
+
+
+
+ ST\STM32F10x\
+ ST\STM32F10x\
+
+ 0
+ 0
+ 0
+ 0
+ 1
+
+ .\Obj\
+ STM3210C-EVAL
+ 1
+ 0
+ 1
+ 1
+ 1
+ .\List\
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+ 0
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+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 3
+
+
+
+
+ SARMCM3.DLL
+
+ DARMSTM.DLL
+ -pSTM32F107VC
+ SARMCM3.DLL
+
+ TARMSTM.DLL
+ -pSTM32F107VC
+
+
+
+ 1
+ 0
+ 0
+ 0
+ 16
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
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+ 1
+
+ 0
+ 7
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Segger\JL2CM3.dll
+
+
+
+
+ 1
+ 0
+ 0
+ 1
+ 1
+ 4099
+
+ Segger\JL2CM3.dll
+ "" ()
+
+
+
+
+ 0
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+ 1
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+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+ "Cortex-M3"
+
+ 0
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+
+
+ 1
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+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 2
+ 0
+ 0
+
+ --diag_suppress 236
+ USE_STDPERIPH_DRIVER, STM32F10X_CL, USE_STM3210C_EVAL
+
+ ..\inc;..\..\Utilities\STM32_EVAL;..\..\Utilities\STM32_EVAL\STM3210C_EVAL;..\..\Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\Libraries\STM32_ETH_Driver\inc;..\..\Libraries\CMSIS\Core\CM3;..\..\Utilities\lwip-1.3.1\port\;..\..\Utilities\lwip-1.3.1\src\include;..\..\Utilities\lwip-1.3.1\src\include\ipv4;..\..\Utilities\lwip-1.3.1\src\include\lwip;..\..\Utilities\efsl\include;..\..\Utilities\efsl\include\interface;..\src
+
+
+
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+ 1
+ 0
+ 0x08000000
+ 0x20000000
+
+
+
+
+
+
+
+
+
+
+
+ User
+
+
+ stm32f10x_it.c
+ 1
+ ..\src\stm32f10x_it.c
+
+
+ main.c
+ 1
+ ..\src\main.c
+
+
+ stm32f107.c
+ 1
+ ..\src\stm32f107.c
+
+
+ netconf.c
+ 1
+ ..\src\netconf.c
+
+
+ SCI.c
+ 1
+ ..\src\SCI.c
+
+
+ readme.txt
+ 5
+ ..\..\readme.txt
+
+
+ TCP_CLIENT.C
+ 1
+ ..\src\TCP_CLIENT.C
+
+
+
+
+ STM32F10x_StdPeriph_Driver
+
+
+ stm32f10x_usart.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c
+
+
+ stm32f10x_gpio.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c
+
+
+ stm32f10x_rcc.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c
+
+
+ stm32f10x_spi.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c
+
+
+ stm32f10x_exti.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c
+
+
+ stm32f10x_flash.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c
+
+
+ misc.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\misc.c
+
+
+ stm32f10x_adc.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c
+
+
+ stm32f10x_tim.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c
+
+
+ stm32f10x_i2c.c
+ 1
+ ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c
+
+
+
+
+ STM32_ETH_Driver
+
+
+ stm32_eth.c
+ 1
+ ..\..\Libraries\STM32_ETH_Driver\src\stm32_eth.c
+
+
+
+
+ LwIP
+
+
+ ethernetif.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\port\ethernetif.c
+
+
+ tcpip.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\tcpip.c
+
+
+ api_lib.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\api_lib.c
+
+
+ netbuf.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\netbuf.c
+
+
+ netifapi.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\netifapi.c
+
+
+ netdb.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\netdb.c
+
+
+ api_msg.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\api_msg.c
+
+
+ err.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\api\err.c
+
+
+ stats.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\stats.c
+
+
+ sys.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\sys.c
+
+
+ tcp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\tcp.c
+
+
+ tcp_in.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\tcp_in.c
+
+
+ tcp_out.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\tcp_out.c
+
+
+ udp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\udp.c
+
+
+ dhcp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\dhcp.c
+
+
+ init.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\init.c
+
+
+ mem.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\mem.c
+
+
+ memp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\memp.c
+
+
+ netif.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\netif.c
+
+
+ pbuf.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\pbuf.c
+
+
+ raw.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\raw.c
+
+
+ autoip.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\autoip.c
+
+
+ icmp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\icmp.c
+
+
+ igmp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\igmp.c
+
+
+ inet.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet.c
+
+
+ inet_chksum.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\inet_chksum.c
+
+
+ ip.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip.c
+
+
+ ip_addr.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_addr.c
+
+
+ ip_frag.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\core\ipv4\ip_frag.c
+
+
+ etharp.c
+ 1
+ ..\..\Utilities\lwip-1.3.1\src\netif\etharp.c
+
+
+
+
+ CMSIS
+
+
+ system_stm32f10x.c
+ 1
+ ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c
+
+
+ core_cm3.c
+ 1
+ ..\..\Libraries\CMSIS\Core\CM3\core_cm3.c
+
+
+
+
+ RVMDK
+
+
+ startup_stm32f10x_cl.s
+ 2
+ ..\..\Libraries\CMSIS\Core\CM3\startup\arm\startup_stm32f10x_cl.s
+
+
+
+
+
+
+
+
diff --git a/F107/Project/inc/main.h b/F107/Project/inc/main.h
new file mode 100644
index 0000000..2389f39
--- /dev/null
+++ b/F107/Project/inc/main.h
@@ -0,0 +1,26 @@
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#include "stm32f10x.h"
+#include "stm32f107.h"
+#include "stm32_eth.h"
+#include "netconf.h"
+#include "helloworld.h"
+#include "httpd.h"
+#include "tftpserver.h"
+#include "lwip/tcp.h"
+#include "TCP_CLIENT.h"
+
+#define SYSTEMTICK_PERIOD_MS 10
+
+typedef struct mb{
+ char name;
+ char number[8];
+}MB;
+
+void Time_Update(void);
+void Delay(uint32_t nCount);
+void System_Periodic_Handle(void);
+void Delay_s(unsigned long ulVal); //利用循环产生一定的延时
+
+#endif
diff --git a/F107/Project/inc/netconf.h b/F107/Project/inc/netconf.h
new file mode 100644
index 0000000..3ee66fa
--- /dev/null
+++ b/F107/Project/inc/netconf.h
@@ -0,0 +1,45 @@
+ /**
+ ******************************************************************************
+ * @file netconf.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief This file contains all the functions prototypes for the netconf.c
+ * file.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __NETCONF_H
+#define __NETCONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+void LwIP_Init(void);
+void LwIP_Pkt_Handle(void);
+void LwIP_Periodic_Handle(__IO uint32_t localtime);
+void Display_Periodic_Handle(__IO uint32_t localtime);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NETCONF_H */
+
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
+
diff --git a/F107/Project/inc/stm32f107.h b/F107/Project/inc/stm32f107.h
new file mode 100644
index 0000000..3ab87c4
--- /dev/null
+++ b/F107/Project/inc/stm32f107.h
@@ -0,0 +1,46 @@
+/**
+ ******************************************************************************
+ * @file stm32f107.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief This file contains all the functions prototypes for the STM32F107
+ * file.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F107_H
+#define __STM32F107_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+#include "stm3210c_eval_lcd.h"
+#include "stm3210c_eval_ioe.h"
+
+
+void System_Setup(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10F107_H */
+
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Project/inc/stm32f10x_conf.h b/F107/Project/inc/stm32f10x_conf.h
new file mode 100644
index 0000000..a122b6d
--- /dev/null
+++ b/F107/Project/inc/stm32f10x_conf.h
@@ -0,0 +1,76 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_conf.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief Library configuration file.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_CONF_H
+#define __STM32F10x_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+ #include "stm32f10x_adc.h"
+/* #include "stm32f10x_bkp.h" */
+/* #include "stm32f10x_can.h" */
+/* #include "stm32f10x_crc.h" */
+/* #include "stm32f10x_dac.h" */
+/* #include "stm32f10x_dbgmcu.h" */
+/* #include "stm32f10x_dma.h" */
+ #include "stm32f10x_exti.h"
+ #include "stm32f10x_flash.h"
+/* #include "stm32f10x_fsmc.h" */
+ #include "stm32f10x_gpio.h"
+ #include "stm32f10x_i2c.h"
+/* #include "stm32f10x_iwdg.h" */
+/* #include "stm32f10x_pwr.h" */
+ #include "stm32f10x_rcc.h"
+/* #include "stm32f10x_rtc.h" */
+/* #include "stm32f10x_sdio.h" */
+ #include "stm32f10x_spi.h"
+ #include "stm32f10x_tim.h"
+ #include "stm32f10x_usart.h"
+/* #include "stm32f10x_wwdg.h" */
+ #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Uncomment the line below to expanse the "assert_param" macro in the
+ Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT 1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F10x_CONF_H */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Project/inc/stm32f10x_it.h b/F107/Project/inc/stm32f10x_it.h
new file mode 100644
index 0000000..cda03ac
--- /dev/null
+++ b/F107/Project/inc/stm32f10x_it.h
@@ -0,0 +1,55 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_it.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F10x_IT_H
+#define __STM32F10x_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void ETH_IRQHandler(void);
+void ETH_WKUP_IRQHandler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F10x_IT_H */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Project/src/HX711.c b/F107/Project/src/HX711.c
new file mode 100644
index 0000000..6863908
--- /dev/null
+++ b/F107/Project/src/HX711.c
@@ -0,0 +1,52 @@
+#include "HX711.h"
+#include "delay.h"
+
+void Init_HX711pin(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); //使能PF端口时钟
+
+ //HX711_SCK
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; // 端口配置
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //推挽输出
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; //IO口速度为50MHz
+ GPIO_Init(GPIOB, &GPIO_InitStructure); //根据设定参数初始化GPIOB
+
+ //HX711_DOUT
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;//浮空输入
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ GPIO_SetBits(GPIOB,GPIO_Pin_0); //初始化设置为0
+}
+
+
+
+//****************************************************
+//读取HX711
+//****************************************************
+unsigned long HX711_Read(void) //增益128
+{
+ unsigned long count;
+ unsigned char i;
+ HX711_DOUT=1;
+ delay_us(1);
+ HX711_SCK=0;
+ count=0;
+ while(HX711_DOUT);
+ for(i=0;i<24;i++)
+ {
+ HX711_SCK=1;
+ count=count<<1;
+ delay_us(1);
+ HX711_SCK=0;
+ if(HX711_DOUT)
+ count++;
+ delay_us(1);
+ }
+ HX711_SCK=1;
+ count=count^0x800000;//第25个脉冲下降沿来时，转换数据
+ delay_us(1);
+ HX711_SCK=0;
+ return(count);
+}
diff --git a/F107/Project/src/HX711.h b/F107/Project/src/HX711.h
new file mode 100644
index 0000000..f777248
--- /dev/null
+++ b/F107/Project/src/HX711.h
@@ -0,0 +1,15 @@
+#ifndef __HX711_H
+#define __HX711_H
+
+#include "sys.h"
+
+#define HX711_SCK PBout(0)// PB0
+#define HX711_DOUT PBout(1)// PB1
+
+
+extern void Init_HX711pin(void);
+extern unsigned long HX711_Read(void);
+
+
+#endif
+
diff --git a/F107/Project/src/SCI.c b/F107/Project/src/SCI.c
new file mode 100644
index 0000000..6a31a52
--- /dev/null
+++ b/F107/Project/src/SCI.c
@@ -0,0 +1,122 @@
+
+#include "stm32f10x.h"
+
+/***********************************************************************
+文件名称：SCI.C
+功 能：完成对串口的基本操作
+***********************************************************************/
+
+
+void SCI_NVIC_Configuration(void);
+
+void USART_Configuration(void)
+{
+
+ GPIO_InitTypeDef GPIO_InitStructure;
+ USART_InitTypeDef USART_InitStructure;
+ RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO,ENABLE);
+ /*
+ * USART1_TX -> PA9 , USART1_RX -> PA10
+ */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ USART_InitStructure.USART_BaudRate = 115200;
+ USART_InitStructure.USART_WordLength = USART_WordLength_9b;//9位数据
+ USART_InitStructure.USART_StopBits = USART_StopBits_1;//1位停止位
+ USART_InitStructure.USART_Parity = USART_Parity_Even;//偶校验
+ USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; //硬件流控制失能
+ USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; //发送和接受使能
+ USART_Init(USART1, &USART_InitStructure);
+
+ USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
+ //USART_ITConfig(USART1, USART_IT_TXE, ENABLE);
+ /***********************************************************************************
+ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+ 使能或者失能USART外设
+ USARTx：x可以是1，2或者3，来选择USART外设
+ NewState: 外设USARTx的新状态
+ 这个参数可以取：ENABLE或者DISABLE
+ ***********************************************************************************/
+ USART_Cmd(USART1, ENABLE);
+ USART_ClearITPendingBit(USART1, USART_IT_TC);//清除中断TC位
+
+
+
+ //以下为串口2配置
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2,ENABLE);
+ GPIO_PinRemapConfig(GPIO_Remap_USART2,ENABLE);
+ /*
+ * USART1_TX -> PA2 , USART1_RX -> PA3
+ */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+
+ USART_InitStructure.USART_BaudRate = 115200;
+ USART_InitStructure.USART_WordLength = USART_WordLength_9b;//9位数据
+ USART_InitStructure.USART_StopBits = USART_StopBits_1;//1位停止位
+ USART_InitStructure.USART_Parity = USART_Parity_Even;//偶校验
+ USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; //硬件流控制失能
+ USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; //发送和接受使能
+ USART_Init(USART2, &USART_InitStructure);
+ USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
+ USART_Cmd(USART2, ENABLE);
+ USART_ClearITPendingBit(USART2, USART_IT_TC);//清除中断TC位
+
+ /***********************************GPIOD.4，RS485方向控制******************************/
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOD, &GPIO_InitStructure);
+}
+
+/***********************************************************************
+函数名称：void USART1_IRQHandler(void)
+功 能：完成SCI的数据的接收，并做标识
+***********************************************************************/
+void USART1_IRQHandler(void)
+{
+ if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)
+ {
+
+ USART_ClearITPendingBit(USART1, USART_IT_RXNE);
+ }
+ if (USART_GetITStatus(USART1, USART_IT_TXE) != RESET)
+ {
+ USART_ClearITPendingBit(USART1, USART_IT_TXE); /* Clear the USART transmit interrupt */
+ }
+}
+
+
+ /***********************************************************************
+函数名称：void USART2_IRQHandler(void)
+功 能：完成SCI的数据的接收，并做标识
+***********************************************************************/
+void USART2_IRQHandler(void)
+{
+ CLI(); //关闭总中断
+ if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET)//接收到了数据
+ {
+
+ USART_ClearITPendingBit(USART2, USART_IT_RXNE);
+ }
+ if (USART_GetITStatus(USART2, USART_IT_TXE) != RESET)
+ {
+ USART_ClearITPendingBit(USART2, USART_IT_TXE); /* Clear the USART transmit interrupt */
+ }
+ SEI(); //打开总中断
+}
diff --git a/F107/Project/src/TCP_CLIENT.C b/F107/Project/src/TCP_CLIENT.C
new file mode 100644
index 0000000..2a6bf4a
--- /dev/null
+++ b/F107/Project/src/TCP_CLIENT.C
@@ -0,0 +1,149 @@
+#include "main.h"
+#include
+#include "usart.h"
+#include "HX711.h"
+#include
+#include "delay.h"
+
+char c[100][8];
+char C[8];
+MB member[100];
+
+unsigned char connect_flag = 0;
+/*延时函数*/
+void Delay_s(unsigned long ulVal) //利用循环产生一定的延时
+{
+ while ( --ulVal != 0 );
+}
+
+/*TCP客户端发送数据函数*/
+err_t TCP_Client_Send_Data(struct tcp_pcb *cpcb,unsigned char *buff,unsigned int length)
+{
+ err_t err;
+ err = tcp_write(cpcb,buff,length,TCP_WRITE_FLAG_COPY); //发送数据
+ tcp_output(cpcb);
+ return err;
+}
+
+/*检查连接*/
+struct tcp_pcb *Check_TCP_Connect(void)
+{
+ struct tcp_pcb *cpcb = 0;
+ connect_flag = 0;
+ for(cpcb = tcp_active_pcbs;cpcb != NULL; cpcb = cpcb->next)
+ {
+ if(cpcb -> state == ESTABLISHED)
+ {
+ connect_flag = 1; //连接标志
+ break;
+ }
+ }
+ if(connect_flag == 0) // TCP_LOCAL_PORT指定的端口未连接或已断开
+ {
+ TCP_Client_Init(TCP_LOCAL_PORT,TCP_SERVER_PORT,TCP_SERVER_IP); //重新连接
+ cpcb = 0;
+ }
+ return cpcb;
+}
+
+
+/*这是一个回调函数，当TCP客户端请求的连接建立时被调用*/
+err_t TCP_Connected(void *arg,struct tcp_pcb *pcb,err_t err)
+{
+ return ERR_OK;
+}
+
+/*tcp客户端接收数据回调函数*/
+err_t TCP_Client_Recv(void *arg, struct tcp_pcb *pcb,struct pbuf *p,err_t err)
+{
+ static int i=0;
+ int j,k,l=0,a;
+ struct pbuf *q;
+ if(p!= NULL)
+ {
+ tcp_recved(pcb,p->tot_len); //获取数据长度 tot_len：tcp数据块的长度
+ for(q=p;q!=NULL;q=q->next)
+ {
+ if(q->tot_len>100)break;
+ {
+ for(k=0;k<100;k++)
+ {
+ if(member[k].name==*((char*) p->payload+6)) //覆盖的情况
+ {
+ for(a=0;a<6;a++)
+ {
+ member[k].number[a]=*((char*) p->payload+a);
+ }
+ member[k].name=*((char*) p->payload+6);
+ member[k].number[6]='\0';
+ l=1;
+ break;
+ }
+ }
+ if(l==0)
+ {
+ for(k=0;k<100;k++)
+ {
+ if(member[k].name!=*((char*) p->payload+6)) //没被覆盖的情况
+ {
+ for(a=0;a<6;a++)
+ {
+ member[i].number[a]=*((char*) p->payload+a);
+ }
+ member[i].name=*((char*) p->payload+6);
+ member[i].number[6]='\0';
+ l=0;
+ i++;
+ break;
+ }
+ }
+ }
+ }
+ if(i==100)i=0;
+ {
+ strncpy(C,member[i-1].number,6);
+ USART4_printf("AT\r\n"); //串口四发送给短信模块
+ delay_ms(10);
+ USART4_printf("AT+CMGF=1\r\n");
+ delay_ms(10);
+ USART4_printf("AT+CSCS=\"GSM\"\r\n");
+ delay_ms(500);
+ USART4_printf("AT+CMGS=\"13559725210\"\r\n"); //15994997557欣锐 13559725210傻屌 13242353288毅营 18988746231鹏
+ delay_ms(500);
+ USART4_printf("%s",C);
+ delay_ms(10);
+ USART4_printf("%c",0x1a);
+ delay_ms(10);
+ }
+ }
+ }
+ else //如果服务器断开连接，则客户端也应断开
+ {
+ tcp_close(pcb);
+ }
+ pbuf_free(p);
+ err = ERR_OK;
+ return err;
+}
+
+/*tcp客户端初始化*/
+void TCP_Client_Init(u16_t local_port,u16_t remote_port,unsigned char a,unsigned char b,unsigned char c,unsigned char d)
+{
+
+ struct ip_addr ipaddr;
+ struct tcp_pcb *tcp_client_pcb;
+ err_t err;
+ IP4_ADDR(&ipaddr,a,b,c,d); //服务器IP地址
+ tcp_client_pcb = tcp_new(); //建立通信的TCP控制块(Clipcb)
+ if (!tcp_client_pcb)
+ {
+ return ;
+ }
+ err = tcp_bind(tcp_client_pcb,IP_ADDR_ANY,local_port); //绑定本地IP地址和端口号 ，本地ip地址在LwIP_Init()中已经初始化
+ if(err != ERR_OK)
+ {
+ return ;
+ }
+ tcp_connect(tcp_client_pcb,&ipaddr,remote_port,TCP_Connected); //注册回调函数
+ tcp_recv(tcp_client_pcb,TCP_Client_Recv); //设置tcp接收回调函数
+}
diff --git a/F107/Project/src/TCP_CLIENT.h b/F107/Project/src/TCP_CLIENT.h
new file mode 100644
index 0000000..f8b045b
--- /dev/null
+++ b/F107/Project/src/TCP_CLIENT.h
@@ -0,0 +1,20 @@
+#ifndef _TCP_CLIENT_H_
+#define _TCP_CLIENT_H_
+#include "lwip/tcp.h"
+
+/***************开发板ip及MAC定义*************************/
+#define BOARD_IP 192,168,1,128 //开发板ip
+#define BOARD_NETMASK 255,255,255,0 //开发板子网掩码
+#define BOARD_WG 192,168,1,1 //开发板子网关
+#define BOARD_MAC_ADDR 0,0,0,3,2,1 //开发板MAC地址
+#define TCP_LOCAL_PORT 8088 //开发板端口
+#define TCP_SERVER_PORT 8086 //电脑端口
+#define TCP_SERVER_IP 192,168,1,192//设置成自己电脑真实的IP地址
+
+extern struct tcp_pcb *tcp_client_pcb;
+
+void TCP_Client_Init(u16_t local_port,u16_t remote_port,unsigned char a,unsigned char b,unsigned char c,unsigned char d);
+err_t TCP_Client_Send_Data(struct tcp_pcb *cpcb,unsigned char *buff,unsigned int length);
+struct tcp_pcb *Check_TCP_Connect(void);
+#endif
+
diff --git a/F107/Project/src/TCP_SERVER.C b/F107/Project/src/TCP_SERVER.C
new file mode 100644
index 0000000..4213ca1
--- /dev/null
+++ b/F107/Project/src/TCP_SERVER.C
@@ -0,0 +1,79 @@
+/***********************************************************************
+文件名称：TCP_SERVER.C
+功 能：完成TCP的数据收发
+编写时间：2013.4.25
+编 写 人：赵
+注 意：
+***********************************************************************/
+#include "stm32_eth.h"
+#include "lwip/tcp.h"
+#include "TCP_SERVER.h"
+
+/***********************************************************************
+函数名称：tcp_server_recv(void *arg, struct tcp_pcb *pcb,struct pbuf *p,err_t err)
+功 能：TCP数据接收和发送
+输入参数：
+输出参数：
+编写时间：2013.4.25
+编 写 人：
+注 意：这是一个回调函数，当一个TCP段到达这个连接时会被调用
+***********************************************************************/
+static err_t tcp_server_recv(void *arg, struct tcp_pcb *pcb,struct pbuf *p,err_t err)
+{
+ char *data;
+ char *data_temp;
+
+ if(p != NULL)
+ {
+ tcp_recved(pcb, p->tot_len); //获取数据长度 tot_len：tcp数据块的长度
+ /******将数据原样返回*******************/
+ tcp_write(pcb,p->payload,p->tot_len,0); // payload为TCP数据块的起始位置
+ pbuf_free(p); /* 释放该TCP段 */
+ }
+ else
+ {
+ tcp_close(pcb); /* 作为TCP服务器不应主动关闭这个连接？ */
+ }
+ err = ERR_OK;
+ return err;
+}
+
+
+/***********************************************************************
+函数名称：tcp_server_accept(void *arg, struct tcp_pcb *pcb,struct pbuf *p,err_t err)
+功 能：回调函数
+输入参数：
+输出参数：
+编写时间：2013.4.25
+编 写 人：
+注 意：这是一个回调函数，当一个连接已经接受时会被调用
+***********************************************************************/
+static err_t tcp_server_accept(void *arg,struct tcp_pcb *pcb,err_t err)
+{
+ tcp_setprio(pcb, TCP_PRIO_MIN); /* 设置回调函数优先级，当存在几个连接时特别重要,此函数必须调用*/
+ tcp_recv(pcb,tcp_server_recv); /* 设置TCP段到时的回调函数 */
+ err = ERR_OK;
+ return err;
+}
+
+
+/***********************************************************************
+函数名称：TCP_server_init(void)
+功 能：完成TCP服务器的初始化，主要是使得TCP通讯快进入监听状态
+输入参数：
+输出参数：
+编写时间：2013.4.25
+编 写 人：
+注 意：
+***********************************************************************/
+void TCP_server_init(void)
+{
+ struct tcp_pcb *pcb;
+
+ /*****************************************************/
+ pcb = tcp_new(); /* 建立通信的TCP控制块(pcb) */
+ tcp_bind(pcb,IP_ADDR_ANY,TCP_LOCAL_PORT); /* 绑定本地IP地址和端口号（作为tcp服务器） */
+ pcb = tcp_listen(pcb); /* 进入监听状态 */
+ tcp_accept(pcb,tcp_server_accept); /* 设置有连接请求时的回调函数 */
+
+}
\ No newline at end of file
diff --git a/F107/Project/src/TCP_SERVER.h b/F107/Project/src/TCP_SERVER.h
new file mode 100644
index 0000000..5b57938
--- /dev/null
+++ b/F107/Project/src/TCP_SERVER.h
@@ -0,0 +1,13 @@
+/********************************************************************
+文件名称：TCP_SERVER.h
+功 能：
+编写时间：2013.4.25
+编 写 人：
+注 意：
+*********************************************************************/
+#ifndef _TCP_TO_RS232_485_CAN_H_
+#define _TCP_TO_RS232_485_CAN_H_
+
+#define TCP_LOCAL_PORT 1030
+
+#endif
diff --git a/F107/Project/src/helloworld.c b/F107/Project/src/helloworld.c
new file mode 100644
index 0000000..8e913bf
--- /dev/null
+++ b/F107/Project/src/helloworld.c
@@ -0,0 +1,82 @@
+#include "helloworld.h"
+#include "lwip/tcp.h"
+#include
+#include
+
+#define MAX_NAME_SIZE 32
+
+struct name
+{
+ int length;
+ char bytes[MAX_NAME_SIZE];
+};
+static err_t HelloWorld_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err);
+static err_t HelloWorld_accept(void *arg, struct tcp_pcb *pcb, err_t err);
+static void HelloWorld_conn_err(void *arg, err_t err);
+
+static err_t HelloWorld_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
+{
+ struct pbuf *q;
+ struct name *name = (struct name *)arg;
+ int done;
+ char *c;
+ int i;
+ if (p != NULL)
+ {
+ tcp_recved(pcb, p->tot_len);
+ if(!name){
+ pbuf_free(p);
+ return ERR_ARG;
+ }
+ done = 0;
+ for(q=p; q != NULL; q = q->next)
+ {
+ c = q->payload;
+ for(i=0; ilen && !done; i++)
+ {
+ done = ((c[i] == 'A'));
+ if(name->length < MAX_NAME_SIZE)
+ {
+ name->bytes[name->length++] = c[i];
+ }
+ }
+ }
+ if(done)
+ {
+ tcp_write(pcb, name->bytes, name->length, TCP_WRITE_FLAG_COPY);
+ name->length = 0;
+ }
+ pbuf_free(p);
+ }
+ else if (err == ERR_OK)
+ {
+ mem_free(name);
+ return tcp_close(pcb);
+ }
+ return ERR_OK;
+}
+
+static err_t HelloWorld_accept(void *arg, struct tcp_pcb *pcb, err_t err)
+{
+ tcp_arg(pcb, mem_calloc(sizeof(struct name), 1));
+ tcp_err(pcb, HelloWorld_conn_err);
+ tcp_recv(pcb, HelloWorld_recv);
+ return ERR_OK;
+}
+
+void HelloWorld_init(void)
+{
+ struct tcp_pcb *pcb;
+ pcb = tcp_new();
+ tcp_bind(pcb, IP_ADDR_ANY, 1031);
+ pcb = tcp_listen(pcb);
+ tcp_accept(pcb, HelloWorld_accept);
+}
+
+static void HelloWorld_conn_err(void *arg, err_t err)
+{
+ struct name *name;
+ name = (struct name *)arg;
+
+ mem_free(name);
+}
diff --git a/F107/Project/src/helloworld.h b/F107/Project/src/helloworld.h
new file mode 100644
index 0000000..8a56637
--- /dev/null
+++ b/F107/Project/src/helloworld.h
@@ -0,0 +1,53 @@
+ /**
+ ******************************************************************************
+ * @file helloworld.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief This file contains all the functions prototypes for the helloworld.c
+ * file.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HELLOWERLOD_H
+#define __HELLOWERLOD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+
+/** @defgroup helloworld_Exported_Functions
+ * @{
+ */
+
+void HelloWorld_init(void);
+
+/**
+ * @}
+ */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HELLOWERLOD_H */
+
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
+
diff --git a/F107/Project/src/main.c b/F107/Project/src/main.c
new file mode 100644
index 0000000..f74beab
--- /dev/null
+++ b/F107/Project/src/main.c
@@ -0,0 +1,160 @@
+#include "main.h"
+#include "usart.h"
+#include "delay.h"
+#include "led.h"
+#include "HX711.h"
+#include
+
+__IO uint32_t LocalTime = 0; ///初始化系统此变量用于创建时间引用，增量为10毫秒
+uint32_t timingdelay;
+u8 a;
+extern char c[100][8];
+extern MB member[100];
+
+/***********LWIP所需调用函数***************/
+/*延时*/
+void Delay(uint32_t nCount)
+{
+ timingdelay = LocalTime + nCount;
+ while(timingdelay > LocalTime)
+ {
+ }
+}
+/*更新系统本地时钟*/
+void Time_Update(void)
+{
+ LocalTime += SYSTEMTICK_PERIOD_MS;
+}
+/*处理系统的定期任务*/
+void System_Periodic_Handle(void)
+{
+ Display_Periodic_Handle(LocalTime);
+ LwIP_Periodic_Handle(LocalTime);
+}
+/*****************************************/
+
+/*************************主函数*******************************/
+int main(void)
+{
+ int flag=0; //接收标志位
+ int nm,p=0; //判断有无标志位
+ unsigned char flag_uart2_rev=0;
+ char str[100]={1}; //缓存
+ unsigned char tcp_data[100];
+ struct tcp_pcb *pcb;
+ System_Setup(); //初始化系统
+ LwIP_Init(); //初始化LwIP satck ip地址设置，mac设置
+ TCP_Client_Init(TCP_LOCAL_PORT,TCP_SERVER_PORT,TCP_SERVER_IP); //tcp客户端初始化
+ USART1_Init(115200);
+ USART2_Init(115200);
+ USART4_Init(9600); //SIM8000规定的通信波特率1
+ USART5_Init(115200);
+ LED_Init1();
+ LED_Init2();
+ LED_Init3();
+ NVIC_Configuration(); //短信模块配置
+
+ while(1)
+ {
+ static unsigned int i=0;
+ u8 Res;
+ /*接收OpenMV传来的数据并发送给数据库*/
+ if(USART_GetFlagStatus(UART5,USART_FLAG_RXNE) != RESET)
+ {
+ a =USART_ReceiveData(UART5);
+ if(a=='A')
+ {
+ tcp_data[0] = 'A';
+ tcp_data[1] = '\0';
+ printf("#1GC1\r\n");
+ GPIO_SetBits(GPIOC,GPIO_Pin_13);
+ pcb = Check_TCP_Connect(); //检查连接
+ if(pcb != 0)
+ {
+ TCP_Client_Send_Data(pcb,tcp_data,sizeof(tcp_data)); //向服务器发送数据
+ }
+ Delay_s(0xfffff); //延时
+ }
+ if(a=='B')
+ {
+ tcp_data[0] = 'B';
+ tcp_data[1] = '\0';
+ printf("#2GC1\r\n");
+ GPIO_SetBits(GPIOC,GPIO_Pin_2);
+ pcb = Check_TCP_Connect(); //检查连接
+ if(pcb != 0)
+ {
+ TCP_Client_Send_Data(pcb,tcp_data,sizeof(tcp_data)); //向服务器发送数据
+ }
+ Delay_s(0xfffff); //延时
+ }
+ if(a=='C')
+ {
+ tcp_data[0] = 'C';
+ tcp_data[1] = '\0';
+ printf("#3GC1\r\n");
+ GPIO_SetBits(GPIOC,GPIO_Pin_3);
+ pcb = Check_TCP_Connect(); //检查连接
+ if(pcb != 0)
+ {
+ TCP_Client_Send_Data(pcb,tcp_data,sizeof(tcp_data)); //向服务器发送数据
+ }
+ Delay_s(0xfffff); //延时
+ }
+ }
+
+ /*接收A53传来的数据并与缓存的数据进行匹配*/
+ if(USART_GetFlagStatus(USART2, USART_FLAG_RXNE) != RESET)
+ {
+ Res =USART_ReceiveData(USART2);
+ if(Res=='E') //判断结束标志位
+ {
+ flag_uart2_rev=1;
+ flag=0;
+ str[i]='\0';
+ i=0;
+ }
+ if(flag==1)
+ {
+ str[i]=Res;
+ i++;
+ }
+ if(Res=='S') //判断开始标志位
+ flag=1;
+ }
+ if(flag_uart2_rev==1)
+ {
+ flag_uart2_rev=0;
+ for(nm=0;nm<3;nm++)
+ {
+ if(!strncmp(str,member[nm].number,6))
+ {
+ if(member[nm].name=='A')
+ {
+ printf("#4GC1\r\n");
+ GPIO_ResetBits(GPIOC,GPIO_Pin_13);
+ }
+ if(member[nm].name=='B')
+ {
+ printf("#6GC1\r\n");
+ GPIO_ResetBits(GPIOC,GPIO_Pin_2);
+ }
+ if(member[nm].name=='C')
+ {
+ printf("#5GC1\r\n");
+ GPIO_ResetBits(GPIOC,GPIO_Pin_3);
+ }
+ p=1;
+ break;
+ }else{
+ p=0;
+ }
+ }
+ delay_ms(1000);
+ if(p==1)USART1_printf("1Z"); //用户验证码和数据库进行匹配，有则为1，反之为0
+ if(p==0)USART1_printf("00");
+ }
+ System_Periodic_Handle(); //作为服务器的例行事件服务，主要是更新TCP timers
+ }
+}
+
diff --git a/F107/Project/src/netconf.c b/F107/Project/src/netconf.c
new file mode 100644
index 0000000..45910db
--- /dev/null
+++ b/F107/Project/src/netconf.c
@@ -0,0 +1,299 @@
+/**
+ ******************************************************************************
+ * @file netconf.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief Network connection configuration
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "lwip/memp.h"
+#include "lwip/tcp.h"
+#include "lwip/udp.h"
+#include "netif/etharp.h"
+#include "lwip/dhcp.h"
+#include "ethernetif.h"
+#include "main.h"
+#include "netconf.h"
+#include
+
+/* Private typedef -----------------------------------------------------------*/
+#define LCD_DELAY 3000
+#define KEY_DELAY 3000
+#define LCD_TIMER_MSECS 250
+#define MAX_DHCP_TRIES 4
+#define SELECTED 1
+#define NOT_SELECTED (!SELECTED)
+#define CLIENTMAC6 2
+//#define CLIENTMAC6 3
+//#define CLIENTMAC6 4
+
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+struct netif netif;
+__IO uint32_t TCPTimer = 0;
+__IO uint32_t ARPTimer = 0;
+
+#ifdef LWIP_DHCP
+__IO uint32_t DHCPfineTimer = 0;
+__IO uint32_t DHCPcoarseTimer = 0;
+static uint32_t IPaddress = 0;
+#endif
+
+__IO uint32_t DisplayTimer = 0;
+uint8_t LedToggle = 4;
+uint8_t Server = 0;
+
+/* Private function prototypes -----------------------------------------------*/
+extern void client_init(void);
+extern void server_init(void);
+void My_IP4_ADDR(struct ip_addr *ipaddr,unsigned char a,unsigned char b,unsigned char c,unsigned char d);
+
+/***************开发板ip及MAC定义*************************
+#define BOARD_IP 192,168,1,252 //开发板ip
+#define BOARD_NETMASK 255,255,255,0 //开发板子网掩码
+#define BOARD_WG 255,255,1,1 //开发板子网关
+#define BOARD_MAC_ADDR 0,0,0,0,0,1 //开发板MAC地址
+*/
+void LwIP_Init(void)
+{
+ struct ip_addr ipaddr;
+ struct ip_addr netmask;
+ struct ip_addr gw;
+ uint8_t macaddress[6]={BOARD_MAC_ADDR};
+
+ /* Initializes the dynamic memory heap defined by MEM_SIZE.*/
+ mem_init();
+
+ /* Initializes the memory pools defined by MEMP_NUM_x.*/
+ memp_init();
+
+
+#if LWIP_DHCP //ip自动获取
+ ipaddr.addr = 0;
+ netmask.addr = 0;
+ gw.addr = 0;
+
+ if(!STM_EVAL_PBGetState(Button_KEY))
+ {
+ Server = SELECTED;
+ }
+ else
+ {
+ macaddress[5]=CLIENTMAC6;
+
+ Server = NOT_SELECTED;
+ }
+
+#else //固定ip？
+ My_IP4_ADDR(&ipaddr,BOARD_IP);
+ My_IP4_ADDR(&netmask, BOARD_NETMASK);
+ My_IP4_ADDR(&gw, BOARD_WG);
+#endif
+
+ Set_MAC_Address(macaddress);
+
+ /* - netif_add(struct netif *netif, struct ip_addr *ipaddr,
+ struct ip_addr *netmask, struct ip_addr *gw,
+ void *state, err_t (* init)(struct netif *netif),
+ err_t (* input)(struct pbuf *p, struct netif *netif))
+
+ Adds your network interface to the netif_list. Allocate a struct
+ netif and pass a pointer to this structure as the first argument.
+ Give pointers to cleared ip_addr structures when using DHCP,
+ or fill them with sane numbers otherwise. The state pointer may be NULL.
+
+ The init function pointer must point to a initialization function for
+ your ethernet netif interface. The following code illustrates it's use.*/
+ netif_add(&netif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, ðernet_input);
+
+ /* Registers the default network interface.*/
+ netif_set_default(&netif);
+
+
+#if LWIP_DHCP
+ /* Creates a new DHCP client for this interface on the first call.
+ Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
+ the predefined regular intervals after starting the client.
+ You can peek in the netif->dhcp struct for the actual DHCP status.*/
+ dhcp_start(&netif);
+#endif
+
+ /* When the netif is fully configured this function must be called.*/
+ netif_set_up(&netif);
+
+}
+
+/**
+ * @brief Called when a frame is received
+ * @param None
+ * @retval None
+ */
+void LwIP_Pkt_Handle(void)
+{
+ /* Read a received packet from the Ethernet buffers and send it to the lwIP for handling */
+ ethernetif_input(&netif);
+}
+
+/**
+ * @brief LwIP periofdic tasks
+ * @param localtime the current LocalTime value
+ * @retval None
+ */
+void LwIP_Periodic_Handle(__IO uint32_t localtime)
+{
+
+ /* TCP periodic process every 250 ms */
+ if (localtime - TCPTimer >= TCP_TMR_INTERVAL)
+ {
+ TCPTimer = localtime;
+ tcp_tmr();
+ }
+ /* ARP periodic process every 5s */
+ if (localtime - ARPTimer >= ARP_TMR_INTERVAL)
+ {
+ ARPTimer = localtime;
+ etharp_tmr();
+ }
+
+#if LWIP_DHCP
+ /* Fine DHCP periodic process every 500ms */
+ if (localtime - DHCPfineTimer >= DHCP_FINE_TIMER_MSECS)
+ {
+ DHCPfineTimer = localtime;
+ dhcp_fine_tmr();
+ }
+ /* DHCP Coarse periodic process every 60s */
+ if (localtime - DHCPcoarseTimer >= DHCP_COARSE_TIMER_MSECS)
+ {
+ DHCPcoarseTimer = localtime;
+ dhcp_coarse_tmr();
+ }
+#endif
+
+}
+
+/**
+ * @brief LCD & LEDs periodic handling
+ * @param localtime: the current LocalTime value
+ * @retval None
+ */
+void Display_Periodic_Handle(__IO uint32_t localtime)
+{
+ /* 250 ms */
+ if (localtime - DisplayTimer >= LCD_TIMER_MSECS)
+ {
+ DisplayTimer = localtime;
+
+ /* We have got a new IP address so update the display */
+ if (IPaddress != netif.ip_addr.addr)
+ {
+ __IO uint8_t iptab[4];
+ uint8_t iptxt[20];
+
+ /* Read the new IP address */
+ IPaddress = netif.ip_addr.addr;
+
+ iptab[0] = (uint8_t)(IPaddress >> 24);
+ iptab[1] = (uint8_t)(IPaddress >> 16);
+ iptab[2] = (uint8_t)(IPaddress >> 8);
+ iptab[3] = (uint8_t)(IPaddress);
+
+ sprintf((char*)iptxt, " %d.%d.%d.%d ", iptab[3], iptab[2], iptab[1], iptab[0]);
+
+ /* Display the new IP address */
+#if LWIP_DHCP
+ if (netif.flags & NETIF_FLAG_DHCP)
+ {
+
+ iptab[0] = (uint8_t)(IPaddress >> 24);
+ iptab[1] = (uint8_t)(IPaddress >> 16);
+ iptab[2] = (uint8_t)(IPaddress >> 8);
+ iptab[3] = (uint8_t)(IPaddress);
+
+ if(Server)
+ {
+ /* Initialize the server application */
+ server_init();
+ }
+ else
+ {
+
+ /* Configure the IO Expander */
+ IOE_Config();
+
+ /* Enable the Touch Screen and Joystick interrupts */
+ IOE_ITConfig(IOE_ITSRC_TSC);
+
+ /* Initialize the client application */
+ client_init();
+ }
+ }
+ else
+#endif
+ {
+ ;
+ }
+ }
+
+#if LWIP_DHCP
+
+ else if (IPaddress == 0)
+ {
+ /* We still waiting for the DHCP server */
+
+ LedToggle &= 3;
+
+ STM_EVAL_LEDToggle((Led_TypeDef)(LedToggle++));
+
+ /* If no response from a DHCP server for MAX_DHCP_TRIES times */
+ /* stop the dhcp client and set a static IP address */
+ if (netif.dhcp->tries > MAX_DHCP_TRIES)
+ {
+ struct ip_addr ipaddr;
+ struct ip_addr netmask;
+ struct ip_addr gw;
+
+ dhcp_stop(&netif);
+
+ IP4_ADDR(&ipaddr, 192, 168, 1, 252);
+ IP4_ADDR(&netmask, 255, 255, 255, 0);
+ IP4_ADDR(&gw, 192, 168, 1, 1);
+
+ netif_set_addr(&netif, &ipaddr , &netmask, &gw);
+
+ }
+ }
+#endif
+ }
+}
+/***********************************************************************
+函数名称：My_IP4_ADDR(void)
+功 能：IP地址的装配
+输入参数：
+输出参数：
+编写时间：2013.4.25
+编 写 人：
+注 意：
+***********************************************************************/
+void My_IP4_ADDR(struct ip_addr *ipaddr,unsigned char a,unsigned char b,unsigned char c,unsigned char d)
+{
+ ipaddr->addr = htonl(((u32_t)((a) & 0xff) << 24) | \
+ ((u32_t)((b) & 0xff) << 16) | \
+ ((u32_t)((c) & 0xff) << 8) | \
+ (u32_t)((d) & 0xff));
+}
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Project/src/stm32f107.c b/F107/Project/src/stm32f107.c
new file mode 100644
index 0000000..a902a68
--- /dev/null
+++ b/F107/Project/src/stm32f107.c
@@ -0,0 +1,360 @@
+/**
+ ******************************************************************************
+ * @file stm32f107.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief STM32F107 hardware configuration
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eth.h"
+#include "stm32f107.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DP83848_PHY /* Ethernet pins mapped on STM3210C-EVAL Board */
+#define PHY_ADDRESS 0x01 /* Relative to STM3210C-EVAL Board */
+
+//#define MII_MODE /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */
+#define RMII_MODE /* RMII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */
+
+/*--------------- LCD Messages ---------------*/
+#define MESSAGE1 " STM32F107 "
+#define MESSAGE2 " Connectivity Line "
+#define MESSAGE3 " * LwIP demos * "
+#define MESSAGE4 " "
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+void GPIO_Configuration(void);
+void NVIC_Configuration(void);
+void ADC_Configuration(void);
+void Ethernet_Configuration(void);
+void USART_Configuration(void);
+
+
+/**
+ * @brief Setup STM32 system (clocks, Ethernet, GPIO, NVIC) and STM3210C-EVAL resources.
+ * @param None
+ * @retval None
+ */
+void System_Setup(void)
+{
+ RCC_ClocksTypeDef RCC_Clocks;
+
+ /* Setup STM32 clock, PLL and Flash configuration) */
+ SystemInit();
+
+ /* Enable USART2 clock */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+
+
+ /* Enable ETHERNET clock */
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx |
+ RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
+
+ /* Enable GPIOs and ADC1 clocks */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC |
+ RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO |
+ RCC_APB2Periph_ADC1, ENABLE);
+
+ /* NVIC configuration */
+ NVIC_Configuration();
+ /* Configure the GPIO ports */
+ GPIO_Configuration();
+
+ USART_Configuration();
+ /* Configure the Ethernet peripheral */
+ Ethernet_Configuration();
+
+ /* SystTick configuration: an interrupt every 10ms */
+ RCC_GetClocksFreq(&RCC_Clocks);
+ SysTick_Config(RCC_Clocks.SYSCLK_Frequency / 100);
+
+ /* Update the SysTick IRQ priority should be higher than the Ethernet IRQ */
+ /* The Localtime should be updated during the Ethernet packets processing */
+ NVIC_SetPriority (SysTick_IRQn, 1);
+}
+
+/**
+ * @brief Configures the Ethernet Interface
+ * @param None
+ * @retval None
+ */
+void Ethernet_Configuration(void)
+{
+ ETH_InitTypeDef ETH_InitStructure;
+
+ /* MII/RMII Media interface selection ------------------------------------------*/
+#ifdef MII_MODE /* Mode MII with STM3210C-EVAL */
+ GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
+
+ /* Get HSE clock = 25MHz on PA8 pin (MCO) */
+ RCC_MCOConfig(RCC_MCO_HSE);
+
+#elif defined RMII_MODE /* Mode RMII with STM3210C-EVAL */
+ GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
+
+ /* Set PLL3 clock output to 50MHz (25MHz /5 *10 =50MHz) */
+ RCC_PLL3Config(RCC_PLL3Mul_10);
+ /* Enable PLL3 */
+ RCC_PLL3Cmd(ENABLE);
+ /* Wait till PLL3 is ready */
+ while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET)
+ {}
+
+ /* Get PLL3 clock on PA8 pin (MCO) */
+ RCC_MCOConfig(RCC_MCO_PLL3CLK);
+#endif
+
+ /* Reset ETHERNET on AHB Bus */
+ ETH_DeInit();
+
+ /* Software reset */
+ ETH_SoftwareReset();
+
+ /* Wait for software reset */
+ while (ETH_GetSoftwareResetStatus() == SET);
+
+ /* ETHERNET Configuration ------------------------------------------------------*/
+ /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
+ ETH_StructInit(Ð_InitStructure);
+
+ /* Fill ETH_InitStructure parametrs */
+ /*------------------------ MAC -----------------------------------*/
+ ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ;
+ ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
+ ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;
+ ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
+ ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
+ ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
+ ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
+ ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
+ ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
+#ifdef CHECKSUM_BY_HARDWARE
+ ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
+#endif
+
+ /*------------------------ DMA -----------------------------------*/
+
+ /* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
+ the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
+ if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
+ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
+ ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+ ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+
+ ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+ ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+ ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
+ ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+ ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
+ ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
+ ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
+ ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
+
+ /* Configure Ethernet */
+ ETH_Init(Ð_InitStructure, PHY_ADDRESS);
+
+ /* Enable the Ethernet Rx Interrupt */
+ ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
+
+}
+
+/**
+ * @brief Configures the different GPIO ports.
+ * @param None
+ * @retval None
+ */
+void GPIO_Configuration(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* ETHERNET pins configuration */
+ /* AF Output Push Pull:
+ - ETH_MII_MDIO / ETH_RMII_MDIO: PA2
+ - ETH_MII_MDC / ETH_RMII_MDC: PC1
+ - ETH_MII_TXD2: PC2
+ - ETH_MII_TX_EN / ETH_RMII_TX_EN: PB11
+ - ETH_MII_TXD0 / ETH_RMII_TXD0: PB12
+ - ETH_MII_TXD1 / ETH_RMII_TXD1: PB13
+ - ETH_MII_PPS_OUT / ETH_RMII_PPS_OUT: PB5
+ - ETH_MII_TXD3: PB8 */
+
+ /* Configure PA2 as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ /* Configure PC1, PC2 and PC3 as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+ /* Configure PB5, PB8, PB11, PB12 and PB13 as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 |
+ GPIO_Pin_12 | GPIO_Pin_13;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ /**************************************************************/
+ /* For Remapped Ethernet pins */
+ /*************************************************************/
+ /* Input (Reset Value):
+ - ETH_MII_CRS CRS: PA0
+ - ETH_MII_RX_CLK / ETH_RMII_REF_CLK: PA1
+ - ETH_MII_COL: PA3
+ - ETH_MII_RX_DV / ETH_RMII_CRS_DV: PD8
+ - ETH_MII_TX_CLK: PC3
+ - ETH_MII_RXD0 / ETH_RMII_RXD0: PD9
+ - ETH_MII_RXD1 / ETH_RMII_RXD1: PD10
+ - ETH_MII_RXD2: PD11
+ - ETH_MII_RXD3: PD12
+ - ETH_MII_RX_ER: PB10 */
+
+ /* ETHERNET pins remapp in STM3210C-EVAL board: RX_DV and RxD[3:0] */
+ GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE);
+
+ /* Configure PA0, PA1 and PA3 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ /* Configure PB10 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ /* Configure PC3 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+ /* Configure PD8, PD9, PD10, PD11 and PD12 as input */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIOD, &GPIO_InitStructure); /**/
+
+ /* ADC Channel9 config --------------------------------------------------------*/
+ /* Relative to STM3210D-EVAL Board */
+ /* Configure PB1(ADC Channel9) as analog input -------------------------*/
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
+ GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+ /* MCO pin configuration------------------------------------------------- */
+ /* Configure MCO (PA8) as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+
+
+}
+
+
+
+/**
+ * @brief Configures the nested vectored interrupt controller.
+ * @param None
+ * @retval None
+ */
+void NVIC_Configuration(void)
+{
+ NVIC_InitTypeDef NVIC_InitStructure;
+
+ /* Set the Vector Table base location at 0x08000000 */
+ NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+
+ /* 2 bit for pre-emption priority, 2 bits for subpriority */
+ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+
+ /* Enable the Ethernet global Interrupt */
+ NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+ NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+ NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+ NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+ NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 4;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+
+ NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+
+}
+
+/*********************定时器2配置**************************************************/
+void TIM_Configuration(unsigned int time)
+{
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 , ENABLE);
+ TIM_DeInit(TIM2);
+ TIM_TimeBaseStructure.TIM_Period=time; /* 自动重装载寄存器周期的值(计数值) */
+ /* 累计 TIM_Period个频率后产生一个更新或者中断 */
+ TIM_TimeBaseStructure.TIM_Prescaler= (36000 - 1); /* 时钟预分频数 例如：时钟频率=72MHZ/(时钟预分频+1) */
+ TIM_TimeBaseStructure.TIM_ClockDivision=TIM_CKD_DIV1; /* 采样分频 */
+ TIM_TimeBaseStructure.TIM_CounterMode=TIM_CounterMode_Up; /* 向上计数模式 */
+ TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+ TIM_ClearFlag(TIM2, TIM_FLAG_Update); /* 清除溢出中断标志 */
+ TIM_ITConfig(TIM2,TIM_IT_Update,ENABLE);
+ TIM_Cmd(TIM2, ENABLE); /* 开启时钟 */
+}
+
+/****************定时器2中断函数*******************************************************/
+void TIM2_IRQHandler(void)
+{
+ //CLI(); //关闭总中断
+ if ( TIM_GetITStatus(TIM2 , TIM_IT_Update) != RESET )
+ {
+ TIM_ClearITPendingBit(TIM2 , TIM_FLAG_Update);
+ }
+ //SEI(); //打开总中断
+}
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Project/src/stm32f10x_it.c b/F107/Project/src/stm32f10x_it.c
new file mode 100644
index 0000000..078cf2a
--- /dev/null
+++ b/F107/Project/src/stm32f10x_it.c
@@ -0,0 +1,171 @@
+/**
+ ******************************************************************************
+ * @file stm32f10x_it.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief Main Interrupt Service Routines.
+ * This file provides template for all exceptions handler and
+ * peripherals interrupt service routine.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x_it.h"
+#include "stm32_eth.h"
+#include "main.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+extern void LwIP_Pkt_Handle(void);
+extern void tcp_led_control(Led_TypeDef Led);
+
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/* Cortex-M3 Processor Exceptions Handlers */
+/******************************************************************************/
+
+/**
+ * @brief This function handles NMI exception.
+ * @param None
+ * @retval None
+ */
+void NMI_Handler(void)
+{}
+
+/**
+ * @brief This function handles Hard Fault exception.
+ * @param None
+ * @retval None
+ */
+void HardFault_Handler(void)
+{
+ /* Go to infinite loop when Hard Fault exception occurs */
+ while (1)
+ {}
+}
+
+/**
+ * @brief This function handles Memory Manage exception.
+ * @param None
+ * @retval None
+ */
+void MemManage_Handler(void)
+{
+ /* Go to infinite loop when Memory Manage exception occurs */
+ while (1)
+ {}
+}
+
+/**
+ * @brief This function handles Bus Fault exception.
+ * @param None
+ * @retval None
+ */
+void BusFault_Handler(void)
+{
+ /* Go to infinite loop when Bus Fault exception occurs */
+ while (1)
+ {}
+}
+
+/**
+ * @brief This function handles Usage Fault exception.
+ * @param None
+ * @retval None
+ */
+void UsageFault_Handler(void)
+{
+ /* Go to infinite loop when Usage Fault exception occurs */
+ while (1)
+ {}
+}
+
+/**
+ * @brief This function handles SVCall exception.
+ * @param None
+ * @retval None
+ */
+void SVC_Handler(void)
+{}
+
+/**
+ * @brief This function handles Debug Monitor exception.
+ * @param None
+ * @retval None
+ */
+void DebugMon_Handler(void)
+{}
+
+/**
+ * @brief This function handles PendSVC exception.
+ * @param None
+ * @retval None
+ */
+void PendSV_Handler(void)
+{}
+
+/**
+ * @brief This function handles SysTick Handler.
+ * @param None
+ * @retval None
+ */
+void SysTick_Handler(void)
+{
+ /* Update the LocalTime by adding SYSTEMTICK_PERIOD_MS each SysTick interrupt */
+ Time_Update();
+}
+
+/******************************************************************************/
+/* STM32F10x Peripherals Interrupt Handlers */
+/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
+/* available peripheral interrupt handler's name please refer to the startup */
+/* file (startup_stm32f10x_xx.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles ETH interrupt request.
+ * @param None
+ * @retval None
+ */
+void ETH_IRQHandler(void)
+{
+ /* Handles all the received frames */
+ while(ETH_GetRxPktSize() != 0)
+ {
+ LwIP_Pkt_Handle();
+ }
+
+ /* Clear the Eth DMA Rx IT pending bits */
+ ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
+ ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
+}
+
+
+/**
+ * @brief This function handles External lines 15 to 10 interrupt request.
+ * @param None
+ * @retval None
+ */
+void EXTI15_10_IRQHandler(void)
+{
+
+;
+}
+
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Project/src/sys.c b/F107/Project/src/sys.c
new file mode 100644
index 0000000..fe2cb09
--- /dev/null
+++ b/F107/Project/src/sys.c
@@ -0,0 +1,5 @@
+#include "sys.h"
+
+//void NVIC_Configuration(void){ //嵌套中断向量控制器 的设置
+// NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); //设置NVIC中断分组2:2位抢占优先级，2位响应优先级
+//}
diff --git a/F107/Project/src/sys.h b/F107/Project/src/sys.h
new file mode 100644
index 0000000..48d5afa
--- /dev/null
+++ b/F107/Project/src/sys.h
@@ -0,0 +1,56 @@
+#ifndef __SYS_H
+#define __SYS_H
+#include "stm32f10x.h"
+
+
+//位带操作,实现51类似的GPIO控制功能
+//具体实现思想,参考<>第五章(87页~92页).
+//IO口操作宏定义
+#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
+#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
+#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
+//IO口地址映射
+#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C
+#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C
+#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C
+#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C
+#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C
+#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C
+#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C
+
+#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808
+#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08
+#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008
+#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408
+#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808
+#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08
+#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08
+
+//IO口操作,只对单一的IO口!
+//确保n的值小于16!
+#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //输出
+#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //输入
+
+#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出
+#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入
+
+#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出
+#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入
+
+#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //输出
+#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //输入
+
+#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出
+#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入
+
+#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //输出
+#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //输入
+
+#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //输出
+#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //输入
+
+
+
+void NVIC_Configuration(void); //嵌套中断控制器的设置
+
+#endif
diff --git a/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h
new file mode 100644
index 0000000..77972df
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval.h
@@ -0,0 +1,171 @@
+/**
+ ******************************************************************************
+ * @file stm3210c_eval.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains definitions for STM3210C_EVAL's Leds, push-buttons
+ * and COM ports hardware resources.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_H
+#define __STM3210C_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @addtogroup STM3210C_EVAL
+ * @{
+ */
+
+
+/** @defgroup STM3210C_EVAL_Exported_Types
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup STM3210C_EVAL_Exported_Constants
+ * @{
+ */
+
+/** @addtogroup STM3210C_EVAL_LED
+ * @{
+ */
+#define LEDn 4
+#define LED1_GPIO_PORT GPIOE
+#define LED1_GPIO_CLK RCC_APB2Periph_GPIOE
+#define LED1_GPIO_PIN GPIO_Pin_2
+
+#define LED2_GPIO_PORT GPIOE
+#define LED2_GPIO_CLK RCC_APB2Periph_GPIOE
+#define LED2_GPIO_PIN GPIO_Pin_3
+
+#define LED3_GPIO_PORT GPIOE
+#define LED3_GPIO_CLK RCC_APB2Periph_GPIOE
+#define LED3_GPIO_PIN GPIO_Pin_4
+
+#define LED4_GPIO_PORT GPIOE
+#define LED4_GPIO_CLK RCC_APB2Periph_GPIOE
+#define LED4_GPIO_PIN GPIO_Pin_5
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM3210C_EVAL_BUTTON
+ * @{
+ */
+#define BUTTONn 3 /*!< Joystick pins are connected to an IO Expander (accessible through I2C1 interface) */
+
+/**
+ * @brief Wakeup push-button
+ */
+#define WAKEUP_BUTTON_PORT GPIOA
+#define WAKEUP_BUTTON_CLK RCC_APB2Periph_GPIOA
+#define WAKEUP_BUTTON_PIN GPIO_Pin_0
+#define WAKEUP_BUTTON_EXTI_LINE EXTI_Line0
+#define WAKEUP_BUTTON_PORT_SOURCE GPIO_PortSourceGPIOA
+#define WAKEUP_BUTTON_PIN_SOURCE GPIO_PinSource0
+#define WAKEUP_BUTTON_IRQn EXTI0_IRQn
+
+/**
+ * @brief Tamper push-button
+ */
+#define TAMPER_BUTTON_PORT GPIOC
+#define TAMPER_BUTTON_CLK RCC_APB2Periph_GPIOC
+#define TAMPER_BUTTON_PIN GPIO_Pin_13
+#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13
+#define TAMPER_BUTTON_PORT_SOURCE GPIO_PortSourceGPIOC
+#define TAMPER_BUTTON_PIN_SOURCE GPIO_PinSource13
+#define TAMPER_BUTTON_IRQn EXTI15_10_IRQn
+
+/**
+ * @brief Key push-button
+ */
+#define KEY_BUTTON_PORT GPIOB
+#define KEY_BUTTON_CLK RCC_APB2Periph_GPIOB
+#define KEY_BUTTON_PIN GPIO_Pin_9
+#define KEY_BUTTON_EXTI_LINE EXTI_Line9
+#define KEY_BUTTON_PORT_SOURCE GPIO_PortSourceGPIOB
+#define KEY_BUTTON_PIN_SOURCE GPIO_PinSource9
+#define KEY_BUTTON_IRQn EXTI9_5_IRQn
+/**
+ * @}
+ */
+
+/** @addtogroup STM3210C_EVAL_COM
+ * @{
+ */
+#define COMn 1
+
+/**
+ * @brief Definition for COM port1, connected to USART2 (USART2 pins remapped on GPIOD)
+ */
+#define EVAL_COM1 USART2
+#define EVAL_COM1_GPIO GPIOD
+#define EVAL_COM1_CLK RCC_APB1Periph_USART2
+#define EVAL_COM1_GPIO_CLK RCC_APB2Periph_GPIOD
+#define EVAL_COM1_RxPin GPIO_Pin_6
+#define EVAL_COM1_TxPin GPIO_Pin_5
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup STM3210C_EVAL_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup STM3210C_EVAL_Exported_Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210C_EVAL_H */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c
new file mode 100644
index 0000000..a562c18
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.c
@@ -0,0 +1,1490 @@
+/**
+ ******************************************************************************
+ * @file stm3210c_eval_ioe.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file includes the IO Expander driver for STMPE811 IO Expander
+ * devices.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+ /* File Info : ---------------------------------------------------------------
+ SUPPORTED FEATURES:
+ - IO Read/write : Set/Reset and Read (Polling/Interrupt)
+ - Joystick: config and Read (Polling/Interrupt)
+ - Touch Screen Features: Single point mode (Polling/Interrupt)
+ - TempSensor Feature: accuracy not determined (Polling).
+
+ UNSUPPORTED FEATURES:
+ - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
+ ----------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210c_eval_ioe.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @defgroup STM3210C_EVAL_IOE
+ * @brief This file includes the IO Expander driver for STMPE811 IO Expander
+ * devices.
+ * @{
+ */
+
+/** @defgroup EVAL_IOE_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup EVAL_IOE_Private_Defines
+ * @{
+ */
+#define TIMEOUT_MAX 0xFFF; /* _x? (x - _x): (_x - x);
+ yDiff = y > _y? (y - _y): (_y - y);
+ if (xDiff + yDiff > 5)
+ {
+ _x = x;
+ _y = y;
+ }
+ }
+ /* Update the X position */
+ TS_State.X = _x;
+
+ /* Update the Y position */
+ TS_State.Y = _y;
+ /* Update the Z Pression index */
+ TS_State.Z = IOE_TS_Read_Z();
+
+ /* Clear the interrupt pending bit and enable the FIFO again */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+
+ /* Return pointer to the updated structure */
+ return &TS_State;
+}
+
+/**
+ * @brief Returns the temperature row value (in 16 bit format).
+ * @param None
+ * @retval The temperature row value.
+ */
+uint32_t IOE_TempSens_GetData(void)
+{
+ static __IO uint32_t tmp = 0;
+
+ /* Aquire data enable */
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x03);
+
+ /* Enable the TEMPSENS module */
+ tmp = (uint32_t)((I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA) & 0x03) << 8);
+ tmp |= (uint32_t)I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_DATA + 1);
+
+ tmp = (uint32_t)((33 * tmp * 100) / 751);
+ tmp = (uint32_t)((tmp + 5) / 10);
+
+ /* return the temprature row value */
+ return tmp;
+}
+
+/**
+ * @brief Checks the selected Global interrupt source pending bit
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param Global_IT: the Global interrupt source to be checked, could be:
+ * @arg Global_IT_GPIO : All IOs interrupt
+ * @arg Global_IT_ADC : ADC interrupt
+ * @arg Global_IT_TEMP : Temperature Sensor interrupts
+ * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+ * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt
+ * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
+ * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
+ * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
+ * @retval Status of the checked flag. Could be SET or RESET.
+ */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+ __IO uint8_t tmp = 0;
+
+ /* get the Interrupt status */
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_STA);
+
+ if ((tmp & (uint8_t)Global_IT) != 0)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief Clears the selected Global interrupt pending bit(s)
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param Global_IT: the Global interrupt to be cleared, could be any combination
+ * of the following values:
+ * @arg Global_IT_GPIO : All IOs interrupt
+ * @arg Global_IT_ADC : ADC interrupt
+ * @arg Global_IT_TEMP : Temperature Sensor interrupts
+ * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+ * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt
+ * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
+ * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
+ * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t Global_IT)
+{
+ /* Write 1 to the bits that have to be cleared */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_STA, Global_IT);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Checks the status of the selected IO interrupt pending bit
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be
+ * from 0 to 7.
+ * @retval Status of the checked flag. Could be SET or RESET.
+ */
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+ uint8_t tmp = 0;
+
+ /* get the Interrupt status */
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA);
+
+ if ((tmp & (uint8_t)IO_IT) != 0)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief Clears the selected IO interrupt pending bit(s).
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param IO_IT: the IO interrupt to be checked could be IO_ITx Where x can be
+ * from 0 to 7.
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT)
+{
+ /* Write 1 to the bits that have to be cleared */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_STA, IO_IT);
+
+ /* Clear the Edge detection pending bit*/
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_ED, IO_IT);
+
+ /* Clear the Rising edge pending bit */
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_RE, IO_IT);
+
+ /* Clear the Falling edge pending bit */
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_GPIO_FE, IO_IT);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Checks if the selected device is correctly configured and
+ * communicates correctly ont the I2C bus.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @retval IOE_OK if IOE is operational. Other value if failure.
+ */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr)
+{
+ /* Return Error if the ID is not correct */
+ if( IOE_ReadID(DeviceAddr) != (uint16_t)STMPE811_ID )
+ {
+ /* Check if a Timeout occured */
+ if (TimeOut == 0)
+ {
+ return IOE_TIEMOUT;
+ }
+ else
+ {
+ return IOE_FAILURE; /* ID is not Correct */
+ }
+ }
+ else
+ {
+ return IOE_OK; /* ID is correct */
+ }
+}
+
+/**
+ * @brief Resets the IO Expander by Software (SYS_CTRL1, RESET bit).
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_Reset(uint8_t DeviceAddr)
+{
+ /* Power Down the IO_Expander */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x02);
+
+ /* wait for a delay to insure registers erasing */
+ _delay_(2);
+
+ /* Power On the Codec after the power off => all registers are reinitialized*/
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL1, 0x00);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Reads the selected device's ID.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @retval The Device ID (two bytes).
+ */
+uint16_t IOE_ReadID(uint8_t DeviceAddr)
+{
+ uint16_t tmp = 0;
+
+ /* Read device ID */
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, 0);
+ tmp = (uint32_t)(tmp << 8);
+ tmp |= (uint32_t)I2C_ReadDeviceRegister(DeviceAddr, 1);
+
+ /* Return the ID */
+ return (uint16_t)tmp;
+}
+
+/**
+ * @brief Configures the selcted IO Expander functionalities.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param IOE_TEMPSENS_FCT: the functions to be configured. could be any
+ * combination of the following values:
+ * @arg IOE_IO_FCT : IO function
+ * @arg IOE_TS_FCT : Touch Screen function
+ * @arg IOE_ADC_FCT : ADC function
+ * @arg IOE_TEMPSENS_FCT : Tempreature Sensor function
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState)
+{
+ uint8_t tmp = 0;
+
+ /* Get the register value */
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2);
+
+ if (NewState != DISABLE)
+ {
+ /* Set the Functionalities to be Enabled */
+ tmp &= ~(uint8_t)Fct;
+ }
+ else
+ {
+ /* Set the Functionalities to be Disabled */
+ tmp |= (uint8_t)Fct;
+ }
+
+ /* Set the register value */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_SYS_CTRL2, tmp);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures the selected pin direction (to be an input or an output)
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param IO_Pin: IO_Pin_x: Where x can be from 0 to 7.
+ * @param Direction: could be Direction_IN or Direction_OUT.
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction)
+{
+ uint8_t tmp = 0;
+
+ /* Get all the Pins direction */
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR);
+
+ if (Direction != Direction_IN)
+ {
+ tmp |= (uint8_t)IO_Pin;
+ }
+ else
+ {
+ tmp &= ~(uint8_t)IO_Pin;
+ }
+
+ /* Write the register new value */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_DIR, tmp);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Enables or disables the Global interrupt.
+ * @param DeviceAddr: The address of the IOExpander, could be :I OE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param NewState: could be ENABLE or DISABLE.
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState)
+{
+ uint8_t tmp = 0;
+
+ /* Read the Interrupt Control register */
+ I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL);
+
+ if (NewState != DISABLE)
+ {
+ /* Set the global interrupts to be Enabled */
+ tmp |= (uint8_t)IOE_GIT_EN;
+ }
+ else
+ {
+ /* Set the global interrupts to be Disabled */
+ tmp &= ~(uint8_t)IOE_GIT_EN;
+ }
+
+ /* Write Back the Interrupt Control register */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_CTRL, tmp);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures the selected source to generate or not a global interrupt
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param Global_IT: the interrupt source to be configured, could be:
+ * @arg Global_IT_GPIO : All IOs interrupt
+ * @arg Global_IT_ADC : ADC interrupt
+ * @arg Global_IT_TEMP : Temperature Sensor interrupts
+ * @arg Global_IT_FE : Touch Screen Controller FIFO Error interrupt
+ * @arg Global_IT_FF : Touch Screen Controller FIFO Full interrupt
+ * @arg Global_IT_FOV : Touch Screen Controller FIFO Overrun interrupt
+ * @arg Global_IT_FTH : Touch Screen Controller FIFO Threshold interrupt
+ * @arg Global_IT_TOUCH : Touch Screen Controller Touch Detected interrupt
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState)
+{
+ uint8_t tmp = 0;
+
+ /* Get the current value of the INT_EN register */
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_INT_EN);
+
+ if (NewState != DISABLE)
+ {
+ /* Set the interrupts to be Enabled */
+ tmp |= (uint8_t)Global_IT;
+ }
+ else
+ {
+ /* Set the interrupts to be Disabled */
+ tmp &= ~(uint8_t)Global_IT;
+ }
+ /* Set the register */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_INT_EN, tmp);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures the selected pins to generate an interrupt or not.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param IO_IT: The IO interrupt to be configured. This parameter could be any
+ * combination of the following values:
+ * @arg IO_IT_x: where x can be from 0 to 7.
+ * @param NewState: could be ENABLE or DISABLE.
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState)
+{
+ uint8_t tmp = 0;
+
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN);
+
+ if (NewState != DISABLE)
+ {
+ /* Set the interrupts to be Enabled */
+ tmp |= (uint8_t)IO_IT;
+ }
+ else
+ {
+ /* Set the interrupts to be Disabled */
+ tmp &= ~(uint8_t)IO_IT;
+ }
+
+ /* Set the register */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_INT_EN, tmp);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures the touch Screen Controller (Single point detection)
+ * @param None
+ * @retval IOE_OK if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_TS_Config(void)
+{
+ uint8_t tmp = 0;
+
+ /* Enable TSC Fct: already done in IOE_Config */
+ tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2);
+ tmp &= ~(uint32_t)(IOE_TS_FCT | IOE_ADC_FCT);
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_SYS_CTRL2, tmp);
+
+ /* Enable the TSC gloabl interrupts */
+ tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN);
+ tmp |= (uint32_t)(IOE_GIT_TOUCH | IOE_GIT_FTH | IOE_GIT_FOV);
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_EN, tmp);
+
+ /* Select Sample Time, bit number and ADC Reference */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL1, 0x49);
+
+ /* Wait for ~20 ms */
+ _delay_(2);
+
+ /* Select the ADC clock speed: 3.25 MHz */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_ADC_CTRL2, 0x01);
+
+ /* Select TSC pins in non default mode */
+ tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF);
+ tmp &= ~(uint8_t)TOUCH_IO_ALL;
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_GPIO_AF, tmp);
+
+ /* Select 2 nF filter capacitor */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CFG, 0x9A);
+
+ /* Select single point reading */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_TH, 0x01);
+
+ /* Write 0x01 to clear the FIFO memory content. */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x01);
+
+ /* Write 0x00 to put the FIFO back into operation mode */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_FIFO_STA, 0x00);
+
+ /* set the data format for Z value: 7 fractional part and 1 whole part */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_FRACT_XYZ, 0x01);
+
+ /* set the driving capability of the device for TSC pins: 50mA */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_I_DRIVE, 0x01);
+
+ /* Use no tracking index, touchscreen controller operation mode (XYZ) and
+ enable the TSC */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_TSC_CTRL, 0x01);
+
+ /* Clear all the status pending bits */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_STA, 0xFF);
+
+ /* Initialize the TS structure to their default values */
+ TS_State.TouchDetected = TS_State.X = TS_State.Y = TS_State.Z = 0;
+
+ /* All configuration done */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures and enables the Temperature sensor module.
+ * @param None
+ * @retval IOE_OK if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_TempSens_Config(void)
+{
+ __IO uint8_t tmp = 0;
+
+ /* Enable Temperature Sensor Fct: already done in IOE_Config */
+ tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2);
+ tmp &= ~(uint32_t)(IOE_TEMPSENS_FCT | IOE_ADC_FCT);
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_SYS_CTRL2, tmp);
+
+ /* Enable the TEMPSENS module */
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x01);
+
+ /* Aquire data enable */
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_TEMP_CTRL, 0x3);
+
+ /* All configuration done */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures the selected pin to be in Alternate function or not
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7.
+ * @param NewState: State of the AF for the selected pin, could be
+ * ENABLE or DISABLE.
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState)
+{
+ uint8_t tmp = 0;
+
+ /* Get the current state of the GPIO_AF register */
+ tmp = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF);
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected pins alternate function */
+ tmp |= (uint8_t)IO_Pin;
+ }
+ else
+ {
+ /* Disable the selected pins alternate function */
+ tmp &= ~(uint8_t)IO_Pin;
+ }
+
+ /* Write back the new valu in GPIO_AF register */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_AF, tmp);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures the Edge for which a transition is detectable for the
+ * the selected pin.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param IO_Pin: IO_Pin_x, Where x can be from 0 to 7.
+ * @param Edge: The edge which will be detected. This parameter can be one or a
+ * a combination of follwing values: EDGE_FALLING and EDGE_RISING .
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge)
+{
+ uint8_t tmp1 = 0, tmp2 = 0;
+
+ /* Get the registers values */
+ tmp1 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE);
+ tmp2 = I2C_ReadDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE);
+
+ /* Disable the Falling Edge */
+ tmp1 &= ~(uint8_t)IO_Pin;
+ /* Disable the Falling Edge */
+ tmp2 &= ~(uint8_t)IO_Pin;
+
+ /* Enable the Falling edge if selected */
+ if (Edge & EDGE_FALLING)
+ {
+ tmp1 |= (uint8_t)IO_Pin;
+ }
+
+ /* Enable the Rising edge if selected */
+ if (Edge & EDGE_RISING)
+ {
+ tmp2 |= (uint8_t)IO_Pin;
+ }
+
+ /* Write back the registers values */
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_FE, tmp1);
+ I2C_WriteDeviceRegister(DeviceAddr, IOE_REG_GPIO_RE, tmp2);
+
+ /* if OK return 0 */
+ return IOE_OK;
+}
+
+/**
+ * @brief Configures the Interrupt line active state and format (level/edge)
+ * @param Polarity: could be
+ * @arg Polarity_Low: Interrupt line is active Low/Falling edge
+ * @arg Polarity_High: Interrupt line is active High/Rising edge
+ * @param Type: Interrupt line activity type, could be one of the following values
+ * @arg Type_Level: Interrupt line is active in level model
+ * @arg Type_Edge: Interrupt line is active in edge model
+ * @retval IOE_OK: if all initializations are OK. Other value if error.
+ */
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type)
+{
+ uint8_t tmp = 0;
+
+ /* Get the register IOE_REG_INT_CTRL value */
+ tmp = I2C_ReadDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL);
+
+ /* Mask the polarity and type bits */
+ tmp &= ~(uint8_t)0x06;
+
+ /* Modify the Interrupt Output line configuration */
+ tmp |= (uint8_t)(Polarity | Type);
+
+ /* Set the register */
+ I2C_WriteDeviceRegister(IOE_1_ADDR, IOE_REG_INT_CTRL, tmp);
+
+
+ /* Get the register IOE_REG_INT_CTRL value */
+ tmp = I2C_ReadDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL);
+ /* Mask the polarity and type bits */
+ tmp &= ~(uint8_t)0x06;
+
+ /* Modify the Interrupt Output line configuration */
+ tmp |= (uint8_t)(Polarity | Type);
+
+ /* Set the register */
+ I2C_WriteDeviceRegister(IOE_2_ADDR, IOE_REG_INT_CTRL, tmp);
+
+ /* If all OK return IOE_OK */
+ return IOE_OK;
+}
+
+/**
+ * @brief Writes a value in a register of the IOE through I2C.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param RegisterAddr: The target register adress
+ * @param RegisterValue: The target register value to be written
+ * @retval IOE_OK: if all operations are OK. Other value if error.
+ */
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue)
+{
+ uint32_t read_verif = 0;
+
+ /* Reset all I2C2 registers */
+ I2C_SoftwareResetCmd(IOE_I2C, ENABLE);
+ I2C_SoftwareResetCmd(IOE_I2C, DISABLE);
+
+ TimeOut = TIMEOUT_MAX;
+
+ /* Enable the IOE_I2C peripheral */
+ I2C_Cmd(IOE_I2C, ENABLE);
+
+ /* Configure the I2C peripheral */
+ IOE_I2C_Config();
+
+ /* Begin the config sequence */
+ I2C_GenerateSTART(IOE_I2C, ENABLE);
+
+ /* Test on EV5 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Transmit the slave address and enable writing operation */
+ I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+
+ /* Test on EV6 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Transmit the first address for r/w operations */
+ I2C_SendData(IOE_I2C, RegisterAddr);
+
+ TimeOut = TIMEOUT_MAX;
+
+ /* Test on EV8 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Prepare the register value to be sent */
+ I2C_SendData(IOE_I2C, RegisterValue);
+
+ /* Test on EV8 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* End the configuration sequence */
+ I2C_GenerateSTOP(IOE_I2C, ENABLE);
+
+#ifdef VERIFY_WRITTENDATA
+ /* Verify (if needed) that the loaded data is correct */
+
+ /* Read the just written register*/
+ read_verif = I2C_ReadDeviceRegister(DeviceAddr, RegisterAddr);
+ /* Load the register and verify its value */
+ if (read_verif != RegisterValue)
+ {
+ /* Control data wrongly tranfered */
+ read_verif = IOE_FAILURE;
+ }
+ else
+ {
+ /* Control data correctly transfered */
+ read_verif = 0;
+ }
+#endif
+
+ /* Return the verifying value: 0 (Passed) or 1 (Failed) */
+ return read_verif;
+}
+
+/**
+ * @brief Reads a register of the audio Codec through I2C.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param RegisterAddr: The target register adress (between 00x and 0x24)
+ * @retval The value of the read register (0xAA if Timout occured)
+ */
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr)
+{
+ uint32_t tmp = 0;
+
+ /* Disable the IOE_I2C peripheral */
+ I2C_Cmd(IOE_I2C, DISABLE);
+
+ /* Reset all I2C2 registers */
+ I2C_SoftwareResetCmd(IOE_I2C, ENABLE);
+ I2C_SoftwareResetCmd(IOE_I2C, DISABLE);
+
+ /* Configure the I2C peripheral */
+ IOE_I2C_Config();
+
+ /* Enable the I2C peripheral */
+ I2C_GenerateSTART(IOE_I2C, ENABLE);
+
+ TimeOut = TIMEOUT_MAX;
+ /* Test on EV5 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+ /* Disable Acknowledgement */
+ I2C_AcknowledgeConfig(IOE_I2C, DISABLE);
+
+ /* Transmit the slave address and enable writing operation */
+ I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Transmitter);
+
+ TimeOut = TIMEOUT_MAX;
+ /* Test on EV6 and clear it */
+
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Transmit the first address for r/w operations */
+ I2C_SendData(IOE_I2C, RegisterAddr);
+
+ /* Test on EV8 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+ /* Regenerate a start condition */
+ I2C_GenerateSTART(IOE_I2C, ENABLE);
+
+ /* Test on EV5 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_MODE_SELECT))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Transmit the slave address and enable writing operation */
+ I2C_Send7bitAddress(IOE_I2C, DeviceAddr, I2C_Direction_Receiver);
+
+ /* Test on EV6 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Test on EV7 and clear it */
+ while (!I2C_CheckEvent(IOE_I2C, I2C_EVENT_MASTER_BYTE_RECEIVED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* End the configuration sequence */
+ I2C_GenerateSTOP(IOE_I2C, ENABLE);
+
+ /* Load the register value */
+ tmp = I2C_ReceiveData(IOE_I2C);
+
+ /* Enable Acknowledgement */
+ I2C_AcknowledgeConfig(IOE_I2C, ENABLE);
+
+ /* Return the read value */
+ return tmp;
+}
+
+
+/**
+ * @brief Reads a buffer of 4 bytes from IO_Expander registers.
+ * @param DeviceAddr: The address of the IOExpander, could be : IOE_1_ADDR
+ * or IOE_2_ADDR.
+ * @param RegisterAddr: The target register adress (between 00x and 0x24)
+ * @retval : The value of the read register (0xAA if Timout occured)
+ */
+uint32_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr)
+{
+ uint8_t Buffer[4] , idx = 2;
+
+ /* Initialize the buffer */
+ Buffer[0] = 0;
+ Buffer[1] = 0;
+ Buffer[2] = 0;
+ Buffer[3] = 0;
+
+ /* Disable the I2C1 peripheral */
+ I2C_Cmd(I2C1, DISABLE);
+
+ /* Reset all I2C2 registers */
+ I2C_SoftwareResetCmd(I2C1, ENABLE);
+ I2C_SoftwareResetCmd(I2C1, DISABLE);
+
+ /* Configure the I2C peripheral */
+ IOE_I2C_Config();
+
+ /* Enable the I2C peripheral */
+ I2C_GenerateSTART(I2C1, ENABLE);
+
+ TimeOut = TIMEOUT_MAX;
+
+ /* Test on EV5 and clear it */
+ while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Send device address for write */
+ I2C_Send7bitAddress(I2C1, DeviceAddr, I2C_Direction_Transmitter);
+
+ /* Test on EV6 and clear it */
+ while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Clear EV6 by setting again the PE bit */
+ I2C_Cmd(I2C1, ENABLE);
+
+ /* Send the device's internal address to write to */
+ I2C_SendData(I2C1, RegisterAddr);
+
+ /* Test on EV8 and clear it */
+ while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Send STRAT condition a second time */
+ I2C_GenerateSTART(I2C1, ENABLE);
+
+ /* Test on EV5 and clear it */
+ while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_MODE_SELECT))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* Send EEPROM address for read */
+ I2C_Send7bitAddress(I2C1, DeviceAddr, I2C_Direction_Receiver);
+
+ /* Test on EV6 and clear it */
+ while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
+ {
+ if (TimeOut-- == 0) return IOE_TIEMOUT;
+ }
+
+ /* While there is data to be read */
+ while(idx)
+ {
+ if(idx == 1)
+ {
+ /* Disable Acknowledgement */
+ I2C_AcknowledgeConfig(I2C1, DISABLE);
+
+ /* Send STOP Condition */
+ I2C_GenerateSTOP(I2C1, ENABLE);
+ }
+
+ /* Test on EV7 and clear it */
+ if(I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_RECEIVED))
+ {
+ /* Read a byte from the EEPROM */
+ Buffer[idx-1] = I2C_ReceiveData(I2C1);
+
+ /* Decrement the read bytes counter */
+ idx--;
+ }
+ }
+
+ /* Enable Acknowledgement to be ready for another reception */
+ I2C_AcknowledgeConfig(I2C1, ENABLE);
+
+ /* return a pointer to the buffer */
+ return *(uint32_t *)Buffer;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+/**
+ * @brief Return Touch Screen X position value
+ * @param None
+ * @retval X position.
+ */
+static uint16_t IOE_TS_Read_X(void)
+{
+ int32_t x, xr;
+
+ x = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Y);
+
+ /* first correction */
+ xr = (x * 320) >> 12;
+ /* second correction */
+ xr = ((xr * 32)/29) - 17;
+
+ if(xr <= 0)
+ xr = 0;
+
+ return (uint16_t)(xr);
+}
+
+/**
+ * @brief Return Touch Screen Y position value
+ * @param None
+ * @retval Y position.
+ */
+static uint16_t IOE_TS_Read_Y(void)
+{
+ int32_t y, yr;
+ y= I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_X);
+
+ yr= (y * 240) >> 12;
+ yr = ((yr * 240) / 217) - 12;
+
+ if(yr <= 0)
+ yr = 0;
+
+ return (uint16_t)(yr);
+}
+
+/**
+ * @brief Return Touch Screen Z position value
+ * @param None
+ * @retval Z position.
+ */
+static uint16_t IOE_TS_Read_Z(void)
+{
+ uint32_t z;
+ z = I2C_ReadDataBuffer(IOE_1_ADDR, IOE_REG_TSC_DATA_Z);
+
+
+ if(z <= 0)
+ z = 0;
+
+ return (uint16_t)(z);
+}
+
+/**
+ * @brief Initializes the GPIO pins used by the IO expander.
+ * @param None
+ * @retval None
+ */
+static void IOE_GPIO_Config(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Enable IOE_I2C and IOE_I2C_PORT & Alternate Function clocks */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_IOE_I2C, ENABLE);
+ RCC_APB2PeriphClockCmd(RCC_APB_IOE_I2C_PORT | RCC_APB_GPIO_IOE_ITPORT | RCC_APB2Periph_AFIO, ENABLE);
+
+ /* Reset IOE_I2C IP */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_IOE_I2C, ENABLE);
+
+ /* Release reset signal of IOE_I2C IP */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_IOE_I2C, DISABLE);
+
+ /* IOE_I2C SCL and SDA pins configuration */
+ GPIO_InitStructure.GPIO_Pin = IOE_SCL_PIN | IOE_SDA_PIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
+ GPIO_Init(IOE_I2C_PORT, &GPIO_InitStructure);
+
+ /* Set EXTI pin as Input PullUp - IO_Expander_INT */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_IOE_ITPIN;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+ GPIO_Init(GPIO_IOE_ITPORT, &GPIO_InitStructure);
+
+ /* Connect IO Expander IT line to EXTI line */
+ GPIO_EXTILineConfig(GPIO_PortSource_IOE_ITPORT, GPIO_PinSource_IOE_ITPIN);
+}
+
+
+/**
+ * @brief Configure the I2C Peripheral used to communicate with IO_Expanders.
+ * @param None
+ * @retval None
+ */
+static void IOE_I2C_Config(void)
+{
+ I2C_InitTypeDef I2C_InitStructure;
+
+ /* IOE_I2C configuration */
+ I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
+ I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
+ I2C_InitStructure.I2C_OwnAddress1 = 0x00;
+ I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
+ I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+ I2C_InitStructure.I2C_ClockSpeed = IOE_I2C_SPEED;
+
+ I2C_Init(IOE_I2C, &I2C_InitStructure);
+}
+
+
+/**
+ * @brief Configures the IO expander Interrupt line and GPIO in EXTI mode.
+ * @param None
+ * @retval None
+ */
+static void IOE_EXTI_Config(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+ NVIC_InitTypeDef NVIC_InitStructure;
+ EXTI_InitTypeDef EXTI_InitStructure;
+
+ /* Enable Button GPIO clock */
+ RCC_APB2PeriphClockCmd(RCC_APB_GPIO_IOE_ITPORT | RCC_APB2Periph_AFIO, ENABLE);
+
+ /* Configure Button pin as input floating */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_IOE_ITPIN;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(GPIO_IOE_ITPORT, &GPIO_InitStructure);
+
+ /* Connect Button EXTI Line to Button GPIO Pin */
+ GPIO_EXTILineConfig(GPIO_PortSource_IOE_ITPORT, GPIO_PinSource_IOE_ITPIN);
+
+ /* Configure Button EXTI line */
+ EXTI_InitStructure.EXTI_Line = EXTI_LINE_IOE_ITLINE;
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+ EXTI_Init(&EXTI_InitStructure);
+
+ /* Enable and set Button EXTI Interrupt to the lowest priority */
+ NVIC_InitStructure.NVIC_IRQChannel = IOE_IT_EXTI_IRQn;
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+ NVIC_Init(&NVIC_InitStructure);
+}
+
+#ifndef USE_Delay
+/**
+ * @brief Inserts a delay time.
+ * @param nCount: specifies the delay time length.
+ * @retval None
+ */
+static void delay(__IO uint32_t nCount)
+{
+ __IO uint32_t index = 0;
+ for(index = (100000 * nCount); index != 0; index--)
+ {
+ }
+}
+#endif /* USE_Delay*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h
new file mode 100644
index 0000000..fc301b1
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_ioe.h
@@ -0,0 +1,466 @@
+/**
+ ******************************************************************************
+ * @file stm3210c_eval_ioe.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the IO Expander
+ * firmware driver.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+ /* File Info : ---------------------------------------------------------------
+ SUPPORTED FEATURES:
+ - IO Read/write : Set/Reset and Read (Polling/Interrupt)
+ - Joystick: config and Read (Polling/Interrupt)
+ - Touch Screen Features: Single point mode (Polling/Interrupt)
+ - TempSensor Feature: accuracy not determined (Polling).
+
+ UNSUPPORTED FEATURES:
+ - Row ADC Feature is not supported (not implemented on STM3210C-EVAL board)
+ ----------------------------------------------------------------------------*/
+
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __IO_EXPANDER_H
+#define __IO_EXPANDER_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @defgroup STM3210C_EVAL_IOE
+ * @brief STM3210C_EVAL_IOE IO Expander driver modules
+ * @{
+ */
+
+
+/** @defgroup EVAL_IOE_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief Touch Screen Information structure
+ */
+typedef struct
+{
+ uint16_t TouchDetected;
+ uint16_t X;
+ uint16_t Y;
+ uint16_t Z;
+}TS_STATE;
+
+/**
+ * @brief Joystick State definitions
+ */
+#ifndef __STM32_EVAL_H
+typedef enum
+{
+ JOY_NONE = 0,
+ JOY_CENTER = 1,
+ JOY_DOWN = 2,
+ JOY_LEFT = 3,
+ JOY_RIGHT = 4,
+ JOY_UP = 5
+} JOY_State_TypeDef;
+#endif /* __STM32_EVAL_H */
+
+/**
+ * @brief IO_Expander Error codes
+ */
+typedef enum
+{
+ IOE_OK = 0,
+ IOE_FAILURE,
+ IOE_TIEMOUT,
+ PARAM_ERROR,
+ IOE1_NOT_OPERATIONAL,
+ IOE2_NOT_OPERATIONAL
+}IOE_Status_TypDef;
+
+/**
+ * @brief IO bit values
+ */
+typedef enum
+{
+ BitReset = 0,
+ BitSet = 1
+}IOE_BitValue_TypeDef;
+
+/**
+ * @}
+ */
+
+
+/** @defgroup EVAL_IOE_Exported_Constants
+ * @{
+ */
+
+/**
+ * @brief Uncomment the line below to enable verfying each written byte in write
+ * operation. The I2C_WriteDeviceRegister() function will then compare the
+ * written and read data and return error status if a mismatch occurs.
+ */
+/* #define VERIFY_WRITTENDATA */
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ * (for precise timing), otherwise default _delay_ function defined within
+ * this driver is used (less precise timing).
+ */
+/* #define USE_Delay */
+
+#ifdef USE_Delay
+#include "main.h"
+
+ #define _delay_ Delay /* !< User can provide more timing precise _delay_ function
+ (with 10ms time base), using SysTick for example */
+#else
+ #define _delay_ delay /* !< Default _delay_ function with less precise timing */
+#endif
+
+/*------------------------------------------------------------------------------
+ Hardware Configuration
+------------------------------------------------------------------------------*/
+/**
+ * @brief I2C port definitions
+ */
+#define IOE_I2C I2C1
+#define IOE_I2C_PORT GPIOB
+#define IOE_SCL_PIN GPIO_Pin_6
+#define IOE_SDA_PIN GPIO_Pin_7
+#define RCC_APB1Periph_IOE_I2C RCC_APB1Periph_I2C1
+#define RCC_APB_IOE_I2C_PORT RCC_APB2Periph_GPIOB
+#define IOE_I2C_SPEED 400000
+
+/**
+ * @brief IO Expander Interrupt line on EXTI
+ */
+#define GPIO_Pin_IOE_ITPIN GPIO_Pin_14
+#define GPIO_IOE_ITPORT GPIOB
+#define RCC_APB_GPIO_IOE_ITPORT RCC_APB2Periph_GPIOB
+#define GPIO_PortSource_IOE_ITPORT GPIO_PortSourceGPIOB
+#define GPIO_PinSource_IOE_ITPIN GPIO_PinSource14
+#define EXTI_LINE_IOE_ITLINE EXTI_Line14
+#define IOE_IT_EXTI_IRQn EXTI15_10_IRQn
+
+/** @brief Eval Board IO Pins definition
+ * @{
+ */
+#define AUDIO_RESET_PIN IO_Pin_2 /* IO_Exapnader_2 */ /* Output */
+#define MII_INT_PIN IO_Pin_0 /* IO_Exapnader_2 */ /* Output */
+#define VBAT_DIV_PIN IO_Pin_0 /* IO_Exapnader_1 */ /* Output */
+#define MEMS_INT1_PIN IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define MEMS_INT2_PIN IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+
+/** @brief Eval Board both IO Exapanders Pins definition
+ * @{
+ */
+#define IO1_IN_ALL_PINS (uint32_t)(MEMS_INT1_PIN | MEMS_INT2_PIN)
+#define IO2_IN_ALL_PINS (uint32_t)(JOY_IO_PINS)
+#define IO1_OUT_ALL_PINS (uint32_t)(VBAT_DIV_PIN)
+#define IO2_OUT_ALL_PINS (uint32_t)(AUDIO_RESET_PIN | MII_INT_PIN)
+
+/**
+ * @brief The 7 bits IO Expanders adresses and chip IDs
+ */
+#define IOE_1_ADDR 0x82
+#define IOE_2_ADDR 0x88
+#define STMPE811_ID 0x0811
+
+
+/*------------------------------------------------------------------------------
+ Functional and Interrupt Management
+------------------------------------------------------------------------------*/
+/**
+ * @brief IO Expander Functionalities definitions
+ */
+#define IOE_ADC_FCT 0x01
+#define IOE_TS_FCT 0x02
+#define IOE_IO_FCT 0x04
+#define IOE_TEMPSENS_FCT 0x08
+
+/**
+ * @brief Interrupt source configuration definitons
+ */
+#define IOE_ITSRC_TSC 0x01 /* IO_Exapnder 1 */
+#define IOE_ITSRC_INMEMS 0x02 /* IO_Exapnder 1 */
+#define IOE_ITSRC_JOYSTICK 0x04 /* IO_Exapnder 2 */
+#define IOE_ITSRC_TEMPSENS 0x08 /* IO_Exapnder 2 */
+
+/**
+ * @brief Glaobal Interrupts definitions
+ */
+#define IOE_GIT_GPIO 0x80
+#define IOE_GIT_ADC 0x40
+#define IOE_GIT_TEMP 0x20
+#define IOE_GIT_FE 0x10
+#define IOE_GIT_FF 0x08
+#define IOE_GIT_FOV 0x04
+#define IOE_GIT_FTH 0x02
+#define IOE_GIT_TOUCH 0x01
+
+
+/*------------------------------------------------------------------------------
+ STMPE811 device register definition
+------------------------------------------------------------------------------*/
+/**
+ * @brief Identification registers
+ */
+#define IOE_REG_CHP_ID 0x00
+#define IOE_REG_ID_VER 0x02
+ /**
+ * @brief General Control Registers
+ */
+#define IOE_REG_SYS_CTRL1 0x03
+#define IOE_REG_SYS_CTRL2 0x04
+#define IOE_REG_SPI_CFG 0x08
+/**
+ * @brief Interrupt Control register
+ */
+#define IOE_REG_INT_CTRL 0x09
+#define IOE_REG_INT_EN 0x0A
+#define IOE_REG_INT_STA 0x0B
+#define IOE_REG_GPIO_INT_EN 0x0C
+#define IOE_REG_GPIO_INT_STA 0x0D
+/**
+ * @brief GPIO Registers
+ */
+#define IOE_REG_GPIO_SET_PIN 0x10
+#define IOE_REG_GPIO_CLR_PIN 0x11
+#define IOE_REG_GPIO_MP_STA 0x12
+#define IOE_REG_GPIO_DIR 0x13
+#define IOE_REG_GPIO_ED 0x14
+#define IOE_REG_GPIO_RE 0x15
+#define IOE_REG_GPIO_FE 0x16
+#define IOE_REG_GPIO_AF 0x17
+/**
+ * @brief ADC Registers
+ */
+#define IOE_REG_ADC_INT_EN 0x0E
+#define IOE_REG_ADC_INT_STA 0x0F
+#define IOE_REG_ADC_CTRL1 0x20
+#define IOE_REG_ADC_CTRL2 0x21
+#define IOE_REG_ADC_CAPT 0x22
+#define IOE_REG_ADC_DATA_CH0 0x30 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH1 0x32 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH2 0x34 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH3 0x36 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH4 0x38 /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH5 0x3A /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH6 0x3B /* 16-Bit register */
+#define IOE_REG_ADC_DATA_CH7 0x3C /* 16-Bit register */
+/**
+ * @brief TouchScreen Registers
+ */
+#define IOE_REG_TSC_CTRL 0x40
+#define IOE_REG_TSC_CFG 0x41
+#define IOE_REG_WDM_TR_X 0x42
+#define IOE_REG_WDM_TR_Y 0x44
+#define IOE_REG_WDM_BL_X 0x46
+#define IOE_REG_WDM_BL_Y 0x48
+#define IOE_REG_FIFO_TH 0x4A
+#define IOE_REG_FIFO_STA 0x4B
+#define IOE_REG_FIFO_SIZE 0x4C
+#define IOE_REG_TSC_DATA_X 0x4D
+#define IOE_REG_TSC_DATA_Y 0x4F
+#define IOE_REG_TSC_DATA_Z 0x51
+#define IOE_REG_TSC_DATA_XYZ 0x52
+#define IOE_REG_TSC_FRACT_XYZ 0x56
+#define IOE_REG_TSC_DATA 0x57
+#define IOE_REG_TSC_I_DRIVE 0x58
+#define IOE_REG_TSC_SHIELD 0x59
+/**
+ * @brief Temperature Sensor registers
+ */
+#define IOE_REG_TEMP_CTRL 0x60
+#define IOE_REG_TEMP_DATA 0x61
+#define IOE_REG_TEMP_TH 0x62
+
+
+/*------------------------------------------------------------------------------
+ Functions parameters defines
+------------------------------------------------------------------------------*/
+/** @brief Touch Screen Pins definition
+ * @{
+ */
+#define TOUCH_YD IO_Pin_1 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XD IO_Pin_2 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_YU IO_Pin_3 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_XU IO_Pin_4 /* IO_Exapnader_1 */ /* Input */
+#define TOUCH_IO_ALL (uint32_t)(IO_Pin_1 | IO_Pin_2 | IO_Pin_3 | IO_Pin_4)
+
+/** @defgroup JOYSTICK Pins definition
+ * @{
+ */
+#define JOY_IO_CENTER IO_Pin_7
+#define JOY_IO_DOWN IO_Pin_6
+#define JOY_IO_LEFT IO_Pin_5
+#define JOY_IO_RIGHT IO_Pin_4
+#define JOY_IO_UP IO_Pin_3
+#define JOY_IO_NONE JOY_IO_PINS
+#define JOY_IO_PINS (uint32_t)(IO_Pin_3 | IO_Pin_4 | IO_Pin_5 | IO_Pin_6 | IO_Pin_7)
+
+/**
+ * @brief IO Pins
+ */
+#define IO_Pin_0 0x01
+#define IO_Pin_1 0x02
+#define IO_Pin_2 0x04
+#define IO_Pin_3 0x08
+#define IO_Pin_4 0x10
+#define IO_Pin_5 0x20
+#define IO_Pin_6 0x40
+#define IO_Pin_7 0x80
+#define IO_Pin_ALL 0xFF
+
+/**
+ * @brief IO Pin directions
+ */
+#define Direction_IN 0x00
+#define Direction_OUT 0x01
+
+/**
+ * @brief Interrupt Line output parameters
+ */
+#define Polarity_Low 0x00
+#define Polarity_High 0x04
+#define Type_Level 0x00
+#define Type_Edge 0x02
+
+/**
+ * @brief IO Interrupts
+ */
+#define IO_IT_0 0x01
+#define IO_IT_1 0x02
+#define IO_IT_2 0x04
+#define IO_IT_3 0x08
+#define IO_IT_4 0x10
+#define IO_IT_5 0x20
+#define IO_IT_6 0x40
+#define IO_IT_7 0x80
+#define ALL_IT 0xFF
+#define IOE_JOY_IT (uint8_t)(IO_IT_3 | IO_IT_4 | IO_IT_5 | IO_IT_6 | IO_IT_7)
+#define IOE_TS_IT (uint8_t)(IO_IT_0 | IO_IT_1 | IO_IT_2)
+#define IOE_INMEMS_IT (uint8_t)(IO_IT_2 | IO_IT_3)
+
+/**
+ * @brief Edge detection value
+ */
+#define EDGE_FALLING 0x01
+#define EDGE_RISING 0x02
+
+/**
+ * @brief Global interrupt Enable bit
+ */
+#define IOE_GIT_EN 0x01
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup EVAL_IOE_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup EVAL_IOE_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief Configuration and initialization functions
+ */
+uint8_t IOE_Config(void);
+uint8_t IOE_ITConfig(uint32_t IOE_ITSRC_Source);
+
+/**
+ * @brief IO pins control functions
+ */
+uint8_t IOE_WriteIOPin(uint8_t IO_Pin, IOE_BitValue_TypeDef BitVal);
+uint8_t IOE_ReadIOPin(uint32_t IO_Pin);
+JOY_State_TypeDef IOE_JoyStickGetState(void);
+
+/**
+ * @brief Touch Screen controller functions
+ */
+TS_STATE* IOE_TS_GetState(void);
+
+/**
+ * @brief Interrupts Mangement functions
+ */
+FlagStatus IOE_GetGITStatus(uint8_t DeviceAddr, uint8_t Global_IT);
+uint8_t IOE_ClearGITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+FlagStatus IOE_GetIOITStatus(uint8_t DeviceAddr, uint8_t IO_IT);
+uint8_t IOE_ClearIOITPending(uint8_t DeviceAddr, uint8_t IO_IT);
+
+/**
+ * @brief Temperature Sensor functions
+ */
+uint32_t IOE_TempSens_GetData(void);
+
+/**
+ * @brief IO-Expander Control functions
+ */
+uint8_t IOE_IsOperational(uint8_t DeviceAddr);
+uint8_t IOE_Reset(uint8_t DeviceAddr);
+uint16_t IOE_ReadID(uint8_t DeviceAddr);
+
+uint8_t IOE_FnctCmd(uint8_t DeviceAddr, uint8_t Fct, FunctionalState NewState);
+uint8_t IOE_IOPinConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Direction);
+uint8_t IOE_GITCmd(uint8_t DeviceAddr, FunctionalState NewState);
+uint8_t IOE_GITConfig(uint8_t DeviceAddr, uint8_t Global_IT, FunctionalState NewState);
+uint8_t IOE_IOITConfig(uint8_t DeviceAddr, uint8_t IO_IT, FunctionalState NewState);
+
+/**
+ * @brief Low Layer functions
+ */
+uint8_t IOE_TS_Config(void);
+uint8_t IOE_TempSens_Config(void);
+uint8_t IOE_IOAFConfig(uint8_t DeviceAddr, uint8_t IO_Pin, FunctionalState NewState);
+uint8_t IOE_IOEdgeConfig(uint8_t DeviceAddr, uint8_t IO_Pin, uint8_t Edge);
+uint8_t IOE_ITOutConfig(uint8_t Polarity, uint8_t Type);
+
+uint8_t I2C_WriteDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t RegisterValue);
+uint8_t I2C_ReadDeviceRegister(uint8_t DeviceAddr, uint8_t RegisterAddr);
+uint32_t I2C_ReadDataBuffer(uint8_t DeviceAddr, uint32_t RegisterAddr);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __IO_EXPANDER_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c
new file mode 100644
index 0000000..9390d41
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.c
@@ -0,0 +1,918 @@
+/**
+ ******************************************************************************
+ * @file stm3210c_eval_lcd.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
+ * Liquid Crystal Display Module of STM3210C-EVAL board.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm3210c_eval_lcd.h"
+#include "fonts.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @defgroup STM3210C_EVAL_LCD
+ * @brief This file includes the LCD driver for AM-240320L8TNQW00H (LCD_ILI9320)
+ * Liquid Crystal Display Module of STM3210C-EVAL board.
+ * @{
+ */
+
+/** @defgroup STM3210C_EVAL_LCD_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup STM3210C_EVAL_LCD_Private_Defines
+ * @{
+ */
+#define START_BYTE 0x70
+#define SET_INDEX 0x00
+#define READ_STATUS 0x01
+#define LCD_WRITE_REG 0x02
+#define LCD_READ_REG 0x03
+/**
+ * @}
+ */
+
+
+/** @defgroup STM3210C_EVAL_LCD_Private_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup STM3210C_EVAL_LCD_Private_Variables
+ * @{
+ */
+ /* Global variables to set the written text color */
+static __IO uint16_t TextColor = 0x0000, BackColor = 0xFFFF;
+/**
+ * @}
+ */
+
+
+/** @defgroup STM3210C_EVAL_LCD_Private_FunctionPrototypes
+ * @{
+ */
+#ifndef USE_Delay
+static void delay(__IO uint32_t nCount);
+#endif /* USE_Delay*/
+/**
+ * @}
+ */
+
+
+/** @defgroup STM3210C_EVAL_LCD_Private_Functions
+ * @{
+ */
+
+
+/**
+ * @brief Setups the LCD.
+ * @param None
+ * @retval None
+ */
+void LCD_Setup(void)
+{
+/* Configure the LCD Control pins --------------------------------------------*/
+ LCD_CtrlLinesConfig();
+
+/* Configure the LCD_SPI interface ----------------------------------------------*/
+ LCD_SPIConfig();
+ _delay_(5); /* Delay 50 ms */
+ /* Start Initial Sequence ------------------------------------------------*/
+ LCD_WriteReg(R229, 0x8000); /* Set the internal vcore voltage */
+ LCD_WriteReg(R0, 0x0001); /* Start internal OSC. */
+ LCD_WriteReg(R1, 0x0100); /* set SS and SM bit */
+ LCD_WriteReg(R2, 0x0700); /* set 1 line inversion */
+ LCD_WriteReg(R3, 0x1030); /* set GRAM write direction and BGR=1. */
+ LCD_WriteReg(R4, 0x0000); /* Resize register */
+ LCD_WriteReg(R8, 0x0202); /* set the back porch and front porch */
+ LCD_WriteReg(R9, 0x0000); /* set non-display area refresh cycle ISC[3:0] */
+ LCD_WriteReg(R10, 0x0000); /* FMARK function */
+ LCD_WriteReg(R12, 0x0000); /* RGB interface setting */
+ LCD_WriteReg(R13, 0x0000); /* Frame marker Position */
+ LCD_WriteReg(R15, 0x0000); /* RGB interface polarity */
+ /* Power On sequence -----------------------------------------------------*/
+ LCD_WriteReg(R16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+ LCD_WriteReg(R17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
+ LCD_WriteReg(R18, 0x0000); /* VREG1OUT voltage */
+ LCD_WriteReg(R19, 0x0000); /* VDV[4:0] for VCOM amplitude */
+ _delay_(20); /* Dis-charge capacitor power voltage (200ms) */
+ LCD_WriteReg(R16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+ LCD_WriteReg(R17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
+ _delay_(5); /* Delay 50 ms */
+ LCD_WriteReg(R18, 0x0139); /* VREG1OUT voltage */
+ _delay_(5); /* Delay 50 ms */
+ LCD_WriteReg(R19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
+ LCD_WriteReg(R41, 0x0013); /* VCM[4:0] for VCOMH */
+ _delay_(5); /* Delay 50 ms */
+ LCD_WriteReg(R32, 0x0000); /* GRAM horizontal Address */
+ LCD_WriteReg(R33, 0x0000); /* GRAM Vertical Address */
+ /* Adjust the Gamma Curve ------------------------------------------------*/
+ LCD_WriteReg(R48, 0x0006);
+ LCD_WriteReg(R49, 0x0101);
+ LCD_WriteReg(R50, 0x0003);
+ LCD_WriteReg(R53, 0x0106);
+ LCD_WriteReg(R54, 0x0b02);
+ LCD_WriteReg(R55, 0x0302);
+ LCD_WriteReg(R56, 0x0707);
+ LCD_WriteReg(R57, 0x0007);
+ LCD_WriteReg(R60, 0x0600);
+ LCD_WriteReg(R61, 0x020b);
+
+ /* Set GRAM area ---------------------------------------------------------*/
+ LCD_WriteReg(R80, 0x0000); /* Horizontal GRAM Start Address */
+ LCD_WriteReg(R81, 0x00EF); /* Horizontal GRAM End Address */
+ LCD_WriteReg(R82, 0x0000); /* Vertical GRAM Start Address */
+ LCD_WriteReg(R83, 0x013F); /* Vertical GRAM End Address */
+ LCD_WriteReg(R96, 0x2700); /* Gate Scan Line */
+ LCD_WriteReg(R97, 0x0001); /* NDL,VLE, REV */
+ LCD_WriteReg(R106, 0x0000); /* set scrolling line */
+ /* Partial Display Control -----------------------------------------------*/
+ LCD_WriteReg(R128, 0x0000);
+ LCD_WriteReg(R129, 0x0000);
+ LCD_WriteReg(R130, 0x0000);
+ LCD_WriteReg(R131, 0x0000);
+ LCD_WriteReg(R132, 0x0000);
+ LCD_WriteReg(R133, 0x0000);
+ /* Panel Control ---------------------------------------------------------*/
+ LCD_WriteReg(R144, 0x0010);
+ LCD_WriteReg(R146, 0x0000);
+ LCD_WriteReg(R147, 0x0003);
+ LCD_WriteReg(R149, 0x0110);
+ LCD_WriteReg(R151, 0x0000);
+ LCD_WriteReg(R152, 0x0000);
+ /* Set GRAM write direction and BGR = 1 */
+ /* I/D=01 (Horizontal : increment, Vertical : decrement) */
+ /* AM=1 (address is updated in vertical writing direction) */
+ LCD_WriteReg(R3, 0x1018);
+ LCD_WriteReg(R7, 0x0173); /* 262K color and display ON */
+}
+
+
+/**
+ * @brief Initializes the LCD.
+ * @param None
+ * @retval None
+ */
+void STM3210C_LCD_Init(void)
+{
+ /* Setups the LCD */
+ LCD_Setup();
+}
+
+
+/**
+ * @brief Sets the Text color.
+ * @param Color: specifies the Text color code RGB(5-6-5).
+ * @retval None
+ */
+void LCD_SetTextColor(__IO uint16_t Color)
+{
+ TextColor = Color;
+}
+
+
+/**
+ * @brief Sets the Background color.
+ * @param Color: specifies the Background color code RGB(5-6-5).
+ * @retval None
+ */
+void LCD_SetBackColor(__IO uint16_t Color)
+{
+ BackColor = Color;
+}
+
+
+/**
+ * @brief Clears the selected line.
+ * @param Line: the Line to be cleared.
+ * This parameter can be one of the following values:
+ * @arg Linex: where x can be 0..9
+ * @retval None
+ */
+void LCD_ClearLine(uint8_t Line)
+{
+ LCD_DisplayStringLine(Line, " ");
+}
+
+
+/**
+ * @brief Clears the hole LCD.
+ * @param Color: the color of the background.
+ * @retval None
+ */
+void LCD_Clear(uint16_t Color)
+{
+ uint32_t index = 0;
+
+ LCD_SetCursor(0x00, 0x013F);
+ LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+ for(index = 0; index < 76800; index++)
+ {
+ LCD_WriteRAM(Color);
+ }
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+
+}
+
+
+/**
+ * @brief Sets the cursor position.
+ * @param Xpos: specifies the X position.
+ * @param Ypos: specifies the Y position.
+ * @retval None
+ */
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos)
+{
+ LCD_WriteReg(R32, Xpos);
+ LCD_WriteReg(R33, Ypos);
+}
+
+
+/**
+ * @brief Draws a character on LCD.
+ * @param Xpos: the Line where to display the character shape.
+ * @param Ypos: start column address.
+ * @param c: pointer to the character data.
+ * @retval None
+ */
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c)
+{
+ uint32_t index = 0, i = 0;
+ uint8_t Xaddress = 0;
+
+ Xaddress = Xpos;
+
+ LCD_SetCursor(Xaddress, Ypos);
+
+ for(index = 0; index < 24; index++)
+ {
+ LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+ for(i = 0; i < 16; i++)
+ {
+ if((c[index] & (1 << i)) == 0x00)
+ {
+ LCD_WriteRAM(BackColor);
+ }
+ else
+ {
+ LCD_WriteRAM(TextColor);
+ }
+ }
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+ Xaddress++;
+ LCD_SetCursor(Xaddress, Ypos);
+ }
+}
+
+
+/**
+ * @brief Displays one character (16dots width, 24dots height).
+ * @param Line: the Line where to display the character shape .
+ * This parameter can be one of the following values:
+ * @arg Linex: where x can be 0..9
+ * @param Column: start column address.
+ * @param Ascii: character ascii code, must be between 0x20 and 0x7E.
+ * @retval None
+ */
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii)
+{
+ Ascii -= 32;
+ LCD_DrawChar(Line, Column, &ASCII_Table[Ascii * 24]);
+}
+
+
+/**
+ * @brief Displays a maximum of 20 char on the LCD.
+ * @param Line: the Line where to display the character shape .
+ * This parameter can be one of the following values:
+ * @arg Linex: where x can be 0..9
+ * @param *ptr: pointer to string to display on LCD.
+ * @retval None
+ */
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr)
+{
+ uint32_t i = 0;
+ uint16_t refcolumn = 319;
+ /* Send the string character by character on lCD */
+ while ((*ptr != 0) & (i < 20))
+ {
+ /* Display one character on LCD */
+ LCD_DisplayChar(Line, refcolumn, *ptr);
+ /* Decrement the column position by 16 */
+ refcolumn -= 16;
+ /* Point on the next character */
+ ptr++;
+ /* Increment the character counter */
+ i++;
+ }
+}
+
+
+/**
+ * @brief Sets a display window
+ * @param Xpos: specifies the X buttom left position.
+ * @param Ypos: specifies the Y buttom left position.
+ * @param Height: display window height.
+ * @param Width: display window width.
+ * @retval None
+ */
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+{
+ /* Horizontal GRAM Start Address */
+ if(Xpos >= Height)
+ {
+ LCD_WriteReg(R80, (Xpos - Height + 1));
+ }
+ else
+ {
+ LCD_WriteReg(R80, 0);
+ }
+ /* Horizontal GRAM End Address */
+ LCD_WriteReg(R81, Xpos);
+ /* Vertical GRAM Start Address */
+ if(Ypos >= Width)
+ {
+ LCD_WriteReg(R82, (Ypos - Width + 1));
+ }
+ else
+ {
+ LCD_WriteReg(R82, 0);
+ }
+ /* Vertical GRAM End Address */
+ LCD_WriteReg(R83, Ypos);
+ LCD_SetCursor(Xpos, Ypos);
+}
+
+
+/**
+ * @brief Disables LCD Window mode.
+ * @param None
+ * @retval None
+ */
+void LCD_WindowModeDisable(void)
+{
+ LCD_SetDisplayWindow(239, 0x13F, 240, 320);
+ LCD_WriteReg(R3, 0x1018);
+}
+
+
+/**
+ * @brief Displays a line.
+ * @param Xpos: specifies the X position.
+ * @param Ypos: specifies the Y position.
+ * @param Length: line length.
+ * @param Direction: line direction.
+ * This parameter can be one of the following values: Vertical or Horizontal.
+ * @retval None
+ */
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction)
+{
+ uint32_t i = 0;
+
+ LCD_SetCursor(Xpos, Ypos);
+ if(Direction == Horizontal)
+ {
+ LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+ for(i = 0; i < Length; i++)
+ {
+ LCD_WriteRAM(TextColor);
+ }
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+ }
+ else
+ {
+ for(i = 0; i < Length; i++)
+ {
+ LCD_WriteRAMWord(TextColor);
+ Xpos++;
+ LCD_SetCursor(Xpos, Ypos);
+ }
+ }
+}
+
+
+/**
+ * @brief Displays a rectangle.
+ * @param Xpos: specifies the X position.
+ * @param Ypos: specifies the Y position.
+ * @param Height: display rectangle height.
+ * @param Width: display rectangle width.
+ * @retval None
+ */
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width)
+{
+ LCD_DrawLine(Xpos, Ypos, Width, Horizontal);
+ LCD_DrawLine((Xpos + Height), Ypos, Width, Horizontal);
+
+ LCD_DrawLine(Xpos, Ypos, Height, Vertical);
+ LCD_DrawLine(Xpos, (Ypos - Width + 1), Height, Vertical);
+}
+
+
+/**
+ * @brief Displays a circle.
+ * @param Xpos: specifies the X position.
+ * @param Ypos: specifies the Y position.
+ * @param Radius
+ * @retval None
+ */
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius)
+{
+ int32_t D;/* Decision Variable */
+ uint32_t CurX;/* Current X Value */
+ uint32_t CurY;/* Current Y Value */
+
+ D = 3 - (Radius << 1);
+ CurX = 0;
+ CurY = Radius;
+
+ while (CurX <= CurY)
+ {
+ LCD_SetCursor(Xpos + CurX, Ypos + CurY);
+ LCD_WriteRAMWord(TextColor);
+ LCD_SetCursor(Xpos + CurX, Ypos - CurY);
+ LCD_WriteRAMWord(TextColor);
+ LCD_SetCursor(Xpos - CurX, Ypos + CurY);
+ LCD_WriteRAMWord(TextColor);
+ LCD_SetCursor(Xpos - CurX, Ypos - CurY);
+ LCD_WriteRAMWord(TextColor);
+ LCD_SetCursor(Xpos + CurY, Ypos + CurX);
+ LCD_WriteRAMWord(TextColor);
+ LCD_SetCursor(Xpos + CurY, Ypos - CurX);
+ LCD_WriteRAMWord(TextColor);
+ LCD_SetCursor(Xpos - CurY, Ypos + CurX);
+ LCD_WriteRAMWord(TextColor);
+ LCD_SetCursor(Xpos - CurY, Ypos - CurX);
+ LCD_WriteRAMWord(TextColor);
+ if (D < 0)
+ {
+ D += (CurX << 2) + 6;
+ }
+ else
+ {
+ D += ((CurX - CurY) << 2) + 10;
+ CurY--;
+ }
+ CurX++;
+ }
+}
+
+/**
+ * @brief Displays a monocolor picture.
+ * @param Pict: pointer to the picture array.
+ * @retval None
+ */
+void LCD_DrawMonoPict(const uint32_t *Pict)
+{
+ uint32_t index = 0, i = 0;
+ LCD_SetCursor(0, 319);
+ LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+ for(index = 0; index < 2400; index++)
+ {
+ for(i = 0; i < 32; i++)
+ {
+ if((Pict[index] & (1 << i)) == 0x00)
+ {
+ LCD_WriteRAM(BackColor);
+ }
+ else
+ {
+ LCD_WriteRAM(TextColor);
+ }
+ }
+ }
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+#ifdef USE_LCD_DrawBMP
+/**
+ * @brief Displays a bitmap picture loaded in the SPI Flash.
+ * @param BmpAddress: Bmp picture address in the SPI Flash.
+ * @retval None
+ */
+//void LCD_DrawBMP(uint32_t BmpAddress)
+//{
+// uint32_t i = 0, size = 0;
+//
+// /* Read bitmap size */
+// SPI_FLASH_BufferRead((uint8_t*)&size, BmpAddress + 2, 4);
+//
+// /* get bitmap data address offset */
+// SPI_FLASH_BufferRead((uint8_t*)&i, BmpAddress + 10, 4);
+//
+// size = (size - i)/2;
+//
+// SPI_FLASH_StartReadSequence(BmpAddress + i);
+//
+// /* Disable SPI1 */
+// SPI_Cmd(SPI1, DISABLE);
+// /* SPI in 16-bit mode */
+// SPI_DataSizeConfig(SPI1, SPI_DataSize_16b);
+//
+// /* Enable SPI1 */
+// SPI_Cmd(SPI1, ENABLE);
+//
+// /* Set GRAM write direction and BGR = 1 */
+// /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
+// /* AM=1 (address is updated in vertical writing direction) */
+// LCD_WriteReg(R3, 0x1008);
+//
+// LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+//
+// /* Read bitmap data from SPI Flash and send them to LCD */
+// for(i = 0; i < size; i++)
+// {
+// LCD_WriteRAM(__REV_HalfWord(SPI_FLASH_SendHalfWord(0xA5A5)));
+// }
+//
+// LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+//
+// /* Deselect the FLASH: Chip Select high */
+// SPI_FLASH_CS_HIGH();
+//
+// /* Disable SPI1 */
+// SPI_Cmd(SPI1, DISABLE);
+// /* SPI in 8-bit mode */
+// SPI_DataSizeConfig(SPI1, SPI_DataSize_8b);
+//
+// /* Enable SPI1 */
+// SPI_Cmd(SPI1, ENABLE);
+//
+// /* Set GRAM write direction and BGR = 1 */
+// /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
+// /* AM = 1 (address is updated in vertical writing direction) */
+// LCD_WriteReg(R3, 0x1018);
+//}
+
+
+/**
+ * @brief Displays a bitmap picture loaded in the SPI Flash.
+ * @param BmpAddress: Bmp picture address in the SPI Flash.
+ * @retval None
+ */
+void LCD_DrawBMP(const uint16_t *BmpAddress)
+{
+ uint32_t i = 0, size = 0;
+ /* Read bitmap size */
+ size = BmpAddress[1] | (BmpAddress[2] << 16);
+ /* get bitmap data address offset */
+ i = BmpAddress[5] | (BmpAddress[6] << 16);
+ size = (size - i)/2;
+ BmpAddress += i/2;
+ /* Set GRAM write direction and BGR = 1 */
+ /* I/D=00 (Horizontal : decrement, Vertical : decrement) */
+ /* AM=1 (address is updated in vertical writing direction) */
+ LCD_WriteReg(R3, 0x1008);
+ LCD_WriteRAM_Prepare(); /* Prepare to write GRAM */
+ /* Read bitmap data from SPI Flash and send them to LCD */
+ for(i = 0; i < size; i++)
+ {
+ LCD_WriteRAM(BmpAddress[i]);
+ }
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+ /* Set GRAM write direction and BGR = 1 */
+ /* I/D = 01 (Horizontal : increment, Vertical : decrement) */
+ /* AM = 1 (address is updated in vertical writing direction) */
+ LCD_WriteReg(R3, 0x1018);
+}
+#endif
+
+/**
+ * @brief Reset LCD control line(/CS) and Send Start-Byte
+ * @param Start_Byte: the Start-Byte to be sent
+ * @retval None
+ */
+void LCD_nCS_StartByte(uint8_t Start_Byte)
+{
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_RESET);
+ SPI_I2S_SendData(LCD_SPI, Start_Byte);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+}
+
+/**
+ * @brief Writes index to select the LCD register.
+ * @param LCD_Reg: address of the selected register.
+ * @retval None
+ */
+void LCD_WriteRegIndex(uint8_t LCD_Reg)
+{
+ /* Reset LCD control line(/CS) and Send Start-Byte */
+ LCD_nCS_StartByte(START_BYTE | SET_INDEX);
+ /* Write 16-bit Reg Index (High Byte is 0) */
+ SPI_I2S_SendData(LCD_SPI, 0x00);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ SPI_I2S_SendData(LCD_SPI, LCD_Reg);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+ * @brief Reads the selected LCD Register.
+ * @param None
+ * @retval LCD Register Value.
+ */
+uint16_t LCD_ReadReg(uint8_t LCD_Reg)
+{
+ uint16_t tmp = 0;
+ uint8_t i = 0;
+
+ /* LCD_SPI prescaler: 4 */
+ LCD_SPI->CR1 &= 0xFFC7;
+ LCD_SPI->CR1 |= 0x0008;
+ /* Write 16-bit Index (then Read Reg) */
+ LCD_WriteRegIndex(LCD_Reg);
+ /* Read 16-bit Reg */
+ /* Reset LCD control line(/CS) and Send Start-Byte */
+ LCD_nCS_StartByte(START_BYTE | LCD_READ_REG);
+
+ for(i = 0; i < 5; i++)
+ {
+ SPI_I2S_SendData(LCD_SPI, 0xFF);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ /* One byte of invalid dummy data read after the start byte */
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+ {
+ }
+ SPI_I2S_ReceiveData(LCD_SPI);
+ }
+ SPI_I2S_SendData(LCD_SPI, 0xFF);
+ /* Read upper byte */
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ /* Read lower byte */
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+ {
+ }
+ tmp = SPI_I2S_ReceiveData(LCD_SPI);
+
+
+ SPI_I2S_SendData(LCD_SPI, 0xFF);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ /* Read lower byte */
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_RXNE) == RESET)
+ {
+ }
+ tmp = ((tmp & 0xFF) << 8) | SPI_I2S_ReceiveData(LCD_SPI);
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+ /* LCD_SPI prescaler: 2 */
+ LCD_SPI->CR1 &= 0xFFC7;
+ return tmp;
+}
+
+
+/**
+ * @brief Prepare to write to the LCD RAM.
+ * @param None
+ * @retval None
+ */
+void LCD_WriteRAM_Prepare(void)
+{
+ LCD_WriteRegIndex(R34); /* Select GRAM Reg */
+ /* Reset LCD control line(/CS) and Send Start-Byte */
+ LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
+}
+
+
+/**
+ * @brief Writes 1 word to the LCD RAM.
+ * @param RGB_Code: the pixel color in RGB mode (5-6-5).
+ * @retval None
+ */
+void LCD_WriteRAMWord(uint16_t RGB_Code)
+{
+ LCD_WriteRAM_Prepare();
+ LCD_WriteRAM(RGB_Code);
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+ * @brief Writes to the selected LCD register.
+ * @param LCD_Reg: address of the selected register.
+ * @param LCD_RegValue: value to write to the selected register.
+ * @retval None
+ */
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue)
+{
+ /* Write 16-bit Index (then Write Reg) */
+ LCD_WriteRegIndex(LCD_Reg);
+ /* Write 16-bit Reg */
+ /* Reset LCD control line(/CS) and Send Start-Byte */
+ LCD_nCS_StartByte(START_BYTE | LCD_WRITE_REG);
+ SPI_I2S_SendData(LCD_SPI, LCD_RegValue>>8);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ SPI_I2S_SendData(LCD_SPI, (LCD_RegValue & 0xFF));
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ LCD_CtrlLinesWrite(LCD_NCS_GPIO_PORT, LCD_NCS_PIN, Bit_SET);
+}
+
+
+/**
+ * @brief Writes to the LCD RAM.
+ * @param RGB_Code: the pixel color in RGB mode (5-6-5).
+ * @retval None
+ */
+void LCD_WriteRAM(uint16_t RGB_Code)
+{
+ SPI_I2S_SendData(LCD_SPI, RGB_Code >> 8);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+ SPI_I2S_SendData(LCD_SPI, RGB_Code & 0xFF);
+ while(SPI_I2S_GetFlagStatus(LCD_SPI, SPI_I2S_FLAG_BSY) != RESET)
+ {
+ }
+}
+
+
+/**
+ * @brief Power on the LCD.
+ * @param None
+ * @retval None
+ */
+void LCD_PowerOn(void)
+{
+ /* Power On sequence ---------------------------------------------------------*/
+ LCD_WriteReg(R16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+ LCD_WriteReg(R17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */
+ LCD_WriteReg(R18, 0x0000); /* VREG1OUT voltage */
+ LCD_WriteReg(R19, 0x0000); /* VDV[4:0] for VCOM amplitude */
+ _delay_(20); /* Dis-charge capacitor power voltage (200ms) */
+ LCD_WriteReg(R16, 0x17B0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */
+ LCD_WriteReg(R17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */
+ _delay_(5); /* Delay 50 ms */
+ LCD_WriteReg(R18, 0x0139); /* VREG1OUT voltage */
+ _delay_(5); /* delay 50 ms */
+ LCD_WriteReg(R19, 0x1d00); /* VDV[4:0] for VCOM amplitude */
+ LCD_WriteReg(R41, 0x0013); /* VCM[4:0] for VCOMH */
+ _delay_(5); /* delay 50 ms */
+ LCD_WriteReg(R7, 0x0173); /* 262K color and display ON */
+}
+
+/**
+ * @brief Enables the Display.
+ * @param None
+ * @retval None
+ */
+void LCD_DisplayOn(void)
+{
+ /* Display On */
+ LCD_WriteReg(R7, 0x0173); /* 262K color and display ON */
+
+}
+
+/**
+ * @brief Disables the Display.
+ * @param None
+ * @retval None
+ */
+void LCD_DisplayOff(void)
+{
+ /* Display Off */
+ LCD_WriteReg(R7, 0x0);
+}
+
+/**
+ * @brief Configures LCD control lines in Output Push-Pull mode.
+ * @param None
+ * @retval None
+ */
+void LCD_CtrlLinesConfig(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Enable GPIO clock */
+ RCC_APB2PeriphClockCmd(LCD_NCS_GPIO_CLK, ENABLE);
+
+ /* Configure NCS in Output Push-Pull mode */
+ GPIO_InitStructure.GPIO_Pin = LCD_NCS_PIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
+}
+
+/**
+ * @brief Sets or reset LCD control lines.
+ * @param GPIOx: where x can be B or D to select the GPIO peripheral.
+ * @param CtrlPins: the Control line. This parameter can be:
+ * @arg LCD_NCS_PIN: Chip Select pin
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal)
+{
+ /* Set or Reset the control line */
+ GPIO_WriteBit(GPIOx, CtrlPins, BitVal);
+}
+
+
+/**
+ * @brief Configures the LCD_SPI interface.
+ * @param None
+ * @retval None
+ */
+void LCD_SPIConfig(void)
+{
+ SPI_InitTypeDef SPI_InitStructure;
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Enable GPIO clock */
+ RCC_APB2PeriphClockCmd(LCD_SPI_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE);
+ GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
+
+ /* Enable SPI clock */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
+
+ /* Configure SPI pins: SCK, MISO and MOSI */
+ GPIO_InitStructure.GPIO_Pin = LCD_SPI_SCK_PIN | LCD_SPI_MISO_PIN | LCD_SPI_MOSI_PIN;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(LCD_SPI_GPIO_PORT, &GPIO_InitStructure);
+
+ SPI_I2S_DeInit(LCD_SPI);
+
+ /* SPI Config */
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_Init(LCD_SPI, &SPI_InitStructure);
+
+ /* SPI enable */
+ SPI_Cmd(LCD_SPI, ENABLE);
+}
+
+#ifndef USE_Delay
+/**
+ * @brief Inserts a delay time.
+ * @param nCount: specifies the delay time length.
+ * @retval None
+ */
+static void delay(__IO uint32_t nCount)
+{
+ __IO uint32_t index = 0;
+ for(index = (100000 * nCount); index != 0; index--)
+ {
+ }
+}
+#endif /* USE_Delay*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h
new file mode 100644
index 0000000..d9f7a12
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/STM3210C_EVAL/stm3210c_eval_lcd.h
@@ -0,0 +1,302 @@
+/**
+ ******************************************************************************
+ * @file stm3210c_eval_lcd.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the functions prototypes for the lcd firmware driver.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM3210C_EVAL_LCD_H
+#define __STM3210C_EVAL_LCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @addtogroup STM3210C_EVAL_LCD
+ * @{
+ */
+
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Types
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Constants
+ * @{
+ */
+
+/**
+ * @brief Uncomment the line below if you want to use LCD_DrawBMP function to
+ * display a bitmap picture on the LCD. This function assumes that the bitmap
+ * file is loaded in the SPI Flash (mounted on STM3210C-EVAL board), however
+ * user can tailor it according to his application hardware requirement.
+ */
+/*#define USE_LCD_DrawBMP*/
+
+/**
+ * @brief Uncomment the line below if you want to use user defined Delay function
+ * (for precise timing), otherwise default _delay_ function defined within
+ * this driver is used (less precise timing).
+ */
+/* #define USE_Delay */
+
+#ifdef USE_Delay
+#include "main.h"
+
+ #define _delay_ Delay /* !< User can provide more timing precise _delay_ function
+ (with 10ms time base), using SysTick for example */
+#else
+ #define _delay_ delay /* !< Default _delay_ function with less precise timing */
+#endif
+
+/**
+ * @brief LCD Control pins
+ */
+#define LCD_NCS_PIN GPIO_Pin_2
+#define LCD_NCS_GPIO_PORT GPIOB
+#define LCD_NCS_GPIO_CLK RCC_APB2Periph_GPIOB
+
+/**
+ * @brief LCD SPI Interface pins
+ */
+#define LCD_SPI_SCK_PIN GPIO_Pin_10
+#define LCD_SPI_MISO_PIN GPIO_Pin_11
+#define LCD_SPI_MOSI_PIN GPIO_Pin_12
+#define LCD_SPI_GPIO_PORT GPIOC
+#define LCD_SPI_GPIO_CLK RCC_APB2Periph_GPIOC
+#define LCD_SPI SPI3
+#define LCD_SPI_CLK RCC_APB1Periph_SPI3
+
+/**
+ * @brief LCD Registers
+ */
+#define R0 0x00
+#define R1 0x01
+#define R2 0x02
+#define R3 0x03
+#define R4 0x04
+#define R5 0x05
+#define R6 0x06
+#define R7 0x07
+#define R8 0x08
+#define R9 0x09
+#define R10 0x0A
+#define R12 0x0C
+#define R13 0x0D
+#define R14 0x0E
+#define R15 0x0F
+#define R16 0x10
+#define R17 0x11
+#define R18 0x12
+#define R19 0x13
+#define R20 0x14
+#define R21 0x15
+#define R22 0x16
+#define R23 0x17
+#define R24 0x18
+#define R25 0x19
+#define R26 0x1A
+#define R27 0x1B
+#define R28 0x1C
+#define R29 0x1D
+#define R30 0x1E
+#define R31 0x1F
+#define R32 0x20
+#define R33 0x21
+#define R34 0x22
+#define R36 0x24
+#define R37 0x25
+#define R40 0x28
+#define R41 0x29
+#define R43 0x2B
+#define R45 0x2D
+#define R48 0x30
+#define R49 0x31
+#define R50 0x32
+#define R51 0x33
+#define R52 0x34
+#define R53 0x35
+#define R54 0x36
+#define R55 0x37
+#define R56 0x38
+#define R57 0x39
+#define R59 0x3B
+#define R60 0x3C
+#define R61 0x3D
+#define R62 0x3E
+#define R63 0x3F
+#define R64 0x40
+#define R65 0x41
+#define R66 0x42
+#define R67 0x43
+#define R68 0x44
+#define R69 0x45
+#define R70 0x46
+#define R71 0x47
+#define R72 0x48
+#define R73 0x49
+#define R74 0x4A
+#define R75 0x4B
+#define R76 0x4C
+#define R77 0x4D
+#define R78 0x4E
+#define R79 0x4F
+#define R80 0x50
+#define R81 0x51
+#define R82 0x52
+#define R83 0x53
+#define R96 0x60
+#define R97 0x61
+#define R106 0x6A
+#define R118 0x76
+#define R128 0x80
+#define R129 0x81
+#define R130 0x82
+#define R131 0x83
+#define R132 0x84
+#define R133 0x85
+#define R134 0x86
+#define R135 0x87
+#define R136 0x88
+#define R137 0x89
+#define R139 0x8B
+#define R140 0x8C
+#define R141 0x8D
+#define R143 0x8F
+#define R144 0x90
+#define R145 0x91
+#define R146 0x92
+#define R147 0x93
+#define R148 0x94
+#define R149 0x95
+#define R150 0x96
+#define R151 0x97
+#define R152 0x98
+#define R153 0x99
+#define R154 0x9A
+#define R157 0x9D
+#define R192 0xC0
+#define R193 0xC1
+#define R229 0xE5
+
+/**
+ * @brief LCD color
+ */
+#define White 0xFFFF
+#define Black 0x0000
+#define Grey 0xF7DE
+#define Blue 0x001F
+#define Blue2 0x051F
+#define Red 0xF800
+#define Magenta 0xF81F
+#define Green 0x07E0
+#define Cyan 0x7FFF
+#define Yellow 0xFFE0
+#define Line0 0
+#define Line1 24
+#define Line2 48
+#define Line3 72
+#define Line4 96
+#define Line5 120
+#define Line6 144
+#define Line7 168
+#define Line8 192
+#define Line9 216
+#define Horizontal 0x00
+#define Vertical 0x01
+/**
+ * @}
+ */
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup STM3210C_EVAL_LCD_Exported_Functions
+ * @{
+ */
+void LCD_Setup(void);
+void STM3210C_LCD_Init(void);
+void LCD_SetTextColor(__IO uint16_t Color);
+void LCD_SetBackColor(__IO uint16_t Color);
+void LCD_ClearLine(uint8_t Line);
+void LCD_Clear(uint16_t Color);
+void LCD_SetCursor(uint8_t Xpos, uint16_t Ypos);
+void LCD_DrawChar(uint8_t Xpos, uint16_t Ypos, const uint16_t *c);
+void LCD_DisplayChar(uint8_t Line, uint16_t Column, uint8_t Ascii);
+void LCD_DisplayStringLine(uint8_t Line, uint8_t *ptr);
+void LCD_SetDisplayWindow(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_WindowModeDisable(void);
+void LCD_DrawLine(uint8_t Xpos, uint16_t Ypos, uint16_t Length, uint8_t Direction);
+void LCD_DrawRect(uint8_t Xpos, uint16_t Ypos, uint8_t Height, uint16_t Width);
+void LCD_DrawCircle(uint8_t Xpos, uint16_t Ypos, uint16_t Radius);
+void LCD_DrawMonoPict(const uint32_t *Pict);
+#ifdef USE_LCD_DrawBMP
+//void LCD_DrawBMP(uint32_t BmpAddress);
+void LCD_DrawBMP(const uint16_t *BmpAddress);
+#endif
+
+void LCD_nCS_StartByte(uint8_t Start_Byte);
+void LCD_WriteRegIndex(uint8_t LCD_Reg);
+void LCD_WriteReg(uint8_t LCD_Reg, uint16_t LCD_RegValue);
+void LCD_WriteRAM_Prepare(void);
+void LCD_WriteRAMWord(uint16_t RGB_Code);
+uint16_t LCD_ReadReg(uint8_t LCD_Reg);
+void LCD_WriteRAM(uint16_t RGB_Code);
+void LCD_PowerOn(void);
+void LCD_DisplayOn(void);
+void LCD_DisplayOff(void);
+
+void LCD_CtrlLinesConfig(void);
+void LCD_CtrlLinesWrite(GPIO_TypeDef* GPIOx, uint16_t CtrlPins, BitAction BitVal);
+void LCD_SPIConfig(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM3210C_EVAL_LCD_H */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/STM32_EVAL/fonts.h b/F107/Utilities/STM32_EVAL/fonts.h
new file mode 100644
index 0000000..e3a6640
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/fonts.h
@@ -0,0 +1,654 @@
+/**
+ ******************************************************************************
+ * @file fonts.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file contains all the LCD fonts size definition.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __FONTS_H
+#define __FONTS_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @addtogroup FONTS
+ * @{
+ */
+
+
+/** @defgroup FONTS_Exported_Types
+ * @{
+ */
+ /* ASCII Table: each character is 16 column (16dots large)
+ and 24 raw (24 dots high) */
+ const uint16_t ASCII_Table[] =
+ {
+/**
+ * @brief Space ' '
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '!'
+ */
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000, 0x0000,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '"'
+ */
+ 0x0000, 0x0000, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC, 0x00CC,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '#'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0C60, 0x0C60,
+ 0x0C60, 0x0630, 0x0630, 0x1FFE, 0x1FFE, 0x0630, 0x0738, 0x0318,
+ 0x1FFE, 0x1FFE, 0x0318, 0x0318, 0x018C, 0x018C, 0x018C, 0x0000,
+/**
+ * @brief '$'
+ */
+ 0x0000, 0x0080, 0x03E0, 0x0FF8, 0x0E9C, 0x1C8C, 0x188C, 0x008C,
+ 0x0098, 0x01F8, 0x07E0, 0x0E80, 0x1C80, 0x188C, 0x188C, 0x189C,
+ 0x0CB8, 0x0FF0, 0x03E0, 0x0080, 0x0080, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '%'
+ */
+ 0x0000, 0x0000, 0x0000, 0x180E, 0x0C1B, 0x0C11, 0x0611, 0x0611,
+ 0x0311, 0x0311, 0x019B, 0x018E, 0x38C0, 0x6CC0, 0x4460, 0x4460,
+ 0x4430, 0x4430, 0x4418, 0x6C18, 0x380C, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '&'
+ */
+ 0x0000, 0x01E0, 0x03F0, 0x0738, 0x0618, 0x0618, 0x0330, 0x01F0,
+ 0x00F0, 0x00F8, 0x319C, 0x330E, 0x1E06, 0x1C06, 0x1C06, 0x3F06,
+ 0x73FC, 0x21F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '''
+ */
+ 0x0000, 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '('
+ */
+ 0x0000, 0x0200, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x0060, 0x0060,
+ 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
+ 0x0060, 0x0060, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0200, 0x0000,
+/**
+ * @brief ')'
+ */
+ 0x0000, 0x0020, 0x0060, 0x00C0, 0x0180, 0x0180, 0x0300, 0x0300,
+ 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
+ 0x0300, 0x0300, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0020, 0x0000,
+/**
+ * @brief '*'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+ 0x06D8, 0x07F8, 0x01E0, 0x0330, 0x0738, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '+'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x3FFC, 0x3FFC, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief ','
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000,
+/**
+ * @brief '-'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x07E0, 0x07E0, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '.'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '/'
+ */
+ 0x0000, 0x0C00, 0x0C00, 0x0600, 0x0600, 0x0600, 0x0300, 0x0300,
+ 0x0300, 0x0380, 0x0180, 0x0180, 0x0180, 0x00C0, 0x00C0, 0x00C0,
+ 0x0060, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '0'
+ */
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x180C, 0x180C, 0x180C,
+ 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C18, 0x0E38,
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '1'
+ */
+ 0x0000, 0x0100, 0x0180, 0x01C0, 0x01F0, 0x0198, 0x0188, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '2'
+ */
+ 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x1800,
+ 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
+ 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '3'
+ */
+ 0x0000, 0x01E0, 0x07F8, 0x0E18, 0x0C0C, 0x0C0C, 0x0C00, 0x0600,
+ 0x03C0, 0x07C0, 0x0C00, 0x1800, 0x1800, 0x180C, 0x180C, 0x0C18,
+ 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '4'
+ */
+ 0x0000, 0x0C00, 0x0E00, 0x0F00, 0x0F00, 0x0D80, 0x0CC0, 0x0C60,
+ 0x0C60, 0x0C30, 0x0C18, 0x0C0C, 0x3FFC, 0x3FFC, 0x0C00, 0x0C00,
+ 0x0C00, 0x0C00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '5'
+ */
+ 0x0000, 0x0FF8, 0x0FF8, 0x0018, 0x0018, 0x000C, 0x03EC, 0x07FC,
+ 0x0E1C, 0x1C00, 0x1800, 0x1800, 0x1800, 0x180C, 0x0C1C, 0x0E18,
+ 0x07F8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '6'
+ */
+ 0x0000, 0x07C0, 0x0FF0, 0x1C38, 0x1818, 0x0018, 0x000C, 0x03CC,
+ 0x0FEC, 0x0E3C, 0x1C1C, 0x180C, 0x180C, 0x180C, 0x1C18, 0x0E38,
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '7'
+ */
+ 0x0000, 0x1FFC, 0x1FFC, 0x0C00, 0x0600, 0x0600, 0x0300, 0x0380,
+ 0x0180, 0x01C0, 0x00C0, 0x00E0, 0x0060, 0x0060, 0x0070, 0x0030,
+ 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '8'
+ */
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C18, 0x0C18, 0x0C18, 0x0638,
+ 0x07F0, 0x07F0, 0x0C18, 0x180C, 0x180C, 0x180C, 0x180C, 0x0C38,
+ 0x0FF8, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '9'
+ */
+ 0x0000, 0x03E0, 0x07F0, 0x0E38, 0x0C1C, 0x180C, 0x180C, 0x180C,
+ 0x1C1C, 0x1E38, 0x1BF8, 0x19E0, 0x1800, 0x0C00, 0x0C00, 0x0E1C,
+ 0x07F8, 0x01F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief ':'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief ';'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0180, 0x0180,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0180, 0x0180, 0x0100, 0x0100, 0x0080, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '<'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x1000, 0x1C00, 0x0F80, 0x03E0, 0x00F8, 0x0018, 0x00F8, 0x03E0,
+ 0x0F80, 0x1C00, 0x1000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '='
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x1FF8, 0x0000, 0x0000, 0x0000, 0x1FF8, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '>'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0008, 0x0038, 0x01F0, 0x07C0, 0x1F00, 0x1800, 0x1F00, 0x07C0,
+ 0x01F0, 0x0038, 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '?'
+ */
+ 0x0000, 0x03E0, 0x0FF8, 0x0C18, 0x180C, 0x180C, 0x1800, 0x0C00,
+ 0x0600, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x0000, 0x0000,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '@'
+ */
+ 0x0000, 0x0000, 0x07E0, 0x1818, 0x2004, 0x29C2, 0x4A22, 0x4411,
+ 0x4409, 0x4409, 0x4409, 0x2209, 0x1311, 0x0CE2, 0x4002, 0x2004,
+ 0x1818, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'A'
+ */
+ 0x0000, 0x0380, 0x0380, 0x06C0, 0x06C0, 0x06C0, 0x0C60, 0x0C60,
+ 0x1830, 0x1830, 0x1830, 0x3FF8, 0x3FF8, 0x701C, 0x600C, 0x600C,
+ 0xC006, 0xC006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'B'
+ */
+ 0x0000, 0x03FC, 0x0FFC, 0x0C0C, 0x180C, 0x180C, 0x180C, 0x0C0C,
+ 0x07FC, 0x0FFC, 0x180C, 0x300C, 0x300C, 0x300C, 0x300C, 0x180C,
+ 0x1FFC, 0x07FC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'C'
+ */
+ 0x0000, 0x07C0, 0x1FF0, 0x3838, 0x301C, 0x700C, 0x6006, 0x0006,
+ 0x0006, 0x0006, 0x0006, 0x0006, 0x0006, 0x6006, 0x700C, 0x301C,
+ 0x1FF0, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'D'
+ */
+ 0x0000, 0x03FE, 0x0FFE, 0x0E06, 0x1806, 0x1806, 0x3006, 0x3006,
+ 0x3006, 0x3006, 0x3006, 0x3006, 0x3006, 0x1806, 0x1806, 0x0E06,
+ 0x0FFE, 0x03FE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'E'
+ */
+ 0x0000, 0x3FFC, 0x3FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x1FFC, 0x1FFC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x3FFC, 0x3FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'F'
+ */
+ 0x0000, 0x3FF8, 0x3FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x0018, 0x0018, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'G'
+ */
+ 0x0000, 0x0FE0, 0x3FF8, 0x783C, 0x600E, 0xE006, 0xC007, 0x0003,
+ 0x0003, 0xFE03, 0xFE03, 0xC003, 0xC007, 0xC006, 0xC00E, 0xF03C,
+ 0x3FF8, 0x0FE0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'H'
+ */
+ 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x3FFC, 0x3FFC, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x300C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'I'
+ */
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'J'
+ */
+ 0x0000, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0600,
+ 0x0600, 0x0600, 0x0600, 0x0600, 0x0600, 0x0618, 0x0618, 0x0738,
+ 0x03F0, 0x01E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'K'
+ */
+ 0x0000, 0x3006, 0x1806, 0x0C06, 0x0606, 0x0306, 0x0186, 0x00C6,
+ 0x0066, 0x0076, 0x00DE, 0x018E, 0x0306, 0x0606, 0x0C06, 0x1806,
+ 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'L'
+ */
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018,
+ 0x1FF8, 0x1FF8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'M'
+ */
+ 0x0000, 0xE00E, 0xF01E, 0xF01E, 0xF01E, 0xD836, 0xD836, 0xD836,
+ 0xD836, 0xCC66, 0xCC66, 0xCC66, 0xC6C6, 0xC6C6, 0xC6C6, 0xC6C6,
+ 0xC386, 0xC386, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'N'
+ */
+ 0x0000, 0x300C, 0x301C, 0x303C, 0x303C, 0x306C, 0x306C, 0x30CC,
+ 0x30CC, 0x318C, 0x330C, 0x330C, 0x360C, 0x360C, 0x3C0C, 0x3C0C,
+ 0x380C, 0x300C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'O'
+ */
+ 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xC003, 0xC003,
+ 0xC003, 0xC003, 0xC003, 0xC003, 0xC003, 0x6006, 0x700E, 0x381C,
+ 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'P'
+ */
+ 0x0000, 0x0FFC, 0x1FFC, 0x380C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x180C, 0x1FFC, 0x07FC, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C,
+ 0x000C, 0x000C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'Q'
+ */
+ 0x0000, 0x07E0, 0x1FF8, 0x381C, 0x700E, 0x6006, 0xE003, 0xC003,
+ 0xC003, 0xC003, 0xC003, 0xC003, 0xE007, 0x6306, 0x3F0E, 0x3C1C,
+ 0x3FF8, 0xF7E0, 0xC000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'R'
+ */
+ 0x0000, 0x0FFE, 0x1FFE, 0x3806, 0x3006, 0x3006, 0x3006, 0x3806,
+ 0x1FFE, 0x07FE, 0x0306, 0x0606, 0x0C06, 0x1806, 0x1806, 0x3006,
+ 0x3006, 0x6006, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'S'
+ */
+ 0x0000, 0x03E0, 0x0FF8, 0x0C1C, 0x180C, 0x180C, 0x000C, 0x001C,
+ 0x03F8, 0x0FE0, 0x1E00, 0x3800, 0x3006, 0x3006, 0x300E, 0x1C1C,
+ 0x0FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'T'
+ */
+ 0x0000, 0x7FFE, 0x7FFE, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'U'
+ */
+ 0x0000, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C,
+ 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x300C, 0x1818,
+ 0x1FF8, 0x07E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'V'
+ */
+ 0x0000, 0x6003, 0x3006, 0x3006, 0x3006, 0x180C, 0x180C, 0x180C,
+ 0x0C18, 0x0C18, 0x0E38, 0x0630, 0x0630, 0x0770, 0x0360, 0x0360,
+ 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'W'
+ */
+ 0x0000, 0x6003, 0x61C3, 0x61C3, 0x61C3, 0x3366, 0x3366, 0x3366,
+ 0x3366, 0x3366, 0x3366, 0x1B6C, 0x1B6C, 0x1B6C, 0x1A2C, 0x1E3C,
+ 0x0E38, 0x0E38, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'X'
+ */
+ 0x0000, 0xE00F, 0x700C, 0x3018, 0x1830, 0x0C70, 0x0E60, 0x07C0,
+ 0x0380, 0x0380, 0x03C0, 0x06E0, 0x0C70, 0x1C30, 0x1818, 0x300C,
+ 0x600E, 0xE007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'Y'
+ */
+ 0x0000, 0xC003, 0x6006, 0x300C, 0x381C, 0x1838, 0x0C30, 0x0660,
+ 0x07E0, 0x03C0, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'Z'
+ */
+ 0x0000, 0x7FFC, 0x7FFC, 0x6000, 0x3000, 0x1800, 0x0C00, 0x0600,
+ 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018, 0x000C, 0x0006,
+ 0x7FFE, 0x7FFE, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '['
+ */
+ 0x0000, 0x03E0, 0x03E0, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
+ 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x0060,
+ 0x0060, 0x0060, 0x0060, 0x0060, 0x0060, 0x03E0, 0x03E0, 0x0000,
+/**
+ * @brief '\'
+ */
+ 0x0000, 0x0030, 0x0030, 0x0060, 0x0060, 0x0060, 0x00C0, 0x00C0,
+ 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0300, 0x0300, 0x0300,
+ 0x0600, 0x0600, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief ']'
+ */
+ 0x0000, 0x03E0, 0x03E0, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
+ 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x0300,
+ 0x0300, 0x0300, 0x0300, 0x0300, 0x0300, 0x03E0, 0x03E0, 0x0000,
+/**
+ * @brief '^'
+ */
+ 0x0000, 0x0000, 0x01C0, 0x01C0, 0x0360, 0x0360, 0x0360, 0x0630,
+ 0x0630, 0x0C18, 0x0C18, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '_'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '''
+ */
+ 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'a'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03F0, 0x07F8,
+ 0x0C1C, 0x0C0C, 0x0F00, 0x0FF0, 0x0CF8, 0x0C0C, 0x0C0C, 0x0F1C,
+ 0x0FF8, 0x18F0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'b'
+ */
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x03D8, 0x0FF8,
+ 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
+ 0x0FF8, 0x03D8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'c'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x07F0,
+ 0x0E30, 0x0C18, 0x0018, 0x0018, 0x0018, 0x0018, 0x0C18, 0x0E30,
+ 0x07F0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'd'
+ */
+ 0x0000, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x1BC0, 0x1FF0,
+ 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
+ 0x1FF0, 0x1BC0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'e'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
+ 0x0C30, 0x1818, 0x1FF8, 0x1FF8, 0x0018, 0x0018, 0x1838, 0x1C30,
+ 0x0FF0, 0x07C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'f'
+ */
+ 0x0000, 0x0F80, 0x0FC0, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'g'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0DE0, 0x0FF8,
+ 0x0E18, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0C0C, 0x0E18,
+ 0x0FF8, 0x0DE0, 0x0C00, 0x0C0C, 0x061C, 0x07F8, 0x01F0, 0x0000,
+/**
+ * @brief 'h'
+ */
+ 0x0000, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x07D8, 0x0FF8,
+ 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
+ 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'i'
+ */
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'j'
+ */
+ 0x0000, 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00F8, 0x0078, 0x0000,
+/**
+ * @brief 'k'
+ */
+ 0x0000, 0x000C, 0x000C, 0x000C, 0x000C, 0x000C, 0x0C0C, 0x060C,
+ 0x030C, 0x018C, 0x00CC, 0x006C, 0x00FC, 0x019C, 0x038C, 0x030C,
+ 0x060C, 0x0C0C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'l'
+ */
+ 0x0000, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'm'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3C7C, 0x7EFF,
+ 0xE3C7, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183, 0xC183,
+ 0xC183, 0xC183, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'n'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0798, 0x0FF8,
+ 0x1C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818,
+ 0x1818, 0x1818, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'o'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03C0, 0x0FF0,
+ 0x0C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C30,
+ 0x0FF0, 0x03C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'p'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03D8, 0x0FF8,
+ 0x0C38, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x0C38,
+ 0x0FF8, 0x03D8, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0000,
+/**
+ * @brief 'q'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1BC0, 0x1FF0,
+ 0x1C30, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C30,
+ 0x1FF0, 0x1BC0, 0x1800, 0x1800, 0x1800, 0x1800, 0x1800, 0x0000,
+/**
+ * @brief 'r'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x07B0, 0x03F0,
+ 0x0070, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030, 0x0030,
+ 0x0030, 0x0030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 's'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03E0, 0x03F0,
+ 0x0E38, 0x0C18, 0x0038, 0x03F0, 0x07C0, 0x0C00, 0x0C18, 0x0E38,
+ 0x07F0, 0x03E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 't'
+ */
+ 0x0000, 0x0000, 0x0080, 0x00C0, 0x00C0, 0x00C0, 0x07F0, 0x07F0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x07C0, 0x0780, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'u'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1818, 0x1818,
+ 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1818, 0x1C38,
+ 0x1FF0, 0x19E0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'v'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x180C, 0x0C18,
+ 0x0C18, 0x0C18, 0x0630, 0x0630, 0x0630, 0x0360, 0x0360, 0x0360,
+ 0x01C0, 0x01C0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'w'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x41C1, 0x41C1,
+ 0x61C3, 0x6363, 0x6363, 0x6363, 0x3636, 0x3636, 0x3636, 0x1C1C,
+ 0x1C1C, 0x1C1C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'x'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x381C, 0x1C38,
+ 0x0C30, 0x0660, 0x0360, 0x0360, 0x0360, 0x0360, 0x0660, 0x0C30,
+ 0x1C38, 0x381C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief 'y'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x3018, 0x1830,
+ 0x1830, 0x1870, 0x0C60, 0x0C60, 0x0CE0, 0x06C0, 0x06C0, 0x0380,
+ 0x0380, 0x0380, 0x0180, 0x0180, 0x01C0, 0x00F0, 0x0070, 0x0000,
+/**
+ * @brief 'z'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1FFC, 0x1FFC,
+ 0x0C00, 0x0600, 0x0300, 0x0180, 0x00C0, 0x0060, 0x0030, 0x0018,
+ 0x1FFC, 0x1FFC, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+/**
+ * @brief '{'
+ */
+ 0x0000, 0x0300, 0x0180, 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x00C0,
+ 0x00C0, 0x0060, 0x0060, 0x0030, 0x0060, 0x0040, 0x00C0, 0x00C0,
+ 0x00C0, 0x00C0, 0x00C0, 0x00C0, 0x0180, 0x0300, 0x0000, 0x0000,
+/**
+ * @brief '|'
+ */
+ 0x0000, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0180, 0x0000,
+/**
+ * @brief '}'
+ */
+ 0x0000, 0x0060, 0x00C0, 0x01C0, 0x0180, 0x0180, 0x0180, 0x0180,
+ 0x0180, 0x0300, 0x0300, 0x0600, 0x0300, 0x0100, 0x0180, 0x0180,
+ 0x0180, 0x0180, 0x0180, 0x0180, 0x00C0, 0x0060, 0x0000, 0x0000,
+/**
+ * @brief '~'
+ */
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x10F0, 0x1FF8, 0x0F08, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ };
+/**
+ * @}
+ */
+
+
+
+/** @defgroup FONTS_Exported_Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup FONTS_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+
+/** @defgroup FONTS_Exported_Functions
+ * @{
+ */
+/**
+ * @}
+ */
+
+#endif /* __FONTS_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/STM32_EVAL/stm32_eval.c b/F107/Utilities/STM32_EVAL/stm32_eval.c
new file mode 100644
index 0000000..db1ba49
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/stm32_eval.c
@@ -0,0 +1,414 @@
+/**
+ ******************************************************************************
+ * @file stm32_eval.c
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief This file provides firmware functions to manage Leds, push-buttons
+ * and COM ports available on STM32 Evaluation Boards from STMicroelectronics.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32_eval.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @defgroup STM32_EVAL
+ * @brief This file provides firmware functions to manage Leds, push-buttons
+ * and COM ports available on STM32 Evaluation Boards from STMicroelectronics.
+ * @{
+ */
+
+/** @defgroup STM32_EVAL_Private_TypesDefinitions
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup STM32_EVAL_Private_Defines
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup STM32_EVAL_Private_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/** @defgroup STM32_EVAL_Private_Variables
+ * @{
+ */
+GPIO_TypeDef* GPIO_PORT[LEDn] = {LED1_GPIO_PORT, LED2_GPIO_PORT, LED3_GPIO_PORT,
+ LED4_GPIO_PORT};
+const uint16_t GPIO_PIN[LEDn] = {LED1_GPIO_PIN, LED2_GPIO_PIN, LED3_GPIO_PIN,
+ LED4_GPIO_PIN};
+const uint32_t GPIO_CLK[LEDn] = {LED1_GPIO_CLK, LED2_GPIO_CLK, LED3_GPIO_CLK,
+ LED4_GPIO_CLK};
+
+#ifdef USE_STM3210C_EVAL
+ GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_PORT, TAMPER_BUTTON_PORT,
+ KEY_BUTTON_PORT};
+
+ const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
+ KEY_BUTTON_PIN};
+
+ const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_CLK, TAMPER_BUTTON_CLK,
+ KEY_BUTTON_CLK};
+
+ const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
+ TAMPER_BUTTON_EXTI_LINE,
+ KEY_BUTTON_EXTI_LINE};
+
+ const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_PORT_SOURCE,
+ TAMPER_BUTTON_PORT_SOURCE,
+ KEY_BUTTON_PORT_SOURCE};
+
+ const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_PIN_SOURCE,
+ TAMPER_BUTTON_PIN_SOURCE,
+ KEY_BUTTON_PIN_SOURCE};
+ const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_IRQn, TAMPER_BUTTON_IRQn,
+ KEY_BUTTON_IRQn};
+
+ USART_TypeDef* COM_USART[COMn] = {EVAL_COM1};
+
+ GPIO_TypeDef* COM_PORT[COMn] = {EVAL_COM1_GPIO};
+
+ const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK};
+
+ const uint32_t COM_POR_CLK[COMn] = {EVAL_COM1_GPIO_CLK};
+
+ const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TxPin};
+
+ const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RxPin};
+
+#else
+ GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {WAKEUP_BUTTON_PORT, TAMPER_BUTTON_PORT,
+ KEY_BUTTON_PORT, RIGHT_BUTTON_PORT,
+ LEFT_BUTTON_PORT, UP_BUTTON_PORT,
+ DOWN_BUTTON_PORT, SEL_BUTTON_PORT};
+
+ const uint16_t BUTTON_PIN[BUTTONn] = {WAKEUP_BUTTON_PIN, TAMPER_BUTTON_PIN,
+ KEY_BUTTON_PIN, RIGHT_BUTTON_PIN,
+ LEFT_BUTTON_PIN, UP_BUTTON_PIN,
+ DOWN_BUTTON_PIN, SEL_BUTTON_PIN};
+
+ const uint32_t BUTTON_CLK[BUTTONn] = {WAKEUP_BUTTON_CLK, TAMPER_BUTTON_CLK,
+ KEY_BUTTON_CLK, RIGHT_BUTTON_CLK,
+ LEFT_BUTTON_CLK, UP_BUTTON_CLK,
+ DOWN_BUTTON_CLK, SEL_BUTTON_CLK};
+
+ const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {WAKEUP_BUTTON_EXTI_LINE,
+ TAMPER_BUTTON_EXTI_LINE,
+ KEY_BUTTON_EXTI_LINE,
+ RIGHT_BUTTON_EXTI_LINE,
+ LEFT_BUTTON_EXTI_LINE,
+ UP_BUTTON_EXTI_LINE,
+ DOWN_BUTTON_EXTI_LINE,
+ SEL_BUTTON_EXTI_LINE};
+
+ const uint16_t BUTTON_PORT_SOURCE[BUTTONn] = {WAKEUP_BUTTON_PORT_SOURCE,
+ TAMPER_BUTTON_PORT_SOURCE,
+ KEY_BUTTON_PORT_SOURCE,
+ RIGHT_BUTTON_PORT_SOURCE,
+ LEFT_BUTTON_PORT_SOURCE,
+ UP_BUTTON_PORT_SOURCE,
+ DOWN_BUTTON_PORT_SOURCE,
+ SEL_BUTTON_PORT_SOURCE};
+
+ const uint16_t BUTTON_PIN_SOURCE[BUTTONn] = {WAKEUP_BUTTON_PIN_SOURCE,
+ TAMPER_BUTTON_PIN_SOURCE,
+ KEY_BUTTON_PIN_SOURCE,
+ RIGHT_BUTTON_PIN_SOURCE,
+ LEFT_BUTTON_PIN_SOURCE,
+ UP_BUTTON_PIN_SOURCE,
+ DOWN_BUTTON_PIN_SOURCE,
+ SEL_BUTTON_PIN_SOURCE};
+
+ const uint16_t BUTTON_IRQn[BUTTONn] = {WAKEUP_BUTTON_IRQn, TAMPER_BUTTON_IRQn,
+ KEY_BUTTON_IRQn, RIGHT_BUTTON_IRQn,
+ LEFT_BUTTON_IRQn, UP_BUTTON_IRQn,
+ DOWN_BUTTON_IRQn, SEL_BUTTON_IRQn};
+
+ USART_TypeDef* COM_USART[COMn] = {EVAL_COM1, EVAL_COM2};
+
+ GPIO_TypeDef* COM_PORT[COMn] = {EVAL_COM1_GPIO, EVAL_COM2_GPIO};
+
+ const uint32_t COM_USART_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK};
+
+ const uint32_t COM_POR_CLK[COMn] = {EVAL_COM1_GPIO_CLK, EVAL_COM2_GPIO_CLK};
+
+ const uint16_t COM_TX_PIN[COMn] = {EVAL_COM1_TxPin, EVAL_COM2_TxPin};
+
+ const uint16_t COM_RX_PIN[COMn] = {EVAL_COM1_RxPin, EVAL_COM2_RxPin};
+
+#endif
+/**
+ * @}
+ */
+
+
+/** @defgroup STM32_EVAL_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup STM32_EVAL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures LED GPIO.
+ * @param Led: Specifies the Led to be configured.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @arg LED4
+ * @retval None
+ */
+void STM_EVAL_LEDInit(Led_TypeDef Led)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Enable the GPIO_LED Clock */
+ RCC_APB2PeriphClockCmd(GPIO_CLK[Led], ENABLE);
+
+ /* Configure the GPIO_LED pin */
+ GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led];
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+
+ GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure);
+}
+
+/**
+ * @brief Turns selected LED On.
+ * @param Led: Specifies the Led to be set on.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @arg LED4
+ * @retval None
+ */
+void STM_EVAL_LEDOn(Led_TypeDef Led)
+{
+ GPIO_PORT[Led]->BSRR = GPIO_PIN[Led];
+}
+
+/**
+ * @brief Turns selected LED Off.
+ * @param Led: Specifies the Led to be set off.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @arg LED4
+ * @retval None
+ */
+void STM_EVAL_LEDOff(Led_TypeDef Led)
+{
+ GPIO_PORT[Led]->BRR = GPIO_PIN[Led];
+}
+
+/**
+ * @brief Toggles the selected LED.
+ * @param Led: Specifies the Led to be toggled.
+ * This parameter can be one of following parameters:
+ * @arg LED1
+ * @arg LED2
+ * @arg LED3
+ * @arg LED4
+ * @retval None
+ */
+void STM_EVAL_LEDToggle(Led_TypeDef Led)
+{
+ GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led];
+}
+
+/**
+ * @brief Configures Button GPIO and EXTI Line.
+ * @param Button: Specifies the Button to be configured.
+ * This parameter can be one of following parameters:
+ * @arg Button_WAKEUP: Wakeup Push Button
+ * @arg Button_TAMPER: Tamper Push Button
+ * @arg Button_KEY: Key Push Button
+ * @arg Button_RIGHT: Joystick Right Push Button
+ * @arg Button_LEFT: Joystick Left Push Button
+ * @arg Button_UP: Joystick Up Push Button
+ * @arg Button_DOWN: Joystick Down Push Button
+ * @arg Button_SEL: Joystick Sel Push Button
+ * @param Button_Mode: Specifies Button mode.
+ * This parameter can be one of following parameters:
+ * @arg Mode_GPIO: Button will be used as simple IO
+ * @arg Mode_EXTI: Button will be connected to EXTI line with interrupt
+ * generation capability
+ * @retval None
+ */
+void STM_EVAL_PBInit(Button_TypeDef Button, Button_Mode_TypeDef Button_Mode)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+ EXTI_InitTypeDef EXTI_InitStructure;
+ NVIC_InitTypeDef NVIC_InitStructure;
+
+ /* Enable Button GPIO clock */
+ RCC_APB2PeriphClockCmd(BUTTON_CLK[Button] | RCC_APB2Periph_AFIO, ENABLE);
+
+ /* Configure Button pin as input floating */
+ GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button];
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure);
+
+ if (Button_Mode == Mode_EXTI)
+ {
+ /* Connect Button EXTI Line to Button GPIO Pin */
+ GPIO_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]);
+
+ /* Configure Button EXTI line */
+ EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button];
+ EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+
+ if(Button != Button_WAKEUP)
+ {
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+ }
+ else
+ {
+ EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+ }
+ EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+ EXTI_Init(&EXTI_InitStructure);
+
+ /* Enable and set Button EXTI Interrupt to the lowest priority */
+ NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button];
+ NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
+ NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+
+ NVIC_Init(&NVIC_InitStructure);
+ }
+}
+
+/**
+ * @brief Returns the selected Button state.
+ * @param Button: Specifies the Button to be checked.
+ * This parameter can be one of following parameters:
+ * @arg Button_WAKEUP: Wakeup Push Button
+ * @arg Button_TAMPER: Tamper Push Button
+ * @arg Button_KEY: Key Push Button
+ * @arg Button_RIGHT: Joystick Right Push Button
+ * @arg Button_LEFT: Joystick Left Push Button
+ * @arg Button_UP: Joystick Up Push Button
+ * @arg Button_DOWN: Joystick Down Push Button
+ * @arg Button_SEL: Joystick Sel Push Button
+ * @retval The Button GPIO pin value.
+ */
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button)
+{
+ return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]);
+}
+
+
+/**
+ * @brief Configures COM port.
+ * @param COM: Specifies the COM port to be configured.
+ * This parameter can be one of following parameters:
+ * @arg COM1
+ * @arg COM2
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that
+ * contains the configuration information for the specified USART peripheral.
+ * @retval None
+ */
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+
+ /* Enable GPIO clock */
+ RCC_APB2PeriphClockCmd(COM_POR_CLK[COM] | RCC_APB2Periph_AFIO, ENABLE);
+
+ /* Enable UART clock */
+#if defined (USE_STM3210E_EVAL)
+ if (COM == COM1)
+ {
+ RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+ }
+ else
+ {
+ RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+ }
+#elif defined (USE_STM3210B_EVAL)
+ if (COM == COM1)
+ {
+ RCC_APB2PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+ }
+ else
+ {
+ /* Enable the USART2 Pins Software Remapping */
+ GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
+ RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+ }
+#elif defined (USE_STM3210C_EVAL)
+ if (COM == COM1)
+ {
+ /* Enable the USART2 Pins Software Remapping */
+ GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
+ RCC_APB1PeriphClockCmd(COM_USART_CLK[COM], ENABLE);
+ }
+#endif
+
+ /* Configure USART Tx as alternate function push-pull */
+ GPIO_InitStructure.GPIO_Pin = COM_TX_PIN[COM];
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_Init(COM_PORT[COM], &GPIO_InitStructure);
+
+ /* Configure USART Rx as input floating */
+ GPIO_InitStructure.GPIO_Pin = COM_RX_PIN[COM];
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+ GPIO_Init(COM_PORT[COM], &GPIO_InitStructure);
+
+ /* USART configuration */
+ USART_Init(COM_USART[COM], USART_InitStruct);
+
+ /* Enable USART */
+ USART_Cmd(COM_USART[COM], ENABLE);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/STM32_EVAL/stm32_eval.h b/F107/Utilities/STM32_EVAL/stm32_eval.h
new file mode 100644
index 0000000..0589e52
--- /dev/null
+++ b/F107/Utilities/STM32_EVAL/stm32_eval.h
@@ -0,0 +1,163 @@
+/**
+ ******************************************************************************
+ * @file stm32_eval.h
+ * @author MCD Application Team
+ * @version V3.1.2
+ * @date 09/28/2009
+ * @brief Header file for stm32_eval.c module.
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_EVAL_H
+#define __STM32_EVAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f10x.h"
+
+/** @addtogroup Utilities
+ * @{
+ */
+
+/** @addtogroup STM32_EVAL
+ * @{
+ */
+
+
+/** @defgroup STM32_EVAL_Exported_Types
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup STM32_EVAL_Exported_Constants
+ * @{
+ */
+
+/**
+ * @brief Uncomment the line corresponding to the STMicroelectronics evaluation
+ * board used in your application.
+ *
+ * Tip: To avoid modifying this file each time you need to switch between these
+ * boards, you can define the board in your toolchain compiler preprocessor.
+ */
+#if !defined (USE_STM3210B_EVAL) && !defined (USE_STM3210E_EVAL) && !defined (USE_STM3210C_EVAL)
+ //#define USE_STM3210B_EVAL
+ //#define USE_STM3210E_EVAL
+ #define USE_STM3210C_EVAL
+#endif
+
+#ifdef USE_STM3210B_EVAL
+ #include "stm3210b_eval.h"
+#elif defined USE_STM3210E_EVAL
+ #include "stm3210e_eval.h"
+#elif defined USE_STM3210C_EVAL
+ #include "stm3210c_eval.h"
+#else
+ #error "Please select first the STM3210X_EVAL board to be used (in stm32_eval.h)"
+#endif
+
+
+typedef enum
+{
+ LED1 = 0,
+ LED2 = 1,
+ LED3 = 2,
+ LED4 = 3
+} Led_TypeDef;
+
+typedef enum
+{
+ Button_WAKEUP = 0,
+ Button_TAMPER = 1,
+ Button_KEY = 2,
+ Button_RIGHT = 3,
+ Button_LEFT = 4,
+ Button_UP = 5,
+ Button_DOWN = 6,
+ Button_SEL = 7
+} Button_TypeDef;
+
+typedef enum
+{
+ Mode_GPIO = 0,
+ Mode_EXTI = 1
+} Button_Mode_TypeDef;
+
+typedef enum
+{
+ JOY_NONE = 0,
+ JOY_CENTER = 1,
+ JOY_DOWN = 2,
+ JOY_LEFT = 3,
+ JOY_RIGHT = 4,
+ JOY_UP = 5
+} JOY_State_TypeDef;
+
+typedef enum
+{
+ COM1 = 0,
+ COM2 = 1
+} COM_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32_EVAL_Exported_Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup STM32_EVAL_Exported_Functions
+ * @{
+ */
+void STM_EVAL_LEDInit(Led_TypeDef Led);
+void STM_EVAL_LEDOn(Led_TypeDef Led);
+void STM_EVAL_LEDOff(Led_TypeDef Led);
+void STM_EVAL_LEDToggle(Led_TypeDef Led);
+void STM_EVAL_PBInit(Button_TypeDef Button, Button_Mode_TypeDef Button_Mode);
+uint32_t STM_EVAL_PBGetState(Button_TypeDef Button);
+void STM_EVAL_COMInit(COM_TypeDef COM, USART_InitTypeDef* USART_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32_EVAL_H */
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/efsl/include/config.h b/F107/Utilities/efsl/include/config.h
new file mode 100644
index 0000000..03a3a22
--- /dev/null
+++ b/F107/Utilities/efsl/include/config.h
@@ -0,0 +1,135 @@
+#ifndef __EFSL_CONFIG_H_
+#define __EFSL_CONFIG_H__
+
+/* Hardware target
+ ---------------
+
+ * Here you will define for what hardware-endpoint EFSL should be compiled.
+ * Look in interfaces.h to see what systems are supported, and add your own
+ * there if you need to write your own driver. Then, define the name you
+ * selected for your hardware there here. Make sure that you only select one
+ * device!
+*/
+
+ #define HW_ENDPOINT_STM32F10X_SD
+
+
+/* Memory configuration
+ --------------------
+
+ * Here you must configure wheter your processor can access memory byte
+ * oriented. All x86 processors can do it, AVR's can do it to. Some DSP
+ * or other microcontrollers can't. If you have an 8 bit system you're safe.
+ * If you are really unsure, leave the setting commented out, it will be slower
+ * but it will work for sure.
+*/
+
+ /* disabled for ARM (mt): */
+ /*#define BYTE_ALIGNMENT */
+
+/* Cache configuration
+ -------------------
+
+ * Here you must configure how much memory of cache you can/want to use.
+ * The number you put at IOMAN_NUMBUFFER is multiplied by 512. So 1 means
+ * 512 bytes cache, 4 means 2048 bytes cache. More is better.
+ * The number after IOMAN_NUMITERATIONS should be untouched.
+ * The last field (IOMAN_DO_MEMALLOC) is to tell ioman to allocate it's
+ * own memory in it's structure, or not. If you choose to do it yourself
+ * you will have to pass a pointer to the memory as the last argument of
+ * ioman_init.
+*/
+ /*#define IOMAN_NUMBUFFER 1*/
+ #define IOMAN_NUMBUFFER 1
+ #define IOMAN_NUMITERATIONS 1
+ #define IOMAN_DO_MEMALLOC
+
+/* Cluster pre-allocation
+ ----------------------
+
+ * When writing files, the function that performs the actual write has to
+ * calculate how many clusters it will need for that request. It then allocates
+ * that number of new clusters to the file. Since this involves some calculations
+ * and writing of the FAT, you might find it beneficial to limit the number of
+ * allocations, and allow fwrite to pre-allocate a number of clusters extra.
+ * This setting determines how many clusters will be extra allocated whenever
+ * this is required.
+ * Take in carefull consideration how large your clustersize is, putting 10 here
+ * with a clustersize of 32kb means you might waste 320 kb.
+ * The first option is for preallocating files, the other is used when enlarging
+ * a directory to accomodate more files
+*/
+ /*#define CLUSTER_PREALLOC_FILE 0*/
+ #define CLUSTER_PREALLOC_FILE 0
+ #define CLUSTER_PREALLOC_DIRECTORY 1
+
+
+/* Endianess configuration
+ -----------------------
+
+ * Here you can configure wheter your architecture is little or big endian. This
+ * is important since all FAT structures are stored in intel little endian order.
+ * So if you have a big endian system the library has to convert all figures to
+ * big endian in order to work.
+ */
+ /*#define LITTLE_ENDIAN*/
+
+
+/* Date and Time support
+ ---------------------
+
+ * Here you can enable or disable date and time support. If you enable
+ * it you will have to create 6 functions, that are described in the
+ * EFSL manual. If the functions are not present when linking your
+ * program with the library you will get unresolved dependencies.
+ */
+ /*#define DATE_TIME_SUPPORT*/
+
+/* Error reporting support
+ -----------------------
+
+ * When you receive an error in userland, it usually only gives limited
+ * information (most likely, fail or success). If error detection and
+ * reporting is important for you, you can enable more detailed error
+ * reporting here. This is optional, the costs are 1 byte per object,
+ * and a small increase in code size.
+ * You can enable error recording for all object, or you can select the
+ * object manually.
+ * For full error reporting use FULL_ERROR_SUPPORT
+ * For only the base-core of the library use BASE_ERROR_SUPPORT
+ * For IO/Man use ERRSUP_IOMAN
+ * For Disc use ERRSUP_IOMAN
+ * For Part use ERRSUP_PARTITION
+ * For Fs use ERRSUP_FILESYSTEM
+ * For File use ERRSUP_FILE
+*/
+
+ #define FULL_ERROR_SUPPORT
+ /*#define BASE_ERROR_SUPPORT*/
+
+/* List options
+ ------------
+
+ * In this section youcan configure what kind of data you will get from
+ * directory listing requests. Please refer to the documentation for
+ * more information
+*/
+
+#define LIST_MAXLENFILENAME 12
+
+
+
+
+/* Debugging configuration
+ -----------------------
+
+ * Here you can configure the debugging behaviour. Debugging is different
+ * on every platform (see debug.h for more information).
+ * If your hardware has no means of output (printf) dont define any anything,
+ * and nothing will happen. For real world use debugging should be turned off.
+*/
+
+// #define DEBUG
+
+
+#endif
diff --git a/F107/Utilities/efsl/include/debug.h b/F107/Utilities/efsl/include/debug.h
new file mode 100644
index 0000000..57d2812
--- /dev/null
+++ b/F107/Utilities/efsl/include/debug.h
@@ -0,0 +1,141 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------------------------------------------- *
+* *
+* Filename : debug.h *
+* Description : Headerfile for debug.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/* Contributions
+ * LPC2000 ARM7 Interface (c)2005 Martin Thomas *
+ */
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+/*****************************************************************************/
+#include "types.h"
+#include "config.h"
+/*****************************************************************************/
+
+#ifndef DEBUG
+ #define TXT(x) ;
+ #define DBG(x) ;
+ #define FUNC_IN(x) ;
+ #define FUNC_OUT(x) ;
+#endif
+
+#ifdef DEBUG
+ #if defined(HW_ENDPOINT_LINUX) || defined(HW_ENDPOINT_LINUX64)
+ #define HW_ENDPOINT_LINUX_ALL
+ #endif
+
+ #ifdef HW_ENDPOINT_ATMEGA128_SD
+ #include
+ #include
+ #include
+ //#include
+
+ #define TXT(x) PSTR(x)
+ #define DBG(x) debug x
+ #define FUNC_IN(x) ;
+ #define FUNC_OUT(x) ;
+ #endif
+
+ #ifdef HW_ENDPOINT_STM32F10X_SD
+ //#include
+ #include
+
+ #define TXT(x) x
+ #define DBG(x) printf x
+ #define FUNC_IN(x) ;
+ #define FUNC_OUT(x) ;
+ #endif
+
+
+
+
+
+ #ifdef HW_ENDPOINT_LINUX_ALL
+ //#include
+ #include
+
+ #define TXT(x) x
+ #define DBG(x) debug x
+ #define FUNC_IN(x) debug_funcin(x)
+ #define FUNC_OUT(x) debug_funcout(x)
+ #endif
+
+ #ifdef HW_ENDPOINT_DSP_TI6713_SD
+ //#include
+ #include
+
+ #define TXT(x) x
+ #define DBG(x) printf x
+ #define FUNC_IN(x) ;
+ #define FUNC_OUT(x) ;
+ #endif
+ #ifdef HW_ENDPOINT_NIOS_2_SD
+ //#include
+ #include
+
+ #define TXT(x) x
+ #define DBG(x) printf x
+ #define FUNC_IN(x) ;
+ #define FUNC_OUT(x) ;
+ #endif
+ #ifdef HW_ENDPOINT_LPC2000_SD
+ #include <__cross_studio_io.h>
+ #define TXT(x) x
+ #define DBG(x) debug_printf x
+ #define FUNC_IN(x) ;
+ #define FUNC_OUT(x) ;
+ #define debug debug_printf
+ #else
+ void debug(void/*const eint8 *format, ...*/); /* This is messy FIXME */
+ #endif
+
+ void debug_init();
+ void debug_end();
+
+ #ifdef HW_ENDPOINT_LINUX_ALL
+ FILE* debugfile;
+ volatile euint8 tw;
+ void debug_funcin(const eint8 *format, ...);
+ void debug_funcout(const eint8 *format, ...);
+ euint8 debug_getByte();
+ euint8 debug_getString(euint8 *data,euint16 length);
+ #endif
+
+ #ifdef HW_ENDPOINT_ATMEGA128_SD
+ void debug_initUART(euint16 baudrate );
+ void debug_sendByte(euint8 data );
+ #endif
+
+#endif
+
+#endif
diff --git a/F107/Utilities/efsl/include/dir.h b/F107/Utilities/efsl/include/dir.h
new file mode 100644
index 0000000..0e3d84a
--- /dev/null
+++ b/F107/Utilities/efsl/include/dir.h
@@ -0,0 +1,84 @@
+/***************************************************************************** \
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : dir.h *
+* Description : Headerfile for dir.c The files are an extend of the fs.c fs.h *
+* pair. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+#ifndef __DDIR_H__
+#define __DDIR_H__
+
+/*****************************************************************************/
+#include "config.h"
+#include "error.h"
+#include "fat.h"
+#include "plibc.h"
+#include "types.h"
+#include "ioman.h"
+#include "time.h"
+#include "fs.h"
+/*****************************************************************************/
+
+#define ATTR_READ_ONLY 0x01
+#define ATTR_HIDDEN 0x02
+#define ATTR_SYSTEM 0x04
+#define ATTR_VOLUME_ID 0x08
+#define ATTR_DIRECTORY 0x10
+#define ATTR_ARCHIVE 0x20
+
+#define OFFSET_DE_FILENAME 0
+#define OFFSET_DE_ATTRIBUTE 11
+#define OFFSET_DE_NTRESERVED 12
+#define OFFSET_DE_CRTIMETNT 13
+#define OFFSET_DE_CREATETIME 14
+#define OFFSET_DE_CREATEDATE 16
+#define OFFSET_DE_LASTACCESSDATE 18
+#define OFFSET_DE_FIRSTCLUSTERHIGH 20
+#define OFFSET_DE_WRITETIME 22
+#define OFFSET_DE_WRITEDATE 24
+#define OFFSET_DE_FIRSTCLUSTERLOW 26
+#define OFFSET_DE_FILESIZE 28
+
+#define DIRFIND_FILE 0
+#define DIRFIND_FREE 1
+
+void dir_getFileStructure(FileSystem *fs,FileRecord *filerec,FileLocation *loc);
+void dir_createDirectoryEntry(FileSystem *fs,FileRecord *filerec,FileLocation *loc);
+void dir_createDefaultEntry(FileSystem *fs,FileRecord *filerec,eint8* fatfilename);
+void dir_setFirstCluster(FileSystem *fs,FileLocation *loc,euint32 cluster_addr);
+void dir_setFileSize(FileSystem *fs,FileLocation *loc,euint32 numbytes);
+euint32 dir_findinRoot(FileSystem *fs,eint8 * fatname, FileLocation *loc);
+euint32 dir_findinDir(FileSystem *fs, eint8 * fatname, euint32 startCluster, FileLocation *loc, euint8 mode);
+euint32 dir_findinBuf(euint8 *buf,eint8 *fatname, FileLocation *loc, euint8 mode);
+euint32 dir_findinCluster(FileSystem *fs,euint32 cluster,eint8 *fatname, FileLocation *loc, euint8 mode);
+euint32 dir_findinRootArea(FileSystem *fs,eint8* fatname, FileLocation *loc, euint8 mode);
+esint8 dir_getFatFileName(eint8* filename, eint8* fatfilename);
+esint8 dir_updateDirectoryEntry(FileSystem *fs,FileRecord *entry,FileLocation *loc);
+esint8 dir_addCluster(FileSystem *fs,euint32 firstCluster);
+#endif
diff --git a/F107/Utilities/efsl/include/disc.h b/F107/Utilities/efsl/include/disc.h
new file mode 100644
index 0000000..b5f6e8a
--- /dev/null
+++ b/F107/Utilities/efsl/include/disc.h
@@ -0,0 +1,88 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : disc.h *
+* Description : This is the header file for disc.c *
+* *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __DISC_H_
+#define __DISC_H_
+
+/*****************************************************************************/
+#include "config.h"
+#include "error.h"
+#include "interface.h"
+#include "ioman.h"
+#include "types.h"
+#include "debug.h"
+/*****************************************************************************/
+
+#define LBA_ADDR_MBR 0
+#define PARTITION_TABLE_OFFSET 0x1BE
+
+/**********************************************************\
+ PartitionField
+ ------------
+* uchar type Type of partition
+* ulong LBA_begin LBA address of first sector.
+* ulong numSectors Number of 512byte sectors
+This structure is a literal representation of a 16 byte
+partitionfield. Direct I/O is possible.
+\**********************************************************/
+struct PartitionField{
+ euint8 bootFlag;
+ euint8 CHS_begin[3];
+ euint8 type;
+ euint8 CHS_end[3];
+ euint32 LBA_begin;
+ euint32 numSectors;
+};
+typedef struct PartitionField PartitionField;
+
+#define SIZE_PARTITION_FIELD 16
+
+/***************************************************************************************\
+ Disc
+ --
+* CompactFlash* sourcedisc Pointer to the hardwareobject that this disc is on.
+* PartitionField* partitions Array of PartitionFields, containing the partition info
+\***************************************************************************************/
+struct Disc{
+ IOManager *ioman;
+ DISC_ERR_EUINT8
+ PartitionField partitions[4];
+};
+typedef struct Disc Disc;
+
+void disc_initDisc(Disc *disc,IOManager *ioman);
+void disc_loadMBR(Disc *disc);
+
+#include "extract.h"
+
+#endif
diff --git a/F107/Utilities/efsl/include/efs.h b/F107/Utilities/efsl/include/efs.h
new file mode 100644
index 0000000..1aceb42
--- /dev/null
+++ b/F107/Utilities/efsl/include/efs.h
@@ -0,0 +1,63 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : efs.h *
+* Description : Headerfile for efs.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __EFS_H__
+#define __EFS_H__
+
+/*****************************************************************************/
+#include "types.h"
+#include "config.h"
+#include "interface.h"
+#include "disc.h"
+#include "partition.h"
+#include "fs.h"
+#include "file.h"
+#include "time.h"
+#include "ui.h"
+/*****************************************************************************/
+
+typedef File EmbeddedFile;
+
+struct EmbeddedFileSystem{
+ hwInterface myCard;
+ IOManager myIOman;
+ Disc myDisc;
+ Partition myPart;
+ FileSystem myFs;
+};
+typedef struct EmbeddedFileSystem EmbeddedFileSystem;
+
+esint8 efs_init(EmbeddedFileSystem * efs,eint8 * opts);
+
+
+#endif
+
diff --git a/F107/Utilities/efsl/include/error.h b/F107/Utilities/efsl/include/error.h
new file mode 100644
index 0000000..b6d948a
--- /dev/null
+++ b/F107/Utilities/efsl/include/error.h
@@ -0,0 +1,123 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : error.h *
+* Description : Header file containing error-defines. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+#ifndef __ERROR_H_
+#define __ERROR_H_
+
+/*****************************************************************************/
+#include "config.h"
+#include "interface.h"
+/*****************************************************************************/
+
+#if defined (FULL_ERROR_SUPPORT)
+ #define ERRSUP_IOMAN
+ #define ERRSUP_DISC
+ #define ERRSUP_PARTITION
+ #define ERRSUP_FAT_FILESYSTEM
+ #define ERRSUP_FAT_FILESYSTEM
+#elif defined (BASE_ERROR_SUPPORT)
+ #define ERRSUP_IOMAN
+ #define ERRSUP_DISC
+ #define ERRSUP_PARTITION
+#endif
+
+#if defined (HWINT_HAS_ERROR_SUPPORT) && defined (INTERFACE_ERROR_SUPPORT)
+ #define ERRSUP_HWINTERFACE
+#endif
+
+#ifdef ERRSUP_IOMAN
+ #define IOMAN_ERR_EUINT8 euint8 error;
+ #define ioman_setError(ioman,errval) ioman->error = errval
+ #define ioman_getError(ioman) ioman->error
+#else
+ #define IOMAN_ERR_EUINT8
+ #define ioman_setError(ioman,errval)
+ #define ioman_getError(ioman) 0
+#endif
+
+#ifdef ERRSUP_DISC
+ #define DISC_ERR_EUINT8 euint8 error;
+ #define disc_setError(disc,errval) disc->error = errval
+ #define disc_getError(disc) disc->error
+#else
+ #define DISC_ERR_EUINT8
+ #define disc_setError(disc,errval)
+ #define disc_getError(disc) 0
+#endif
+
+#ifdef ERRSUP_PART
+ #define PART_ERR_EUINT8 euint8 error;
+ #define part_setError(part,errval) part->error = errval
+ #define part_getError(part) part->error
+#else
+ #define PART_ERR_EUINT8
+ #define part_setError(part,errval)
+ #define part_getError(part) 0
+#endif
+
+#ifdef ERRSUP_FAT_FILESYSTEM
+ #define FILESYSTEM_ERR_EUINT8 euint8 error;
+ #define fs_setError(fs,errval) fs->error = errval
+ #define fs_getError(fs) fs->error
+#else
+ #define FILESYSTEM_ERR_EUINT8
+ #define fs_setError(fs,errval)
+ #define fs_getError(fs) 0
+#endif
+
+#ifdef ERRSUP_FILE
+ #define FILE_ERR_EUINT8 euint8 error;
+ #define file_setError(file,errval) file->error = errval
+ #define file_getError(file) file->error
+#else
+ #define FILE_ERR_EUINT8
+ #define file_setError(file,errval)
+ #define file_getError(file) 0
+#endif
+
+#define IOMAN_NOERROR 0
+#define IOMAN_ERR_SETATTROUTOFBOUNDS 1
+#define IOMAN_ERR_GETATTROUTOFBOUNDS 2
+#define IOMAN_ERR_READFAIL 3
+#define IOMAN_ERR_WRITEFAIL 4
+#define IOMAN_ERR_OPOUTOFBOUNDS 5
+#define IOMAN_ERR_PUSHBEYONDSTACK 6
+#define IOMAN_ERR_POPEMPTYSTACK 7
+#define IOMAN_ERR_CACHEPTROUTOFRANGE 8
+#define IOMAN_ERR_WRITEREADONLYSECTOR 9
+#define IOMAN_ERR_NOMEMORY 10
+
+#define DISC_NOERROR 0
+
+#define PART_NOERROR 0
+
+
+#endif
diff --git a/F107/Utilities/efsl/include/extract.h b/F107/Utilities/efsl/include/extract.h
new file mode 100644
index 0000000..6ae114f
--- /dev/null
+++ b/F107/Utilities/efsl/include/extract.h
@@ -0,0 +1,74 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : extract.h *
+* Description : Headerfile for extract.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __EXTRACT_H_
+#define __EXTRACT_H_
+
+/*****************************************************************************/
+#include "config.h"
+#include "disc.h"
+#include "types.h"
+/*****************************************************************************/
+
+#ifdef BIG_ENDIAN
+
+#define ltb_end16(x) ((((uint16)(x) & 0xff00) >> 8) | \
+ (((uint16)(x) & 0x00ff) << 8))
+#define ltb_end32(x) ((((uint32)(x) & 0xff000000) >> 24) | \
+ (((uint32)(x) & 0x00ff0000) >> 8) | \
+ (((uint32)(x) & 0x0000ff00) << 8) | \
+ (((uint32)(x) & 0x000000ff) << 24))
+
+#else
+
+#define ltb_end16(x) (x)
+#define ltb_end32(x) (x)
+
+#endif
+
+#define btl_end16 ltb_end16
+#define btl_end32 ltb_end32
+
+
+/*****************************************************************************/
+
+euint16 ex_getb16(euint8* buf,euint32 offset);
+void ex_setb16(euint8* buf,euint32 offset,euint16 data);
+
+euint32 ex_getb32(euint8* buf,euint32 offset);
+void ex_setb32(euint8* buf,euint32 offset,euint32 data);
+
+void ex_getPartitionField(euint8* buf,PartitionField* pf, euint32 offset);
+void ex_setPartitionField(euint8* buf,PartitionField* pf, euint32 offset);
+
+#endif
+
diff --git a/F107/Utilities/efsl/include/fat.h b/F107/Utilities/efsl/include/fat.h
new file mode 100644
index 0000000..2cc009b
--- /dev/null
+++ b/F107/Utilities/efsl/include/fat.h
@@ -0,0 +1,62 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : fat.h *
+* Description : Headerfile for fat.c The files are an extend of the fs.c fs.h *
+* pair. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __FAT_H_
+#define __FAT_H_
+
+/*****************************************************************************/
+#include "config.h"
+#include "error.h"
+#include "file.h"
+#include "debug.h"
+#include "types.h"
+/*****************************************************************************/
+
+euint32 fat_getSectorAddressFatEntry(FileSystem *fs,euint32 cluster_addr);
+euint32 fat_getNextClusterAddress(FileSystem *fs, euint32 cluster_addr, euint16 *linear);
+void fat_setNextClusterAddress(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr);
+eint16 fat_isEocMarker(FileSystem *fs,euint32 fat_entry);
+euint32 fat_giveEocMarker(FileSystem *fs);
+euint32 fat_findClusterAddress(FileSystem *fs,euint32 cluster,euint32 offset, euint8 *linear);
+euint32 fat_getNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr, euint8 * buf);
+void fat_setNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr,euint8 * buf);
+esint16 fat_getNextClusterChain(FileSystem *fs, ClusterChain *Cache);
+void fat_bogus(void);
+esint16 fat_LogicToDiscCluster(FileSystem *fs, ClusterChain *Cache,euint32 logiccluster);
+eint16 fat_allocClusterChain(FileSystem *fs,ClusterChain *Cache,euint32 num_clusters);
+eint16 fat_unlinkClusterChain(FileSystem *fs,ClusterChain *Cache);
+euint32 fat_countClustersInChain(FileSystem *fs,euint32 firstcluster);
+euint32 fat_DiscToLogicCluster(FileSystem *fs,euint32 firstcluster,euint32 disccluster);
+euint32 fat_countFreeClusters(FileSystem *fs);
+
+#endif
diff --git a/F107/Utilities/efsl/include/file.h b/F107/Utilities/efsl/include/file.h
new file mode 100644
index 0000000..bb73d83
--- /dev/null
+++ b/F107/Utilities/efsl/include/file.h
@@ -0,0 +1,96 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : file.h *
+* Description : Headerfile for file.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __FILE_H_
+#define __FILE_H_
+
+/*****************************************************************************/
+#include "config.h"
+#include "error.h"
+#include "time.h"
+#include "fs.h"
+#include "dir.h"
+#include "plibc.h"
+#include "debug.h"
+#include "types.h"
+#include "fat.h"
+
+/*****************************************************************************/
+
+#define MODE_READ 0x72
+#define MODE_WRITE 0x77
+#define MODE_APPEND 0x61
+
+#define FILE_STATUS_OPEN 0
+#define FILE_STATUS_WRITE 1
+
+/*****************************************************************************\
+ * File
+ * ------
+ * FileRecord DirEntry Copy of the FileRecord for this file
+ * FileLocation Location Location of the direntry
+ * FileSystem *fs Pointer to the filesystem this file is on
+ * FileCache Cache Pointer to the cache object of the file
+ * euint8 FileStatus Contains bitfield regarding filestatus
+ * euint32 FilePtr Offsetpointer for fread/fwrite functions
+ * euint32 FileSize Working copy of the filesize, always use this,
+ it is more up to date than DirEntry->FileSize,
+ which is only updated when flushing to disc.
+\*****************************************************************************/
+struct File{
+ FileRecord DirEntry;
+ FileLocation Location; /* Location in directory!! */
+ FileSystem *fs;
+ ClusterChain Cache;
+ euint8 FileStatus;
+ euint32 FilePtr;
+ euint32 FileSize;
+};
+typedef struct File File;
+
+
+esint8 file_fopen(File *file, FileSystem *fs,eint8 *filename, eint8 mode);
+esint8 file_fclose(File *file);
+esint16 file_setpos(File *file,euint32 pos);
+euint32 file_fread(File *file,euint32 offset, euint32 size,euint8 *buf);
+euint32 file_read (File *file,euint32 size,euint8 *buf);
+euint32 file_fwrite(File* file,euint32 offset,euint32 size,euint8* buf);
+euint32 file_write (File* file,euint32 size,euint8* buf);
+eint8* file_normalToFatName(eint8* filename,eint8* fatfilename);
+euint8 file_validateChar(euint8 c);
+void file_initFile(File *file, FileSystem *fs, FileLocation *loc);
+eint16 file_allocClusterChain(File *file,euint32 num_clusters);
+void file_setAttr(File* file,euint8 attribute,euint8 val);
+euint8 file_getAttr(File* file,euint8 attribute);
+euint32 file_requiredCluster(File *file,euint32 offset, euint32 size);
+
+#endif
diff --git a/F107/Utilities/efsl/include/fs.h b/F107/Utilities/efsl/include/fs.h
new file mode 100644
index 0000000..db0ba07
--- /dev/null
+++ b/F107/Utilities/efsl/include/fs.h
@@ -0,0 +1,166 @@
+
+#ifndef __FS_H_
+#define __FS_H_
+
+/*****************************************************************************/
+#include "config.h"
+#include "error.h"
+#include "partition.h"
+#include "types.h"
+#include "debug.h"
+#include "time.h"
+/*****************************************************************************/
+
+#define FAT12 1
+#define FAT16 2
+#define FAT32 3
+
+#define FS_INFO_SECTOR 1
+#define FSINFO_MAGIC_BEGIN 0x41615252
+#define FSINFO_MAGIC_END 0xAA550000
+
+/*****************************************************************************************\
+ VolumeId
+ ------
+* ushort BytesPerSector Must be 512 or shit happens.
+* uchar SectorsPerCluster Must be multiple of 2 (1,2,4,8,16 or 32)
+* ushort ReservedSectorCount Number of sectors after which the first FAT begins.
+* uchar NumberOfFats Should be 2
+* ushort RootEntryCount Number of filerecords the Rootdir can contain. NOT for FAT32
+* ushort SectorCount16 Number of Sectors for 12/16 bit FAT
+* ushort FatSectorCount16 Number of Sectors for 1 FAT on FAT12/16 bit FAT's
+* ulong SectorCount32 Number of Sectors for 32 bit FAT
+* ulong FatSectorCount32 Number of Sectors for 1 FAT on FAT32
+* ulong RootCluster Clusternumber of the first cluster of the RootDir on FAT 32
+This is NOT a complete volumeId copy, no direct I/O is possible.
+\*****************************************************************************************/
+struct VolumeId{
+ euint16 BytesPerSector;
+ euint8 SectorsPerCluster;
+ euint16 ReservedSectorCount;
+ euint8 NumberOfFats;
+ euint16 RootEntryCount;
+ euint16 SectorCount16;
+ euint16 FatSectorCount16;
+ euint32 SectorCount32;
+ euint32 FatSectorCount32;
+ euint32 RootCluster;
+};
+typedef struct VolumeId VolumeId;
+
+/**************************************************************************************************\
+ FileSystem
+ --------
+* Partition* part Pointer to partition on which this FS resides.
+* VolumeId volumeId Contains important FS info.
+* ulong DataClusterCount Number of dataclusters. This number determines the FATType.
+* ulong FatSectorCount Number of sectors for 1 FAT, regardless of FATType
+* ulong SectorCount Number of sectors, regardless of FATType
+* ulong FirstSectorRootDir First sector of the RootDir.
+* uchar type Determines FATType (FAT12 FAT16 or FAT32 are defined)
+
+\**************************************************************************************************/
+struct FileSystem{
+ Partition *part;
+ VolumeId volumeId;
+ euint32 DataClusterCount;
+ euint32 FatSectorCount;
+ euint32 SectorCount;
+ euint32 FirstSectorRootDir;
+ euint32 FirstClusterCurrentDir;
+ euint32 FreeClusterCount;
+ euint32 NextFreeCluster;
+ euint8 type;
+};
+typedef struct FileSystem FileSystem;
+
+/**************************************************************************************************\ FileLocation
+ ----------
+* euint32 Sector Sector where the directoryentry of the file/directory can be found.
+* euint8 Offset Offset (in 32byte segments) where in the sector the entry is.
+
+\**************************************************************************************************/
+struct FileLocation{
+ euint32 Sector;
+ euint8 Offset;
+ euint8 attrib;
+};
+typedef struct FileLocation FileLocation;
+
+/*****************************************************************************\
+* FileCache
+* -----------
+* This struct acts as cache for the current file. It contains the current
+* FATPointer (next location in the FAT table), LogicCluster
+* (the last part of the file that was read) and DataCluster
+* (the last cluster that was read).
+* euint8 Linear For how many more clusters the file is nonfragmented
+* euint32 LogicCluster This field determines the n'th cluster of the file as current
+* euint32 DiscCluster If this field is 0, it means the cache is invalid. Otherwise
+ it is the clusternumber corresponding with
+ logic(FirstCluster+LogicCluster).
+* euint32 FirstCluster First cluster of the chain. Zero or one are invalid.
+* euint32 LastCluster Last cluster of the chain (is not always filled in)
+\*****************************************************************************/
+struct ClusterChain{
+ euint8 Linear;
+ esint32 LogicCluster;
+ euint32 DiscCluster;
+ euint32 FirstCluster;
+ euint32 LastCluster;
+ euint32 ClusterCount;
+};
+typedef struct ClusterChain ClusterChain;
+
+/*****************************************************************************\
+* FileRecord *
+* ------------ *
+* This struct represents a 32 byte file entry as it occurs in the data area *
+* of the filesystem. Direct I/O is possible. *
+\*****************************************************************************/
+struct FileRecord{
+ euint8 FileName[11];
+ euint8 Attribute;
+ euint8 NTReserved;
+ euint8 MilliSecTimeStamp;
+ euint16 CreatedTime;
+ euint16 CreatedDate;
+ euint16 AccessDate;
+ euint16 FirstClusterHigh;
+ euint16 WriteTime;
+ euint16 WriteDate;
+ euint16 FirstClusterLow;
+ euint32 FileSize;
+};
+typedef struct FileRecord FileRecord;
+
+
+eint16 fs_initFs(FileSystem *fs,Partition *part);
+eint16 fs_isValidFat(Partition *part);
+void fs_loadVolumeId(FileSystem *fs, Partition *part);
+esint16 fs_verifySanity(FileSystem *fs);
+void fs_countDataSectors(FileSystem *fs);
+void fs_determineFatType(FileSystem *fs);
+void fs_findFirstSectorRootDir(FileSystem *fs);
+void fs_initCurrentDir(FileSystem *fs);
+euint32 fs_getSectorAddressRootDir(FileSystem *fs,euint32 secref);
+euint32 fs_clusterToSector(FileSystem *fs,euint32 cluster);
+euint32 fs_sectorToCluster(FileSystem *fs,euint32 sector);
+euint32 fs_getNextFreeCluster(FileSystem *fs,euint32 startingcluster);
+euint32 fs_giveFreeClusterHint(FileSystem *fs);
+esint16 fs_findFreeFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint8 mode);
+esint8 fs_findFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint32 *lastDir);
+esint8 fs_findFile_broken(FileSystem *fs,eint8* filename,FileLocation *loc);
+euint32 fs_getLastCluster(FileSystem *fs,ClusterChain *Cache);
+euint32 fs_getFirstClusterRootDir(FileSystem *fs);
+euint16 fs_makeDate(void);
+euint16 fs_makeTime(void);
+void fs_setFirstClusterInDirEntry(FileRecord *rec,euint32 cluster_addr);
+void fs_initClusterChain(FileSystem *fs,ClusterChain *cache,euint32 cluster_addr);
+esint8 fs_flushFs(FileSystem *fs);
+esint8 fs_umount(FileSystem *fs);
+esint8 fs_clearCluster(FileSystem *fs,euint32 cluster);
+esint8 fs_getFsInfo(FileSystem *fs,euint8 force_update);
+esint8 fs_setFsInfo(FileSystem *fs);
+
+#endif
diff --git a/F107/Utilities/efsl/include/interface.h b/F107/Utilities/efsl/include/interface.h
new file mode 100644
index 0000000..d950f23
--- /dev/null
+++ b/F107/Utilities/efsl/include/interface.h
@@ -0,0 +1,49 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* -------------------------------------------------------- *
+* *
+* Filename : interface.h *
+* Description : This headerfile includes the right interface headerfile *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+#ifndef __TYPES_H__
+#define __TYPES_H__
+
+/*****************************************************************************/
+#include "types.h"
+#include "config.h"
+/*****************************************************************************/
+
+#if defined(HW_ENDPOINT_STM32F10X_SD)
+ #include "sd_stm32.h"
+
+#else
+ #error "NO INTERFACE DEFINED - see interface.h"
+#endif
+
+#endif
+
diff --git a/F107/Utilities/efsl/include/interface/sd.h b/F107/Utilities/efsl/include/interface/sd.h
new file mode 100644
index 0000000..b676f39
--- /dev/null
+++ b/F107/Utilities/efsl/include/interface/sd.h
@@ -0,0 +1,58 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------------------------------------------- *
+* *
+* Filename : sd.h *
+* Revision : Initial developement *
+* Description : Headerfile for sd.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+#ifndef __SD_H_
+#define __SD_H_
+
+#include "config.h"
+#include "types.h"
+#include "../debug.h"
+
+#include "sd_stm32.h"
+
+#define CMDREAD 17
+#define CMDWRITE 24
+#define CMDREADCSD 9
+
+esint8 sd_Init(hwInterface *iface);
+void sd_Command(hwInterface *iface,euint8 cmd, euint16 paramx, euint16 paramy);
+euint8 sd_Resp8b(hwInterface *iface);
+void sd_Resp8bError(hwInterface *iface,euint8 value);
+euint16 sd_Resp16b(hwInterface *iface);
+esint8 sd_State(hwInterface *iface);
+
+esint8 sd_readSector(hwInterface *iface,euint32 address,euint8* buf, euint16 len);
+esint8 sd_writeSector(hwInterface *iface,euint32 address, euint8* buf);
+esint8 sd_getDriveSize(hwInterface *iface, euint32* drive_size );
+
+#endif
diff --git a/F107/Utilities/efsl/include/interface/sd_stm32.h b/F107/Utilities/efsl/include/interface/sd_stm32.h
new file mode 100644
index 0000000..dd4cd44
--- /dev/null
+++ b/F107/Utilities/efsl/include/interface/sd_stm32.h
@@ -0,0 +1,56 @@
+/**
+ ******************************************************************************
+ * @file sd_stm32.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief Header for sd_stm32.c
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __SD_STM32_H
+#define __SD_STM32_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "../debug.h"
+#include "config.h"
+
+
+/* Exported types ------------------------------------------------------------*/
+/*************************************************************\
+ hwInterface
+ ----------
+* FILE* imagefile File emulation of hw interface.
+* long sectorCount Number of sectors on the file.
+\*************************************************************/
+struct hwInterface{
+ /*FILE *imageFile;*/
+ eint32 sectorCount;
+};
+typedef struct hwInterface hwInterface;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+esint8 if_initInterface(hwInterface* file,eint8* opts);
+esint8 if_readBuf(hwInterface* file,euint32 address,euint8* buf);
+esint8 if_writeBuf(hwInterface* file,euint32 address,euint8* buf);
+esint8 if_setPos(hwInterface* file,euint32 address);
+void if_spiInit(hwInterface *iface);
+euint8 if_spiSend(hwInterface *iface, euint8 outgoing);
+
+
+#endif /*__SD_STM32_H */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/efsl/include/ioman.h b/F107/Utilities/efsl/include/ioman.h
new file mode 100644
index 0000000..3b740d8
--- /dev/null
+++ b/F107/Utilities/efsl/include/ioman.h
@@ -0,0 +1,135 @@
+/*****************************************************************************/
+/* libfat - General purpose FAT library *
+* ---------------------------------- *
+* *
+* Filename : ioman.h *
+* Description : Header file for ioman.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __IOMAN_H__
+#define __IOMAN_H__
+
+/*****************************************************************************/
+#include "interface.h"
+#include "error.h"
+#include "plibc.h"
+#include "debug.h"
+#include "types.h"
+#include "config.h"
+/*****************************************************************************/
+
+#define IOMAN_STATUS_ATTR_VALIDDATA 0
+#define IOMAN_STATUS_ATTR_USERBUFFER 1
+#define IOMAN_STATUS_ATTR_WRITE 2
+
+#define IOM_MODE_READONLY 1
+#define IOM_MODE_READWRITE 2
+#define IOM_MODE_EXP_REQ 4
+
+struct IOManStack{
+ euint32 sector;
+ euint8 status;
+ euint8 usage;
+};
+typedef struct IOManStack IOManStack;
+
+struct IOManager{
+ hwInterface *iface;
+
+ euint8 *bufptr;
+ euint16 numbuf;
+ euint16 numit;
+
+ IOMAN_ERR_EUINT8
+
+ IOManStack stack[IOMAN_NUMBUFFER][IOMAN_NUMITERATIONS];
+
+ euint32 sector[IOMAN_NUMBUFFER];
+ euint8 status[IOMAN_NUMBUFFER];
+ euint8 usage[IOMAN_NUMBUFFER];
+ euint8 reference[IOMAN_NUMBUFFER];
+ euint8 itptr[IOMAN_NUMBUFFER];
+#ifdef IOMAN_DO_MEMALLOC
+ euint8 cache_mem[IOMAN_NUMBUFFER * 512];
+#endif
+};
+typedef struct IOManager IOManager;
+
+#define IOBJ ioman
+
+#define ioman_isValid(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA)
+#define ioman_isUserBuf(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER)
+#define ioman_isWritable(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE)
+
+#define ioman_setValid(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA,1)
+#define ioman_setUserBuf(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER,1)
+#define ioman_setWritable(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE,1)
+
+#define ioman_setNotValid(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA,0)
+#define ioman_setNotUserBuf(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER,0)
+#define ioman_setNotWritable(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE,0)
+
+#define ioman_isReqRo(mode) ((mode)&(IOM_MODE_READONLY))
+#define ioman_isReqRw(mode) ((mode)&(IOM_MODE_READWRITE))
+#define ioman_isReqExp(mode) ((mode)&(IOM_MODE_EXP_REQ))
+
+esint8 ioman_init(IOManager *ioman, hwInterface *iface, euint8* bufferarea);
+void ioman_reset(IOManager *ioman);
+euint8* ioman_getBuffer(IOManager *ioman,euint8* bufferarea);
+void ioman_setAttr(IOManager *ioman,euint16 bufplace,euint8 attribute,euint8 val);
+euint8 ioman_getAttr(IOManager *ioman,euint16 bufplace,euint8 attribute);
+euint8 ioman_getUseCnt(IOManager *ioman,euint16 bufplace);
+void ioman_incUseCnt(IOManager *ioman,euint16 bufplace);
+void ioman_decUseCnt(IOManager *ioman,euint16 bufplace);
+void ioman_resetUseCnt(IOManager *ioman,euint16 bufplace);
+euint8 ioman_getRefCnt(IOManager *ioman,euint16 bufplace);
+void ioman_incRefCnt(IOManager *ioman,euint16 bufplace);
+void ioman_decRefCnt(IOManager *ioman,euint16 bufplace);
+void ioman_resetRefCnt(IOManager *ioman,euint16 bufplace);
+esint8 ioman_pop(IOManager *ioman,euint16 bufplace);
+esint8 ioman_push(IOManager *ioman,euint16 bufplace);
+euint8* ioman_getPtr(IOManager *ioman,euint16 bufplace);
+esint16 ioman_getBp(IOManager *ioman,euint8* buf);
+esint8 ioman_readSector(IOManager *ioman,euint32 address,euint8* buf);
+esint8 ioman_writeSector(IOManager *ioman, euint32 address, euint8* buf);
+void ioman_resetCacheItem(IOManager *ioman,euint16 bufplace);
+esint32 ioman_findSectorInCache(IOManager *ioman, euint32 address);
+esint32 ioman_findFreeSpot(IOManager *ioman);
+esint32 ioman_findUnusedSpot(IOManager *ioman);
+esint32 ioman_findOverallocableSpot(IOManager *ioman);
+esint8 ioman_putSectorInCache(IOManager *ioman,euint32 address, euint16 bufplace);
+esint8 ioman_flushSector(IOManager *ioman, euint16 bufplace);
+euint8* ioman_getSector(IOManager *ioman,euint32 address, euint8 mode);
+esint8 ioman_releaseSector(IOManager *ioman,euint8* buf);
+esint8 ioman_directSectorRead(IOManager *ioman,euint32 address, euint8* buf);
+esint8 ioman_directSectorWrite(IOManager *ioman,euint32 address, euint8* buf);
+esint8 ioman_flushRange(IOManager *ioman,euint32 address_low, euint32 address_high);
+esint8 ioman_flushAll(IOManager *ioman);
+
+void ioman_printStatus(IOManager *ioman);
+
+#endif
diff --git a/F107/Utilities/efsl/include/ioman_v2.h b/F107/Utilities/efsl/include/ioman_v2.h
new file mode 100644
index 0000000..ab6bf39
--- /dev/null
+++ b/F107/Utilities/efsl/include/ioman_v2.h
@@ -0,0 +1,123 @@
+/*****************************************************************************\
+* libfat - General purpose FAT library *
+* ---------------------------------- *
+* *
+* Filename : ioman.h *
+* Description : Header file for ioman.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+#ifndef __IOMAN_H__
+#define __IOMAN_H__
+
+/*****************************************************************************/
+#include "interface.h"
+#include "plibc.h"
+#include "debug.h"
+#include "types.h"
+#include "config.h"
+/*****************************************************************************/
+
+#define IOMAN_STATUS_ATTR_VALIDDATA 0
+#define IOMAN_STATUS_ATTR_USERBUFFER 1
+#define IOMAN_STATUS_ATTR_WRITE 2
+
+#define IOM_MODE_READONLY 0
+#define IOM_MODE_READWRITE 1
+
+struct IOManStack{
+ euint32 sector;
+ euint8 status;
+ euint8 usage;
+};
+typedef struct IOManStack IOManStack;
+
+struct IOManager{
+ hwInterface *iface;
+
+ euint8 *bufptr;
+ euint16 numbuf;
+ euint16 numit;
+
+ IOManStack stack[IOMAN_NUMBUFFER][IOMAN_NUMITERATIONS];
+
+ euint32 sector[IOMAN_NUMBUFFER];
+ euint8 status[IOMAN_NUMBUFFER];
+ euint8 usage[IOMAN_NUMBUFFER];
+ euint8 reference[IOMAN_NUMBUFFER];
+ euint8 itptr[IOMAN_NUMBUFFER];
+};
+typedef struct IOManager IOManager;
+
+#define IOBJ ioman
+
+#define ioman_isValid(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA)
+#define ioman_isUserBuf(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER)
+#define ioman_isWritable(bp) ioman_getAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE)
+
+#define ioman_setValid(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA,1)
+#define ioman_setUserBuf(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER,1)
+#define ioman_setWritable(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE,1)
+
+#define ioman_setNotValid(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_VALIDDATA,0)
+#define ioman_setNotUserBuf(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_USERBUFFER,0)
+#define ioman_setNotWritable(bp) ioman_setAttr(IOBJ,bp,IOMAN_STATUS_ATTR_WRITE,0)
+
+esint8 ioman_init(IOManager *ioman, hwInterface *iface, euint8* bufferarea);
+void ioman_reset(IOManager *ioman);
+euint8* ioman_getBuffer(IOManager *ioman,euint8* bufferarea);
+void ioman_setAttr(IOManager *ioman,euint16 bufplace,euint8 attribute,euint8 val);
+euint8 ioman_getAttr(IOManager *ioman,euint16 bufplace,euint8 attribute);
+euint8 ioman_getUseCnt(IOManager *ioman,euint16 bufplace);
+void ioman_incUseCnt(IOManager *ioman,euint16 bufplace);
+void ioman_decUseCnt(IOManager *ioman,euint16 bufplace);
+void ioman_resetUseCnt(IOManager *ioman,euint16 bufplace);
+euint8 ioman_getRefCnt(IOManager *ioman,euint16 bufplace);
+void ioman_incRefCnt(IOManager *ioman,euint16 bufplace);
+void ioman_decRefCnt(IOManager *ioman,euint16 bufplace);
+void ioman_resetRefCnt(IOManager *ioman,euint16 bufplace);
+esint8 ioman_pop(IOManager *ioman,euint16 bufplace);
+esint8 ioman_push(IOManager *ioman,euint16 bufplace);
+euint8* ioman_getPtr(IOManager *ioman,euint16 bufplace);
+esint16 ioman_getBp(IOManager *ioman,euint8* buf);
+esint8 ioman_readSector(IOManager *ioman,euint32 address,euint8* buf);
+esint8 ioman_writeSector(IOManager *ioman, euint32 address, euint8* buf);
+void ioman_resetCacheItem(IOManager *ioman,euint16 bufplace);
+
+esint32 ioman_findSectorInCache(IOManager *ioman, euint32 address);
+esint32 ioman_findFreeSpot(IOManager *ioman);
+esint32 ioman_findUnusedSpot(IOManager *ioman);
+esint32 ioman_findOverallocableSpot(IOManager *ioman);
+
+esint8 ioman_putSectorInCache(IOManager *ioman,euint32 address, euint16 bufplace);
+esint8 ioman_flushSector(IOManager *ioman, euint16 bufplace);
+
+euint8* ioman_getSector(IOManager *ioman,euint32 address, euint8 mode);
+esint8 ioman_releaseSector(IOManager *ioman,euint8* buf);
+
+void ioman_printStatus(IOManager *ioman);
+
+#endif
diff --git a/F107/Utilities/efsl/include/ls.h b/F107/Utilities/efsl/include/ls.h
new file mode 100644
index 0000000..244d420
--- /dev/null
+++ b/F107/Utilities/efsl/include/ls.h
@@ -0,0 +1,68 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : ls.h *
+* Description : Headerfile for ls.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __LS_H__
+#define __LS_H__
+
+/*****************************************************************************/
+#include "config.h"
+#include "fs.h"
+#include "dir.h"
+#include "fat.h"
+/*****************************************************************************/
+
+struct ListDirEntry{
+ euint8 FileName[LIST_MAXLENFILENAME];
+ euint32 FileSize;
+ euint8 Attribute;
+};
+typedef struct ListDirEntry ListDirEntry;
+
+struct DirList{
+ FileSystem *fs;
+ euint16 cEntry,rEntry;
+ /*FileRecord currentEntry;*/
+ ListDirEntry currentEntry;
+ ClusterChain Cache;
+};
+typedef struct DirList DirList;
+
+esint8 ls_openDir(DirList *dlist,FileSystem *fs,eint8* dirname);
+esint8 ls_getNext(DirList *dlist);
+
+esint8 ls_getDirEntry(DirList *dlist);
+esint8 ls_getRealDirEntry(DirList *dlist);
+esint8 ls_getRootAreaEntry(DirList *dlist);
+esint8 ls_isValidFileEntry(ListDirEntry *entry);
+void ls_fileEntryToDirListEntry(DirList *dlist, euint8* buf, euint16 offset);
+
+#endif
diff --git a/F107/Utilities/efsl/include/mkfs.h b/F107/Utilities/efsl/include/mkfs.h
new file mode 100644
index 0000000..91f80bc
--- /dev/null
+++ b/F107/Utilities/efsl/include/mkfs.h
@@ -0,0 +1,48 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------------------------------------------- *
+* *
+* Filename : mkfs.h *
+* Description : Headerfile for mkfs.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+#ifndef __MKFS_H_
+#define __MKFS_H_
+
+/*****************************************************************************/
+#include "partition.h"
+#include "plibc.h"
+#include "debug.h"
+#include "types.h"
+#include "config.h"
+/*****************************************************************************/
+
+#define MKFS_ERR_TOOLITTLESECTORS 1
+
+signed short mkfs_makevfat(Partition *part);
+
+#endif
diff --git a/F107/Utilities/efsl/include/partition.h b/F107/Utilities/efsl/include/partition.h
new file mode 100644
index 0000000..0292ee2
--- /dev/null
+++ b/F107/Utilities/efsl/include/partition.h
@@ -0,0 +1,78 @@
+
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------------------------------------------- *
+* *
+* Filename : partition.h *
+* Description : Headerfile for partition.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+#ifndef __PARTITION_H__
+#define __PARTITION_H__
+
+/*****************************************************************************/
+#include "config.h"
+#include "error.h"
+#include "interface.h"
+#include "disc.h"
+#include "types.h"
+/*****************************************************************************/
+
+#define PT_FAT12 0x01
+#define PT_FAT16A 0x04
+#define PT_FAT16 0x06
+#define PT_FAT32 0x0B
+#define PT_FAT32A 0x5C
+#define PT_FAT16B 0x5E
+
+/*************************************************************************************\
+ Partition
+ -------
+* Disc* disc Pointer to disc containing this partition.
+* eint8 activePartition Array subscript for disc->partitions[activePartition]
+\*************************************************************************************/
+struct Partition{
+ Disc *disc;
+ esint8 activePartition;
+};
+typedef struct Partition Partition;
+
+void part_initPartition(Partition *part,Disc* refDisc);
+eint16 part_isFatPart(euint8 type);
+esint8 part_readBuf(Partition *part, euint32 address, euint8* buf);
+esint8 part_readPartBuf(Partition *part, euint32 address, euint8* buf, euint32 offset, euint16 len);
+eint16 part_writeBuf(Partition *part,euint32 address,euint8* buf);
+euint8* part_getSect(Partition *part, euint32 address,euint8 mode);
+esint8 part_relSect(Partition *part, euint8* buf);
+esint8 part_flushPart(Partition *part,euint32 addr_l, euint32 addr_h);
+esint8 part_directSectorRead(Partition *part, euint32 address, euint8* buf);
+esint8 part_directSectorWrite(Partition *part, euint32 address, euint8* buf);
+euint32 part_getRealLBA(Partition *part,euint32 address);
+
+#include "extract.h"
+
+#endif
diff --git a/F107/Utilities/efsl/include/plibc.h b/F107/Utilities/efsl/include/plibc.h
new file mode 100644
index 0000000..ab6990b
--- /dev/null
+++ b/F107/Utilities/efsl/include/plibc.h
@@ -0,0 +1,48 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------------------------------------------- *
+* *
+* Filename : plibc.h *
+* Description : Headerfile for plibc.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+#ifndef __PLIBC_H__
+#define __PLIBC_H__
+
+/*****************************************************************************/
+#include "debug.h"
+#include "types.h"
+#include "config.h"
+/*****************************************************************************/
+
+euint16 strMatch(eint8* bufa, eint8*bufb,euint32 n);
+void memCpy(void* psrc, void* pdest, euint32 size);
+void memClr(void *pdest,euint32 size);
+void memSet(void *pdest,euint32 size,euint8 data);
+
+
+#endif
diff --git a/F107/Utilities/efsl/include/time.h b/F107/Utilities/efsl/include/time.h
new file mode 100644
index 0000000..d9475ec
--- /dev/null
+++ b/F107/Utilities/efsl/include/time.h
@@ -0,0 +1,44 @@
+/*****************************************************************************/
+
+/*****************************************************************************/
+#ifndef __TIME_H_
+#define __TIME_H_
+
+/*****************************************************************************/
+#include "types.h"
+/*****************************************************************************/
+
+#ifdef DATE_TIME_SUPPORT
+ #define time_getYear(void) efsl_getYear()
+ #define time_getMonth(void) efsl_getMonth()
+ #define time_getDay(void) efsl_getDay()
+ #define time_getHour(void) efsl_getHour()
+ #define time_getMinute(void) efsl_getMinute()
+ #define time_getSecond(void) efsl_getSecond()
+ #define time_getDate(void) fs_makeDate()
+ #define time_getTime(void) fs_makeTime()
+#else
+ #define time_getYear(void) 0x0;
+ #define time_getMonth(void) 0x0;
+ #define time_getDay(void) 0x0;
+ #define time_getHour(void) 0x0;
+ #define time_getMinute(void) 0x0;
+ #define time_getSecond(void) 0x0;
+ #define time_getDate(void) 0x0;
+ #define time_getTime(void) 0x0;
+#endif
+
+#ifdef DATE_TIME_SUPPORT
+euint16 efsl_getYear(void);
+euint8 efsl_getMonth(void);
+euint8 efsl_getDay(void);
+euint8 efsl_getHour(void);
+euint8 efsl_getMinute(void);
+euint8 efsl_getSecond(void);
+euint16 fs_makeDate(void);
+euint16 fs_makeTime(void);
+#endif
+
+euint8 fs_hasTimeSupport(void);
+
+#endif
diff --git a/F107/Utilities/efsl/include/types.h b/F107/Utilities/efsl/include/types.h
new file mode 100644
index 0000000..f245230
--- /dev/null
+++ b/F107/Utilities/efsl/include/types.h
@@ -0,0 +1,72 @@
+
+
+#ifndef __EFS_TYPES_H__
+#define __EFS_TYPES_H__
+
+/*****************************************************************************/
+#include "config.h"
+/*****************************************************************************/
+
+#if defined(HW_ENDPOINT_LINUX)
+ typedef char eint8;
+ typedef signed char esint8;
+ typedef unsigned char euint8;
+ typedef short eint16;
+ typedef signed short esint16;
+ typedef unsigned short euint16;
+ typedef long eint32;
+ typedef signed long esint32;
+ typedef unsigned long euint32;
+#elif defined(HW_ENDPOINT_LINUX64)
+ typedef char eint8;
+ typedef signed char esint8;
+ typedef unsigned char euint8;
+ typedef short eint16;
+ typedef signed short esint16;
+ typedef unsigned short euint16;
+ typedef int eint32;
+ typedef signed int esint32;
+ typedef unsigned int euint32;
+#elif defined (HW_ENDPOINT_ATMEGA128_SD)
+ typedef char eint8;
+ typedef signed char esint8;
+ typedef unsigned char euint8;
+ typedef short eint16;
+ typedef signed short esint16;
+ typedef unsigned short euint16;
+ typedef long eint32;
+ typedef signed long esint32;
+ typedef unsigned long euint32;
+#elif defined(HW_ENDPOINT_DSP_TI6713_SD)
+ typedef char eint8;
+ typedef signed char esint8;
+ typedef unsigned char euint8;
+ typedef short eint16;
+ typedef signed short esint16;
+ typedef unsigned short euint16;
+ typedef int eint32;
+ typedef signed int esint32;
+ typedef unsigned int euint32;
+#elif defined(NIOS_2)
+ typedef char eint8;
+ typedef signed char esint8;
+ typedef unsigned char euint8;
+ typedef short eint16;
+ typedef signed short esint16;
+ typedef unsigned short euint16;
+ typedef int eint32;
+ typedef signed int esint32;
+ typedef unsigned int euint32;
+#else
+ typedef char eint8;
+ typedef signed char esint8;
+ typedef unsigned char euint8;
+ typedef short eint16;
+ typedef signed short esint16;
+ typedef unsigned short euint16;
+ typedef long eint32;
+ typedef signed long esint32;
+ typedef unsigned long euint32;
+#endif
+
+#endif
diff --git a/F107/Utilities/efsl/include/ui.h b/F107/Utilities/efsl/include/ui.h
new file mode 100644
index 0000000..7c1311a
--- /dev/null
+++ b/F107/Utilities/efsl/include/ui.h
@@ -0,0 +1,18 @@
+
+
+#ifndef __UI_H__
+#define __UI_H__
+
+/*****************************************************************************/
+#include "fs.h"
+#include "types.h"
+#include "fat.h"
+#include "dir.h"
+#include "config.h"
+/*****************************************************************************/
+
+short listFiles(FileSystem *fs, char *dir);
+esint16 rmfile(FileSystem *fs,euint8* filename);
+esint8 mkdir(FileSystem *fs,eint8* dirname);
+
+#endif
diff --git a/F107/Utilities/efsl/source/dir.c b/F107/Utilities/efsl/source/dir.c
new file mode 100644
index 0000000..f87f7c9
--- /dev/null
+++ b/F107/Utilities/efsl/source/dir.c
@@ -0,0 +1,361 @@
+
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : dir.c *
+* Description : The functions of dir.c are part of fs.c, they deal with all *
+* the directory specific stuff. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+/*****************************************************************************/
+#include "dir.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void dir_getFileStructure(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
+ * Description: This function stores the filerecord located at loc in filerec.
+ * It fetches the required sector for this.
+ * Return value: void
+*/
+void dir_getFileStructure(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
+{
+ euint8 *buf;
+
+ buf=part_getSect(fs->part,loc->Sector,IOM_MODE_READONLY);
+ *filerec=*(((FileRecord*)buf)+loc->Offset);
+ part_relSect(fs->part,buf);
+}
+
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void dir_createDirectoryEntry(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
+ * Description: This function writes the filerecord stored in filerec to disc at
+ * location loc.
+ * Return value: void
+*/
+void dir_createDirectoryEntry(FileSystem *fs,FileRecord *filerec,FileLocation *loc)
+{
+ euint8 *buf;
+
+ buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
+ memCpy(filerec,buf+(loc->Offset*sizeof(*filerec)),sizeof(*filerec));
+ part_relSect(fs->part,buf);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void dir_createDefaultEntry(FileSystem *fs,FileRecord *filerec,eint8* fatfilename)
+ * Description: This function fills in a filerecord with safe default values, and
+ * a given fatfilename. If your system has a means of knowing time, here is an
+ * excellent place to apply it to the filerecord.
+ * Return value: void
+*/
+void dir_createDefaultEntry(FileSystem *fs,FileRecord *filerec,eint8* fatfilename)
+{
+ memCpy(fatfilename,filerec->FileName,11);
+ filerec->Attribute=0x00;
+ filerec->NTReserved=0x00;
+ filerec->MilliSecTimeStamp=0x00;
+ filerec->CreatedTime=time_getTime();
+ filerec->CreatedDate=time_getDate();
+ filerec->AccessDate=filerec->CreatedDate;
+ filerec->FirstClusterHigh=0x0000;
+ filerec->WriteTime=filerec->CreatedTime;
+ filerec->WriteDate=filerec->CreatedDate;
+ filerec->FirstClusterLow=0x0000;
+ filerec->FileSize=0x00000000;
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void dir_setFirstCluster(File *file,euint32 cluster_addr)
+ * Description: This function requires modification to release it from
+ * depending on the file object.
+ * Return value:
+*/
+void dir_setFirstCluster(FileSystem *fs,FileLocation *loc,euint32 cluster_addr)
+{
+ euint8 *buf;
+
+ buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
+ (((FileRecord*)buf)+loc->Offset)->FirstClusterHigh=cluster_addr>>16;
+ (((FileRecord*)buf)+loc->Offset)->FirstClusterLow=cluster_addr&0xFFFF;
+ part_relSect(fs->part,buf);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void dir_setFileSize(FileSystem *fs, FileLocation *loc,euint32 numbytes)
+ * Description: This function changes the filesize recorded at loc->Sector
+ * to 'numbytes'.
+ * Return value: void
+*/
+void dir_setFileSize(FileSystem *fs, FileLocation *loc,euint32 numbytes)
+{
+ euint8 *buf;
+
+ buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
+ (((FileRecord*)buf)+loc->Offset)->FileSize=numbytes;
+ part_relSect(fs->part,buf);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint8 dir_updateDirectoryEntry(FileSystem *fs,FileRecord *entry,FileLocation *loc))
+ * This function changes the entire entity stores at loc to the data recorded
+ * in entry. This is for custom updates to the directoryentry.
+ * Return value: 0 on success, -1 on failure
+*/
+esint8 dir_updateDirectoryEntry(FileSystem *fs,FileRecord *entry,FileLocation *loc)
+{
+ euint8 *buf;
+
+ buf = part_getSect(fs->part,loc->Sector,IOM_MODE_READWRITE);
+ memCpy(entry,buf+(loc->Offset*sizeof(*entry)),sizeof(*entry));
+ part_relSect(fs->part,buf);
+ return(0);
+}
+
+/* ****************************************************************************
+ * euint32 dir_findFileinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc)
+ * This function searches for a given fatfilename in the buffer provided.
+ * It will iterate through the 16 direntry's in the buffer and searches
+ * for the fatfilename. If found, it will store the offset and attribute
+ * entry of the directoryrecord in the loc structure.
+ * If loc is 0, then it's members are not touched.
+ * Return value: This function returns 0 when it cannot find the file,
+ * if it can find the file it will return the first cluster number.
+*/
+euint32 dir_findFileinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc)
+{
+ FileRecord fileEntry;
+ euint8 c;
+
+ for(c=0; c<16; c++)
+ {
+ fileEntry = *(((FileRecord*)buf) + c);
+ /* Check if the entry is for short filenames */
+ if( !( (fileEntry.Attribute & 0x0F) == 0x0F ) )
+ {
+ if( strMatch((eint8*)fileEntry.FileName,fatname,11) == 0 )
+ {
+ /* The entry has been found, return the location in the dir */
+ if(loc)loc->Offset = c;
+ if(loc)loc->attrib = fileEntry.Attribute;
+ if((((euint32 )fileEntry.FirstClusterHigh)<<16)+ fileEntry.FirstClusterLow==0){
+ return(1); /* Lie about cluster, 0 means not found! */
+ }else{
+ return
+ (
+ (((euint32 )fileEntry.FirstClusterHigh)<<16)
+ + fileEntry.FirstClusterLow
+ );
+ }
+ }
+ }
+ }
+ return(0);
+}
+
+/* ****************************************************************************
+ * euint32 dir_findFreeEntryinBuf(euint8* buf, FileLocation *loc)
+ * This function searches for a free entry in a given sector 'buf'.
+ * It will put the offset into the loc->Offset field, given that loc is not 0.
+ * Return value: 1 when it found a free spot, 0 if it hasn't.
+*/
+euint32 dir_findFreeEntryinBuf(euint8* buf, FileLocation *loc)
+{
+ FileRecord fileEntry;
+ euint8 c;
+
+ for(c=0;c<16;c++){
+ fileEntry = *(((FileRecord*)buf) + c);
+ if( !( (fileEntry.Attribute & 0x0F) == 0x0F ) ){
+ if(fileEntry.FileName[0] == 0x00 ||
+ fileEntry.FileName[0] == 0xE5 ){
+ if(loc)loc->Offset=c;
+ return(1);
+ }
+ }
+ }
+ return(0);
+}
+
+/* ****************************************************************************
+ * euint32 dir_findinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc)
+ * Description: This function searches for a given fatfilename in a buffer.
+ * Return value: Returns 0 on not found, and the firstcluster when the name is found.
+*/
+euint32 dir_findinBuf(euint8 *buf, eint8 *fatname, FileLocation *loc, euint8 mode)
+{
+ switch(mode){
+ case DIRFIND_FILE:
+ return(dir_findFileinBuf(buf,fatname,loc));
+ //break;
+ case DIRFIND_FREE:
+ return(dir_findFreeEntryinBuf(buf,loc));
+ //break;
+ default:
+ return(0);
+ //break;
+ }
+ //return(0);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 dir_findinCluster(FileSystem *fs,euint32 cluster,eint8 *fatname, FileLocation *loc, euint8 mode)
+ * This function will search for an existing (fatname) or free directory entry
+ * in a full cluster.
+ * Return value: 0 on failure, firstcluster on finding file, and 1 on finding free spot.
+*/
+euint32 dir_findinCluster(FileSystem *fs,euint32 cluster,eint8 *fatname, FileLocation *loc, euint8 mode)
+{
+ euint8 c,*buf=0;
+ euint32 fclus;
+
+ for(c=0;cvolumeId.SectorsPerCluster;c++){
+ buf = part_getSect(fs->part,fs_clusterToSector(fs,cluster)+c,IOM_MODE_READONLY);
+ if((fclus=dir_findinBuf(buf,fatname,loc,mode))){
+ if(loc)loc->Sector=fs_clusterToSector(fs,cluster)+c;
+ part_relSect(fs->part,buf);
+ return(fclus);
+ }
+ part_relSect(fs->part,buf); /* Thanks Mike ;) */
+ }
+ return(0);
+}
+
+/* ****************************************************************************
+ * euint32 dir_findinDir(FileSystem *fs, eint8* fatname,euint32 firstcluster, FileLocation *loc, euint8 mode)
+ * This function will search for an existing (fatname) or free directory entry
+ * in a directory, following the clusterchains.
+ * Return value: 0 on failure, firstcluster on finding file, and 1 on finding free spot.
+*/
+euint32 dir_findinDir(FileSystem *fs, eint8* fatname,euint32 firstcluster, FileLocation *loc, euint8 mode)
+{
+ euint32 c=0,cluster;
+ ClusterChain Cache;
+
+ Cache.DiscCluster = Cache.FirstCluster = firstcluster;
+ Cache.LogicCluster = Cache.LastCluster = Cache.Linear = 0;
+
+ if(firstcluster <= 1){
+ return(dir_findinRootArea(fs,fatname,loc,mode));
+ }
+
+ while(!fat_LogicToDiscCluster(fs,&Cache,c++)){
+ if((cluster=dir_findinCluster(fs,Cache.DiscCluster,fatname,loc,mode))){
+ return(cluster);
+ }
+ }
+ return(0);
+}
+
+/* ****************************************************************************
+ * euint32 dir_findinDir(FileSystem *fs, eint8* fatname,euint32 firstcluster, FileLocation *loc, euint8 mode)
+ * This function will search for an existing (fatname) or free directory entry
+ * in the rootdirectory-area of a FAT12/FAT16 filesystem.
+ * Return value: 0 on failure, firstcluster on finding file, and 1 on finding free spot.
+*/
+euint32 dir_findinRootArea(FileSystem *fs,eint8* fatname, FileLocation *loc, euint8 mode)
+{
+ euint32 c,fclus;
+ euint8 *buf=0;
+
+ if((fs->type != FAT12) && (fs->type != FAT16))return(0);
+
+ for(c=fs->FirstSectorRootDir;c<(fs->FirstSectorRootDir+fs->volumeId.RootEntryCount/32);c++){
+ buf = part_getSect(fs->part,c,IOM_MODE_READONLY);
+ if((fclus=dir_findinBuf(buf,fatname,loc,mode))){
+ if(loc)loc->Sector=c;
+ part_relSect(fs->part,buf);
+ return(fclus);
+ }
+ part_relSect(fs->part,buf);
+ }
+ part_relSect(fs->part,buf);
+ return(0);
+}
+
+/* ****************************************************************************
+ * esint8 dir_getFatFileName(eint8* filename, eint8* fatfilename)
+ * This function will take a full directory path, and strip off all leading
+ * dirs and characters, leaving you with the MS-DOS notation of the actual filename.
+ * Return value: 1 on success, 0 on not being able to produca a filename
+*/
+esint8 dir_getFatFileName(eint8* filename, eint8* fatfilename)
+{
+ eint8 ffnamec[11],*next,nn=0;
+
+ memClr(ffnamec,11); memClr(fatfilename,11);
+ next = filename;
+
+ if(*filename=='/')next++;
+
+ while((next=file_normalToFatName(next,ffnamec))){
+ memCpy(ffnamec,fatfilename,11);
+ nn++;
+ }
+ if(nn)return(1);
+ return(0);
+}
+
+/* ****************************************************************************
+ * esint8 dir_addCluster(FileSystem *fs,euint32 firstCluster)
+ * This function extends a directory by 1 cluster + optional the number of
+ * clusters you want pre-allocated. It will also delete the contents of that
+ * cluster. (or clusters)
+ * Return value: 0 on success, -1 on fail
+*/
+esint8 dir_addCluster(FileSystem *fs,euint32 firstCluster)
+{
+ euint32 lastc,logicalc;
+ ClusterChain cache;
+
+ fs_initClusterChain(fs,&cache,firstCluster);
+ if(fat_allocClusterChain(fs,&cache,1)){
+ return(-1);
+ }
+ lastc = fs_getLastCluster(fs,&cache);
+ if(CLUSTER_PREALLOC_DIRECTORY){
+ if(fat_allocClusterChain(fs,&cache,CLUSTER_PREALLOC_DIRECTORY)){
+ return(-1);
+ }
+ logicalc = fat_DiscToLogicCluster(fs,firstCluster,lastc);
+ while(!fat_LogicToDiscCluster(fs,&cache,++logicalc)){
+ fs_clearCluster(fs,cache.DiscCluster);
+ }
+ }else{
+ fs_clearCluster(fs,lastc);
+ }
+ return(0);
+}
+
+
diff --git a/F107/Utilities/efsl/source/disc.c b/F107/Utilities/efsl/source/disc.c
new file mode 100644
index 0000000..b03c719
--- /dev/null
+++ b/F107/Utilities/efsl/source/disc.c
@@ -0,0 +1,68 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : disc.c *
+* Description : This file contains the functions regarding the whole disc *
+* such as loading the MBR and performing read/write tests. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+/*****************************************************************************/
+#include "disc.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void disc_initDisc(Disc *disc,hcInterface* source)
+ * Description: This initialises the disc by loading the MBR and setting the
+ * pointer to the hardware object.
+*/
+void disc_initDisc(Disc *disc,IOManager* ioman)
+{
+ disc->ioman=ioman;
+ disc_setError(disc,DISC_NOERROR);
+ disc_loadMBR(disc);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void disc_loadMBR(Disc *disc)
+ * Description: This functions copies the partitiontable to the partitions field.
+*/
+void disc_loadMBR(Disc *disc)
+{
+ euint8 x;
+ euint8 *buf;
+
+ buf=ioman_getSector(disc->ioman,LBA_ADDR_MBR,IOM_MODE_READONLY|IOM_MODE_EXP_REQ);
+ for(x=0;x<4;x++){
+ ex_getPartitionField(buf,&(disc->partitions[x]),PARTITION_TABLE_OFFSET+(x*SIZE_PARTITION_FIELD));
+ }
+ ioman_releaseSector(disc->ioman,buf);
+}
+/*****************************************************************************/
+
+
diff --git a/F107/Utilities/efsl/source/efs.c b/F107/Utilities/efsl/source/efs.c
new file mode 100644
index 0000000..be4b843
--- /dev/null
+++ b/F107/Utilities/efsl/source/efs.c
@@ -0,0 +1,68 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : efs.h *
+* Description : This should become the wrapper around efs. It will contain *
+* functions like efs_init etc. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+/*****************************************************************************/
+#include "efs.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint8 efs_init(EmbeddedFileSystem * efs,eint8* opts)
+ * Description: This function initialises all subelements of a filesystem.
+ * It sets the pointerchain and verifies each step.
+ * Return value: 0 on success and -1 on failure.
+*/
+esint8 efs_init(EmbeddedFileSystem * efs,eint8* opts)
+{
+ if(if_initInterface(&efs->myCard, opts)==0)
+ {
+ ioman_init(&efs->myIOman,&efs->myCard,0);
+ disc_initDisc(&efs->myDisc, &efs->myIOman);
+ part_initPartition(&efs->myPart, &efs->myDisc);
+ if(efs->myPart.activePartition==-1){
+ efs->myDisc.partitions[0].type=0x0B;
+ efs->myDisc.partitions[0].LBA_begin=0;
+ efs->myDisc.partitions[0].numSectors=efs->myCard.sectorCount;
+ /*efs->myPart.activePartition = 0;*/
+ /*efs->myPart.disc = &(efs->myDisc);*/
+ part_initPartition(&efs->myPart, &efs->myDisc);
+ }
+ /*part_initPartition(&efs->myPart, &efs->myDisc);*/
+ if(fs_initFs(&efs->myFs, &efs->myPart))
+ return(-2);
+ return(0);
+ }
+ return(-1);
+}
+/*****************************************************************************/
+
+
diff --git a/F107/Utilities/efsl/source/extract.c b/F107/Utilities/efsl/source/extract.c
new file mode 100644
index 0000000..912ab65
--- /dev/null
+++ b/F107/Utilities/efsl/source/extract.c
@@ -0,0 +1,158 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : extract.c *
+* Description : This file contains functions to copy structures that get *
+* corrupted when using direct memory copy *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+/*****************************************************************************/
+#include "extract.h"
+/*****************************************************************************/
+
+/*****************************************************************************/
+#ifdef BYTE_ALIGNMENT
+/*****************************************************************************/
+
+euint16 ex_getb16(euint8* buf,euint32 offset)
+{
+ return(ltb_end16(*((euint16*)(buf+offset))));
+}
+/*****************************************************************************/
+
+euint32 ex_getb32(euint8* buf,euint32 offset)
+{
+ return(ltb_end32(*((euint32*)(buf+offset))));
+}
+/*****************************************************************************/
+
+void ex_setb16(euint8* buf,euint32 offset,euint16 data)
+{
+ *((euint16*)(buf+offset)) = btl_end16(data);
+}
+/*****************************************************************************/
+
+void ex_setb32(euint8* buf,euint32 offset,euint32 data)
+{
+ *((euint32*)(buf+offset)) = btl_end32(data);
+}
+/*****************************************************************************/
+
+void ex_getPartitionField(euint8* buf,PartitionField* pf, euint32 offset)
+{
+ *pf=*((PartitionField*)(buf+offset));
+}
+/*****************************************************************************/
+
+void ex_setPartitionField(euint8* buf,PartitionField* pf, euint32 offset)
+{
+
+}
+/*****************************************************************************/
+
+
+
+
+/*****************************************************************************/
+/*****************************************************************************/
+#else
+/*****************************************************************************/
+/*****************************************************************************/
+
+
+
+euint16 ex_getb16(euint8* buf,euint32 offset)
+{
+ return(ltb_end16(((*(buf+offset+1))<<8) + ((*(buf+offset+0))<<0)));
+}
+/*****************************************************************************/
+
+euint32 ex_getb32(euint8* buf,euint32 offset)
+{
+ return(ltb_end32(((euint32)buf[offset+3]<<24)+
+ ((euint32)buf[offset+2]<<16)+
+ ((euint32)buf[offset+1]<<8)+
+ ((euint32)buf[offset+0]<<0)));
+}
+/*****************************************************************************/
+
+void ex_setb16(euint8* buf,euint32 offset,euint16 data)
+{
+#ifdef BIG_ENDIAN
+ *(buf+offset+1) = data>>0;
+ *(buf+offset+0) = data>>8;
+#else
+ *(buf+offset+0) = data>>0;
+ *(buf+offset+1) = data>>8;
+#endif
+}
+/*****************************************************************************/
+
+void ex_setb32(euint8* buf,euint32 offset,euint32 data)
+{
+#ifdef BIG_ENDIAN
+ *(buf+offset+3) = data>> 0;
+ *(buf+offset+2) = data>> 8;
+ *(buf+offset+1) = data>>16;
+ *(buf+offset+0) = data>>24;
+#else
+ *(buf+offset+0) = data>> 0;
+ *(buf+offset+1) = data>> 8;
+ *(buf+offset+2) = data>>16;
+ *(buf+offset+3) = data>>24;
+#endif
+}
+/*****************************************************************************/
+
+void ex_getPartitionField(euint8* buf,PartitionField* pf, euint32 offset)
+{
+ pf->bootFlag = *(buf + offset);
+ pf->CHS_begin[0] = *(buf + offset + 1);
+ pf->CHS_begin[1] = *(buf + offset + 2);
+ pf->CHS_begin[2] = *(buf + offset + 3);
+ pf->type = *(buf + offset + 4);
+ pf->CHS_end[0] = *(buf + offset + 5);
+ pf->CHS_end[1] = *(buf + offset + 6);
+ pf->CHS_end[2] = *(buf + offset + 7);
+ pf->LBA_begin = ex_getb32(buf + offset,8);
+ pf->numSectors = ex_getb32(buf + offset,12);
+}
+/*****************************************************************************/
+
+void ex_setPartitionField(euint8* buf,PartitionField* pf, euint32 offset)
+{
+
+}
+/*****************************************************************************/
+
+
+
+/*****************************************************************************/
+#endif
+/*****************************************************************************/
+
diff --git a/F107/Utilities/efsl/source/fat.c b/F107/Utilities/efsl/source/fat.c
new file mode 100644
index 0000000..f7e754e
--- /dev/null
+++ b/F107/Utilities/efsl/source/fat.c
@@ -0,0 +1,567 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : fat.c *
+* Description : This file contains all the functions dealing with the FAT *
+* in a Microsoft FAT filesystem. It belongs under fs.c *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/*****************************************************************************/
+#include "fs.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * unsigned long fat_getSectorAddressFatEntry(FileSystem *fs,unsigned long cluster_addr)
+ * Description: Returns the sectornumber that holds the fat entry for cluster cluster_addr.
+ * This works for all FAT types.
+ * Return value: Sectornumber, or 0. Warning, no boundary check.
+*/
+euint32 fat_getSectorAddressFatEntry(FileSystem *fs,euint32 cluster_addr)
+{
+ euint32 base = fs->volumeId.ReservedSectorCount,res;
+
+ switch(fs->type){
+ case FAT12:
+ res=(cluster_addr*3/1024);
+ if(res>=fs->FatSectorCount){
+ return(0);
+ }else{
+ return(base+res);
+ }
+ //break;
+ case FAT16:
+ res=cluster_addr/256;
+ if(res>=fs->FatSectorCount){
+ return(0);
+ }else{
+ return(base+res);
+ }
+ //break;
+ case FAT32:
+ res=cluster_addr/128;
+ if(res>=fs->FatSectorCount){
+ return(0);
+ }else{
+ return(base+res);
+ }
+ //break;
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+
+/* ****************************************************************************
+ * unsigned long fat_getNextClusterAddress(FileSystem *fs,unsigned long cluster_addr
+ * Description: This function loads the sector of the fat which contains the entry
+ * for cluster_addr. It then fetches and (if required) calculates it's value.
+ * This value is the EoC marker -or- the number of the next cluster in the chain.
+ * Return value: Clusternumber or EoC
+*/
+euint32 fat_getNextClusterAddress(FileSystem *fs,euint32 cluster_addr,euint16 *linear)
+{
+ euint8 *buf;
+ euint8 hb,lb;
+ euint16 offset;
+ euint32 sector;
+ euint32 nextcluster=0;
+
+ sector=fat_getSectorAddressFatEntry(fs,cluster_addr);
+ if( (fs->FatSectorCount <= (sector-fs->volumeId.ReservedSectorCount)) || sector==0 )
+ {
+ return(0);
+ }
+
+ buf=part_getSect(fs->part,sector,IOM_MODE_READONLY);
+
+ switch(fs->type)
+ {
+ case FAT12:
+ offset = ((cluster_addr%1024)*3/2)%512;
+ hb = buf[offset];
+ if(offset == 511){
+ part_relSect(fs->part,buf);
+ buf=part_getSect(fs->part,sector+1,IOM_MODE_READONLY);
+ lb = buf[0];
+ }else{
+ lb = buf[offset + 1];
+ }
+ if(cluster_addr%2==0){
+ nextcluster = ( ((lb&0x0F)<<8) + (hb) );
+ }else{
+ nextcluster = ( (lb<<4) + (hb>>4) );
+ }
+ break;
+ case FAT16:
+ offset=cluster_addr%256;
+ nextcluster = *((euint16 *)buf + offset);
+ break;
+ case FAT32:
+ offset=cluster_addr%128;
+ nextcluster = *((euint32 *)buf + offset);
+ break;
+ }
+
+ part_relSect(fs->part,buf);
+
+ return(nextcluster);
+}
+/*****************************************************************************/
+
+
+/* ****************************************************************************
+ * void fat_setNextClusterAddress(FileSystem *fs,unsigned long cluster_addr,unsigned long next_cluster_addr)
+ * Description: This function makes an entry in the fattable for cluster_addr. The value it puts there
+ * is next_cluster_addr.
+*/
+void fat_setNextClusterAddress(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr)
+{
+ euint8 *buf,*buf2;
+ euint16 offset;
+ euint32 sector;
+
+ sector=fat_getSectorAddressFatEntry(fs,cluster_addr);
+
+ if(( fs->FatSectorCount <= (sector - fs->volumeId.ReservedSectorCount )||(sector==0))){
+ //DBG((TXT("HARDERROR:::fat_getNextClusterAddress READ PAST FAT BOUNDARY\n")));
+ return;
+ }
+
+ buf=part_getSect(fs->part,sector,IOM_MODE_READWRITE);
+
+ switch(fs->type){
+ case FAT12:
+ offset = ((cluster_addr%1024)*3/2)%512;
+ if(offset == 511){
+ if(cluster_addr%2==0){
+ buf[offset]=next_cluster_addr&0xFF;
+ }else{
+ buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
+ }
+ buf2=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cluster_addr)+1,IOM_MODE_READWRITE);
+ if(cluster_addr%2==0){
+ buf2[0]=(buf2[0]&0xF0)+((next_cluster_addr>>8)&0xF);
+ }else{
+ buf2[0]=(next_cluster_addr>>4)&0xFF;
+ }
+ part_relSect(fs->part,buf2);
+ }else{
+ if(cluster_addr%2==0){
+ buf[offset]=next_cluster_addr&0xFF;
+ buf[offset+1]=(buf[offset+1]&0xF0)+((next_cluster_addr>>8)&0xF);
+ }else{
+ buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
+ buf[offset+1]=(next_cluster_addr>>4)&0xFF;
+ }
+ }
+ part_relSect(fs->part,buf);
+ break;
+ case FAT16:
+ offset=cluster_addr%256;
+ *((euint16*)buf+offset)=next_cluster_addr;
+ part_relSect(fs->part,buf);
+ break;
+ case FAT32:
+ offset=cluster_addr%128;
+ *((euint32*)buf+offset)=next_cluster_addr;
+ part_relSect(fs->part,buf);
+ break;
+ }
+
+}
+/*****************************************************************************/
+
+
+/* ****************************************************************************
+ * short fat_isEocMarker(FileSystem *fs,unsigned long fat_entry)
+ * Description: Checks if a certain value is the EoC marker for the filesystem
+ * noted in fs->type.
+ * Return value: Returns 0 when it is the EoC marker, and 1 otherwise.
+*/
+eint16 fat_isEocMarker(FileSystem *fs,euint32 fat_entry)
+{
+ switch(fs->type){
+ case FAT12:
+ if(fat_entry<0xFF8){
+ return(0);
+ }
+ break;
+ case FAT16:
+ if(fat_entry<0xFFF8){
+ return(0);
+ }
+ break;
+ case FAT32:
+ if((fat_entry&0x0FFFFFFF)<0xFFFFFF8){
+ return(0);
+ }
+ break;
+ }
+ return(1);
+}
+/*****************************************************************************/
+
+
+/* ****************************************************************************
+ * unsigned long fat_giveEocMarker(FileSystem *fs)
+ * Description: Returns an EoC markernumber valid for the filesystem noted in
+ * fs->type.
+ * Note, for FAT32, the upper 4 bits are set to zero, although they should be un
+ * touched according to MicroSoft specifications. I didn't care.
+ * Return value: The EoC marker cast to an ulong.
+*/
+euint32 fat_giveEocMarker(FileSystem *fs)
+{
+ switch(fs->type)
+ {
+ case FAT12:
+ return(0xFFF);
+ //break;
+ case FAT16:
+ return(0xFFFF);
+ //break;
+ case FAT32:
+ return(0x0FFFFFFF);
+ //break;
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 fat_getNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr, euint8* buf)
+ * Description: This function retrieves the contents of a FAT field. It does not fetch
+ * it's own buffer, it is given as a parameter. (ioman makes this function rather obsolete)
+ * Only in the case of a FAT12 crosssector data entry a sector is retrieved here.
+ * Return value: The value of the clusterfield is returned.
+*/
+euint32 fat_getNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr, euint8* buf)
+{
+ euint8 *buf2; /* For FAT12 fallover only */
+ euint8 hb,lb;
+ euint16 offset;
+ euint32 nextcluster=0;
+
+ switch(fs->type)
+ {
+ case FAT12:
+ offset = ((cluster_addr%1024)*3/2)%512;
+ hb = buf[offset];
+ if(offset == 511){
+ buf2=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cluster_addr)+1,IOM_MODE_READONLY);
+ lb = buf2[0];
+ part_relSect(fs->part,buf2);
+ }else{
+ lb = buf[offset + 1];
+ }
+ if(cluster_addr%2==0){
+ nextcluster = ( ((lb&0x0F)<<8) + (hb) );
+ }else{
+ nextcluster = ( (lb<<4) + (hb>>4) );
+ }
+ break;
+ case FAT16:
+ offset=cluster_addr%256;
+ nextcluster = *((euint16*)buf + offset);
+ break;
+ case FAT32:
+ offset=cluster_addr%128;
+ nextcluster = *((euint32*)buf + offset);
+ break;
+ }
+ return(nextcluster);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void fat_setNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr,euint8* buf)
+ * Description: This function fills in a fat entry. The entry is cluster_addr and the
+ * data entered is next_cluster_addr. This function is also given a *buf, so it does
+ * not write the data itself, except in the case of FAT 12 cross sector data, where
+ * the second sector is handled by this function.
+ * Return value:
+*/
+void fat_setNextClusterAddressWBuf(FileSystem *fs,euint32 cluster_addr,euint32 next_cluster_addr,euint8* buf)
+{
+ euint16 offset;
+ euint8 *buf2;
+
+ switch(fs->type)
+ {
+ case FAT12:
+ offset = ((cluster_addr%1024)*3/2)%512;
+ if(offset == 511){
+ if(cluster_addr%2==0){
+ buf[offset]=next_cluster_addr&0xFF;
+ }else{
+ buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
+ }
+ buf2=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cluster_addr)+1,IOM_MODE_READWRITE);
+ if(cluster_addr%2==0){
+ buf2[0]=(buf2[0]&0xF0)+((next_cluster_addr>>8)&0xF);
+ }else{
+ buf2[0]=(next_cluster_addr>>4)&0xFF;
+ }
+ part_relSect(fs->part,buf2);
+ }else{
+ if(cluster_addr%2==0){
+ buf[offset]=next_cluster_addr&0xFF;
+ buf[offset+1]=(buf[offset+1]&0xF0)+((next_cluster_addr>>8)&0xF);
+ }else{
+ buf[offset]=(buf[offset]&0xF)+((next_cluster_addr<<4)&0xF0);
+ buf[offset+1]=(next_cluster_addr>>4)&0xFF;
+ }
+ }
+ break;
+ case FAT16:
+ offset=cluster_addr%256;
+ *((euint16*)buf+offset)=next_cluster_addr;
+ break;
+ case FAT32:
+ offset=cluster_addr%128;
+ *((euint32*)buf+offset)=next_cluster_addr;
+ break;
+ }
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint16 fat_getNextClusterChain(FileSystem *fs, ClusterChain *Cache)
+ * Description: This function is to advance the clusterchain of a Cache.
+ * First, the function verifies if the Cache is valid. It could correct it if it
+ * is not, but this is not done at the time. If the cachen is valid, the next step is
+ * to see what the next cluster is, if this is the End of Clustermark, the cache is
+ * updated to know the lastcluster but will remain untouched otherwise. -1 is returned.
+ * If there are more clusters the function scans the rest of the chain until the next
+ * cluster is no longer lineair, or until it has run out of fat data (only 1 sector) is
+ * examined, namely the one fetched to check for EoC.
+ * With lineair is meant that logical cluster n+1 should be 1 more than logical cluster n
+ * at the disc level.
+ * Return value: 0 on success, or -1 when EoC.
+*/
+esint16 fat_getNextClusterChain(FileSystem *fs, ClusterChain *Cache)
+{
+ euint32 sect,lr,nlr,dc;
+ esint16 lin=0;
+ euint8 *buf;
+
+ if(Cache->DiscCluster==0)
+ {
+ return(-1);
+ }
+
+ sect=fat_getSectorAddressFatEntry(fs,Cache->DiscCluster);
+ buf=part_getSect(fs->part,sect,IOM_MODE_READONLY);
+ dc=fat_getNextClusterAddressWBuf(fs,Cache->DiscCluster,buf);
+ if(fat_isEocMarker(fs,dc))
+ {
+ Cache->LastCluster=Cache->DiscCluster;
+ part_relSect(fs->part,buf);
+ return(-1);
+ }
+
+ Cache->DiscCluster=dc;
+ Cache->LogicCluster++;
+
+ lr=Cache->DiscCluster-1;
+ nlr=lr+1;
+
+ while(nlr-1==lr && fat_getSectorAddressFatEntry(fs,nlr)==sect)
+ {
+ lr=nlr;
+ nlr=fat_getNextClusterAddressWBuf(fs,lr,buf);
+ lin++;
+ }
+
+ Cache->Linear=lin-1<0?0:lin-1;
+
+ part_relSect(fs->part,buf);
+ return(0);
+}
+/*****************************************************************************/
+
+
+/* ****************************************************************************
+ * esint16 fat_LogicToDiscCluster(FileSystem *fs, ClusterChain *Cache,euint32 logiccluster)
+ * Description: This function is used to follow clusterchains. When called it will convert
+ * a logical cluster, to a disc cluster, using a Cache object. All it does is call
+ * getNextClusterChain in the proper manner, and rewind clusterchains if required.
+ * It is NOT recommended to go backwards in clusterchains, since this will require
+ * scanning the entire chain every time.
+ * Return value: 0 on success and -1 on failure (meaning out of bounds).
+*/
+esint16 fat_LogicToDiscCluster(FileSystem *fs, ClusterChain *Cache,euint32 logiccluster)
+{
+ if(logicclusterLogicCluster || Cache->DiscCluster==0){
+ Cache->LogicCluster=0;
+ Cache->DiscCluster=Cache->FirstCluster;
+ Cache->Linear=0;
+ }
+
+ if(Cache->LogicCluster==logiccluster){
+ return(0);
+ }
+
+ while(Cache->LogicCluster!=logiccluster)
+ {
+ if(Cache->Linear!=0)
+ {
+ Cache->Linear--;
+ Cache->LogicCluster++;
+ Cache->DiscCluster++;
+ }
+ else
+ {
+ if((fat_getNextClusterChain(fs,Cache))!=0){
+ return(-1);
+ }
+ }
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * eint16 fat_allocClusterChain(FileSystem *fs,ClusterChain *Cache,euint32 num_clusters)
+ * Description: This function extends a clusterchain by num_clusters. It returns the
+ * number of clusters it *failed* to allocate.
+ * Return value: 0 on success, all other values are the number of clusters it could
+ * not allocate.
+*/
+eint16 fat_allocClusterChain(FileSystem *fs,ClusterChain *Cache,euint32 num_clusters)
+{
+ euint32 cc,ncl=num_clusters,lc;
+ euint8 *bufa=0,*bufb=0;
+ euint8 overflow=0;
+
+ if(Cache->FirstCluster<=1)return(num_clusters);
+
+ lc=fs_getLastCluster(fs,Cache);
+ cc=lc;
+
+ while(ncl > 0){
+ cc++;
+ if(cc>=fs->DataClusterCount+1){
+ if(overflow){
+ bufa=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,lc),IOM_MODE_READWRITE);
+ fat_setNextClusterAddressWBuf(fs,lc,fat_giveEocMarker(fs),bufa);
+ Cache->LastCluster=lc;
+ part_relSect(fs->part,bufa);
+ fs->FreeClusterCount-=num_clusters-ncl;
+ return(num_clusters-ncl);
+ }
+ cc=2;
+ overflow++;
+ }
+ bufa=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,cc),IOM_MODE_READONLY);
+ if(fat_getNextClusterAddressWBuf(fs,cc,bufa)==0){
+ bufb=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,lc),IOM_MODE_READWRITE);
+ fat_setNextClusterAddressWBuf(fs,lc,cc,bufb);
+ part_relSect(fs->part,bufb);
+ ncl--;
+ lc=cc;
+ }
+ part_relSect(fs->part,bufa);
+ if(ncl==0){
+ bufa=part_getSect(fs->part,fat_getSectorAddressFatEntry(fs,lc),IOM_MODE_READWRITE);
+ fat_setNextClusterAddressWBuf(fs,lc,fat_giveEocMarker(fs),bufa);
+ Cache->LastCluster=lc;
+ part_relSect(fs->part,bufa);
+ }
+ }
+ if(Cache->ClusterCount)Cache->ClusterCount+=num_clusters;
+ return(0);
+}
+
+/* ****************************************************************************
+ * eint16 fat_unlinkClusterChain(FileSystem *fs,ClusterChain *Cache)
+ * Description: This function removes a clusterchain. Starting at FirstCluster
+ * it follows the chain until the end, resetting all values to 0.
+ * Return value: 0 on success.
+*/
+eint16 fat_unlinkClusterChain(FileSystem *fs,ClusterChain *Cache)
+{
+ euint32 c,tbd=0;
+
+ Cache->LogicCluster=0;
+ Cache->DiscCluster=Cache->FirstCluster;
+
+ c=0;
+
+ while(!fat_LogicToDiscCluster(fs,Cache,c++)){
+ if(tbd!=0){
+ fat_setNextClusterAddress(fs,tbd,0);
+ }
+ tbd=Cache->DiscCluster;
+ }
+ fat_setNextClusterAddress(fs,Cache->DiscCluster,0);
+ fs->FreeClusterCount+=c;
+ return(0);
+}
+
+euint32 fat_countClustersInChain(FileSystem *fs,euint32 firstcluster)
+{
+ ClusterChain cache;
+ euint32 c=0;
+
+ if(firstcluster<=1)return(0);
+
+ cache.DiscCluster = cache.LogicCluster = cache.LastCluster = cache.Linear = 0;
+ cache.FirstCluster = firstcluster;
+
+ while(!(fat_LogicToDiscCluster(fs,&cache,c++)));
+
+ return(c-1);
+}
+
+euint32 fat_DiscToLogicCluster(FileSystem *fs,euint32 firstcluster,euint32 disccluster)
+{
+ ClusterChain cache;
+ euint32 c=0,r=0;
+
+ cache.DiscCluster = cache.LogicCluster = cache.LastCluster = cache.Linear = 0;
+ cache.FirstCluster = firstcluster;
+
+ while(!(fat_LogicToDiscCluster(fs,&cache,c++)) && !r){
+ if(cache.DiscCluster == disccluster){
+ r = cache.LogicCluster;
+ }
+ }
+ return(r);
+}
+
+euint32 fat_countFreeClusters(FileSystem *fs)
+{
+ euint32 c=2,fc=0;
+
+ while(c<=fs->DataClusterCount+1){
+ if(fat_getNextClusterAddress(fs,c,0)==0)fc++;
+ c++;
+ }
+ return(fc);
+}
diff --git a/F107/Utilities/efsl/source/file.c b/F107/Utilities/efsl/source/file.c
new file mode 100644
index 0000000..3f17fa5
--- /dev/null
+++ b/F107/Utilities/efsl/source/file.c
@@ -0,0 +1,504 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : file.c *
+* Description : This file contains functions dealing with files such as: *
+* fopen, fread and fwrite. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/*****************************************************************************/
+#include "file.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 file_fread(File *file,euint32 offset, euint32 size,euint8 *buf)
+ * Description: This function reads 'size' bytes from 'file' starting at
+ * 'offset' and puts the result in '*buf'.
+ * Return value: amount of bytes actually read (can differ from the given
+ * size when the file was smaller
+*/
+euint32 file_fread(File *file,euint32 offset, euint32 size,euint8 *buf)
+{
+ euint32 bytes_read=0,size_left=size,coffset=offset;
+ euint32 cclus,csec,cbyte;
+ euint32 rclus,rsec;
+ euint32 btr;
+ euint8 *tbuf;
+
+ if(!file_getAttr(file,FILE_STATUS_OPEN))return(0);
+
+ if(offset>=file->FileSize)
+ size_left=0; /* Offset check */
+
+ if( (offset+size > file->FileSize) && size_left!=0)
+ size_left=file->FileSize-offset;
+
+ while(size_left>0){
+
+ cclus = coffset/(512*file->fs->volumeId.SectorsPerCluster);
+ csec = (coffset/(512))%file->fs->volumeId.SectorsPerCluster;
+ cbyte = coffset%512;
+
+ if(cbyte!=0 || size_left<512){
+ btr = 512-(coffset%512)>=size_left?size_left:512-(coffset%512);
+ }else{
+ btr = 512;
+ }
+
+ if((fat_LogicToDiscCluster(file->fs,&(file->Cache),cclus))!=0){
+ return(0);
+ }
+ rclus=file->Cache.DiscCluster;
+ rsec=fs_clusterToSector(file->fs,rclus);
+
+
+ if(btr==512){
+ /*part_readBuf(file->fs->part,rsec+csec,buf+bytes_read);*/
+ part_directSectorRead(file->fs->part,rsec+csec,buf+bytes_read);
+ }else{
+ /*part_readBuf(file->fs->part,rsec+csec,tbuf);*/
+ tbuf = part_getSect(file->fs->part,rsec+csec,IOM_MODE_READONLY);
+ memCpy(tbuf+(coffset%512),buf+bytes_read,btr);
+ part_relSect(file->fs->part,tbuf);
+ }
+
+ coffset+=btr;
+ bytes_read+=btr;
+ size_left-=btr;
+ }
+
+ return(bytes_read);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 file_read (File *file,euint32 size,euint8 *buf)
+ * Description: This function reads from a file, taking the FilePtr into account
+ * and advancing it according to the freadcall.
+ * Return value: Value obtained from fread
+*/
+euint32 file_read(File *file,euint32 size,euint8 *buf)
+{
+ euint32 r;
+
+ r=file_fread(file,file->FilePtr,size,buf);
+ file->FilePtr+=r;
+ return(r);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 file_write(File *file, euint32 size,euint8 *buf)
+ * Description: This function writes to a file, taking FilePtr into account
+ * and advancing it according to the fwritecall.
+ * Return value: Value obtained from fread
+*/
+euint32 file_write(File *file, euint32 size,euint8 *buf)
+{
+ euint32 r;
+
+ r=file_fwrite(file,file->FilePtr,size,buf);
+ file->FilePtr+=r;
+ return(r);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint16 file_setpos(File *file,euint32 pos)
+ * Description: This function does a sanity check on the requested position
+ * and changes the fileptr accordingly.
+ * Return value: 0 on success and -1 on failure.
+*/
+esint16 file_setpos(File *file,euint32 pos)
+{
+ if(pos<=file->FileSize){
+ file->FilePtr=pos;
+ return(0);
+ }
+ return(-1);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 file_fwrite(File* file,euint32 offset,euint32 size,euint8* buf)
+ * Description: This function writes to a file, at offset 'offset' and size 'size'.
+ * It also updates the FileSize in the object, and discstructure.
+ * Return value: Bytes actually written.
+*/
+euint32 file_fwrite(File* file,euint32 offset,euint32 size,euint8* buf)
+{
+ euint32 need_cluster;
+ euint32 cclus,csec,cbyte;
+ euint32 size_left=size,bytes_written=0;
+ euint32 rclus,rsec;
+ euint32 coffset=offset;
+ euint16 btr;
+ euint8 *tbuf;
+
+ if(!file_getAttr(file,FILE_STATUS_OPEN) || !file_getAttr(file,FILE_STATUS_WRITE))return(0);
+
+ if(offset>file->FileSize){
+ offset=file->FileSize;
+ }
+
+ need_cluster = file_requiredCluster(file,offset,size);
+
+ if(need_cluster){
+ if(fat_allocClusterChain(file->fs,&(file->Cache),need_cluster+CLUSTER_PREALLOC_FILE)!=0){
+ return(0);
+ }
+ }
+
+ while(size_left>0){
+
+ cclus = coffset/(512*file->fs->volumeId.SectorsPerCluster);
+ csec = (coffset/(512))%file->fs->volumeId.SectorsPerCluster;
+ cbyte = coffset%512;
+
+ if(cbyte!=0 || size_left<512){
+ btr = 512-(coffset%512)>=size_left?size_left:512-(coffset%512);
+ }else{
+ btr = 512;
+ }
+
+ if((fat_LogicToDiscCluster(file->fs,&(file->Cache),cclus))!=0){
+ file->FileSize+=bytes_written;
+ dir_setFileSize(file->fs,&(file->Location),file->FileSize);
+ return(bytes_written);
+ }
+ rclus=file->Cache.DiscCluster;
+ rsec=fs_clusterToSector(file->fs,rclus);
+
+ if(btr==512){
+ /*part_writeBuf(file->fs->part,rsec+csec,buf+bytes_written);*/
+ part_directSectorWrite(file->fs->part,rsec+csec,buf+bytes_written);
+ }else{
+ /*part_readBuf(file->fs->part,rsec+csec,tbuf);*/
+ tbuf = part_getSect(file->fs->part,rsec+csec,IOM_MODE_READWRITE);
+ memCpy(buf+bytes_written,tbuf+(coffset%512),btr);
+ /*part_writeBuf(file->fs->part,rsec+csec,tbuf);*/
+ part_relSect(file->fs->part,tbuf);
+ }
+
+ coffset+=btr;
+ bytes_written+=btr;
+ size_left-=btr;
+ }
+
+ if(bytes_written>file->FileSize-offset){
+ file->FileSize+=bytes_written-(file->FileSize-offset);
+ }
+
+ return(bytes_written);
+}
+
+/* ***************************************************************************\
+ * signed eint8 file_fopen(FileSystem *fs,File* file,eint8* filename)
+ * Description: This functions opens a file.
+ * This function is about to be redesigned. No Docs.
+ * Return value:
+*/
+esint8 file_fopen(File* file,FileSystem *fs,eint8* filename,eint8 mode)
+{
+ FileLocation loc;
+ FileRecord wtmp;
+ eint8 fatfilename[11];
+ euint32 sec;
+
+ dir_getFatFileName(filename,fatfilename);
+
+ switch(mode)
+ {
+ case MODE_READ:
+ if(fs_findFile(fs,filename,&loc,0)==1)
+ {
+ dir_getFileStructure(fs,&(file->DirEntry), &loc);
+ file_initFile(file,fs,&loc);
+ file_setAttr(file,FILE_STATUS_OPEN,1);
+ file_setAttr(file,FILE_STATUS_WRITE,0);
+ return(0);
+ }
+ return(-1);
+ //break;
+ case MODE_WRITE:
+ if(fs_findFile(fs,filename,&loc,&sec)) /* File may NOT exist, but parent HAS to exist */
+ {
+ return(-2);
+ }
+ if(sec==0){ /* Parent dir does not exist */
+ return(-4);
+ }
+ if(fs_findFreeFile(fs,filename,&loc,0))
+ {
+ dir_createDefaultEntry(fs,&wtmp,fatfilename);
+ dir_createDirectoryEntry(fs,&wtmp,&loc);
+ memCpy(&wtmp,&(file->DirEntry),sizeof(wtmp));
+ file_initFile(file,fs,&loc);
+ sec=fs_getNextFreeCluster(file->fs,fs_giveFreeClusterHint(file->fs));
+ dir_setFirstCluster(file->fs,&(file->Location),sec);
+ fs_setFirstClusterInDirEntry(&(file->DirEntry),sec);
+ fs_initClusterChain(fs,&(file->Cache),sec);
+ fat_setNextClusterAddress(fs,sec,fat_giveEocMarker(fs));
+ file_setAttr(file,FILE_STATUS_OPEN,1);
+ file_setAttr(file,FILE_STATUS_WRITE,1);
+ return(0);
+ }
+ else
+ {
+ return(-3);
+ }
+ //break;
+ case MODE_APPEND:
+ if(fs_findFile(fs,filename,&loc,0)==1) /* File exists */
+ {
+ dir_getFileStructure(fs,&(file->DirEntry), &loc);
+ file_initFile(file,fs,&loc);
+ if(file->Cache.FirstCluster==0){
+ sec=fs_getNextFreeCluster(file->fs,fs_giveFreeClusterHint(file->fs));
+ dir_setFirstCluster(file->fs,&(file->Location),sec);
+ fs_setFirstClusterInDirEntry(&(file->DirEntry),sec);
+ fat_setNextClusterAddress(fs,sec,fat_giveEocMarker(fs));
+ file_initFile(file,fs,&loc);
+ }
+ file_setpos(file,file->FileSize);
+ file_setAttr(file,FILE_STATUS_OPEN,1);
+ file_setAttr(file,FILE_STATUS_WRITE,1);
+ }
+ else /* File does not excist */
+ {
+ if(fs_findFreeFile(fs,filename,&loc,0))
+ {
+ dir_createDefaultEntry(fs,&wtmp,fatfilename);
+ dir_createDirectoryEntry(fs,&wtmp,&loc);
+ memCpy(&wtmp,&(file->DirEntry),sizeof(wtmp));
+ file_initFile(file,fs,&loc);
+ sec=fs_getNextFreeCluster(file->fs,fs_giveFreeClusterHint(file->fs));
+ dir_setFirstCluster(file->fs,&(file->Location),sec);
+ fs_setFirstClusterInDirEntry(&(file->DirEntry),sec);
+ fs_initClusterChain(fs,&(file->Cache),sec);
+ fat_setNextClusterAddress(fs,sec,fat_giveEocMarker(fs));
+ file_setAttr(file,FILE_STATUS_OPEN,1);
+ file_setAttr(file,FILE_STATUS_WRITE,1);
+ }
+ else
+ {
+ return(-3);
+ }
+ }
+ return(0);
+ //break;
+ default:
+ return(-4);
+ // break;
+ }
+ //return(-5);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint8 file_fclose(File *file)
+ * Description: This function closes a file, by clearing the object.
+ * Return value: 0 on success.
+*/
+esint8 file_fclose(File *file)
+{
+ if(fs_hasTimeSupport()){
+ file->DirEntry.AccessDate = time_getDate();
+ if(file_getAttr(file,FILE_STATUS_WRITE)){
+ file->DirEntry.FileSize = file->FileSize;
+ file->DirEntry.WriteDate = file->DirEntry.AccessDate;
+ file->DirEntry.WriteTime = time_getTime();
+ }
+ dir_updateDirectoryEntry(file->fs,&(file->DirEntry),&(file->Location));
+ }else{
+ if(file_getAttr(file,FILE_STATUS_WRITE)){
+ dir_setFileSize(file->fs,&(file->Location),file->FileSize);
+ }
+ }
+
+ memClr(file,sizeof(*file));
+ file_setAttr(file,FILE_STATUS_OPEN,0);
+ file_setAttr(file,FILE_STATUS_WRITE,0);
+ return(0);
+}
+
+
+/* ****************************************************************************
+ * void file_initFile(File *file, FileSystem *fs, FileLocation *loc)
+ * Description: This function initialises a new file object, by filling in
+ * the fs pointer, filesize (note, that DirEntry must already be filled in)
+ * and known cache parameters.
+ * Return value: void
+*/
+void file_initFile(File *file, FileSystem *fs, FileLocation *loc)
+{
+ file->fs=fs;
+ file->FileSize=file->DirEntry.FileSize;
+ file->FilePtr=0;
+ file->Location.Sector=loc->Sector;
+ file->Location.Offset=loc->Offset;
+ file->Cache.Linear=0;
+ file->Cache.FirstCluster=(((euint32)file->DirEntry.FirstClusterHigh)<<16)+
+ file->DirEntry.FirstClusterLow;
+ file->Cache.LastCluster=0;
+ file->Cache.LogicCluster=0;
+ file->Cache.DiscCluster=file->Cache.FirstCluster;
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint8* file_normalToFatName(eint8* filename,eint8* fatfilename)
+ * Description: This function converts a human readable filename (limited to
+ * 8.3 eint8 character) to a valid FAT (not VFAT) filename. Invalid characters are
+ * changed to capital X and only the first 11 characters are used.
+ * Furthermore all letters are capitalised.
+ * Return value: pointer after the filename
+*/
+eint8* file_normalToFatName(eint8* filename,eint8* fatfilename)
+{
+ euint8 c,dot=0,vc=0;
+
+ for(c=0;c<11;c++)fatfilename[c]=' ';
+
+ c=0;
+
+ if(*filename == '.'){
+ fatfilename[0]='.';
+ vc++;
+ if(*(filename+1) == '.'){
+ fatfilename[1]='.';
+ filename+=2;
+ }else{
+ filename++;
+ }
+ }else{
+ while(*filename != '\0' && *filename != ' ' && *filename != '/'){
+ if(*filename=='.' && !dot){
+ dot=1;
+ c=8;
+ }else{
+ if(dot){
+ if(c<=10){
+ fatfilename[c]=file_validateChar(*filename);
+ c++;
+ }
+ }else{
+ if(c<=7){
+ fatfilename[c]=file_validateChar(*filename);
+ c++; vc++;
+ }
+ }
+ }
+ filename++;
+ }
+ }
+
+ if(vc>0){
+ if(*filename=='\0'){
+ return(filename);
+ }else{
+ return(filename+1);
+ }
+ }else{
+ return(0);
+ }
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ *
+ * Description: This function takes the character c, and if it is not a *
+ * valid FAT Filename character returns X. If it is a lowercase letter the *
+ * uppercase equivalent is returned. The remaining characters are returned *
+ * as they are.
+ * Return value: The validated char
+*/
+euint8 file_validateChar(euint8 c)
+{
+ if( (c<0x20) || (c>0x20&&c<0x30&&c!='-') || (c>0x39&&c<0x41) || (c>0x5A&&c<0x61&&c!='_') || (c>0x7A&&c!='~') )
+ return(0x58);
+ if( c>=0x61 && c<=0x7A )
+ return(c-32);
+
+ return(c);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void ioman_setAttr(IOManager *ioman,euint16 bufplace,euint8 attribute,euint8 val)
+ * Description: This sets the attribute of 'bufplace' to the given value (binary).
+ *
+ * Return value: void
+*/
+void file_setAttr(File* file,euint8 attribute,euint8 val)
+{
+ if(val){
+ file->FileStatus|=1<FileStatus&=~(1<FileStatus&(1<file->FileSize){
+ if(file->Cache.ClusterCount==0){ /* Number of cluster unknown */
+ hc = fat_countClustersInChain(file->fs,file->Cache.FirstCluster);
+ file->Cache.ClusterCount = hc;
+ }else{
+ hc = file->Cache.ClusterCount; /* This better be right */
+ }
+ clustersize = file->fs->volumeId.BytesPerSector * file->fs->volumeId.SectorsPerCluster;
+ if((size-file->FileSize+offset)>
+ ((hc-((file->FileSize+clustersize-1)/clustersize))*clustersize)){
+ clusters_required = (((offset+size)-(hc*clustersize))+clustersize-1)/clustersize;
+ }else{
+ clusters_required = 0;
+ }
+ }else{
+ clusters_required = 0;
+ }
+ return(clusters_required);
+}
diff --git a/F107/Utilities/efsl/source/fs.c b/F107/Utilities/efsl/source/fs.c
new file mode 100644
index 0000000..d82c83d
--- /dev/null
+++ b/F107/Utilities/efsl/source/fs.c
@@ -0,0 +1,523 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : fs.c *
+* Description : These are general filesystem functions, supported by the *
+* functions of dir.c and fat.c file.c uses these functions *
+* heavily, but is not used by fs.c (not true anymore) *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/*****************************************************************************/
+#include "fs.h"
+#include "fat.h"
+#include "dir.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * eint16 fs_initFs(FileSystem *fs,Partition *part)
+ * Description: This functions glues the initialisation of the filesystem together.
+ * It loads the volumeID, computes the FS type and searches for the rootsector.
+ * Return value: Returns 0 on succes and -1 on error (if magic code is wrong)
+*/
+eint16 fs_initFs(FileSystem *fs,Partition *part)
+{
+ if(!fs_isValidFat(part)){
+ return(-1);
+ }
+ fs->part=part;
+ fs_loadVolumeId(fs,part);
+ if(!fs_verifySanity(fs))return(-2);
+ fs_countDataSectors(fs);
+ fs_determineFatType(fs);
+ fs_findFirstSectorRootDir(fs);
+ fs_initCurrentDir(fs);
+ return(0);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * eint16 fs_isValidFat(Partition *part)
+ * Description: This functions loads the volumeID and checks if the magic
+ * value is present.
+ * Return value: returns 0 when magic code is missing, 1 if it is there.
+*/
+eint16 fs_isValidFat(Partition *part)
+{
+ euint8 *buf;
+
+ buf=part_getSect(part,0,IOM_MODE_READONLY|IOM_MODE_EXP_REQ); /* Load Volume label */
+ if( ex_getb16(buf,0x1FE) != 0xAA55 ){
+ return (0);
+ }
+ part_relSect(part,buf);
+ return(1);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void fs_loadVolumeId(FileSystem *fs, Partition *part)
+ * Description: This function loads all relevant fields from the volumeid.
+*/
+void fs_loadVolumeId(FileSystem *fs, Partition *part)
+{
+ euint8 *buf;
+
+ buf=part_getSect(part,0,IOM_MODE_READONLY|IOM_MODE_EXP_REQ);
+
+ fs->volumeId.BytesPerSector=ex_getb16(buf,0x0B);
+ fs->volumeId.SectorsPerCluster=*((eint8*)(buf+0x0D));
+ fs->volumeId.ReservedSectorCount=ex_getb16(buf,0x0E);
+ fs->volumeId.NumberOfFats=*((eint8*)(buf+0x10));
+ fs->volumeId.RootEntryCount=ex_getb16(buf,0x11);
+ fs->volumeId.SectorCount16=ex_getb16(buf,0x13);
+ fs->volumeId.FatSectorCount16=ex_getb16(buf,0x16);
+ fs->volumeId.SectorCount32=ex_getb32(buf,0x20);
+ fs->volumeId.FatSectorCount32=ex_getb32(buf,0x24);
+ fs->volumeId.RootCluster=ex_getb32(buf,0x2C);
+
+ part_relSect(part,buf);
+
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint16 fs_verifySanity(FileSystem *fs)
+ * Description: Does some sanity calculations.
+ * Return value: 1 on success, 0 when discrepancies were found.
+*/
+esint16 fs_verifySanity(FileSystem *fs)
+{
+ esint16 sane=1; /* Sane until proven otherwise */
+ /* First check, BPS, we only support 512 */
+ if(fs->volumeId.BytesPerSector!=512)sane=0;
+ /* Check is SPC is valid (multiple of 2, and clustersize >=32KB */
+ if(!((fs->volumeId.SectorsPerCluster == 1 ) |
+ (fs->volumeId.SectorsPerCluster == 2 ) |
+ (fs->volumeId.SectorsPerCluster == 4 ) |
+ (fs->volumeId.SectorsPerCluster == 8 ) |
+ (fs->volumeId.SectorsPerCluster == 16) |
+ (fs->volumeId.SectorsPerCluster == 32) |
+ (fs->volumeId.SectorsPerCluster == 64) ))sane=0;
+ /* Any number of FAT's should be supported... (untested) */
+ /* There should be at least 1 reserved sector */
+ if(fs->volumeId.ReservedSectorCount==0)sane=0;
+ if(fs->volumeId.FatSectorCount16 != 0){
+ if(fs->volumeId.FatSectorCount16 > fs->part->disc->partitions[fs->part->activePartition].numSectors)sane=0;
+ }else{
+ if(fs->volumeId.FatSectorCount32 > fs->part->disc->partitions[fs->part->activePartition].numSectors)sane=0;
+ }
+ return(sane);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void fs_countDataSectors(FileSystem *fs)
+ * Description: This functions calculates the sectorcounts, fatsectorcounts and
+ * dataclustercounts. It fills in the general fields.
+*/
+void fs_countDataSectors(FileSystem *fs)
+{
+ euint32 rootDirSectors,dataSectorCount;
+
+ rootDirSectors=((fs->volumeId.RootEntryCount*32) +
+ (fs->volumeId.BytesPerSector - 1)) /
+ fs->volumeId.BytesPerSector;
+
+ if(fs->volumeId.FatSectorCount16 != 0)
+ {
+ fs->FatSectorCount=fs->volumeId.FatSectorCount16;
+ fs->volumeId.FatSectorCount32=0;
+ }
+ else
+ {
+ fs->FatSectorCount=fs->volumeId.FatSectorCount32;
+ fs->volumeId.FatSectorCount16=0;
+ }
+
+ if(fs->volumeId.SectorCount16!=0)
+ {
+ fs->SectorCount=fs->volumeId.SectorCount16;
+ fs->volumeId.SectorCount32=0;
+ }
+ else
+ {
+ fs->SectorCount=fs->volumeId.SectorCount32;
+ fs->volumeId.SectorCount16=0;
+ }
+
+ dataSectorCount=fs->SectorCount - (
+ fs->volumeId.ReservedSectorCount +
+ (fs->volumeId.NumberOfFats * fs->FatSectorCount) +
+ rootDirSectors);
+
+ fs->DataClusterCount=dataSectorCount/fs->volumeId.SectorsPerCluster;
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void fs_determineFatType(FileSystem *fs)
+ * Description: This function looks af the Dataclustercount and determines the
+ * FAT type. It fills in fs->type.
+*/
+void fs_determineFatType(FileSystem *fs)
+{
+ if(fs->DataClusterCount < 4085)
+ {
+ fs->type=FAT12;
+ fs->volumeId.RootCluster=0;
+ }
+ else if(fs->DataClusterCount < 65525)
+ {
+ fs->type=FAT16;
+ fs->volumeId.RootCluster=0;
+ }
+ else
+ {
+ fs->type=FAT32;
+ }
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void fs_findFirstSectorRootDir(FileSystem *fs)
+ * Description: This functions fills in the fs->FirstSectorRootDir field, even
+ * for FAT32, although that is not necessary (because you have FirstClusterRootDir).
+*/
+void fs_findFirstSectorRootDir(FileSystem *fs)
+{
+ if(fs->type==FAT32)
+ fs->FirstSectorRootDir = fs->volumeId.ReservedSectorCount +
+ (fs->volumeId.NumberOfFats*fs->volumeId.FatSectorCount32) +
+ (fs->volumeId.RootCluster-2)*fs->volumeId.SectorsPerCluster;
+ else
+ fs->FirstSectorRootDir = fs->volumeId.ReservedSectorCount +
+ (fs->volumeId.NumberOfFats*fs->volumeId.FatSectorCount16);
+}
+/*****************************************************************************/
+
+void fs_initCurrentDir(FileSystem *fs)
+{
+ fs->FirstClusterCurrentDir = fs_getFirstClusterRootDir(fs);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * long fs_clusterToSector(FileSystem *fs,euint32 cluster)
+ * Description: This function converts a clusternumber in the effective sector
+ * number where this cluster starts. Boundary check is not implemented
+ * Return value: A long is returned representing the sectornumber.
+*/
+euint32 fs_clusterToSector(FileSystem *fs,euint32 cluster)
+{
+ eint32 base;
+
+ if(fs->type==FAT32)
+ {
+ base=
+ fs->volumeId.ReservedSectorCount+
+ fs->FatSectorCount*fs->volumeId.NumberOfFats;
+ }
+ else
+ {
+ base=
+ fs->volumeId.ReservedSectorCount+
+ fs->FatSectorCount*fs->volumeId.NumberOfFats+
+ fs->volumeId.RootEntryCount/16;
+ }
+ return( base + (cluster-2)*fs->volumeId.SectorsPerCluster );
+}
+/*****************************************************************************/
+
+/* Function is unused, but may be usefull */
+euint32 fs_sectorToCluster(FileSystem *fs,euint32 sector)
+{
+ eint32 base;
+
+ if(fs->type==FAT32)
+ {
+ base=
+ fs->volumeId.ReservedSectorCount+
+ fs->FatSectorCount*fs->volumeId.NumberOfFats;
+ }
+ else
+ {
+ base=
+ fs->volumeId.ReservedSectorCount+
+ fs->FatSectorCount*fs->volumeId.NumberOfFats+
+ fs->volumeId.RootEntryCount/16;
+ }
+ return(((sector-base)-((sector-base)%fs->volumeId.SectorsPerCluster))/fs->volumeId.SectorsPerCluster+2 );
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 fs_getNextFreeCluster(FileSystem *fs,euint32 startingcluster)
+ * Description: This functions searches for a free cluster, starting it's search at
+ * cluster startingcluster. This allow to speed up searches and try to avoid
+ * fragmentation. Implementing rollover search is still to be done.
+ * Return value: If a free cluster is found it's number is returned. If none is
+ * found 0 is returned.
+*/
+euint32 fs_getNextFreeCluster(FileSystem *fs,euint32 startingcluster)
+{
+ euint32 r;
+
+ while(startingclusterDataClusterCount){
+ r=fat_getNextClusterAddress(fs,startingcluster,0);
+ if(r==0){
+ return(startingcluster);
+ }
+ startingcluster++;
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 fs_giveFreeClusterHint(FileSystem *fs)
+ *
+ * Description: This function should return a clusternumber that is free or
+ * lies close before free clusters. The result MUST be checked to see if
+ * it is free! Implementationhint: search the largest clusternumber in the
+ * files in the rootdirectory.
+ *
+ * Return value: Returns it's best guess.
+*/
+euint32 fs_giveFreeClusterHint(FileSystem *fs)
+{
+ return(2); /* Now THIS is a hint ;) */
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint8 fs_findFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint32 *lastDir)
+ *
+ * Description: This function looks if the given filename is on the given fs
+ * and, if found, fills in its location in loc.
+ * The function will first check if the pathname starts with a slash. If so it will
+ * set the starting directory to the rootdirectory. Else, it will take the firstcluster-
+ * currentdir (That you can change with chdir()) as startingpoint.
+ * The lastdir pointer will be the first cluster of the last directory fs_findfile
+ * enters. It starts out at the root/current dir and then traverses the path along with
+ * fs_findFile.
+ * It is set to 0 in case of errors (like dir/dir/dir/file/dir/dir...)
+ * Return value: Returns 0 when nothing was found, 1 when the thing found
+ * was a file and 2 if the thing found was a directory.
+*/
+
+esint8 fs_findFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint32 *lastDir)
+{
+ euint32 fccd,tmpclus;
+ eint8 ffname[11],*next,it=0,filefound=0;
+
+ if(*filename=='/'){
+ fccd = fs_getFirstClusterRootDir(fs);
+ filename++;
+ if(lastDir)*lastDir=fccd;
+ if(!*filename){
+ return(2);
+ }
+ }else{
+ fccd = fs->FirstClusterCurrentDir;
+ if(lastDir)*lastDir=fccd;
+ }
+
+
+ while((next=file_normalToFatName(filename,ffname))!=0){
+ if((tmpclus=dir_findinDir(fs,ffname,fccd,loc,DIRFIND_FILE))==0){
+ /* We didn't find what we wanted */
+ /* We should check, to see if there is more after it, so that
+ * we can invalidate lastDir
+ */
+ if((file_normalToFatName(next,ffname))!=0){
+ if(lastDir)*lastDir=0;
+ }
+ return(0);
+ }
+ it++;
+ if(loc->attrib&ATTR_DIRECTORY){
+ fccd = tmpclus;
+ filename = next;
+ if(lastDir)*lastDir=fccd;
+ if(filefound)*lastDir=0;
+ }else{
+ filefound=1;
+ if((file_normalToFatName(next,ffname))!=0){
+ if(lastDir)*lastDir=0;
+ return(0);
+ }else{
+ filename=next;
+ }
+ }
+ }
+
+ if(it==0)return(0);
+ if(loc->attrib&ATTR_DIRECTORY || !filefound)return(2);
+ return(1);
+}
+/*****************************************************************************/
+
+esint16 fs_findFreeFile(FileSystem *fs,eint8* filename,FileLocation *loc,euint8 mode)
+{
+ euint32 targetdir=0;
+ eint8 ffname[11];
+
+ if(fs_findFile(fs,filename,loc,&targetdir))return(0);
+ if(!dir_getFatFileName(filename,ffname))return(0);
+ if(dir_findinDir(fs,ffname,targetdir,loc,DIRFIND_FREE)){
+ return(1);
+ }else{
+ if(dir_addCluster(fs,targetdir)){
+ return(0);
+ }else{
+ if(dir_findinDir(fs,ffname,targetdir,loc,DIRFIND_FREE)){
+ return(1);
+ }
+ }
+ }
+
+ return(0);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint32 fs_getLastCluster(FileSystem *fs,ClusterChain *Cache)
+ * Description: This function searches the last cluster of a chain.
+ * Return value: The LastCluster (also stored in cache);
+*/
+euint32 fs_getLastCluster(FileSystem *fs,ClusterChain *Cache)
+{
+ if(Cache->DiscCluster==0){
+ Cache->DiscCluster=Cache->FirstCluster;
+ Cache->LogicCluster=0;
+ }
+
+ if(Cache->LastCluster==0)
+ {
+ while(fat_getNextClusterChain(fs, Cache)==0)
+ {
+ Cache->LogicCluster+=Cache->Linear;
+ Cache->DiscCluster+=Cache->Linear;
+ Cache->Linear=0;
+ }
+ }
+ return(Cache->LastCluster);
+}
+/*****************************************************************************/
+
+euint32 fs_getFirstClusterRootDir(FileSystem *fs)
+{
+ switch(fs->type){
+ case FAT32:
+ return(fs->volumeId.RootCluster);
+ //break;
+ default:
+ return(1);
+ //break;
+ }
+}
+/*****************************************************************************/
+
+void fs_initClusterChain(FileSystem *fs,ClusterChain *cache,euint32 cluster_addr)
+{
+ cache->FirstCluster=cluster_addr;
+ cache->DiscCluster=cluster_addr;
+ cache->LogicCluster=0;
+ cache->LastCluster=0; /* Warning flag here */
+ cache->Linear=0;
+ cache->ClusterCount=0; /* 0 means NOT known */
+}
+/*****************************************************************************/
+
+void fs_setFirstClusterInDirEntry(FileRecord *rec,euint32 cluster_addr)
+{
+ rec->FirstClusterHigh=cluster_addr>>16;
+ rec->FirstClusterLow=cluster_addr&0xFFFF;
+}
+/*****************************************************************************/
+
+esint8 fs_flushFs(FileSystem *fs)
+{
+ return(part_flushPart(fs->part,0,fs->SectorCount));
+}
+/*****************************************************************************/
+
+esint8 fs_umount(FileSystem *fs)
+{
+ return(fs_flushFs(fs));
+}
+/*****************************************************************************/
+
+esint8 fs_clearCluster(FileSystem *fs,euint32 cluster)
+{
+ euint16 c;
+ euint8* buf;
+
+ for(c=0;c<(fs->volumeId.SectorsPerCluster);c++){
+ buf = part_getSect(fs->part,fs_clusterToSector(fs,cluster)+c,IOM_MODE_READWRITE);
+ memClr(buf,512);
+ part_relSect(fs->part,buf);
+ }
+ return(0);
+}
+
+esint8 fs_getFsInfo(FileSystem *fs,euint8 force_update)
+{
+ euint8 *buf;
+
+ if(!fs->type==FAT32)return(0);
+ buf = part_getSect(fs->part,FS_INFO_SECTOR,IOM_MODE_READONLY);
+ if(ex_getb32(buf,0)!=FSINFO_MAGIC_BEGIN || ex_getb32(buf,508)!=FSINFO_MAGIC_END){
+ part_relSect(fs->part,buf);
+ return(-1);
+ }
+ fs->FreeClusterCount = ex_getb32(buf,488);
+ fs->NextFreeCluster = ex_getb32(buf,492);
+ part_relSect(fs->part,buf);
+ if(force_update){
+ fs->FreeClusterCount=fat_countFreeClusters(fs);
+ }
+ return(0);
+}
+
+esint8 fs_setFsInfo(FileSystem *fs)
+{
+ euint8* buf;
+
+ if(!fs->type==FAT32)return(0);
+ buf = part_getSect(fs->part,FS_INFO_SECTOR,IOM_MODE_READWRITE);
+ if(ex_getb32(buf,0)!=FSINFO_MAGIC_BEGIN || ex_getb32(buf,508)!=FSINFO_MAGIC_END){
+ part_relSect(fs->part,buf);
+ return(-1);
+ }
+ ex_setb32(buf,488,fs->FreeClusterCount);
+ ex_setb32(buf,492,fs->NextFreeCluster);
+ part_relSect(fs->part,buf);
+ return(0);
+}
+
diff --git a/F107/Utilities/efsl/source/interface/sd.c b/F107/Utilities/efsl/source/interface/sd.c
new file mode 100644
index 0000000..fcaf292
--- /dev/null
+++ b/F107/Utilities/efsl/source/interface/sd.c
@@ -0,0 +1,344 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : sd.c *
+* Revision : Initial developement *
+* Description : This file contains the functions needed to use efs for *
+* accessing files on an SD-card. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/*****************************************************************************/
+#include "interface/sd.h"
+/*****************************************************************************/
+
+esint8 sd_Init(hwInterface *iface)
+{
+ esint16 i;
+ euint8 resp;
+
+ /* Try to send reset command up to 100 times */
+ i=100;
+ do{
+ sd_Command(iface,0, 0, 0);
+ resp=sd_Resp8b(iface);
+ }
+ while(resp!=1 && i--);
+
+ if(resp!=1){
+ if(resp==0xff){
+ return(-1);
+ }
+ else{
+ sd_Resp8bError(iface,resp);
+ return(-2);
+ }
+ }
+
+ /* Wait till card is ready initialising (returns 0 on CMD1) */
+ /* Try up to 32000 times. */
+ i=32000;
+ do{
+ sd_Command(iface,1, 0, 0);
+
+ resp=sd_Resp8b(iface);
+ if(resp!=0)
+ sd_Resp8bError(iface,resp);
+ }
+ while(resp==1 && i--);
+
+ if(resp!=0){
+ sd_Resp8bError(iface,resp);
+ return(-3);
+ }
+
+ return(0);
+}
+/*****************************************************************************/
+
+void sd_Command(hwInterface *iface,euint8 cmd, euint16 paramx, euint16 paramy)
+{
+ if_spiSend(iface,0xff);
+
+ if_spiSend(iface,0x40 | cmd);
+ if_spiSend(iface,(euint8) (paramx >> 8)); /* MSB of parameter x */
+ if_spiSend(iface,(euint8) (paramx)); /* LSB of parameter x */
+ if_spiSend(iface,(euint8) (paramy >> 8)); /* MSB of parameter y */
+ if_spiSend(iface,(euint8) (paramy)); /* LSB of parameter y */
+
+ if_spiSend(iface,0x95); /* Checksum (should be only valid for first command (0) */
+
+ if_spiSend(iface,0xff); /* eat empty command - response */
+}
+/*****************************************************************************/
+
+euint8 sd_Resp8b(hwInterface *iface)
+{
+ euint8 i;
+ euint8 resp;
+
+ /* Respone will come after 1 - 8 pings */
+ for(i=0;i<8;i++){
+ resp = if_spiSend(iface,0xff);
+ if(resp != 0xff)
+ return(resp);
+ }
+
+ return(resp);
+}
+/*****************************************************************************/
+
+euint16 sd_Resp16b(hwInterface *iface)
+{
+ euint16 resp;
+
+ resp = ( sd_Resp8b(iface) << 8 ) & 0xff00;
+ resp |= if_spiSend(iface,0xff);
+
+ return(resp);
+}
+/*****************************************************************************/
+
+void sd_Resp8bError(hwInterface *iface,euint8 value)
+{
+ switch(value)
+ {
+ case 0x40:
+ //DBG((TXT("Argument out of bounds.\n")));
+ break;
+ case 0x20:
+ //DBG((TXT("Address out of bounds.\n")));
+ break;
+ case 0x10:
+ //DBG((TXT("Error during erase sequence.\n")));
+ break;
+ case 0x08:
+ //DBG((TXT("CRC failed.\n")));
+ break;
+ case 0x04:
+ //DBG((TXT("Illegal command.\n")));
+ break;
+ case 0x02:
+ //DBG((TXT("Erase reset (see SanDisk docs p5-13).\n")));
+ break;
+ case 0x01:
+ //DBG((TXT("Card is initialising.\n")));
+ break;
+ default:
+ //DBG((TXT("Unknown error 0x%x (see SanDisk docs p5-13).\n"),value));
+ break;
+ }
+}
+/*****************************************************************************/
+
+esint8 sd_State(hwInterface *iface)
+{
+ eint16 value;
+
+ sd_Command(iface,13, 0, 0);
+ value=sd_Resp16b(iface);
+
+ switch(value)
+ {
+ case 0x000:
+ return(1);
+ //break;
+ case 0x0001:
+ //DBG((TXT("Card is Locked.\n")));
+ break;
+ case 0x0002:
+ //DBG((TXT("WP Erase Skip, Lock/Unlock Cmd Failed.\n")));
+ break;
+ case 0x0004:
+ //DBG((TXT("General / Unknown error -- card broken?.\n")));
+ break;
+ case 0x0008:
+ //DBG((TXT("Internal card controller error.\n")));
+ break;
+ case 0x0010:
+ //DBG((TXT("Card internal ECC was applied, but failed to correct the data.\n")));
+ break;
+ case 0x0020:
+ //DBG((TXT("Write protect violation.\n")));
+ break;
+ case 0x0040:
+ //DBG((TXT("An invalid selection, sectors for erase.\n")));
+ break;
+ case 0x0080:
+ //DBG((TXT("Out of Range, CSD_Overwrite.\n")));
+ break;
+ default:
+ if(value>0x00FF)
+ sd_Resp8bError(iface,(euint8) (value>>8));
+ else
+ //DBG((TXT("Unknown error: 0x%x (see SanDisk docs p5-14).\n"),value));
+ break;
+ }
+ return(-1);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * WAIT ?? -- FIXME
+ * CMDWRITE
+ * WAIT
+ * CARD RESP
+ * WAIT
+ * DATA BLOCK OUT
+ * START BLOCK
+ * DATA
+ * CHKS (2B)
+ * BUSY...
+ */
+
+esint8 sd_writeSector(hwInterface *iface,euint32 address, euint8* buf)
+{
+ euint32 place;
+ euint16 i;
+ euint16 t=0;
+
+ /*DBG((TXT("Trying to write %u to sector %u.\n"),(void *)&buf,address));*/
+ place=512*address;
+ sd_Command(iface,CMDWRITE, (euint16) (place >> 16), (euint16) place);
+
+ sd_Resp8b(iface); /* Card response */
+
+ if_spiSend(iface,0xfe); /* Start block */
+ for(i=0;i<512;i++)
+ if_spiSend(iface,buf[i]); /* Send data */
+ if_spiSend(iface,0xff); /* Checksum part 1 */
+ if_spiSend(iface,0xff); /* Checksum part 2 */
+
+ if_spiSend(iface,0xff);
+
+ while(if_spiSend(iface,0xff)!=0xff){
+ t++;
+ /* Removed NOP */
+ }
+ /*DBG((TXT("Nopp'ed %u times.\n"),t));*/
+
+ return(0);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * WAIT ?? -- FIXME
+ * CMDCMD
+ * WAIT
+ * CARD RESP
+ * WAIT
+ * DATA BLOCK IN
+ * START BLOCK
+ * DATA
+ * CHKS (2B)
+ */
+
+esint8 sd_readSector(hwInterface *iface,euint32 address, euint8* buf, euint16 len)
+{
+ euint8 cardresp;
+ euint8 firstblock;
+ euint8 c;
+ euint16 fb_timeout=0xffff;
+ euint32 i;
+ euint32 place;
+
+ /*DBG((TXT("sd_readSector::Trying to read sector %u and store it at %p.\n"),address,&buf[0]));*/
+ place=512*address;
+ sd_Command(iface,CMDREAD, (euint16) (place >> 16), (euint16) place);
+
+ cardresp=sd_Resp8b(iface); /* Card response */
+
+ /* Wait for startblock */
+ do
+ firstblock=sd_Resp8b(iface);
+ while(firstblock==0xff && fb_timeout--);
+
+ if(cardresp!=0x00 || firstblock!=0xfe){
+ sd_Resp8bError(iface,firstblock);
+ return(-1);
+ }
+
+ for(i=0;i<512;i++){
+ c = if_spiSend(iface,0xff);
+ if(i>6;
+
+ by= iob[5] & 0x0F;
+ read_bl_len = 1;
+ read_bl_len <<= by;
+
+ by=iob[9] & 0x03;
+ by <<= 1;
+ by += iob[10] >> 7;
+
+ c_size_mult = 1;
+ c_size_mult <<= (2+by);
+
+ *drive_size = (euint32)(c_size+1) * (euint32)c_size_mult * (euint32)read_bl_len;
+
+ return 0;
+}
diff --git a/F107/Utilities/efsl/source/interface/sd_stm32.c b/F107/Utilities/efsl/source/interface/sd_stm32.c
new file mode 100644
index 0000000..081b7d4
--- /dev/null
+++ b/F107/Utilities/efsl/source/interface/sd_stm32.c
@@ -0,0 +1,187 @@
+/**
+ ******************************************************************************
+ * @file sd_stm32.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 11/20/2009
+ * @brief efs 礢D card driver's low level interface for STM32F107 (using
+ * 礢D card provided with STM3210C-EVAL board)
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * © COPYRIGHT 2009 STMicroelectronics
+ */
+
+/* Includes ------------------------------------------------------------------*/
+
+#include "stm32f10x_spi.h"
+#include "interface/sd.h"
+#include "config.h"
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Select MSD Card: ChipSelect pin low */
+#define MSD_CS_LOW() GPIO_ResetBits(GPIOA, GPIO_Pin_4)
+/* Deselect MSD Card: ChipSelect pin high */
+#define MSD_CS_HIGH() GPIO_SetBits(GPIOA, GPIO_Pin_4)
+
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SPI_Config(void);
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief Initializes the SPI and GPIOs used to drive the 礢D card.
+ * @param None
+ * @retval None
+ */
+void SPI_Config(void)
+{
+ GPIO_InitTypeDef GPIO_InitStructure;
+ SPI_InitTypeDef SPI_InitStructure;
+
+ /* GPIOA and GPIOC Periph clock enable */
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
+
+ GPIO_PinRemapConfig(GPIO_Remap_SPI3, ENABLE);
+
+ /* SPI3 Periph clock enable */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
+
+ /* Configure SPI3 pins: SCK, MISO and MOSI */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+ GPIO_Init(GPIOC, &GPIO_InitStructure);
+
+ /* Configure PA4 pin: CS pin */
+ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
+ GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+ /* SPI3 Config */
+ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+ SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+ SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+ SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+ SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+ SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+ SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+ SPI_InitStructure.SPI_CRCPolynomial = 7;
+ SPI_Init(SPI3, &SPI_InitStructure);
+
+ /* SPI3 enable */
+ SPI_Cmd(SPI3, ENABLE);
+}
+
+/*****************************************************************************/
+
+esint8 if_readBuf(hwInterface* file, euint32 address, euint8* buf)
+{
+ return(sd_readSector(file, address, buf, 512));
+}
+/*****************************************************************************/
+
+esint8 if_writeBuf(hwInterface* file, euint32 address, euint8* buf)
+{
+ return(sd_writeSector(file, address, buf));
+}
+/*****************************************************************************/
+
+esint8 if_setPos(hwInterface* file, euint32 address)
+{
+ return(0);
+}
+/*****************************************************************************/
+
+// Utility-functions which does not toogle CS.
+// Only needed during card-init. During init
+// the automatic chip-select is disabled for SSP
+
+static euint8 my_if_spiSend(hwInterface *iface, euint8 outgoing)
+{
+ euint8 incoming;
+
+ SPI_I2S_SendData(SPI3, outgoing);
+ while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET);
+ incoming = SPI_I2S_ReceiveData(SPI3);
+
+ return(incoming);
+}
+/*****************************************************************************/
+
+void if_spiInit(hwInterface *iface)
+{
+ euint8 i;
+
+ SPI_Config();
+
+ MSD_CS_HIGH();
+
+ /* Send 20 spi commands with card not selected */
+ for (i = 0;i < 21;i++)
+ my_if_spiSend(iface, 0xff);
+}
+/*****************************************************************************/
+
+euint8 if_spiSend(hwInterface *iface, euint8 outgoing)
+{
+ euint8 incoming;
+
+ MSD_CS_LOW();
+
+ SPI_I2S_SendData(SPI3, outgoing);
+
+ while (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) == RESET);
+
+ incoming = SPI_I2S_ReceiveData(SPI3);
+
+ MSD_CS_HIGH();
+
+ return(incoming);
+}
+/*****************************************************************************/
+
+esint8 if_initInterface(hwInterface* file, eint8* opts)
+{
+ euint32 sc;
+
+ if_spiInit(file); /* init at low speed */
+
+ if (sd_Init(file) < 0)
+ {
+ DBG((TXT("Card failed to init, breaking up...\n")));
+ return(-1);
+ }
+ if (sd_State(file) < 0)
+ {
+ DBG((TXT("Card didn't return the ready state, breaking up...\n")));
+ return(-2);
+ }
+
+ sd_getDriveSize(file, &sc);
+ file->sectorCount = sc / 512;
+ if ( (sc % 512) != 0)
+ {
+ file->sectorCount--;
+ }
+
+ DBG((TXT("Drive Size is %lu Bytes (%lu Sectors)\n"), sc, file->sectorCount));
+ DBG((TXT("Init done...\n")));
+
+ return(0);
+}
+
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/F107/Utilities/efsl/source/ioman.c b/F107/Utilities/efsl/source/ioman.c
new file mode 100644
index 0000000..478d0ce
--- /dev/null
+++ b/F107/Utilities/efsl/source/ioman.c
@@ -0,0 +1,594 @@
+/*****************************************************************************/
+/* libfat - General purpose FAT library *
+* ---------------------------------- *
+* *
+* Filename : ioman.c *
+* Description : The IO Manager receives all requests for sectors in a central *
+* allowing it to make smart decision regarding caching. *
+* The IOMAN_NUMBUFFER parameter determines how many sectors *
+* ioman can cache. ioman also supports overallocating and *
+* backtracking sectors. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+/*****************************************************************************/
+#include "ioman.h"
+/*****************************************************************************/
+
+esint8 ioman_init(IOManager *ioman, hwInterface *iface, euint8* bufferarea)
+{
+ ioman->iface=iface;
+
+ ioman->bufptr = ioman_getBuffer(ioman,bufferarea);
+ ioman->numbuf = IOMAN_NUMBUFFER;
+ ioman->numit = IOMAN_NUMITERATIONS;
+
+ ioman_reset(ioman);
+ return(0);
+}
+/*****************************************************************************/
+
+void ioman_reset(IOManager *ioman)
+{
+ euint16 nb,ni;
+
+ memClr(ioman->sector,sizeof(euint32)*ioman->numbuf);
+ memClr(ioman->status,sizeof(euint8) *ioman->numbuf);
+ memClr(ioman->usage ,sizeof(euint8) *ioman->numbuf);
+ memClr(ioman->itptr ,sizeof(euint8) *ioman->numbuf);
+ ioman_setError(ioman,IOMAN_NOERROR);
+
+ for(nb=0;nbnumbuf;nb++){
+ for(ni=0;ninumit;ni++){
+ ioman->stack[nb][ni].sector=0;
+ ioman->stack[nb][ni].status=0;
+ ioman->stack[nb][ni].usage =0;
+ }
+ }
+}
+/*****************************************************************************/
+
+euint8* ioman_getBuffer(IOManager *ioman,euint8* bufferarea)
+{
+#ifdef IOMAN_DO_MEMALLOC
+ return(ioman->cache_mem);
+#else
+ return(bufferarea);
+#endif
+}
+/*****************************************************************************/
+
+void ioman_setAttr(IOManager *ioman,euint16 bufplace,euint8 attribute,euint8 val)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_SETATTROUTOFBOUNDS);
+ return; /* Out of bounds */
+ }
+
+ if(val){
+ ioman->status[bufplace]|=1<status[bufplace]&=~(1<=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_GETATTROUTOFBOUNDS);
+ return(0xFF); /* Out of bounds */
+ }
+
+ return(ioman->status[bufplace]&(1<=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return(0x00);
+ }
+ return(ioman->usage[bufplace]);
+}
+/*****************************************************************************/
+
+
+void ioman_incUseCnt(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return;
+ }
+ if(ioman->usage[bufplace]==0xFF)return;
+ else ioman->usage[bufplace]++;
+}
+/*****************************************************************************/
+
+void ioman_decUseCnt(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return;
+ }
+ if(ioman->usage[bufplace]==0x0)return;
+ else ioman->usage[bufplace]--;
+}
+/*****************************************************************************/
+
+void ioman_resetUseCnt(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return;
+ }
+ ioman->usage[bufplace]=0x00;
+}
+/*****************************************************************************/
+
+euint8 ioman_getRefCnt(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return(0x00);
+ }
+ return(ioman->reference[bufplace]);
+}
+/*****************************************************************************/
+
+void ioman_incRefCnt(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return;
+ }
+ if(ioman->reference[bufplace]==0xFF)return;
+ else ioman->reference[bufplace]++;
+}
+/*****************************************************************************/
+
+void ioman_decRefCnt(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return;
+ }
+ if(ioman->reference[bufplace]==0x00)return;
+ else ioman->reference[bufplace]--;
+}
+/*****************************************************************************/
+
+void ioman_resetRefCnt(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return;
+ }
+ ioman->reference[bufplace]=0x00;
+}
+/*****************************************************************************/
+
+esint8 ioman_pop(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_POPEMPTYSTACK);
+ return(-1);
+ }
+ if(ioman->itptr[bufplace]==0 || ioman->itptr[bufplace]>IOMAN_NUMITERATIONS)return(-1);
+ ioman->sector[bufplace] = ioman->stack[bufplace][ioman->itptr[bufplace]].sector;
+ ioman->status[bufplace] = ioman->stack[bufplace][ioman->itptr[bufplace]].status;
+ ioman->usage[bufplace] = ioman->stack[bufplace][ioman->itptr[bufplace]].usage;
+ ioman->itptr[bufplace]--;
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ioman_push(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return(-1);
+ }
+ if(ioman->itptr[bufplace]>=IOMAN_NUMITERATIONS){
+ ioman_setError(ioman,IOMAN_ERR_PUSHBEYONDSTACK);
+ return(-1);
+ }
+ ioman->itptr[bufplace]++;
+ ioman->stack[bufplace][ioman->itptr[bufplace]].sector = ioman->sector[bufplace];
+ ioman->stack[bufplace][ioman->itptr[bufplace]].status = ioman->status[bufplace];
+ ioman->stack[bufplace][ioman->itptr[bufplace]].usage = ioman->usage[bufplace];
+ return(0);
+}
+/*****************************************************************************/
+
+euint8* ioman_getPtr(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return(0);
+ }
+ return(ioman->bufptr+bufplace*512);
+}
+/*****************************************************************************/
+
+esint16 ioman_getBp(IOManager *ioman,euint8* buf)
+{
+ if(buf<(ioman->bufptr) || buf>=( ioman->bufptr+(ioman->numbuf*512) )){
+ ioman_setError(ioman,IOMAN_ERR_CACHEPTROUTOFRANGE);
+ return(-1);
+ }
+ return((buf-(ioman->bufptr))/512);
+}
+/*****************************************************************************/
+
+esint8 ioman_readSector(IOManager *ioman,euint32 address,euint8* buf)
+{
+ esint8 r;
+
+ if(buf==0){
+ return(-1);
+ }
+
+ r=if_readBuf(ioman->iface,address,buf);
+
+ if(r!=0){
+ ioman_setError(ioman,IOMAN_ERR_READFAIL);
+ return(-1);
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ioman_writeSector(IOManager *ioman, euint32 address, euint8* buf)
+{
+ esint8 r;
+
+ if(buf==0)return(-1);
+
+ r=if_writeBuf(ioman->iface,address,buf);
+
+ if(r<=0){
+ ioman_setError(ioman,IOMAN_ERR_WRITEFAIL);
+ return(-1);
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+void ioman_resetCacheItem(IOManager *ioman,euint16 bufplace)
+{
+ if(bufplace>=ioman->numbuf){
+ ioman_setError(ioman,IOMAN_ERR_OPOUTOFBOUNDS);
+ return;
+ }
+ ioman->sector[bufplace] = 0;
+ ioman->status[bufplace] = 0;
+ ioman->usage[bufplace] = 0;
+ ioman->reference[bufplace] = 0;
+}
+/*****************************************************************************/
+
+esint32 ioman_findSectorInCache(IOManager *ioman, euint32 address)
+{
+ euint16 c;
+
+ for(c=0;cnumbuf;c++){
+ if(ioman_isValid(c) && ioman->sector[c] == address)return(c);
+ }
+ return(-1);
+}
+/*****************************************************************************/
+
+esint32 ioman_findFreeSpot(IOManager *ioman)
+{
+ euint16 c;
+
+ for(c=0;cnumbuf;c++){
+ if(!ioman_isValid(c))return(c);
+ }
+ return(-1);
+}
+/*****************************************************************************/
+
+esint32 ioman_findUnusedSpot(IOManager *ioman)
+{
+ esint32 r=-1;
+ euint16 c;
+ euint8 fr=0,lr=0xFF;
+
+ for(c=0;cnumbuf;c++){
+ if(ioman_getUseCnt(ioman,c)==0){
+ if(!ioman_isWritable(c) && !fr){
+ fr=1;
+ lr=0xFF;
+ r=-1;
+ }
+ if(ioman_isWritable(c) && !fr){
+ if(ioman_getRefCnt(ioman,c)<=lr){
+ r=c;
+ lr=ioman_getRefCnt(ioman,c);
+ }
+ }
+ if(fr && !ioman_isWritable(c)){
+ if(ioman_getRefCnt(ioman,c)<=lr){
+ r=c;
+ lr=ioman_getRefCnt(ioman,c);
+ }
+ }
+ }
+ }
+ return(r);
+}
+/*****************************************************************************/
+
+esint32 ioman_findOverallocableSpot(IOManager *ioman)
+{
+ euint8 points,lp=0xFF;
+ euint16 c;
+ esint32 r=-1;
+
+ for(c=0;cnumbuf;c++){
+ if(ioman->itptr[c]numit){
+ points = 0;
+ if(ioman_isWritable(c))points+=0x7F;
+ points += ((euint16)(ioman->itptr[c]*0x4D))/(ioman->numit);
+ points += ((euint16)(ioman_getRefCnt(ioman,c)*0x33))/0xFF;
+ if(pointssector[bufplace]=address;
+ return(0);
+}
+/***************** if(bufplace>=ioman->numbuf)return;
+************************************************************/
+
+esint8 ioman_flushSector(IOManager *ioman, euint16 bufplace)
+{
+ euint8* buf;
+
+ if((buf = ioman_getPtr(ioman,bufplace))==0){
+ ioman_setError(ioman,IOMAN_ERR_CACHEPTROUTOFRANGE);
+ return(-1);
+ }
+ if(!ioman_isWritable(bufplace)){
+ ioman_setError(ioman,IOMAN_ERR_WRITEREADONLYSECTOR);
+ return(-1);
+ }
+ if(!(ioman_writeSector(ioman,ioman->sector[bufplace],buf))){
+ ioman_setError(ioman,IOMAN_ERR_WRITEFAIL);
+ return(-1);
+ }
+ if(ioman->usage==0)ioman_setNotWritable(bufplace);
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ioman_flushRange(IOManager *ioman,euint32 address_low, euint32 address_high)
+{
+ euint32 c;
+
+ if(address_low>address_high){
+ c=address_low; address_low=address_high;address_high=c;
+ }
+
+ for(c=0;cnumbuf;c++){
+ if((ioman->sector[c]>=address_low) && (ioman->sector[c]<=address_high) && (ioman_isWritable(c))){
+ if(ioman_flushSector(ioman,c)){
+ return(-1);
+ }
+ if(ioman->usage[c]==0)ioman_setNotWritable(c);
+ }
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ioman_flushAll(IOManager *ioman)
+{
+ euint16 c;
+
+ for(c=0;cnumbuf;c++){
+ if(ioman_isWritable(c)){
+ if(ioman_flushSector(ioman,c)){
+ return(-1);
+ }
+ if(ioman->usage[c]==0)ioman_setNotWritable(c);
+ }
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+euint8* ioman_getSector(IOManager *ioman,euint32 address, euint8 mode)
+{
+ esint32 bp;
+
+ if((bp=ioman_findSectorInCache(ioman,address))!=-1){
+ if(ioman_isReqRw(mode)){
+ ioman_setWritable(bp);
+ }
+ ioman_incUseCnt(ioman,bp);
+ if(!ioman_isReqExp(mode))ioman_incRefCnt(ioman,bp);
+ return(ioman_getPtr(ioman,bp));
+ }
+
+ if((bp=ioman_findFreeSpot(ioman))==-1){
+ if(((bp=ioman_findUnusedSpot(ioman))!=-1)&&(ioman_isWritable(bp))){
+ ioman_flushSector(ioman,bp);
+ }
+ }
+
+ if(bp!=-1){
+ ioman_resetCacheItem(ioman,bp);
+ if((ioman_putSectorInCache(ioman,address,bp))){
+ return(0);
+ }
+ if(mode==IOM_MODE_READWRITE){
+ ioman_setWritable(bp);
+ }
+ ioman_incUseCnt(ioman,bp);
+ if(!ioman_isReqExp(mode))ioman_incRefCnt(ioman,bp);
+ return(ioman_getPtr(ioman,bp));
+ }
+
+ if((bp=ioman_findOverallocableSpot(ioman))!=-1){
+ if(ioman_isWritable(bp)){
+ ioman_flushSector(ioman,bp);
+ }
+ if(ioman_push(ioman,bp)){
+ return(0);
+ }
+ ioman_resetCacheItem(ioman,bp);
+ if((ioman_putSectorInCache(ioman,address,bp))){
+ return(0);
+ }
+ if(ioman_isReqRw(mode)){
+ ioman_setWritable(bp);
+ }
+ ioman_incUseCnt(ioman,bp);
+ if(!ioman_isReqExp(mode))ioman_incRefCnt(ioman,bp);
+ return(ioman_getPtr(ioman,bp));
+ }
+ ioman_setError(ioman,IOMAN_ERR_NOMEMORY);
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ioman_releaseSector(IOManager *ioman,euint8* buf)
+{
+ euint16 bp;
+
+ bp=ioman_getBp(ioman,buf);
+ ioman_decUseCnt(ioman,bp);
+
+ if(ioman_getUseCnt(ioman,bp)==0 && ioman->itptr[bp]!=0){
+ if(ioman_isWritable(bp)){
+ ioman_flushSector(ioman,bp);
+ }
+ ioman_pop(ioman,bp);
+ ioman_putSectorInCache(ioman,ioman->sector[bp],bp);
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ioman_directSectorRead(IOManager *ioman,euint32 address, euint8* buf)
+{
+ euint8* ibuf;
+ esint16 bp;
+
+ if((bp=ioman_findSectorInCache(ioman,address))!=-1){
+ ibuf=ioman_getPtr(ioman,bp);
+ memCpy(ibuf,buf,512);
+ return(0);
+ }
+
+ if((bp=ioman_findFreeSpot(ioman))!=-1){
+ if((ioman_putSectorInCache(ioman,address,bp))){
+ return(-1);
+ }
+ ibuf=ioman_getPtr(ioman,bp);
+ memCpy(ibuf,buf,512);
+ return(0);
+ }
+
+ if(ioman_readSector(ioman,address,buf)){
+ return(-1);
+ }
+
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ioman_directSectorWrite(IOManager *ioman,euint32 address, euint8* buf)
+{
+ euint8* ibuf;
+ esint16 bp;
+
+ if((bp=ioman_findSectorInCache(ioman,address))!=-1){
+ ibuf=ioman_getPtr(ioman,bp);
+ memCpy(buf,ibuf,512);
+ ioman_setWritable(bp);
+ return(0);
+ }
+
+ if((bp=ioman_findFreeSpot(ioman))!=-1){
+ ibuf=ioman_getPtr(ioman,bp);
+ memCpy(buf,ibuf,512);
+ ioman_resetCacheItem(ioman,bp);
+ ioman->sector[bp]=address;
+ ioman_setWritable(bp);
+ ioman_setValid(bp);
+ return(0);
+ }
+
+ if(ioman_writeSector(ioman,address,buf)){
+ return(-1);
+ }
+
+ return(0);
+}
+/*****************************************************************************/
+
+void ioman_printStatus(IOManager *ioman)
+{
+ euint16 c;
+
+ //DBG((TXT("IO-Manager -- Report\n====================\n")));
+ //DBG((TXT("Buffer is %i sectors, from %p to %p\n"),
+ //ioman->numbuf,ioman->bufptr,ioman->bufptr+(ioman->numbuf*512)));
+ for(c=0;cnumbuf;c++){
+ if(ioman_isValid(c)){
+ //DBG((TXT("BP %3i\t SC %8li\t\t US %i\t RF %i\t %s %s\n"),
+ //c,ioman->sector[c],ioman_getUseCnt(ioman,c),ioman_getRefCnt(ioman,c),
+ //ioman_isUserBuf(c) ? "USRBUF" : " ",
+ //ioman_isWritable(c) ? "WRITABLE" : "READONLY"));
+ }
+ }
+}
+/*****************************************************************************/
+
diff --git a/F107/Utilities/efsl/source/ls.c b/F107/Utilities/efsl/source/ls.c
new file mode 100644
index 0000000..f17204d
--- /dev/null
+++ b/F107/Utilities/efsl/source/ls.c
@@ -0,0 +1,140 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : ls.c *
+* Description : This file contains functions to list the files in a directory *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+/*****************************************************************************/
+#include "ls.h"
+/*****************************************************************************/
+
+esint8 ls_openDir(DirList *dlist,FileSystem *fs,eint8* dirname)
+{
+ FileLocation loc;
+ euint32 fc;
+
+ dlist->fs=fs;
+
+ if(fs_findFile(dlist->fs,dirname,&loc,&fc)!=2)
+ {
+ return(-1);
+ }
+
+ fs_initClusterChain(dlist->fs,&(dlist->Cache),fc);
+ memClr(&(dlist->currentEntry),sizeof(dlist->currentEntry));
+ dlist->rEntry=0;
+ dlist->cEntry=0xFFFF;
+
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ls_getDirEntry(DirList *dlist)
+{
+ if(dlist->Cache.FirstCluster == 1){
+ return(ls_getRootAreaEntry(dlist));
+ }else if(dlist->Cache.FirstCluster){
+ return(ls_getRealDirEntry(dlist));
+ }
+ return(-1);
+}
+/*****************************************************************************/
+
+esint8 ls_getNext(DirList *dlist)
+{
+ do{
+ if(ls_getDirEntry(dlist))return(-1);
+ dlist->rEntry++;
+ }while(!ls_isValidFileEntry(&(dlist->currentEntry)));
+ dlist->cEntry++;
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ls_getRealDirEntry(DirList *dlist)
+{
+ euint8* buf;
+
+ if(dlist->Cache.FirstCluster<=1)return(-1);
+
+ if(fat_LogicToDiscCluster(dlist->fs,
+ &(dlist->Cache),
+ (dlist->rEntry)/(16 * dlist->fs->volumeId.SectorsPerCluster))){
+ return(-1);
+ }
+
+ buf = part_getSect(dlist->fs->part,
+ fs_clusterToSector(dlist->fs,dlist->Cache.DiscCluster) + (dlist->rEntry/16)%dlist->fs->volumeId.SectorsPerCluster,
+ IOM_MODE_READONLY);
+
+ /*memCpy(buf+(dlist->rEntry%16)*32,&(dlist->currentEntry),32);*/
+ ls_fileEntryToDirListEntry(dlist,buf,32*(dlist->rEntry%16));
+
+ part_relSect(dlist->fs->part,buf);
+
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ls_getRootAreaEntry(DirList *dlist)
+{
+ euint8 *buf=0;
+
+ if((dlist->fs->type != FAT12) && (dlist->fs->type != FAT16))return(-1);
+ if(dlist->rEntry>=dlist->fs->volumeId.RootEntryCount)return(-1);
+
+ buf = part_getSect(dlist->fs->part,
+ dlist->fs->FirstSectorRootDir+dlist->rEntry/16,
+ IOM_MODE_READONLY);
+ /*memCpy(buf+32*(dlist->rEntry%16),&(dlist->currentEntry),32);*/
+ ls_fileEntryToDirListEntry(dlist,buf,32*(dlist->rEntry%16));
+ part_relSect(dlist->fs->part,buf);
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 ls_isValidFileEntry(ListDirEntry *entry)
+{
+ if(entry->FileName[0] == 0 || entry->FileName[0] == 0xE5 || entry->FileName[0] == '.')return(0);
+ if((entry->Attribute&0x0F)==0x0F)return(0);
+ return(1);
+}
+/*****************************************************************************/
+
+void ls_fileEntryToDirListEntry(DirList *dlist, euint8* buf, euint16 offset)
+{
+ if(offset>480 || offset%32)return;
+
+ buf+=offset;
+ memCpy(buf+OFFSET_DE_FILENAME,dlist->currentEntry.FileName,LIST_MAXLENFILENAME);
+ dlist->currentEntry.Attribute = *(buf+OFFSET_DE_ATTRIBUTE);
+ dlist->currentEntry.FileSize = ex_getb32(buf,OFFSET_DE_FILESIZE);
+}
+/*****************************************************************************/
+
diff --git a/F107/Utilities/efsl/source/mkfs.c b/F107/Utilities/efsl/source/mkfs.c
new file mode 100644
index 0000000..d67692a
--- /dev/null
+++ b/F107/Utilities/efsl/source/mkfs.c
@@ -0,0 +1,153 @@
+/*****************************************************************************/
+/* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : mkfs.c *
+* Description : These functions are used for creating an empty filesystem. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil */
+/*****************************************************************************/
+
+/*****************************************************************************/
+#include "mkfs.h"
+/*****************************************************************************/
+
+signed short mkfs_makevfat(Partition *part)
+{
+ unsigned long c,cc,ret;
+ unsigned long ns,fs,ds,dc;
+ unsigned char buf[512];
+
+ ns=part->disc->partitions[part->activePartition].numSectors;
+
+ if( ns < 66581 ){
+ //DBG((TXT("This is not possible due to insufficient sectors. Sorry\n")));
+ return(MKFS_ERR_TOOLITTLESECTORS);
+ }
+
+ ret=0;
+
+ for(c=1<<6;c>=1;c>>=1){
+
+ /* First guess */
+ ds = ns - 32;
+ fs = ((ds/c)+127)/128;
+ /* ds was guess too large, so fs is too large now too. */
+
+ for(cc=0;cc<2;cc++){
+
+ /* Round 2, error round */
+ ds = ns - 32 - 2*fs;
+ fs = ((ds/c)+127)/128;
+ /* Since fs was too large, ds became too small. So the fs for this small ds is too small as well. */
+
+ /* Round 3, correction round */
+ ds = ns - 32 - 2*fs;
+ fs = ((ds/c)+127)/128;
+ /* The fs was too small, so ds was too large. The calculated fs should be slightly too large. */
+
+ }
+
+ /* Round 4, finalise */
+ ds = ns - 32 - 2*fs;
+
+ dc = ds / c;
+ if(ret<(fs*128-dc)/128)ret=(fs*128-dc)/128;
+
+ /* Check if with current setting we have a valid fat ? */
+
+ if(dc >= 65525 + 16){
+ break;
+ }
+ }
+
+ /* Generate BPB */
+ memClr(buf,512);
+
+ /* Boot code */
+ *(buf+0)=0xE9; *(buf+1)=0x00; *(buf+2)=0x00; /* RESET */
+
+ /* OEM name */
+ memCpy("DSCOSMSH",buf+3,8);
+
+ /* Bytes/Sector */
+ *((unsigned short*)(buf+11)) = 512;
+
+ /* Sectors/Cluster */
+ *(buf+13) = c;
+
+ /* Reserved Sectors */
+ *((unsigned short*)(buf+14)) = 32;
+
+ /* Number of FAT Tables */
+ *(buf+16) = 2;
+
+ /* RootEntryCount */
+ *((unsigned short*)(buf+17)) = 0;
+
+ /* Total Sector Count __16 */
+ *((unsigned short*)(buf+19)) = 0;
+
+ /* Media (crap) */
+ *(buf+21) = 0xF8;
+
+ /* FAT size 16 */
+ *((unsigned short*)(buf+22)) = 0;
+
+ /* Total Sector Count __32 */
+ *((unsigned long*)(buf+32)) = ns;
+
+ /* Fat Size 32 */
+ *((unsigned long*)(buf+36)) = fs;
+
+ /* First Cluster Root Dir */
+ *((unsigned long*)(buf+44)) = 2;
+
+ /* VolumeID */
+ *((unsigned long*)(buf+67)) = 0x13371337;
+
+ /* Volume Label */
+ memCpy("DISCOSMASH!",buf+71,11);
+
+ /* Filesystemtype */
+ memCpy("FAT32 ",buf+82,8);
+
+ /* Magic */
+ *(buf+510) = 0x55; *(buf+511) = 0xAA;
+
+ part_writeBuf(part,0,buf);
+
+ memClr(buf,512);
+ for(c=32;c<(32+2*fs);c++){
+ part_writeBuf(part,c,buf);
+ }
+ *(((unsigned long*)buf) )=0x0FFFFFF8;
+ *(((unsigned long*)buf)+1)=0x0FFFFFFF;
+ *(((unsigned long*)buf)+2)=0x0FFFFFF8;
+ part_writeBuf(part,32,buf);
+ part_writeBuf(part,32+fs,buf);
+
+ return(0);
+}
diff --git a/F107/Utilities/efsl/source/partition.c b/F107/Utilities/efsl/source/partition.c
new file mode 100644
index 0000000..9ff09c6
--- /dev/null
+++ b/F107/Utilities/efsl/source/partition.c
@@ -0,0 +1,153 @@
+
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : partition.c *
+* Description : These functions are partition specific. Searching FAT type *
+* partitions and read/write functions to partitions. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/*****************************************************************************/
+#include "partition.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * void part_initPartition(Partition *part,Disc* refDisc)
+ * Description: This function searches the 4 partitions for a FAT class partition
+ * and marks the first one found as the active to be used partition.
+*/
+void part_initPartition(Partition *part,Disc* refDisc)
+{
+ eint16 c;
+
+ part->disc=refDisc;
+ part->activePartition=-1; /* No partition selected */
+ part_setError(part,PART_NOERROR);
+ for(c=3;c>=0;c--){
+ if(part_isFatPart(part->disc->partitions[c].type))
+ part->activePartition=c;
+ }
+}
+/*****************************************************************************/
+
+
+/* ****************************************************************************
+ * eint16 part_isFatPart(euint8 type)
+ * Description: This functions checks if a partitiontype (eint8) is of the FAT
+ * type in the broadest sense. I
+ * Return value: If it is FAT, returns 1, otherwise 0.
+*/
+eint16 part_isFatPart(euint8 type)
+{
+ if(type == PT_FAT12 ||
+ type == PT_FAT16A ||
+ type == PT_FAT16 ||
+ type == PT_FAT32 ||
+ type == PT_FAT32A ||
+ type == PT_FAT16B )
+ {
+ return(1);
+ }
+ return(0);
+}
+/*****************************************************************************/
+
+esint8 part_readBuf(Partition *part, euint32 address, euint8* buf)
+{
+ return(if_readBuf(part->disc->ioman->iface,part_getRealLBA(part,address), buf));
+}
+
+/* ****************************************************************************
+ * eint16 part_writeBuf(Partition *part,euint32 address,euint8* buf)
+ * Description: This function writes 512 bytes, from buf. It's offset is address
+ * sectors from the beginning of the partition.
+ * Return value: It returns whatever the hardware function returns. (-1=error)
+*/
+eint16 part_writeBuf(Partition *part,euint32 address,euint8* buf)
+{
+ /*DBG((TXT("part_writeBuf :: %li\n"),address));*/
+ return(if_writeBuf(part->disc->ioman->iface,part_getRealLBA(part,address),buf));
+}
+/*****************************************************************************/
+
+
+/* ****************************************************************************
+ * euint32 part_getRealLBA(Partition *part,euint32 address)
+ * Description: This function calculates what the partition offset for
+ * a partition is + the address.
+ * Return value: Sector address.
+*/
+euint32 part_getRealLBA(Partition *part,euint32 address)
+{
+ return(part->disc->partitions[part->activePartition].LBA_begin+address);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * euint8* part_getSect(Partition *part, euint32 address, euint8 mode)
+ * Description: This function calls ioman_getSector, but recalculates the sector
+ * address to be partition relative.
+ * Return value: Whatever getSector returns. (pointer or 0)
+*/
+euint8* part_getSect(Partition *part, euint32 address, euint8 mode)
+{
+ return(ioman_getSector(part->disc->ioman,part_getRealLBA(part,address),mode));
+}
+
+/* ****************************************************************************
+ * esint8 part_relSect(Partition *part, euint8* buf)
+ * Description: This function calls ioman_releaseSector.
+ * Return value: Whatever releaseSector returns.
+*/
+esint8 part_relSect(Partition *part, euint8* buf)
+{
+ return(ioman_releaseSector(part->disc->ioman,buf));
+}
+
+esint8 part_flushPart(Partition *part,euint32 addr_l, euint32 addr_h)
+{
+ return(
+ ioman_flushRange(part->disc->ioman,part_getRealLBA(part,addr_l),part_getRealLBA(part,addr_h))
+ );
+}
+
+esint8 part_directSectorRead(Partition *part,euint32 address, euint8* buf)
+{
+ return(
+ ioman_directSectorRead(part->disc->ioman,part_getRealLBA(part,address),buf)
+ );
+}
+
+esint8 part_directSectorWrite(Partition *part,euint32 address, euint8* buf)
+{
+ return(
+ ioman_directSectorWrite(part->disc->ioman,part_getRealLBA(part,address),buf)
+ );
+}
+
+
diff --git a/F107/Utilities/efsl/source/plibc.c b/F107/Utilities/efsl/source/plibc.c
new file mode 100644
index 0000000..85bd558
--- /dev/null
+++ b/F107/Utilities/efsl/source/plibc.c
@@ -0,0 +1,83 @@
+
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : plibc.c *
+* Description : This file contains replacements of common c library functions *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/*****************************************************************************/
+#include "plibc.h"
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * unsigned short strMatch(char* bufa, char*bufb, unsigned long n)
+ * Description: Compares bufa and bufb for a length of n bytes.
+ * Return value: Returns the number of character NOT matching.
+*/
+euint16 strMatch(eint8* bufa, eint8*bufb,euint32 n)
+{
+ euint32 c;
+ euint16 res=0;
+ for(c=0;c0){
+ *((eint8*)pdest+size-1)=*((eint8*)psrc+size-1);
+ size--;
+ }
+}
+/*****************************************************************************/
+
+void memClr(void *pdest,euint32 size)
+{
+ while(size>0){
+ *(((eint8*)pdest)+size-1)=0x00;
+ size--;
+ }
+}
+
+void memSet(void *pdest,euint32 size,euint8 data)
+{
+ while(size>0){
+ *(((eint8*)pdest)+size-1)=data;
+ size--;
+ }
+}
+
+
diff --git a/F107/Utilities/efsl/source/time.c b/F107/Utilities/efsl/source/time.c
new file mode 100644
index 0000000..0f84c92
--- /dev/null
+++ b/F107/Utilities/efsl/source/time.c
@@ -0,0 +1,57 @@
+
+/*****************************************************************************/
+#include "time.h"
+/*****************************************************************************/
+
+euint16 fs_makeDate(void)
+{
+#ifndef DATE_TIME_SUPPORT
+ return(0);
+#else
+ euint8 m,d;
+ euint16 y;
+
+ y = time_getYear()-1980;
+ m = time_getMonth();
+ d = time_getDay();
+
+ return(
+ (y>127?127<<9:(y&0x3F)<<9) |
+ ((m==0||m>12)?1:(m&0xF)<<5) |
+ ((d==0||d>31)?1:(d&0x1F))
+ );
+#endif
+}
+/*****************************************************************************/
+
+euint16 fs_makeTime(void)
+{
+#ifndef DATE_TIME_SUPPORT
+ return(0);
+#else
+ euint8 s,m,h;
+
+ s = time_getSecond();
+ m = time_getMinute();
+ h = time_getHour();
+
+ return(
+ (h>23?0:(h&0x1F)<<11) |
+ (m>59?0:(m&0x3F)<<5) |
+ (s>59?0:(s-s%2)/2)
+ );
+#endif
+}
+/*****************************************************************************/
+
+euint8 fs_hasTimeSupport(void)
+{
+#ifdef DATE_TIME_SUPPORT
+ return(1);
+#else
+ return(0);
+#endif
+}
+/*****************************************************************************/
+
+
diff --git a/F107/Utilities/efsl/source/ui.c b/F107/Utilities/efsl/source/ui.c
new file mode 100644
index 0000000..cce9fef
--- /dev/null
+++ b/F107/Utilities/efsl/source/ui.c
@@ -0,0 +1,230 @@
+/*****************************************************************************\
+* efs - General purpose Embedded Filesystem library *
+* --------------------- ----------------------------------- *
+* *
+* Filename : ui.c *
+* Description : This file contains functions which will be presented to the *
+* user of this library. *
+* *
+* This program is free software; you can redistribute it and/or *
+* modify it under the terms of the GNU General Public License *
+* as published by the Free Software Foundation; version 2 *
+* of the License. *
+ *
+* This program is distributed in the hope that it will be useful, *
+* but WITHOUT ANY WARRANTY; without even the implied warranty of *
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+* GNU General Public License for more details. *
+* *
+* As a special exception, if other files instantiate templates or *
+* use macros or inline functions from this file, or you compile this *
+* file and link it with other works to produce a work based on this file, *
+* this file does not by itself cause the resulting work to be covered *
+* by the GNU General Public License. However the source code for this *
+* file must still be made available in accordance with section (3) of *
+* the GNU General Public License. *
+* *
+* This exception does not invalidate any other reasons why a work based *
+* on this file might be covered by the GNU General Public License. *
+* *
+* (c)2006 Lennart Yseboodt *
+* (c)2006 Michael De Nil *
+\*****************************************************************************/
+
+/*****************************************************************************/
+#include "ui.h"
+/*****************************************************************************/
+
+/*****************************************************************************
+ * short listfiles(char *dir)
+ *
+ * Deschription: This function returns the number of files / directories
+ * inside the given directory.
+ *
+ * Return value: number of files/directories in the given directory or -1
+ * if directory does not exist.
+\*****************************************************************************/
+
+short listFiles(FileSystem *fs, char *dirname)
+{
+ unsigned long startCluster;
+ unsigned char fileEntryCount;
+ unsigned short counter=0;
+ unsigned long offset=0;
+ FileRecord fileEntry;
+ FileLocation loc;
+ unsigned char buf[512];
+ File dir;
+ unsigned short i;
+
+ /* Find out if we are searching in the root dir or in */
+ if(dirname[0]=='/' && dirname[1]=='\0')
+ {
+ if( (fs->type == FAT12) || (fs->type == FAT16) )
+ {
+ for(i=0;i<=(fs->volumeId.RootEntryCount/16);i++)
+ {
+ loc.Sector=fs->FirstSectorRootDir + i;
+ part_readBuf(fs->part,loc.Sector,buf);
+ /* I STOPPED HERE*/
+ /* FIXME */
+ }
+ }
+ }
+ else /* Normal directory */
+ {
+ /* Check if path given is a directory */
+ if(fs_findFile(fs,dirname,&loc,0)!=2)
+ {
+ FUNC_OUT((TXT("")));
+ return(-1);
+ }
+
+ /* Find out what the startcluster of the directory is */
+ part_readBuf(fs->part,loc.Sector, buf);
+ fileEntry = *(((FileRecord*)buf) + loc.Offset);
+ startCluster = (((unsigned long)fileEntry.FirstClusterHigh)<<16)
+ + fileEntry.FirstClusterLow;
+
+ /* Init of dir */
+ dir.fs=fs;
+ dir.Cache.LogicCluster=-1;
+ dir.Cache.FirstCluster=startCluster;
+ dir.DirEntry.Attribute=ATTR_DIRECTORY;
+
+ while((file_fread(&dir,offset,512,buf)))
+ {
+ //DBG((TXT("Read 512 bytes from dir with offset %li.\n"),offset));
+ for(fileEntryCount=0;fileEntryCount<16;fileEntryCount++)
+ {
+ fileEntry = *(((FileRecord*)buf) + fileEntryCount);
+ if( !( (fileEntry.Attribute & 0x0F) == 0x0F ) )
+ {
+ if
+ (
+ (fileEntry.FileName[0]>='A' && fileEntry.FileName[0]<='Z')
+ ||
+ (fileEntry.FileName[0]>='0' && fileEntry.FileName[0]<='9')
+ )
+ {
+ //DBG((TXT("Filename: %s\n"),fileEntry.FileName));
+ counter++;
+ }
+ }
+ }
+ offset+=512;
+ }
+ }
+
+ FUNC_OUT((TXT("")));
+ return(counter);
+
+ //return(-1);
+}
+/*****************************************************************************/
+
+/* ****************************************************************************
+ * esint16 rmfile(FileSystem *fs,euint8* filename)
+ * Description: This function takes a filename as argument and deletes it,
+ * by freeing it's clusterchain, and deleting it's entry from the directory.
+ * Return value: 0 on success, -1 on errors, like file not found.
+*/
+esint16 rmfile(FileSystem *fs,euint8* filename)
+{
+ FileLocation loc;
+ ClusterChain cache;
+ euint8* buf;
+ euint32 firstCluster=0;
+
+ if((fs_findFile(fs,(eint8*)filename,&loc,0))==1){
+ buf=part_getSect(fs->part,loc.Sector,IOM_MODE_READWRITE);
+ firstCluster = ex_getb16(buf,loc.Offset*32+20);
+ firstCluster <<= 16;
+ firstCluster += ex_getb16(buf,loc.Offset*32+26);
+ /* Bugfix:
+ * By clearing the entire structure, you mark end of directory.
+ * If this is not the case, files that are further away cannot
+ * be opened anymore by implementations that follow the spec. */
+ /*memClr(buf+(loc.Offset*32),32);*/
+ *(buf+(loc.Offset*32)+0) = 0xE5; /* Mark file deleted */
+ part_relSect(fs->part,buf);
+ cache.DiscCluster = cache.LastCluster = cache.Linear = cache.LogicCluster = 0;
+ cache.FirstCluster = firstCluster;
+ fat_unlinkClusterChain(fs,&cache);
+ return(0);
+ }
+ return(-1);
+}
+
+/*****************************************************************************/
+esint8 mkdir(FileSystem *fs,eint8* dirname)
+{
+ FileLocation loc;
+ FileRecord direntry;
+ euint32 nc,parentdir;
+ euint8* buf;
+ eint8 ffname[11];
+
+ if( fs_findFile(fs,dirname,&loc,&parentdir) ){
+ return(-1);
+ }
+ if(parentdir==0)return(-2);
+
+ if(!fs_findFreeFile(fs,dirname,&loc,0))return(-3);
+
+ /* You may never search for a free cluster, and the call
+ * functions that may cause changes to the FAT table, that
+ * is why getNextFreeCluster has to be called AFTER calling
+ * fs_findFreeFile, which may have to expand a directory in
+ * order to store the new filerecord !!
+ */
+
+ nc = fs_getNextFreeCluster(fs,fs_giveFreeClusterHint(fs));
+ if(nc==0)return(0);
+
+ fs_clearCluster(fs,nc);
+
+ buf = part_getSect(fs->part,loc.Sector,IOM_MODE_READWRITE);
+
+ dir_getFatFileName(dirname,ffname);
+ memClr(&direntry,sizeof(direntry));
+ memCpy(ffname,&direntry,11);
+ direntry.FileSize = 0;
+ direntry.FirstClusterHigh=nc>>16;
+ direntry.FirstClusterLow=nc&0xFFFF;
+ direntry.Attribute = ATTR_DIRECTORY;
+ memCpy(&direntry,buf+(32*loc.Offset),32);
+
+ part_relSect(fs->part,buf);
+
+ buf = part_getSect(fs->part,fs_clusterToSector(fs,nc),IOM_MODE_READWRITE);
+
+ memClr(&direntry,sizeof(direntry));
+ memCpy(". ",&direntry,11);
+ direntry.Attribute = ATTR_DIRECTORY;
+ direntry.FileSize = 0;
+ direntry.FirstClusterHigh=nc>>16;
+ direntry.FirstClusterLow=nc&0xFFFF;
+ memCpy(&direntry,buf,32);
+
+ if(fs->type == FAT32 && parentdir == fs->volumeId.RootCluster){
+ parentdir = 0;
+ }
+ if(fs->type != FAT32 && parentdir<=1){
+ parentdir = 0;
+ }
+
+ memClr(&direntry,sizeof(direntry));
+ memCpy(".. ",&direntry,11);
+ direntry.Attribute = ATTR_DIRECTORY;
+ direntry.FileSize = 0;
+ direntry.FirstClusterHigh=parentdir>>16;
+ direntry.FirstClusterLow=parentdir&0xFFFF;
+ memCpy(&direntry,buf+32,32);
+
+ part_relSect(fs->part,buf);
+
+ fat_setNextClusterAddress(fs,nc,fat_giveEocMarker(fs));
+
+ return(0);
+}
diff --git a/F107/Utilities/lwip-1.3.1/CHANGELOG b/F107/Utilities/lwip-1.3.1/CHANGELOG
new file mode 100644
index 0000000..a457650
--- /dev/null
+++ b/F107/Utilities/lwip-1.3.1/CHANGELOG
@@ -0,0 +1,2248 @@
+FUTURE
+
+ * TODO: The lwIP source code makes some invalid assumptions on processor
+ word-length, storage sizes and alignment. See the mailing lists for
+ problems with exoteric (/DSP) architectures showing these problems.
+ We still have to fix some of these issues neatly.
+
+ * TODO: the PPP code is broken in a few ways. There are namespace
+ collisions on BSD systems and many assumptions on word-length
+ (sizeof(int)). In ppp.c an assumption is made on the availability of
+ a thread subsystem. Either PPP needs to be moved to contrib/ports/???
+ or rearranged to be more generic.
+
+HISTORY
+
+(CVS HEAD)
+
+ * [Enter new changes just after this line - do not remove this line]
+
+ ++ New features:
+
+ ++ Bugfixes:
+
+
+(STABLE-1.3.1)
+
+ ++ New features:
+
+ 2009-05-10 Simon Goldschmidt
+ * opt.h, sockets.c, pbuf.c, netbuf.h, pbuf.h: task #7013: Added option
+ LWIP_NETIF_TX_SINGLE_PBUF to try to create transmit packets from only
+ one pbuf to help MACs that don't support scatter-gather DMA.
+
+ 2009-05-09 Simon Goldschmidt
+ * icmp.h, icmp.c: Shrinked ICMP code, added option to NOT check icoming
+ ECHO pbuf for size (just use it): LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
+
+ 2009-05-05 Simon Goldschmidt, Jakob Stoklund Olesen
+ * ip.h, ip.c: Added ip_current_netif() & ip_current_header() to receive
+ extended info about the currently received packet.
+
+ 2009-04-27 Simon Goldschmidt
+ * sys.h: Made SYS_LIGHTWEIGHT_PROT and sys_now() work with NO_SYS=1
+
+ 2009-04-25 Simon Goldschmidt
+ * mem.c, opt.h: Added option MEM_USE_POOLS_TRY_BIGGER_POOL to try the next
+ bigger malloc pool if one is empty (only usable with MEM_USE_POOLS).
+
+ 2009-04-21 Simon Goldschmidt
+ * dns.c, init.c, dns.h, opt.h: task #7507, patch #6786: DNS supports static
+ hosts table. New configuration options DNS_LOCAL_HOSTLIST and
+ DNS_LOCAL_HOSTLIST_IS_DYNAMIC. Also, DNS_LOOKUP_LOCAL_EXTERN() can be defined
+ as an external function for lookup.
+
+ 2009-04-15 Simon Goldschmidt
+ * dhcp.c: patch #6763: Global DHCP XID can be redefined to something more unique
+
+ 2009-03-31 Kieran Mansley
+ * tcp.c, tcp_out.c, tcp_in.c, sys.h, tcp.h, opts.h: add support for
+ TCP timestamp options, off by default. Rework tcp_enqueue() to
+ take option flags rather than specified option data
+
+ 2009-02-18 Simon Goldschmidt
+ * cc.h: Added printf formatter for size_t: SZT_F
+
+ 2009-02-16 Simon Goldschmidt (patch by Rishi Khan)
+ * icmp.c, opt.h: patch #6539: (configurable) response to broadcast- and multicast
+ pings
+
+ 2009-02-12 Simon Goldschmidt
+ * init.h: Added LWIP_VERSION to get the current version of the stack
+
+ 2009-02-11 Simon Goldschmidt (suggested by Gottfried Spitaler)
+ * opt.h, memp.h/.c: added MEMP_MEM_MALLOC to use mem_malloc/mem_free instead
+ of the pool allocator (can save code size with MEM_LIBC_MALLOC if libc-malloc
+ is otherwise used)
+
+ 2009-01-28 Jonathan Larmour (suggested by Bill Bauerbach)
+ * ipv4/inet_chksum.c, ipv4/lwip/inet_chksum.h: inet_chksum_pseudo_partial()
+ is only used by UDPLITE at present, so conditionalise it.
+
+ 2008-12-03 Simon Goldschmidt (base on patch from Luca Ceresoli)
+ * autoip.c: checked in (slightly modified) patch #6683: Customizable AUTOIP
+ "seed" address. This should reduce AUTOIP conflicts if
+ LWIP_AUTOIP_CREATE_SEED_ADDR is overridden.
+
+ 2008-10-02 Jonathan Larmour and Rishi Khan
+ * sockets.c (lwip_accept): Return EWOULDBLOCK if would block on non-blocking
+ socket.
+
+ 2008-06-30 Simon Goldschmidt
+ * mem.c, opt.h, stats.h: fixed bug #21433: Calling mem_free/pbuf_free from
+ interrupt context isn't safe: LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT allows
+ mem_free to run between mem_malloc iterations. Added illegal counter for
+ mem stats.
+
+ 2008-06-27 Simon Goldschmidt
+ * stats.h/.c, some other files: patch #6483: stats module improvement:
+ Added defines to display each module's statistic individually, added stats
+ defines for MEM, MEMP and SYS modules, removed (unused) rexmit counter.
+
+ 2008-06-17 Simon Goldschmidt
+ * err.h: patch #6459: Made err_t overridable to use a more efficient type
+ (define LWIP_ERR_T in cc.h)
+
+ 2008-06-17 Simon Goldschmidt
+ * slipif.c: patch #6480: Added a configuration option for slipif for symmetry
+ to loopif
+
+ 2008-06-17 Simon Goldschmidt (patch by Luca Ceresoli)
+ * netif.c, loopif.c, ip.c, netif.h, loopif.h, opt.h: Checked in slightly
+ modified version of patch # 6370: Moved loopif code to netif.c so that
+ loopback traffic is supported on all netifs (all local IPs).
+ Added option to limit loopback packets for each netifs.
+
+
+ ++ Bugfixes:
+ 2009-08-12 Kieran Mansley
+ * tcp_in.c, tcp.c: Fix bug #27209: handle trimming of segments when
+ out of window or out of order properly
+
+ 2009-08-12 Kieran Mansley
+ * tcp_in.c: Fix bug #27199: use snd_wl2 instead of snd_wl1
+
+ 2009-07-28 Simon Goldschmidt
+ * mem.h: Fixed bug #27105: "realloc() cannot replace mem_realloc()"s
+
+ 2009-07-27 Kieran Mansley
+ * api.h api_msg.h netdb.h sockets.h: add missing #include directives
+
+ 2009-07-09 Kieran Mansley
+ * api_msg.c, sockets.c, api.h: BUG23240 use signed counters for
+ recv_avail and don't increment counters until message successfully
+ sent to mbox
+
+ 2009-06-25 Kieran Mansley
+ * api_msg.c api.h: BUG26722: initialise netconn write variables
+ in netconn_alloc
+
+ 2009-06-25 Kieran Mansley
+ * tcp.h: BUG26879: set ret value in TCP_EVENT macros when function is not set
+
+ 2009-06-25 Kieran Mansley
+ * tcp.c, tcp_in.c, tcp_out.c, tcp.h: BUG26301 and BUG26267: correct
+ simultaneous close behaviour, and make snd_nxt have the same meaning
+ as in the RFCs.
+
+ 2009-05-12 Simon Goldschmidt
+ * etharp.h, etharp.c, netif.c: fixed bug #26507: "Gratuitous ARP depends on
+ arp_table / uses etharp_query" by adding etharp_gratuitous()
+
+ 2009-05-12 Simon Goldschmidt
+ * ip.h, ip.c, igmp.c: bug #26487: Added ip_output_if_opt that can add IP options
+ to the IP header (used by igmp_ip_output_if)
+
+ 2009-05-06 Simon Goldschmidt
+ * inet_chksum.c: On little endian architectures, use LWIP_PLATFORM_HTONS (if
+ defined) for SWAP_BYTES_IN_WORD to speed up checksumming.
+
+ 2009-05-05 Simon Goldschmidt
+ * sockets.c: bug #26405: Prematurely released semaphore causes lwip_select()
+ to crash
+
+ 2009-05-04 Simon Goldschmidt
+ * init.c: snmp was not initialized in lwip_init()
+
+ 2009-05-04 Fr閐閞ic Bernon
+ * dhcp.c, netbios.c: Changes if IP_SOF_BROADCAST is enabled.
+
+ 2009-05-03 Simon Goldschmidt
+ * tcp.h: bug #26349: Nagle algorithm doesn't send although segment is full
+ (and unsent->next == NULL)
+
+ 2009-05-02 Simon Goldschmidt
+ * tcpip.h, tcpip.c: fixed tcpip_untimeout (does not need the time, broken after
+ 1.3.0 in CVS only) - fixes compilation of ppp_oe.c
+
+ 2009-05-02 Simon Goldschmidt
+ * msg_in.c: fixed bug #25636: SNMPSET value is ignored for integer fields
+
+ 2009-05-01 Simon Goldschmidt
+ * pap.c: bug #21680: PPP upap_rauthnak() drops legal NAK packets
+
+ 2009-05-01 Simon Goldschmidt
+ * ppp.c: bug #24228: Memory corruption with PPP and DHCP
+
+ 2009-04-29 Fr閐閞ic Bernon
+ * raw.c, udp.c, init.c, opt.h, ip.h, sockets.h: bug #26309: Implement the
+ SO(F)_BROADCAST filter for all API layers. Avoid the unindented reception
+ of broadcast packets even when this option wasn't set. Port maintainers
+ which want to enable this filter have to set IP_SOF_BROADCAST=1 in opt.h.
+ If you want this option also filter broadcast on recv operations, you also
+ have to set IP_SOF_BROADCAST_RECV=1 in opt.h.
+
+ 2009-04-28 Simon Goldschmidt, Jakob Stoklund Olesen
+ * dhcp.c: patch #6721, bugs #25575, #25576: Some small fixes to DHCP and
+ DHCP/AUTOIP cooperation
+
+ 2009-04-25 Simon Goldschmidt, Oleg Tyshev
+ * tcp_out.c: bug #24212: Deadlocked tcp_retransmit due to exceeded pcb->cwnd
+ Fixed by sorting the unsent and unacked queues (segments are inserted at the
+ right place in tcp_output and tcp_rexmit).
+
+ 2009-04-25 Simon Goldschmidt
+ * memp.c, mem.c, memp.h, mem_std.h: bug #26213 "Problem with memory allocation
+ when debugging": memp_sizes contained the wrong sizes (including sanity
+ regions); memp pools for MEM_USE_POOLS were too small
+
+ 2009-04-24 Simon Goldschmidt, Fr閐閞ic Bernon
+ * inet.c: patch #6765: Fix a small problem with the last changes (incorrect
+ behavior, with with ip address string not ended by a '\0', a space or a
+ end of line)
+
+ 2009-04-19 Simon Goldschmidt
+ * rawapi.txt: Fixed bug #26069: Corrected documentation: if tcp_connect fails,
+ pcb->err is called, not pcb->connected (with an error code).
+
+ 2009-04-19 Simon Goldschmidt
+ * tcp_out.c: Fixed bug #26236: "TCP options (timestamp) don't work with
+ no-copy-tcpwrite": deallocate option data, only concat segments with same flags
+
+ 2009-04-19 Simon Goldschmidt
+ * tcp_out.c: Fixed bug #25094: "Zero-length pbuf" (options are now allocated
+ in the header pbuf, not the data pbuf)
+
+ 2009-04-18 Simon Goldschmidt
+ * api_msg.c: fixed bug #25695: Segmentation fault in do_writemore()
+
+ 2009-04-15 Simon Goldschmidt
+ * sockets.c: tried to fix bug #23559: lwip_recvfrom problem with tcp
+
+ 2009-04-15 Simon Goldschmidt
+ * dhcp.c: task #9192: mem_free of dhcp->options_in and dhcp->msg_in
+
+ 2009-04-15 Simon Goldschmidt
+ * ip.c, ip6.c, tcp_out.c, ip.h: patch #6808: Add a utility function
+ ip_hinted_output() (for smaller code mainly)
+
+ 2009-04-15 Simon Goldschmidt
+ * inet.c: patch #6765: Supporting new line characters in inet_aton()
+
+ 2009-04-15 Simon Goldschmidt
+ * dhcp.c: patch #6764: DHCP rebind and renew did not send hostnam option;
+ Converted constant OPTION_MAX_MSG_SIZE to netif->mtu, check if netif->mtu
+ is big enough in dhcp_start
+
+ 2009-04-15 Simon Goldschmidt
+ * netbuf.c: bug #26027: netbuf_chain resulted in pbuf memory leak
+
+ 2009-04-15 Simon Goldschmidt
+ * sockets.c, ppp.c: bug #25763: corrected 4 occurrences of SMEMCPY to MEMCPY
+
+ 2009-04-15 Simon Goldschmidt
+ * sockets.c: bug #26121: set_errno can be overridden
+
+ 2009-04-09 Kieran Mansley (patch from Luca Ceresoli )
+ * init.c, opt.h: Patch#6774 TCP_QUEUE_OOSEQ breaks compilation when
+ LWIP_TCP==0
+
+ 2009-04-09 Kieran Mansley (patch from Roy Lee )
+ * tcp.h: Patch#6802 Add do-while-clauses to those function like
+ macros in tcp.h
+
+ 2009-03-31 Kieran Mansley
+ * tcp.c, tcp_in.c, tcp_out.c, tcp.h, opt.h: Rework the way window
+ updates are calculated and sent (BUG20515)
+
+ * tcp_in.c: cope with SYN packets received during established states,
+ and retransmission of initial SYN.
+
+ * tcp_out.c: set push bit correctly when tcp segments are merged
+
+ 2009-03-27 Kieran Mansley
+ * tcp_out.c set window correctly on probes (correcting change made
+ yesterday)
+
+ 2009-03-26 Kieran Mansley
+ * tcp.c, tcp_in.c, tcp.h: add tcp_abandon() to cope with dropping
+ connections where no reset required (bug #25622)
+
+ * tcp_out.c: set TCP_ACK flag on keepalive and zero window probes
+ (bug #20779)
+
+ 2009-02-18 Simon Goldschmidt (Jonathan Larmour and Bill Auerbach)
+ * ip_frag.c: patch #6528: the buffer used for IP_FRAG_USES_STATIC_BUF could be
+ too small depending on MEM_ALIGNMENT
+
+ 2009-02-16 Simon Goldschmidt
+ * sockets.h/.c, api_*.h/.c: fixed arguments of socket functions to match the standard;
+ converted size argument of netconn_write to 'size_t'
+
+ 2009-02-16 Simon Goldschmidt
+ * tcp.h, tcp.c: fixed bug #24440: TCP connection close problem on 64-bit host
+ by moving accept callback function pointer to TCP_PCB_COMMON
+
+ 2009-02-12 Simon Goldschmidt
+ * dhcp.c: fixed bug #25345 (DHCPDECLINE is sent with "Maximum message size"
+ option)
+
+ 2009-02-11 Simon Goldschmidt
+ * dhcp.c: fixed bug #24480 (releasing old udp_pdb and pbuf in dhcp_start)
+
+ 2009-02-11 Simon Goldschmidt
+ * opt.h, api_msg.c: added configurable default valud for netconn->recv_bufsize:
+ RECV_BUFSIZE_DEFAULT (fixes bug #23726: pbuf pool exhaustion on slow recv())
+
+ 2009-02-10 Simon Goldschmidt
+ * tcp.c: fixed bug #25467: Listen backlog is not reset on timeout in SYN_RCVD:
+ Accepts_pending is decrease on a corresponding listen pcb when a connection
+ in state SYN_RCVD is close.
+
+ 2009-01-28 Jonathan Larmour
+ * pbuf.c: reclaim pbufs from TCP out-of-sequence segments if we run
+ out of pool pbufs.
+
+ 2008-12-19 Simon Goldschmidt
+ * many files: patch #6699: fixed some warnings on platform where sizeof(int) == 2
+
+ 2008-12-10 Tamas Somogyi, Fr閐閞ic Bernon
+ * sockets.c: fixed bug #25051: lwip_recvfrom problem with udp: fromaddr and
+ port uses deleted netbuf.
+
+ 2008-10-18 Simon Goldschmidt
+ * tcp_in.c: fixed bug ##24596: Vulnerability on faulty TCP options length
+ in tcp_parseopt
+
+ 2008-10-15 Simon Goldschmidt
+ * ip_frag.c: fixed bug #24517: IP reassembly crashes on unaligned IP headers
+ by packing the struct ip_reass_helper.
+
+ 2008-10-03 David Woodhouse, Jonathan Larmour
+ * etharp.c (etharp_arp_input): Fix type aliasing problem copying ip address.
+
+ 2008-10-02 Jonathan Larmour
+ * dns.c: Hard-code structure sizes, to avoid issues on some compilers where
+ padding is included.
+
+ 2008-09-30 Jonathan Larmour
+ * sockets.c (lwip_accept): check addr isn't NULL. If it's valid, do an
+ assertion check that addrlen isn't NULL.
+
+ 2008-09-30 Jonathan Larmour
+ * tcp.c: Fix bug #24227, wrong error message in tcp_bind.
+
+ 2008-08-26 Simon Goldschmidt
+ * inet.h, ip_addr.h: fixed bug #24132: Cross-dependency between ip_addr.h and
+ inet.h -> moved declaration of struct in_addr from ip_addr.h to inet.h
+
+ 2008-08-14 Simon Goldschmidt
+ * api_msg.c: fixed bug #23847: do_close_internal references freed memory (when
+ tcp_close returns != ERR_OK)
+
+ 2008-07-08 Fr閐閞ic Bernon
+ * stats.h: Fix some build bugs introduced with patch #6483 (missing some parameters
+ in macros, mainly if MEM_STATS=0 and MEMP_STATS=0).
+
+ 2008-06-24 Jonathan Larmour
+ * tcp_in.c: Fix for bug #23693 as suggested by Art R. Ensure cseg is unused
+ if tcp_seg_copy fails.
+
+ 2008-06-17 Simon Goldschmidt
+ * inet_chksum.c: Checked in some ideas of patch #6460 (loop optimizations)
+ and created defines for swapping bytes and folding u32 to u16.
+
+ 2008-05-30 Kieran Mansley
+ * tcp_in.c Remove redundant "if" statement, and use real rcv_wnd
+ rather than rcv_ann_wnd when deciding if packets are in-window.
+ Contributed by
+
+ 2008-05-30 Kieran Mansley
+ * mem.h: Fix BUG#23254. Change macro definition of mem_* to allow
+ passing as function pointers when MEM_LIBC_MALLOC is defined.
+
+ 2008-05-09 Jonathan Larmour
+ * err.h, err.c, sockets.c: Fix bug #23119: Reorder timeout error code to
+ stop it being treated as a fatal error.
+
+ 2008-04-15 Simon Goldschmidt
+ * dhcp.c: fixed bug #22804: dhcp_stop doesn't clear NETIF_FLAG_DHCP
+ (flag now cleared)
+
+ 2008-03-27 Simon Goldschmidt
+ * mem.c, tcpip.c, tcpip.h, opt.h: fixed bug #21433 (Calling mem_free/pbuf_free
+ from interrupt context isn't safe): set LWIP_USE_HEAP_FROM_INTERRUPT to 1
+ in lwipopts.h or use pbuf_free_callback(p)/mem_free_callback(m) to free pbufs
+ or heap memory from interrupt context
+
+ 2008-03-26 Simon Goldschmidt
+ * tcp_in.c, tcp.c: fixed bug #22249: division by zero could occur if a remote
+ host sent a zero mss as TCP option.
+
+
+(STABLE-1.3.0)
+
+ ++ New features:
+
+ 2008-03-10 Jonathan Larmour
+ * inet_chksum.c: Allow choice of one of the sample algorithms to be
+ made from lwipopts.h. Fix comment on how to override LWIP_CHKSUM.
+
+ 2008-01-22 Fr閐閞ic Bernon
+ * tcp.c, tcp_in.c, tcp.h, opt.h: Rename LWIP_CALCULATE_EFF_SEND_MSS in
+ TCP_CALCULATE_EFF_SEND_MSS to have coherent TCP options names.
+
+ 2008-01-14 Fr閐閞ic Bernon
+ * rawapi.txt, api_msg.c, tcp.c, tcp_in.c, tcp.h: changes for task #7675 "Enable
+ to refuse data on a TCP_EVENT_RECV call". Important, behavior changes for the
+ tcp_recv callback (see rawapi.txt).
+
+ 2008-01-14 Fr閐閞ic Bernon, Marc Chaland
+ * ip.c: Integrate patch #6369" ip_input : checking before realloc".
+
+ 2008-01-12 Fr閐閞ic Bernon
+ * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+ netconn::sem per netconn::op_completed like suggested for the task #7490
+ "Add return value to sys_mbox_post".
+
+ 2008-01-12 Fr閐閞ic Bernon
+ * api_msg.c, opt.h: replace DEFAULT_RECVMBOX_SIZE per DEFAULT_TCP_RECVMBOX_SIZE,
+ DEFAULT_UDP_RECVMBOX_SIZE and DEFAULT_RAW_RECVMBOX_SIZE (to optimize queues
+ sizes), like suggested for the task #7490 "Add return value to sys_mbox_post".
+
+ 2008-01-10 Fr閐閞ic Bernon
+ * tcpip.h, tcpip.c: add tcpip_callback_with_block function for the task #7490
+ "Add return value to sys_mbox_post". tcpip_callback is always defined as
+ "blocking" ("block" parameter = 1).
+
+ 2008-01-10 Fr閐閞ic Bernon
+ * tcpip.h, tcpip.c, api.h, api_lib.c, api_msg.c, sockets.c: replace the field
+ netconn::mbox (sys_mbox_t) per netconn::sem (sys_sem_t) for the task #7490
+ "Add return value to sys_mbox_post".
+
+ 2008-01-05 Fr閐閞ic Bernon
+ * sys_arch.txt, api.h, api_lib.c, api_msg.h, api_msg.c, tcpip.c, sys.h, opt.h:
+ Introduce changes for task #7490 "Add return value to sys_mbox_post" with some
+ modifications in the sys_mbox api: sys_mbox_new take a "size" parameters which
+ indicate the number of pointers query by the mailbox. There is three defines
+ in opt.h to indicate sizes for tcpip::mbox, netconn::recvmbox, and for the
+ netconn::acceptmbox. Port maintainers, you can decide to just add this new
+ parameter in your implementation, but to ignore it to keep the previous behavior.
+ The new sys_mbox_trypost function return a value to know if the mailbox is
+ full or if the message is posted. Take a look to sys_arch.txt for more details.
+ This new function is used in tcpip_input (so, can be called in an interrupt
+ context since the function is not blocking), and in recv_udp and recv_raw.
+
+ 2008-01-04 Fr閐閞ic Bernon, Simon Goldschmidt, Jonathan Larmour
+ * rawapi.txt, api.h, api_lib.c, api_msg.h, api_msg.c, sockets.c, tcp.h, tcp.c,
+ tcp_in.c, init.c, opt.h: rename backlog options with TCP_ prefix, limit the
+ "backlog" parameter in an u8_t, 0 is interpreted as "smallest queue", add
+ documentation in the rawapi.txt file.
+
+ 2007-12-31 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+ * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Add TCP persist timer
+
+ 2007-12-31 Fr閐閞ic Bernon, Luca Ceresoli
+ * autoip.c, etharp.c: ip_addr.h: Integrate patch #6348: "Broadcast ARP packets
+ in autoip". The change in etharp_raw could be removed, since all calls to
+ etharp_raw use ethbroadcast for the "ethdst_addr" parameter. But it could be
+ wrong in the future.
+
+ 2007-12-30 Fr閐閞ic Bernon, Tom Evans
+ * ip.c: Fix bug #21846 "LwIP doesn't appear to perform any IP Source Address
+ Filtering" reported by Tom Evans.
+
+ 2007-12-21 Fr閐閞ic Bernon, Simon Goldschmidt, Jonathan Larmour
+ * tcp.h, opt.h, api.h, api_msg.h, tcp.c, tcp_in.c, api_lib.c, api_msg.c,
+ sockets.c, init.c: task #7252: Implement TCP listen backlog: Warning: raw API
+ applications have to call 'tcp_accepted(pcb)' in their accept callback to
+ keep accepting new connections.
+
+ 2007-12-13 Fr閐閞ic Bernon
+ * api_msg.c, err.h, err.c, sockets.c, dns.c, dns.h: replace "enum dns_result"
+ by err_t type. Add a new err_t code "ERR_INPROGRESS".
+
+ 2007-12-12 Fr閐閞ic Bernon
+ * dns.h, dns.c, opt.h: move DNS options to the "right" place. Most visibles
+ are the one which have ram usage.
+
+ 2007-12-05 Fr閐閞ic Bernon
+ * netdb.c: add a LWIP_DNS_API_HOSTENT_STORAGE option to decide to use a static
+ set of variables (=0) or a local one (=1). In this last case, your port should
+ provide a function "struct hostent* sys_thread_hostent( struct hostent* h)"
+ which have to do a copy of "h" and return a pointer ont the "per-thread" copy.
+
+ 2007-12-03 Simon Goldschmidt
+ * ip.c: ip_input: check if a packet is for inp first before checking all other
+ netifs on netif_list (speeds up packet receiving in most cases)
+
+ 2007-11-30 Simon Goldschmidt
+ * udp.c, raw.c: task #7497: Sort lists (pcb, netif, ...) for faster access
+ UDP: move a (connected) pcb selected for input to the front of the list of
+ pcbs so that it is found faster next time. Same for RAW pcbs that have eaten
+ a packet.
+
+ 2007-11-28 Simon Goldschmidt
+ * etharp.c, stats.c, stats.h, opt.h: Introduced ETHARP_STATS
+
+ 2007-11-25 Simon Goldschmidt
+ * dhcp.c: dhcp_unfold_reply() uses pbuf_copy_partial instead of its own copy
+ algorithm.
+
+ 2007-11-24 Simon Goldschmidt
+ * netdb.h, netdb.c, sockets.h/.c: Moved lwip_gethostbyname from sockets.c
+ to the new file netdb.c; included lwip_getaddrinfo.
+
+ 2007-11-21 Simon Goldschmidt
+ * tcp.h, opt.h, tcp.c, tcp_in.c: implemented calculating the effective send-mss
+ based on the MTU of the netif used to send. Enabled by default. Disable by
+ setting LWIP_CALCULATE_EFF_SEND_MSS to 0. This fixes bug #21492.
+
+ 2007-11-19 Fr閐閞ic Bernon
+ * api_msg.c, dns.h, dns.c: Implement DNS_DOES_NAME_CHECK option (check if name
+ received match the name query), implement DNS_USES_STATIC_BUF (the place where
+ copy dns payload to parse the response), return an error if there is no place
+ for a new query, and fix some minor problems.
+
+ 2007-11-16 Simon Goldschmidt
+ * new files: ipv4/inet.c, ipv4/inet_chksum.c, ipv6/inet6.c
+ removed files: core/inet.c, core/inet6.c
+ Moved inet files into ipv4/ipv6 directory; splitted inet.c/inet.h into
+ inet and chksum part; changed includes in all lwIP files as appropriate
+
+ 2007-11-16 Simon Goldschmidt
+ * api.h, api_msg.h, api_lib.c, api_msg.c, socket.h, socket.c: Added sequential
+ dns resolver function for netconn api (netconn_gethostbyname) and socket api
+ (gethostbyname/gethostbyname_r).
+
+ 2007-11-15 Jim Pettinato, Fr閐閞ic Bernon
+ * opt.h, init.c, tcpip.c, dhcp.c, dns.h, dns.c: add DNS client for simple name
+ requests with RAW api interface. Initialization is done in lwip_init() with
+ build time options. DNS timer is added in tcpip_thread context. DHCP can set
+ DNS server ip addresses when options are received. You need to set LWIP_DNS=1
+ in your lwipopts.h file (LWIP_DNS=0 in opt.h). DNS_DEBUG can be set to get
+ some traces with LWIP_DEBUGF. Sanity check have been added. There is a "todo"
+ list with points to improve.
+
+ 2007-11-06 Simon Goldschmidt
+ * opt.h, mib2.c: Patch #6215: added ifAdminStatus write support (if explicitly
+ enabled by defining SNMP_SAFE_REQUESTS to 0); added code to check link status
+ for ifOperStatus if LWIP_NETIF_LINK_CALLBACK is defined.
+
+ 2007-11-06 Simon Goldschmidt
+ * api.h, api_msg.h and dependent files: Task #7410: Removed the need to include
+ core header files in api.h (ip/tcp/udp/raw.h) to hide the internal
+ implementation from netconn api applications.
+
+ 2007-11-03 Fr閐閞ic Bernon
+ * api.h, api_lib.c, api_msg.c, sockets.c, opt.h: add SO_RCVBUF option for UDP &
+ RAW netconn. You need to set LWIP_SO_RCVBUF=1 in your lwipopts.h (it's disabled
+ by default). Netconn API users can use the netconn_recv_bufsize macro to access
+ it. This is a first release which have to be improve for TCP. Note it used the
+ netconn::recv_avail which need to be more "thread-safe" (note there is already
+ the problem for FIONREAD with lwip_ioctl/ioctlsocket).
+
+ 2007-11-01 Fr閐閞ic Bernon, Marc Chaland
+ * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, tcp.h, tcp_out.c:
+ Integrate "patch #6250 : MSG_MORE flag for send". MSG_MORE is used at socket api
+ layer, NETCONN_MORE at netconn api layer, and TCP_WRITE_FLAG_MORE at raw api
+ layer. This option enable to delayed TCP PUSH flag on multiple "write" calls.
+ Note that previous "copy" parameter for "write" APIs is now called "apiflags".
+
+ 2007-10-24 Fr閐閞ic Bernon
+ * api.h, api_lib.c, api_msg.c: Add macro API_EVENT in the same spirit than
+ TCP_EVENT_xxx macros to get a code more readable. It could also help to remove
+ some code (like we have talk in "patch #5919 : Create compile switch to remove
+ select code"), but it could be done later.
+
+ 2007-10-08 Simon Goldschmidt
+ * many files: Changed initialization: many init functions are not needed any
+ more since we now rely on the compiler initializing global and static
+ variables to zero!
+
+ 2007-10-06 Simon Goldschmidt
+ * ip_frag.c, memp.c, mib2.c, ip_frag.h, memp_std.h, opt.h: Changed IP_REASSEMBLY
+ to enqueue the received pbufs so that multiple packets can be reassembled
+ simultaneously and no static reassembly buffer is needed.
+
+ 2007-10-05 Simon Goldschmidt
+ * tcpip.c, etharp.h, etharp.c: moved ethernet_input from tcpip.c to etharp.c so
+ all netifs (or ports) can use it.
+
+ 2007-10-05 Fr閐閞ic Bernon
+ * netifapi.h, netifapi.c: add function netifapi_netif_set_default. Change the
+ common function to reduce a little bit the footprint (for all functions using
+ only the "netif" parameter).
+
+ 2007-10-03 Fr閐閞ic Bernon
+ * netifapi.h, netifapi.c: add functions netifapi_netif_set_up, netifapi_netif_set_down,
+ netifapi_autoip_start and netifapi_autoip_stop. Use a common function to reduce
+ a little bit the footprint (for all functions using only the "netif" parameter).
+
+ 2007-09-15 Fr閐閞ic Bernon
+ * udp.h, udp.c, sockets.c: Changes for "#20503 IGMP Improvement". Add IP_MULTICAST_IF
+ option in socket API, and a new field "multicast_ip" in "struct udp_pcb" (for
+ netconn and raw API users), only if LWIP_IGMP=1. Add getsockopt processing for
+ IP_MULTICAST_TTL and IP_MULTICAST_IF.
+
+ 2007-09-10 Fr閐閞ic Bernon
+ * snmp.h, mib2.c: enable to remove SNMP timer (which consumne several cycles
+ even when it's not necessary). snmp_agent.txt tell to call snmp_inc_sysuptime()
+ each 10ms (but, it's intrusive if you use sys_timeout feature). Now, you can
+ decide to call snmp_add_sysuptime(100) each 1000ms (which is bigger "step", but
+ call to a lower frequency). Or, you can decide to not call snmp_inc_sysuptime()
+ or snmp_add_sysuptime(), and to define the SNMP_GET_SYSUPTIME(sysuptime) macro.
+ This one is undefined by default in mib2.c. SNMP_GET_SYSUPTIME is called inside
+ snmp_get_sysuptime(u32_t *value), and enable to change "sysuptime" value only
+ when it's queried (any direct call to "sysuptime" is changed by a call to
+ snmp_get_sysuptime).
+
+ 2007-09-09 Fr閐閞ic Bernon, Bill Florac
+ * igmp.h, igmp.c, netif.h, netif.c, ip.c: To enable to have interfaces with IGMP,
+ and others without it, there is a new NETIF_FLAG_IGMP flag to set in netif->flags
+ if you want IGMP on an interface. igmp_stop() is now called inside netif_remove().
+ igmp_report_groups() is now called inside netif_set_link_up() (need to have
+ LWIP_NETIF_LINK_CALLBACK=1) to resend reports once the link is up (avoid to wait
+ the next query message to receive the matching multicast streams).
+
+ 2007-09-08 Fr閐閞ic Bernon
+ * sockets.c, ip.h, api.h, tcp.h: declare a "struct ip_pcb" which only contains
+ IP_PCB. Add in the netconn's "pcb" union a "struct ip_pcb *ip;" (no size change).
+ Use this new field to access to common pcb fields (ttl, tos, so_options, etc...).
+ Enable to access to these fields with LWIP_TCP=0.
+
+ 2007-09-05 Fr閐閞ic Bernon
+ * udp.c, ipv4/icmp.c, ipv4/ip.c, ipv6/icmp.c, ipv6/ip6.c, ipv4/icmp.h,
+ ipv6/icmp.h, opt.h: Integrate "task #7272 : LWIP_ICMP option". The new option
+ LWIP_ICMP enable/disable ICMP module inside the IP stack (enable per default).
+ Be careful, disabling ICMP make your product non-compliant to RFC1122, but
+ help to reduce footprint, and to reduce "visibility" on the Internet.
+
+ 2007-09-05 Fr閐閞ic Bernon, Bill Florac
+ * opt.h, sys.h, tcpip.c, slipif.c, ppp.c, sys_arch.txt: Change parameters list
+ for sys_thread_new (see "task #7252 : Create sys_thread_new_ex()"). Two new
+ parameters have to be provided: a task name, and a task stack size. For this
+ one, since it's platform dependant, you could define the best one for you in
+ your lwipopts.h. For port maintainers, you can just add these new parameters
+ in your sys_arch.c file, and but it's not mandatory, use them in your OS
+ specific functions.
+
+ 2007-09-05 Fr閐閞ic Bernon
+ * inet.c, autoip.c, msg_in.c, msg_out.c, init.c: Move some build time checkings
+ inside init.c for task #7142 "Sanity check user-configurable values".
+
+ 2007-09-04 Fr閐閞ic Bernon, Bill Florac
+ * igmp.h, igmp.c, memp_std.h, memp.c, init.c, opt.h: Replace mem_malloc call by
+ memp_malloc, and use a new MEMP_NUM_IGMP_GROUP option (see opt.h to define the
+ value). It will avoid potential fragmentation problems, use a counter to know
+ how many times a group is used on an netif, and free it when all applications
+ leave it. MEMP_NUM_IGMP_GROUP got 8 as default value (and init.c got a sanity
+ check if LWIP_IGMP!=0).
+
+ 2007-09-03 Fr閐閞ic Bernon
+ * igmp.h, igmp.c, sockets.c, api_msg.c: Changes for "#20503 IGMP Improvement".
+ Initialize igmp_mac_filter to NULL in netif_add (this field should be set in
+ the netif's "init" function). Use the "imr_interface" field (for socket layer)
+ and/or the "interface" field (for netconn layer), for join/leave operations.
+ The igmp_join/leavegroup first parameter change from a netif to an ipaddr.
+ This field could be a netif's ipaddr, or "any" (same meaning than ip_addr_isany).
+
+ 2007-08-30 Fr閐閞ic Bernon
+ * Add netbuf.h, netbuf.c, Change api.h, api_lib.c: #7249 "Split netbuf functions
+ from api/api_lib". Now netbuf API is independant of netconn, and can be used
+ with other API (application based on raw API, or future "socket2" API). Ports
+ maintainers just have to add src/api/netbuf.c in their makefile/projects.
+
+ 2007-08-30 Fr閐閞ic Bernon, Jonathan Larmour
+ * init.c: Add first version of lwip_sanity_check for task #7142 "Sanity check
+ user-configurable values".
+
+ 2007-08-29 Fr閐閞ic Bernon
+ * igmp.h, igmp.c, tcpip.c, init.c, netif.c: change igmp_init and add igmp_start.
+ igmp_start is call inside netif_add. Now, igmp initialization is in the same
+ spirit than the others modules. Modify some IGMP debug traces.
+
+ 2007-08-29 Fr閐閞ic Bernon
+ * Add init.h, init.c, Change opt.h, tcpip.c: Task #7213 "Add a lwip_init function"
+ Add lwip_init function to regroup all modules initializations, and to provide
+ a place to add code for task #7142 "Sanity check user-configurable values".
+ Ports maintainers should remove direct initializations calls from their code,
+ and add init.c in their makefiles. Note that lwip_init() function is called
+ inside tcpip_init, but can also be used by raw api users since all calls are
+ disabled when matching options are disabled. Also note that their is new options
+ in opt.h, you should configure in your lwipopts.h (they are enabled per default).
+
+ 2007-08-26 Marc Boucher
+ * api_msg.c: do_close_internal(): Reset the callbacks and arg (conn) to NULL
+ since they can under certain circumstances be called with an invalid conn
+ pointer after the connection has been closed (and conn has been freed).
+
+ 2007-08-25 Fr閐閞ic Bernon (Artem Migaev's Patch)
+ * netif.h, netif.c: Integrate "patch #6163 : Function to check if link layer is up".
+ Add a netif_is_link_up() function if LWIP_NETIF_LINK_CALLBACK option is set.
+
+ 2007-08-22 Fr閐閞ic Bernon
+ * netif.h, netif.c, opt.h: Rename LWIP_NETIF_CALLBACK in LWIP_NETIF_STATUS_CALLBACK
+ to be coherent with new LWIP_NETIF_LINK_CALLBACK option before next release.
+
+ 2007-08-22 Fr閐閞ic Bernon
+ * tcpip.h, tcpip.c, ethernetif.c, opt.h: remove options ETHARP_TCPIP_INPUT &
+ ETHARP_TCPIP_ETHINPUT, now, only "ethinput" code is supported, even if the
+ name is tcpip_input (we keep the name of 1.2.0 function).
+
+ 2007-08-17 Jared Grubb
+ * memp_std.h, memp.h, memp.c, mem.c, stats.c: (Task #7136) Centralize mempool
+ settings into new memp_std.h and optional user file lwippools.h. This adds
+ more dynamic mempools, and allows the user to create an arbitrary number of
+ mempools for mem_malloc.
+
+ 2007-08-16 Marc Boucher
+ * api_msg.c: Initialize newconn->state to NETCONN_NONE in accept_function;
+ otherwise it was left to NETCONN_CLOSE and sent_tcp() could prematurely
+ close the connection.
+
+ 2007-08-16 Marc Boucher
+ * sockets.c: lwip_accept(): check netconn_peer() error return.
+
+ 2007-08-16 Marc Boucher
+ * mem.c, mem.h: Added mem_calloc().
+
+ 2007-08-16 Marc Boucher
+ * tcpip.c, tcpip.h memp.c, memp.h: Added distinct memp (MEMP_TCPIP_MSG_INPKT)
+ for input packets to prevent floods from consuming all of MEMP_TCPIP_MSG
+ and starving other message types.
+ Renamed MEMP_TCPIP_MSG to MEMP_TCPIP_MSG_API
+
+ 2007-08-16 Marc Boucher
+ * pbuf.c, pbuf.h, etharp.c, tcp_in.c, sockets.c: Split pbuf flags in pbuf
+ type and flgs (later renamed to flags).
+ Use enum pbuf_flag as pbuf_type. Renumber PBUF_FLAG_*.
+ Improved lwip_recvfrom(). TCP push now propagated.
+
+ 2007-08-16 Marc Boucher
+ * ethernetif.c, contrib/ports/various: ethbroadcast now a shared global
+ provided by etharp.
+
+ 2007-08-16 Marc Boucher
+ * ppp_oe.c ppp_oe.h, auth.c chap.c fsm.c lcp.c ppp.c ppp.h,
+ etharp.c ethernetif.c, etharp.h, opt.h tcpip.h, tcpip.c:
+ Added PPPoE support and various PPP improvements.
+
+ 2007-07-25 Simon Goldschmidt
+ * api_lib.c, ip_frag.c, pbuf.c, api.h, pbuf.h: Introduced pbuf_copy_partial,
+ making netbuf_copy_partial use this function.
+
+ 2007-07-25 Simon Goldschmidt
+ * tcp_in.c: Fix bug #20506: Slow start / initial congestion window starts with
+ 2 * mss (instead of 1 * mss previously) to comply with some newer RFCs and
+ other stacks.
+
+ 2007-07-13 Jared Grubb (integrated by Fr閐閞ic Bernon)
+ * opt.h, netif.h, netif.c, ethernetif.c: Add new configuration option to add
+ a link callback in the netif struct, and functions to handle it. Be carefull
+ for port maintainers to add the NETIF_FLAG_LINK_UP flag (like in ethernetif.c)
+ if you want to be sure to be compatible with future changes...
+
+ 2007-06-30 Fr閐閞ic Bernon
+ * sockets.h, sockets.c: Implement MSG_PEEK flag for recv/recvfrom functions.
+
+ 2007-06-21 Simon Goldschmidt
+ * etharp.h, etharp.c: Combined etharp_request with etharp_raw for both
+ LWIP_AUTOIP =0 and =1 to remove redundant code.
+
+ 2007-06-21 Simon Goldschmidt
+ * mem.c, memp.c, mem.h, memp.h, opt.h: task #6863: Introduced the option
+ MEM_USE_POOLS to use 4 pools with different sized elements instead of a
+ heap. This both prevents memory fragmentation and gives a higher speed
+ at the cost of more memory consumption. Turned off by default.
+
+ 2007-06-21 Simon Goldschmidt
+ * api_lib.c, api_msg.c, api.h, api_msg.h: Converted the length argument of
+ netconn_write (and therefore also api_msg_msg.msg.w.len) from u16_t into
+ int to be able to send a bigger buffer than 64K with one time (mainly
+ used from lwip_send).
+
+ 2007-06-21 Simon Goldschmidt
+ * tcp.h, api_msg.c: Moved the nagle algorithm from netconn_write/do_write
+ into a define (tcp_output_nagle) in tcp.h to provide it to raw api users, too.
+
+ 2007-06-21 Simon Goldschmidt
+ * api.h, api_lib.c, api_msg.c: Fixed bug #20021: Moved sendbuf-processing in
+ netconn_write from api_lib.c to api_msg.c to also prevent multiple context-
+ changes on low memory or empty send-buffer.
+
+ 2007-06-18 Simon Goldschmidt
+ * etharp.c, etharp.h: Changed etharp to use a defined hardware address length
+ of 6 to avoid loading netif->hwaddr_len every time (since this file is only
+ used for ethernet and struct eth_addr already had a defined length of 6).
+
+ 2007-06-17 Simon Goldschmidt
+ * sockets.c, sockets.h: Implemented socket options SO_NO_CHECK for UDP sockets
+ to disable UDP checksum generation on transmit.
+
+ 2007-06-13 Fr閐閞ic Bernon, Simon Goldschmidt
+ * debug.h, api_msg.c: change LWIP_ERROR to use it to check errors like invalid
+ pointers or parameters, and let the possibility to redefined it in cc.h. Use
+ this macro to check "conn" parameter in api_msg.c functions.
+
+ 2007-06-11 Simon Goldschmidt
+ * sockets.c, sockets.h: Added UDP lite support for sockets
+
+ 2007-06-10 Simon Goldschmidt
+ * udp.h, opt.h, api_msg.c, ip.c, udp.c: Included switch LWIP_UDPLITE (enabled
+ by default) to switch off UDP-Lite support if not needed (reduces udp.c code
+ size)
+
+ 2007-06-09 Dominik Spies (integrated by Fr閐閞ic Bernon)
+ * autoip.h, autoip.c, dhcp.h, dhcp.c, netif.h, netif.c, etharp.h, etharp.c, opt.h:
+ AutoIP implementation available for IPv4, with new options LWIP_AUTOIP and
+ LWIP_DHCP_AUTOIP_COOP if you want to cooperate with DHCP. Some tips to adapt
+ (see TODO mark in the source code).
+
+ 2007-06-09 Simon Goldschmidt
+ * etharp.h, etharp.c, ethernetif.c: Modified order of parameters for
+ etharp_output() to match netif->output so etharp_output() can be used
+ directly as netif->output to save one function call.
+
+ 2007-06-08 Simon Goldschmidt
+ * netif.h, ethernetif.c, slipif.c, loopif.c: Added define
+ NETIF_INIT_SNMP(netif, type, speed) to initialize per-netif snmp variables,
+ added initialization of those to ethernetif, slipif and loopif.
+
+ 2007-05-18 Simon Goldschmidt
+ * opt.h, ip_frag.c, ip_frag.h, ip.c: Added option IP_FRAG_USES_STATIC_BUF
+ (defaulting to off for now) that can be set to 0 to send fragmented
+ packets by passing PBUF_REFs down the stack.
+
+ 2007-05-23 Fr閐閞ic Bernon
+ * api_lib.c: Implement SO_RCVTIMEO for accept and recv on TCP
+ connections, such present in patch #5959.
+
+ 2007-05-23 Fr閐閞ic Bernon
+ * api.h, api_lib.c, api_msg.c, sockets.c: group the different NETCONN_UDPxxx
+ code in only one part...
+
+ 2007-05-18 Simon Goldschmidt
+ * opt.h, memp.h, memp.c: Added option MEMP_OVERFLOW_CHECK to check for memp
+ elements to overflow. This is achieved by adding some bytes before and after
+ each pool element (increasing their size, of course), filling them with a
+ prominent value and checking them on freeing the element.
+ Set it to 2 to also check every element in every pool each time memp_malloc()
+ or memp_free() is called (slower but more helpful).
+
+ 2007-05-10 Simon Goldschmidt
+ * opt.h, memp.h, memp.c, pbuf.c (see task #6831): use a new memp pool for
+ PBUF_POOL pbufs instead of the old pool implementation in pbuf.c to reduce
+ code size.
+
+ 2007-05-11 Fr閐閞ic Bernon
+ * sockets.c, api_lib.c, api_msg.h, api_msg.c, netifapi.h, netifapi.c, tcpip.c:
+ Include a function pointer instead of a table index in the message to reduce
+ footprint. Disable some part of lwip_send and lwip_sendto if some options are
+ not set (LWIP_TCP, LWIP_UDP, LWIP_RAW).
+
+ 2007-05-10 Simon Goldschmidt
+ * *.h (except netif/ppp/*.h): Included patch #5448: include '#ifdef __cplusplus
+ \ extern "C" {' in all header files. Now you can write your application using
+ the lwIP stack in C++ and simply #include the core files. Note I have left
+ out the netif/ppp/*h header files for now, since I don't know which files are
+ included by applications and which are for internal use only.
+
+ 2007-05-09 Simon Goldschmidt
+ * opt.h, *.c/*.h: Included patch #5920: Create define to override C-library
+ memcpy. 2 Defines are created: MEMCPY() for normal memcpy, SMEMCPY() for
+ situations where some compilers might inline the copy and save a function
+ call. Also replaced all calls to memcpy() with calls to (S)MEMCPY().
+
+ 2007-05-08 Simon Goldschmidt
+ * mem.h: If MEM_LIBC_MALLOC==1, allow the defines (e.g. mem_malloc() -> malloc())
+ to be overriden in case the C-library malloc implementation is not protected
+ against concurrent access.
+
+ 2007-05-04 Simon Goldschmidt (Atte Kojo)
+ * etharp.c: Introduced fast one-entry-cache to speed up ARP lookup when sending
+ multiple packets to the same host.
+
+ 2007-05-04 Fr閐閞ic Bernon, Jonathan Larmour
+ * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fix bug #19162 "lwip_sento: a possible
+ to corrupt remote addr/port connection state". Reduce problems "not enought memory" with
+ netbuf (if we receive lot of datagrams). Improve lwip_sendto (only one exchange between
+ sockets api and api_msg which run in tcpip_thread context). Add netconn_sento function.
+ Warning, if you directly access to "fromaddr" & "fromport" field from netbuf struct,
+ these fields are now renamed "addr" & "port".
+
+ 2007-04-11 Jonathan Larmour
+ * sys.h, api_lib.c: Provide new sys_mbox_tryfetch function. Require ports to provide new
+ sys_arch_mbox_tryfetch function to get a message if one is there, otherwise return
+ with SYS_MBOX_EMPTY. sys_arch_mbox_tryfetch can be implemented as a function-like macro
+ by the port in sys_arch.h if desired.
+
+ 2007-04-06 Fr閐閞ic Bernon, Simon Goldschmidt
+ * opt.h, tcpip.h, tcpip.c, netifapi.h, netifapi.c: New configuration option LWIP_NETIF_API
+ allow to use thread-safe functions to add/remove netif in list, and to start/stop dhcp
+ clients, using new functions from netifapi.h. Disable as default (no port change to do).
+
+ 2007-04-05 Fr閐閞ic Bernon
+ * sockets.c: remplace ENOBUFS errors on alloc_socket by ENFILE to be more BSD compliant.
+
+ 2007-04-04 Simon Goldschmidt
+ * arch.h, api_msg.c, dhcp.c, msg_in.c, sockets.c: Introduced #define LWIP_UNUSED_ARG(x)
+ use this for and architecture-independent form to tell the compiler you intentionally
+ are not using this variable. Can be overriden in cc.h.
+
+ 2007-03-28 Fr閐閞ic Bernon
+ * opt.h, netif.h, dhcp.h, dhcp.c: New configuration option LWIP_NETIF_HOSTNAME allow to
+ define a hostname in netif struct (this is just a pointer, so, you can use a hardcoded
+ string, point on one of your's ethernetif field, or alloc a string you will free yourself).
+ It will be used by DHCP to register a client hostname, but can also be use when you call
+ snmp_set_sysname.
+
+ 2007-03-28 Fr閐閞ic Bernon
+ * netif.h, netif.c: A new NETIF_FLAG_ETHARP flag is defined in netif.h, to allow to
+ initialize a network interface's flag with. It tell this interface is an ethernet
+ device, and we can use ARP with it to do a "gratuitous ARP" (RFC 3220 "IP Mobility
+ Support for IPv4" section 4.6) when interface is "up" with netif_set_up().
+
+ 2007-03-26 Fr閐閞ic Bernon, Jonathan Larmour
+ * opt.h, tcpip.c: New configuration option LWIP_ARP allow to disable ARP init at build
+ time if you only use PPP or SLIP. The default is enable. Note we don't have to call
+ etharp_init in your port's initilization sequence if you use tcpip.c, because this call
+ is done in tcpip_init function.
+
+ 2007-03-22 Fr閐閞ic Bernon
+ * stats.h, stats.c, msg_in.c: Stats counters can be change to u32_t if necessary with the
+ new option LWIP_STATS_LARGE. If you need this option, define LWIP_STATS_LARGE to 1 in
+ your lwipopts.h. More, unused counters are not defined in the stats structs, and not
+ display by stats_display(). Note that some options (SYS_STATS and RAW_STATS) are defined
+ but never used. Fix msg_in.c with the correct #if test for a stat display.
+
+ 2007-03-21 Kieran Mansley
+ * netif.c, netif.h: Apply patch#4197 with some changes (originator: rireland@hmgsl.com).
+ Provides callback on netif up/down state change.
+
+ 2007-03-11 Fr閐閞ic Bernon, Mace Gael, Steve Reynolds
+ * sockets.h, sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c, igmp.h, igmp.c,
+ ip.c, netif.h, tcpip.c, opt.h:
+ New configuration option LWIP_IGMP to enable IGMP processing. Based on only one
+ filter per all network interfaces. Declare a new function in netif to enable to
+ control the MAC filter (to reduce lwIP traffic processing).
+
+ 2007-03-11 Fr閐閞ic Bernon
+ * tcp.h, tcp.c, sockets.c, tcp_out.c, tcp_in.c, opt.h: Keepalive values can
+ be configured at run time with LWIP_TCP_KEEPALIVE, but don't change this
+ unless you know what you're doing (default are RFC1122 compliant). Note
+ that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set in seconds.
+
+ 2007-03-08 Fr閐閞ic Bernon
+ * tcp.h: Keepalive values can be configured at compile time, but don't change
+ this unless you know what you're doing (default are RFC1122 compliant).
+
+ 2007-03-08 Fr閐閞ic Bernon
+ * sockets.c, api.h, api_lib.c, tcpip.c, sys.h, sys.c, err.c, opt.h:
+ Implement LWIP_SO_RCVTIMEO configuration option to enable/disable SO_RCVTIMEO
+ on UDP sockets/netconn.
+
+ 2007-03-08 Simon Goldschmidt
+ * snmp_msg.h, msg_in.c: SNMP UDP ports can be configured at compile time.
+
+ 2007-03-06 Fr閐閞ic Bernon
+ * api.h, api_lib.c, sockets.h, sockets.c, tcpip.c, sys.h, sys.c, err.h:
+ Implement SO_RCVTIMEO on UDP sockets/netconn.
+
+ 2007-02-28 Kieran Mansley (based on patch from Simon Goldschmidt)
+ * api_lib.c, tcpip.c, memp.c, memp.h: make API msg structs allocated
+ on the stack and remove the API msg type from memp
+
+ 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+ * sockets.h, sockets.c: Move socket initialization to new
+ lwip_socket_init() function.
+ NOTE: this changes the API with ports. Ports will have to be
+ updated to call lwip_socket_init() now.
+
+ 2007-02-26 Jonathan Larmour (based on patch from Simon Goldschmidt)
+ * api_lib.c: Use memcpy in netbuf_copy_partial.
+
+
+ ++ Bug fixes:
+
+ 2008-03-17 Fr閐閞ic Bernon, Ed Kerekes
+ * igmp.h, igmp.c: Fix bug #22613 "IGMP iphdr problem" (could have
+ some problems to fill the IP header on some targets, use now the
+ ip.h macros to do it).
+
+ 2008-03-13 Fr閐閞ic Bernon
+ * sockets.c: Fix bug #22435 "lwip_recvfrom with TCP break;". Using
+ (lwip_)recvfrom with valid "from" and "fromlen" parameters, on a
+ TCP connection caused a crash. Note that using (lwip_)recvfrom
+ like this is a bit slow and that using (lwip)getpeername is the
+ good lwip way to do it (so, using recv is faster on tcp sockets).
+
+ 2008-03-12 Fr閐閞ic Bernon, Jonathan Larmour
+ * api_msg.c, contrib/apps/ping.c: Fix bug #22530 "api_msg.c's
+ recv_raw() does not consume data", and the ping sample (with
+ LWIP_SOCKET=1, the code did the wrong supposition that lwip_recvfrom
+ returned the IP payload, without the IP header).
+
+ 2008-03-04 Jonathan Larmour
+ * mem.c, stats.c, mem.h: apply patch #6414 to avoid compiler errors
+ and/or warnings on some systems where mem_size_t and size_t differ.
+ * pbuf.c, ppp.c: Fix warnings on some systems with mem_malloc.
+
+ 2008-03-04 Kieran Mansley (contributions by others)
+ * Numerous small compiler error/warning fixes from contributions to
+ mailing list after 1.3.0 release candidate made.
+
+ 2008-01-25 Cui hengbin (integrated by Fr閐閞ic Bernon)
+ * dns.c: Fix bug #22108 "DNS problem" caused by unaligned structures.
+
+ 2008-01-15 Kieran Mansley
+ * tcp_out.c: BUG20511. Modify persist timer to start when we are
+ prevented from sending by a small send window, not just a zero
+ send window.
+
+ 2008-01-09 Jonathan Larmour
+ * opt.h, ip.c: Rename IP_OPTIONS define to IP_OPTIONS_ALLOWED to avoid
+ conflict with Linux system headers.
+
+ 2008-01-06 Jonathan Larmour
+ * dhcp.c: fix bug #19927: "DHCP NACK problem" by clearing any existing set IP
+ address entirely on receiving a DHCPNAK, and restarting discovery.
+
+ 2007-12-21 Simon Goldschmidt
+ * sys.h, api_lib.c, api_msg.c, sockets.c: fix bug #21698: "netconn->recv_avail
+ is not protected" by using new macros for interlocked access to modify/test
+ netconn->recv_avail.
+
+ 2007-12-20 Kieran Mansley (based on patch from Oleg Tyshev)
+ * tcp_in.c: fix bug# 21535 (nrtx not reset correctly in SYN_SENT state)
+
+ 2007-12-20 Kieran Mansley (based on patch from Per-Henrik Lundbolm)
+ * tcp.c, tcp_in.c, tcp_out.c, tcp.h: fix bug #20199 (better handling
+ of silly window avoidance and prevent lwIP from shrinking the window)
+
+ 2007-12-04 Simon Goldschmidt
+ * tcp.c, tcp_in.c: fix bug #21699 (segment leak in ooseq processing when last
+ data packet was lost): add assert that all segment lists are empty in
+ tcp_pcb_remove before setting pcb to CLOSED state; don't directly set CLOSED
+ state from LAST_ACK in tcp_process
+
+ 2007-12-02 Simon Goldschmidt
+ * sockets.h: fix bug #21654: exclude definition of struct timeval from #ifndef FD_SET
+ If including for system-struct timeval, LWIP_TIMEVAL_PRIVATE now
+ has to be set to 0 in lwipopts.h
+
+ 2007-12-02 Simon Goldschmidt
+ * api_msg.c, api_lib.c: fix bug #21656 (recvmbox problem in netconn API): always
+ allocate a recvmbox in netconn_new_with_proto_and_callback. For a tcp-listen
+ netconn, this recvmbox is later freed and a new mbox is allocated for acceptmbox.
+ This is a fix for thread-safety and allocates all items needed for a netconn
+ when the netconn is created.
+
+ 2007-11-30 Simon Goldschmidt
+ * udp.c: first attempt to fix bug #21655 (DHCP doesn't work reliably with multiple
+ netifs): if LWIP_DHCP is enabled, UDP packets to DHCP_CLIENT_PORT are passed
+ to netif->dhcp->pcb only (if that exists) and not to any other pcb for the same
+ port (only solution to let UDP pcbs 'bind' to a netif instead of an IP address)
+
+ 2007-11-27 Simon Goldschmidt
+ * ip.c: fixed bug #21643 (udp_send/raw_send don't fail if netif is down) by
+ letting ip_route only use netifs that are up.
+
+ 2007-11-27 Simon Goldschmidt
+ * err.h, api_lib.c, api_msg.c, sockets.c: Changed error handling: ERR_MEM, ERR_BUF
+ and ERR_RTE are seen as non-fatal, all other errors are fatal. netconns and
+ sockets block most operations once they have seen a fatal error.
+
+ 2007-11-27 Simon Goldschmidt
+ * udp.h, udp.c, dhcp.c: Implemented new function udp_sendto_if which takes the
+ netif to send as an argument (to be able to send on netifs that are down).
+
+ 2007-11-26 Simon Goldschmidt
+ * tcp_in.c: Fixed bug #21582: pcb->acked accounting can be wrong when ACKs
+ arrive out-of-order
+
+ 2007-11-21 Simon Goldschmidt
+ * tcp.h, tcp_out.c, api_msg.c: Fixed bug #20287: tcp_output_nagle sends too early
+ Fixed the nagle algorithm; nagle now also works for all raw API applications
+ and has to be explicitly disabled with 'tcp_pcb->flags |= TF_NODELAY'
+
+ 2007-11-12 Fr閐閞ic Bernon
+ * sockets.c, api.h, api_lib.c, api_msg.h, api_msg.c: Fixed bug #20900. Now, most
+ of the netconn_peer and netconn_addr processing is done inside tcpip_thread
+ context in do_getaddr.
+
+ 2007-11-10 Simon Goldschmidt
+ * etharp.c: Fixed bug: assert fired when MEMP_ARP_QUEUE was empty (which can
+ happen any time). Now the packet simply isn't enqueued when out of memory.
+
+ 2007-11-01 Simon Goldschmidt
+ * tcp.c, tcp_in.c: Fixed bug #21494: The send mss (pcb->mss) is set to 536 (or
+ TCP_MSS if that is smaller) as long as no MSS option is received from the
+ remote host.
+
+ 2007-11-01 Simon Goldschmidt
+ * tcp.h, tcp.c, tcp_in.c: Fixed bug #21491: The MSS option sent (with SYN)
+ is now based on TCP_MSS instead of pcb->mss (on passive open now effectively
+ sending our configured TCP_MSS instead of the one received).
+
+ 2007-11-01 Simon Goldschmidt
+ * tcp_in.c: Fixed bug #21181: On active open, the initial congestion window was
+ calculated based on the configured TCP_MSS, not on the MSS option received
+ with SYN+ACK.
+
+ 2007-10-09 Simon Goldschmidt
+ * udp.c, inet.c, inet.h: Fixed UDPLite: send: Checksum was always generated too
+ short and also was generated wrong if checksum coverage != tot_len;
+ receive: checksum was calculated wrong if checksum coverage != tot_len
+
+ 2007-10-08 Simon Goldschmidt
+ * mem.c: lfree was not updated in mem_realloc!
+
+ 2007-10-07 Fr閐閞ic Bernon
+ * sockets.c, api.h, api_lib.c: First step to fix "bug #20900 : Potential
+ crash error problem with netconn_peer & netconn_addr". VERY IMPORTANT:
+ this change cause an API breakage for netconn_addr, since a parameter
+ type change. Any compiler should cause an error without any changes in
+ yours netconn_peer calls (so, it can't be a "silent change"). It also
+ reduce a little bit the footprint for socket layer (lwip_getpeername &
+ lwip_getsockname use now a common lwip_getaddrname function since
+ netconn_peer & netconn_addr have the same parameters).
+
+ 2007-09-20 Simon Goldschmidt
+ * tcp.c: Fixed bug #21080 (tcp_bind without check pcbs in TIME_WAIT state)
+ by checking tcp_tw_pcbs also
+
+ 2007-09-19 Simon Goldschmidt
+ * icmp.c: Fixed bug #21107 (didn't reset IP TTL in ICMP echo replies)
+
+ 2007-09-15 Mike Kleshov
+ * mem.c: Fixed bug #21077 (inaccuracy in calculation of lwip_stat.mem.used)
+
+ 2007-09-06 Fr閐閞ic Bernon
+ * several-files: replace some #include "arch/cc.h" by "lwip/arch.h", or simply remove
+ it as long as "lwip/opt.h" is included before (this one include "lwip/debug.h" which
+ already include "lwip/arch.h"). Like that, default defines are provided by "lwip/arch.h"
+ if they are not defined in cc.h, in the same spirit than "lwip/opt.h" for lwipopts.h.
+
+ 2007-08-30 Fr閐閞ic Bernon
+ * igmp.h, igmp.c: Some changes to remove some redundant code, add some traces,
+ and fix some coding style.
+
+ 2007-08-28 Fr閐閞ic Bernon
+ * tcpip.c: Fix TCPIP_MSG_INPKT processing: now, tcpip_input can be used for any
+ kind of packets. These packets are considered like Ethernet packets (payload
+ pointing to ethhdr) if the netif got the NETIF_FLAG_ETHARP flag. Else, packets
+ are considered like IP packets (payload pointing to iphdr).
+
+ 2007-08-27 Fr閐閞ic Bernon
+ * api.h, api_lib.c, api_msg.c: First fix for "bug #20900 : Potential crash error
+ problem with netconn_peer & netconn_addr". Introduce NETCONN_LISTEN netconn_state
+ and remove obsolete ones (NETCONN_RECV & NETCONN_ACCEPT).
+
+ 2007-08-24 Kieran Mansley
+ * inet.c Modify (acc >> 16) test to ((acc >> 16) != 0) to help buggy
+ compiler (Paradigm C++)
+
+ 2007-08-09 Fr閐閞ic Bernon, Bill Florac
+ * stats.h, stats.c, igmp.h, igmp.c, opt.h: Fix for bug #20503 : IGMP Improvement.
+ Introduce IGMP_STATS to centralize statistics management.
+
+ 2007-08-09 Fr閐閞ic Bernon, Bill Florac
+ * udp.c: Fix for bug #20503 : IGMP Improvement. Enable to receive a multicast
+ packet on a udp pcb binded on an netif's IP address, and not on "any".
+
+ 2007-08-09 Fr閐閞ic Bernon, Bill Florac
+ * igmp.h, igmp.c, ip.c: Fix minor changes from bug #20503 : IGMP Improvement.
+ This is mainly on using lookup/lookfor, and some coding styles...
+
+ 2007-07-26 Fr閐閞ic Bernon (and "thedoctor")
+ * igmp.c: Fix bug #20595 to accept IGMPv3 "Query" messages.
+
+ 2007-07-25 Simon Goldschmidt
+ * api_msg.c, tcp.c: Another fix for bug #20021: by not returning an error if
+ tcp_output fails in tcp_close, the code in do_close_internal gets simpler
+ (tcp_output is called again later from tcp timers).
+
+ 2007-07-25 Simon Goldschmidt
+ * ip_frag.c: Fixed bug #20429: use the new pbuf_copy_partial instead of the old
+ copy_from_pbuf, which illegally modified the given pbuf.
+
+ 2007-07-25 Simon Goldschmidt
+ * tcp_out.c: tcp_enqueue: pcb->snd_queuelen didn't work for chaine PBUF_RAMs:
+ changed snd_queuelen++ to snd_queuelen += pbuf_clen(p).
+
+ 2007-07-24 Simon Goldschmidt
+ * api_msg.c, tcp.c: Fix bug #20480: Check the pcb passed to tcp_listen() for the
+ correct state (must be CLOSED).
+
+ 2007-07-13 Thomas Taranowski (commited by Jared Grubb)
+ * memp.c: Fix bug #20478: memp_malloc returned NULL+MEMP_SIZE on failed
+ allocation. It now returns NULL.
+
+ 2007-07-13 Fr閐閞ic Bernon
+ * api_msg.c: Fix bug #20318: api_msg "recv" callbacks don't call pbuf_free in
+ all error cases.
+
+ 2007-07-13 Fr閐閞ic Bernon
+ * api_msg.c: Fix bug #20315: possible memory leak problem if tcp_listen failed,
+ because current code doesn't follow rawapi.txt documentation.
+
+ 2007-07-13 Kieran Mansley
+ * src/core/tcp_in.c Apply patch#5741 from Oleg Tyshev to fix bug in
+ out of sequence processing of received packets
+
+ 2007-07-03 Simon Goldschmidt
+ * nearly-all-files: Added assertions where PBUF_RAM pbufs are used and an
+ assumption is made that this pbuf is in one piece (i.e. not chained). These
+ assumptions clash with the possibility of converting to fully pool-based
+ pbuf implementations, where PBUF_RAM pbufs might be chained.
+
+ 2007-07-03 Simon Goldschmidt
+ * api.h, api_lib.c, api_msg.c: Final fix for bug #20021 and some other problems
+ when closing tcp netconns: removed conn->sem, less context switches when
+ closing, both netconn_close and netconn_delete should safely close tcp
+ connections.
+
+ 2007-07-02 Simon Goldschmidt
+ * ipv4/ip.h, ipv6/ip.h, opt.h, netif.h, etharp.h, ipv4/ip.c, netif.c, raw.c,
+ tcp_out.c, udp.c, etharp.c: Added option LWIP_NETIF_HWADDRHINT (default=off)
+ to cache ARP table indices with each pcb instead of single-entry cache for
+ the complete stack.
+
+ 2007-07-02 Simon Goldschmidt
+ * tcp.h, tcp.c, tcp_in.c, tcp_out.c: Added some ASSERTS and casts to prevent
+ warnings when assigning to smaller types.
+
+ 2007-06-28 Simon Goldschmidt
+ * tcp_out.c: Added check to prevent tcp_pcb->snd_queuelen from overflowing.
+
+ 2007-06-28 Simon Goldschmidt
+ * tcp.h: Fixed bug #20287: Fixed nagle algorithm (sending was done too early if
+ a segment contained chained pbufs)
+
+ 2007-06-28 Fr閐閞ic Bernon
+ * autoip.c: replace most of rand() calls by a macro LWIP_AUTOIP_RAND which compute
+ a "pseudo-random" value based on netif's MAC and some autoip fields. It's always
+ possible to define this macro in your own lwipopts.h to always use C library's
+ rand(). Note that autoip_create_rand_addr doesn't use this macro.
+
+ 2007-06-28 Fr閐閞ic Bernon
+ * netifapi.h, netifapi.c, tcpip.h, tcpip.c: Update code to handle the option
+ LWIP_TCPIP_CORE_LOCKING, and do some changes to be coherent with last modifications
+ in api_lib/api_msg (use pointers and not type with table, etc...)
+
+ 2007-06-26 Simon Goldschmidt
+ * udp.h: Fixed bug #20259: struct udp_hdr was lacking the packin defines.
+
+ 2007-06-25 Simon Goldschmidt
+ * udp.c: Fixed bug #20253: icmp_dest_unreach was called with a wrong p->payload
+ for udp packets with no matching pcb.
+
+ 2007-06-25 Simon Goldschmidt
+ * udp.c: Fixed bug #20220: UDP PCB search in udp_input(): a non-local match
+ could get udp input packets if the remote side matched.
+
+ 2007-06-13 Simon Goldschmidt
+ * netif.c: Fixed bug #20180 (TCP pcbs listening on IP_ADDR_ANY could get
+ changed in netif_set_ipaddr if previous netif->ip_addr.addr was 0.
+
+ 2007-06-13 Simon Goldschmidt
+ * api_msg.c: pcb_new sets conn->err if protocol is not implemented
+ -> netconn_new_..() does not allocate a new connection for unsupported
+ protocols.
+
+ 2007-06-13 Fr閐閞ic Bernon, Simon Goldschmidt
+ * api_lib.c: change return expression in netconn_addr and netconn_peer, because
+ conn->err was reset to ERR_OK without any reasons (and error was lost)...
+
+ 2007-06-13 Fr閐閞ic Bernon, Matthias Weisser
+ * opt.h, mem.h, mem.c, memp.c, pbuf.c, ip_frag.c, vj.c: Fix bug #20162. Rename
+ MEM_ALIGN in LWIP_MEM_ALIGN and MEM_ALIGN_SIZE in LWIP_MEM_ALIGN_SIZE to avoid
+ some macro names collision with some OS macros.
+
+ 2007-06-11 Simon Goldschmidt
+ * udp.c: UDP Lite: corrected the use of chksum_len (based on RFC3828: if it's 0,
+ create checksum over the complete packet. On RX, if it's < 8 (and not 0),
+ discard the packet. Also removed the duplicate 'udphdr->chksum = 0' for both
+ UDP & UDP Lite.
+
+ 2007-06-11 Srinivas Gollakota & Oleg Tyshev
+ * tcp_out.c: Fix for bug #20075 : "A problem with keep-alive timer and TCP flags"
+ where TCP flags wasn't initialized in tcp_keepalive.
+
+ 2007-06-03 Simon Goldschmidt
+ * udp.c: udp_input(): Input pbuf was not freed if pcb had no recv function
+ registered, p->payload was modified without modifying p->len if sending
+ icmp_dest_unreach() (had no negative effect but was definitively wrong).
+
+ 2007-06-03 Simon Goldschmidt
+ * icmp.c: Corrected bug #19937: For responding to an icmp echo request, icmp
+ re-used the input pbuf even if that didn't have enough space to include the
+ link headers. Now the space is tested and a new pbuf is allocated for the
+ echo response packet if the echo request pbuf isn't big enough.
+
+ 2007-06-01 Simon Goldschmidt
+ * sockets.c: Checked in patch #5914: Moved sockopt processing into tcpip_thread.
+
+ 2007-05-23 Fr閐閞ic Bernon
+ * api_lib.c, sockets.c: Fixed bug #5958 for netconn_listen (acceptmbox only
+ allocated by do_listen if success) and netconn_accept errors handling. In
+ most of api_lib functions, we replace some errors checkings like "if (conn==NULL)"
+ by ASSERT, except for netconn_delete.
+
+ 2007-05-23 Fr閐閞ic Bernon
+ * api_lib.c: Fixed bug #5957 "Safe-thread problem inside netconn_recv" to return
+ an error code if it's impossible to fetch a pbuf on a TCP connection (and not
+ directly close the recvmbox).
+
+ 2007-05-22 Simon Goldschmidt
+ * tcp.c: Fixed bug #1895 (tcp_bind not correct) by introducing a list of
+ bound but unconnected (and non-listening) tcp_pcbs.
+
+ 2007-05-22 Fr閐閞ic Bernon
+ * sys.h, sys.c, api_lib.c, tcpip.c: remove sys_mbox_fetch_timeout() (was only
+ used for LWIP_SO_RCVTIMEO option) and use sys_arch_mbox_fetch() instead of
+ sys_mbox_fetch() in api files. Now, users SHOULD NOT use internal lwIP features
+ like "sys_timeout" in their application threads.
+
+ 2007-05-22 Fr閐閞ic Bernon
+ * api.h, api_lib.c, api_msg.h, api_msg.c: change the struct api_msg_msg to see
+ which parameters are used by which do_xxx function, and to avoid "misusing"
+ parameters (patch #5938).
+
+ 2007-05-22 Simon Goldschmidt
+ * api_lib.c, api_msg.c, raw.c, api.h, api_msg.h, raw.h: Included patch #5938:
+ changed raw_pcb.protocol from u16_t to u8_t since for IPv4 and IPv6, proto
+ is only 8 bits wide. This affects the api, as there, the protocol was
+ u16_t, too.
+
+ 2007-05-18 Simon Goldschmidt
+ * memp.c: addition to patch #5913: smaller pointer was returned but
+ memp_memory was the same size -> did not save memory.
+
+ 2007-05-16 Simon Goldschmidt
+ * loopif.c, slipif.c: Fix bug #19729: free pbuf if netif->input() returns
+ != ERR_OK.
+
+ 2007-05-16 Simon Goldschmidt
+ * api_msg.c, udp.c: If a udp_pcb has a local_ip set, check if it is the same
+ as the one of the netif used for sending to prevent sending from old
+ addresses after a netif address gets changed (partly fixes bug #3168).
+
+ 2007-05-16 Fr閐閞ic Bernon
+ * tcpip.c, igmp.h, igmp.c: Fixed bug "#19800 : IGMP: igmp_tick() will not work
+ with NO_SYS=1". Note that igmp_init is always in tcpip_thread (and not in
+ tcpip_init) because we have to be sure that network interfaces are already
+ added (mac filter is updated only in igmp_init for the moment).
+
+ 2007-05-16 Simon Goldschmidt
+ * mem.c, memp.c: Removed semaphores from memp, changed sys_sem_wait calls
+ into sys_arch_sem_wait calls to prevent timers from running while waiting
+ for the heap. This fixes bug #19167.
+
+ 2007-05-13 Simon Goldschmidt
+ * tcp.h, sockets.h, sockets.c: Fixed bug from patch #5865 by moving the defines
+ for socket options (lwip_set/-getsockopt) used with level IPPROTO_TCP from
+ tcp.h to sockets.h.
+
+ 2007-05-07 Simon Goldschmidt
+ * mem.c: Another attempt to fix bug #17922.
+
+ 2007-05-04 Simon Goldschmidt
+ * pbuf.c, pbuf.h, etharp.c: Further update to ARP queueing: Changed pbuf_copy()
+ implementation so that it can be reused (don't allocate the target
+ pbuf inside pbuf_copy()).
+
+ 2007-05-04 Simon Goldschmidt
+ * memp.c: checked in patch #5913: in memp_malloc() we can return memp as mem
+ to save a little RAM (next pointer of memp is not used while not in pool).
+
+ 2007-05-03 "maq"
+ * sockets.c: Fix ioctl FIONREAD when some data remains from last recv.
+ (patch #3574).
+
+ 2007-04-23 Simon Goldschmidt
+ * loopif.c, loopif.h, opt.h, src/netif/FILES: fix bug #2595: "loopif results
+ in NULL reference for incoming TCP packets". Loopif has to be configured
+ (using LWIP_LOOPIF_MULTITHREADING) to directly call netif->input()
+ (multithreading environments, e.g. netif->input() = tcpip_input()) or
+ putting packets on a list that is fed to the stack by calling loopif_poll()
+ (single-thread / NO_SYS / polling environment where e.g.
+ netif->input() = ip_input).
+
+ 2007-04-17 Jonathan Larmour
+ * pbuf.c: Use s32_t in pbuf_realloc(), as an s16_t can't reliably hold
+ the difference between two u16_t's.
+ * sockets.h: FD_SETSIZE needs to match number of sockets, which is
+ MEMP_NUM_NETCONN in sockets.c right now.
+
+ 2007-04-12 Jonathan Larmour
+ * icmp.c: Reset IP header TTL in ICMP ECHO responses (bug #19580).
+
+ 2007-04-12 Kieran Mansley
+ * tcp.c, tcp_in.c, tcp_out.c, tcp.h: Modify way the retransmission
+ timer is reset to fix bug#19434, with help from Oleg Tyshev.
+
+ 2007-04-11 Simon Goldschmidt
+ * etharp.c, pbuf.c, pbuf.h: 3rd fix for bug #11400 (arp-queuing): More pbufs than
+ previously thought need to be copied (everything but PBUF_ROM!). Cleaned up
+ pbuf.c: removed functions no needed any more (by etharp).
+
+ 2007-04-11 Kieran Mansley
+ * inet.c, ip_addr.h, sockets.h, sys.h, tcp.h: Apply patch #5745: Fix
+ "Constant is long" warnings with 16bit compilers. Contributed by
+ avatar@mmlab.cse.yzu.edu.tw
+
+ 2007-04-05 Fr閐閞ic Bernon, Jonathan Larmour
+ * api_msg.c: Fix bug #16830: "err_tcp() posts to connection mailbox when no pend on
+ the mailbox is active". Now, the post is only done during a connect, and do_send,
+ do_write and do_join_leave_group don't do anything if a previous error was signaled.
+
+ 2007-04-03 Fr閐閞ic Bernon
+ * ip.c: Don't set the IP_DF ("Don't fragment") flag in the IP header in IP output
+ packets. See patch #5834.
+
+ 2007-03-30 Fr閐閞ic Bernon
+ * api_msg.c: add a "pcb_new" helper function to avoid redundant code, and to add
+ missing pcb allocations checking (in do_bind, and for each raw_new). Fix style.
+
+ 2007-03-30 Fr閐閞ic Bernon
+ * most of files: prefix all debug.h define with "LWIP_" to avoid any conflict with
+ others environment defines (these were too "generic").
+
+ 2007-03-28 Fr閐閞ic Bernon
+ * api.h, api_lib.c, sockets.c: netbuf_ref doesn't check its internal pbuf_alloc call
+ result and can cause a crash. lwip_send now check netbuf_ref result.
+
+ 2007-03-28 Simon Goldschmidt
+ * sockets.c Remove "#include " from sockets.c to avoid multiple
+ definition of macros (in errno.h and lwip/arch.h) if LWIP_PROVIDE_ERRNO is
+ defined. This is the way it should have been already (looking at
+ doc/sys_arch.txt)
+
+ 2007-03-28 Kieran Mansley
+ * opt.h Change default PBUF_POOL_BUFSIZE (again) to accomodate default MSS +
+ IP and TCP headers *and* physical link headers
+
+ 2007-03-26 Fr閐閞ic Bernon (based on patch from Dmitry Potapov)
+ * api_lib.c: patch for netconn_write(), fixes a possible race condition which cause
+ to send some garbage. It is not a definitive solution, but the patch does solve
+ the problem for most cases.
+
+ 2007-03-22 Fr閐閞ic Bernon
+ * api_msg.h, api_msg.c: Remove obsolete API_MSG_ACCEPT and do_accept (never used).
+
+ 2007-03-22 Fr閐閞ic Bernon
+ * api_lib.c: somes resources couldn't be freed if there was errors during
+ netconn_new_with_proto_and_callback.
+
+ 2007-03-22 Fr閐閞ic Bernon
+ * ethernetif.c: update netif->input calls to check return value. In older ports,
+ it's a good idea to upgrade them, even if before, there could be another problem
+ (access to an uninitialized mailbox).
+
+ 2007-03-21 Simon Goldschmidt
+ * sockets.c: fixed bug #5067 (essentialy a signed/unsigned warning fixed
+ by casting to unsigned).
+
+ 2007-03-21 Fr閐閞ic Bernon
+ * api_lib.c, api_msg.c, tcpip.c: integrate sys_mbox_fetch(conn->mbox, NULL) calls from
+ api_lib.c to tcpip.c's tcpip_apimsg(). Now, use a local variable and not a
+ dynamic one from memp to send tcpip_msg to tcpip_thread in a synchrone call.
+ Free tcpip_msg from tcpip_apimsg is not done in tcpip_thread. This give a
+ faster and more reliable communication between api_lib and tcpip.
+
+ 2007-03-21 Fr閐閞ic Bernon
+ * opt.h: Add LWIP_NETIF_CALLBACK (to avoid compiler warning) and set it to 0.
+
+ 2007-03-21 Fr閐閞ic Bernon
+ * api_msg.c, igmp.c, igmp.h: Fix C++ style comments
+
+ 2007-03-21 Kieran Mansley
+ * opt.h Change default PBUF_POOL_BUFSIZE to accomodate default MSS +
+ IP and TCP headers
+
+ 2007-03-21 Kieran Mansley
+ * Fix all uses of pbuf_header to check the return value. In some
+ cases just assert if it fails as I'm not sure how to fix them, but
+ this is no worse than before when they would carry on regardless
+ of the failure.
+
+ 2007-03-21 Kieran Mansley
+ * sockets.c, igmp.c, igmp.h, memp.h: Fix C++ style comments and
+ comment out missing header include in icmp.c
+
+ 2007-03-20 Fr閐閞ic Bernon
+ * memp.h, stats.c: Fix stats_display function where memp_names table wasn't
+ synchronized with memp.h.
+
+ 2007-03-20 Fr閐閞ic Bernon
+ * tcpip.c: Initialize tcpip's mbox, and verify if initialized in tcpip_input,
+ tcpip_ethinput, tcpip_callback, tcpip_apimsg, to fix a init problem with
+ network interfaces. Also fix a compiler warning.
+
+ 2007-03-20 Kieran Mansley
+ * udp.c: Only try and use pbuf_header() to make space for headers if
+ not a ROM or REF pbuf.
+
+ 2007-03-19 Fr閐閞ic Bernon
+ * api_msg.h, api_msg.c, tcpip.h, tcpip.c: Add return types to tcpip_apimsg()
+ and api_msg_post().
+
+ 2007-03-19 Fr閐閞ic Bernon
+ * Remove unimplemented "memp_realloc" function from memp.h.
+
+ 2007-03-11 Simon Goldschmidt
+ * pbuf.c: checked in patch #5796: pbuf_alloc: len field claculation caused
+ memory corruption.
+
+ 2007-03-11 Simon Goldschmidt (based on patch from Dmitry Potapov)
+ * api_lib.c, sockets.c, api.h, api_msg.h, sockets.h: Fixed bug #19251
+ (missing `const' qualifier in socket functions), to get more compatible to
+ standard POSIX sockets.
+
+ 2007-03-11 Fr閐閞ic Bernon (based on patch from Dmitry Potapov)
+ * sockets.c: Add asserts inside bind, connect and sendto to check input
+ parameters. Remove excessive set_errno() calls after get_socket(), because
+ errno is set inside of get_socket(). Move last sock_set_errno() inside
+ lwip_close.
+
+ 2007-03-09 Simon Goldschmidt
+ * memp.c: Fixed bug #11400: New etharp queueing introduced bug: memp_memory
+ was allocated too small.
+
+ 2007-03-06 Simon Goldschmidt
+ * tcpip.c: Initialize dhcp timers in tcpip_thread (if LWIP_DHCP) to protect
+ the stack from concurrent access.
+
+ 2007-03-06 Fr閐閞ic Bernon, Dmitry Potapov
+ * tcpip.c, ip_frag.c, ethernetif.c: Fix some build problems, and a redundancy
+ call to "lwip_stats.link.recv++;" in low_level_input() & ethernetif_input().
+
+ 2007-03-06 Simon Goldschmidt
+ * ip_frag.c, ip_frag.h: Reduce code size: don't include code in those files
+ if IP_FRAG == 0 and IP_REASSEMBLY == 0
+
+ 2007-03-06 Fr閐閞ic Bernon, Simon Goldschmidt
+ * opt.h, ip_frag.h, tcpip.h, tcpip.c, ethernetif.c: add new configuration
+ option named ETHARP_TCPIP_ETHINPUT, which enable the new tcpip_ethinput.
+ Allow to do ARP processing for incoming packets inside tcpip_thread
+ (protecting ARP layer against concurrent access). You can also disable
+ old code using tcp_input with new define ETHARP_TCPIP_INPUT set to 0.
+ Older ports have to use tcpip_ethinput.
+
+ 2007-03-06 Simon Goldschmidt (based on patch from Dmitry Potapov)
+ * err.h, err.c: fixed compiler warning "initialization dircards qualifiers
+ from pointer target type"
+
+ 2007-03-05 Fr閐閞ic Bernon
+ * opt.h, sockets.h: add new configuration options (LWIP_POSIX_SOCKETS_IO_NAMES,
+ ETHARP_TRUST_IP_MAC, review SO_REUSE)
+
+ 2007-03-04 Fr閐閞ic Bernon
+ * api_msg.c: Remove some compiler warnings : parameter "pcb" was never
+ referenced.
+
+ 2007-03-04 Fr閐閞ic Bernon
+ * api_lib.c: Fix "[patch #5764] api_lib.c cleanup: after patch #5687" (from
+ Dmitry Potapov).
+ The api_msg struct stay on the stack (not moved to netconn struct).
+
+ 2007-03-04 Simon Goldschmidt (based on patch from Dmitry Potapov)
+ * pbuf.c: Fix BUG#19168 - pbuf_free can cause deadlock (if
+ SYS_LIGHTWEIGHT_PROT=1 & freeing PBUF_RAM when mem_sem is not available)
+ Also fixed cast warning in pbuf_alloc()
+
+ 2007-03-04 Simon Goldschmidt
+ * etharp.c, etharp.h, memp.c, memp.h, opt.h: Fix BUG#11400 - don't corrupt
+ existing pbuf chain when enqueuing multiple pbufs to a pending ARP request
+
+ 2007-03-03 Fr閐閞ic Bernon
+ * udp.c: remove obsolete line "static struct udp_pcb *pcb_cache = NULL;"
+ It is static, and never used in udp.c except udp_init().
+
+ 2007-03-02 Simon Goldschmidt
+ * tcpip.c: Moved call to ip_init(), udp_init() and tcp_init() from
+ tcpip_thread() to tcpip_init(). This way, raw API connections can be
+ initialized before tcpip_thread is running (e.g. before OS is started)
+
+ 2007-03-02 Fr閐閞ic Bernon
+ * rawapi.txt: Fix documentation mismatch with etharp.h about etharp_tmr's call
+ interval.
+
+ 2007-02-28 Kieran Mansley
+ * pbuf.c: Fix BUG#17645 - ensure pbuf payload pointer is not moved
+ outside the region of the pbuf by pbuf_header()
+
+ 2007-02-28 Kieran Mansley
+ * sockets.c: Fix BUG#19161 - ensure milliseconds timeout is non-zero
+ when supplied timeout is also non-zero
+
+(STABLE-1.2.0)
+
+ 2006-12-05 Leon Woestenberg
+ * CHANGELOG: Mention STABLE-1.2.0 release.
+
+ ++ New features:
+
+ 2006-12-01 Christiaan Simons
+ * mem.h, opt.h: Added MEM_LIBC_MALLOC option.
+ Note this is a workaround. Currently I have no other options left.
+
+ 2006-10-26 Christiaan Simons (accepted patch by Jonathan Larmour)
+ * ipv4/ip_frag.c: rename MAX_MTU to IP_FRAG_MAX_MTU and move define
+ to include/lwip/opt.h.
+ * ipv4/lwip/ip_frag.h: Remove unused IP_REASS_INTERVAL.
+ Move IP_REASS_MAXAGE and IP_REASS_BUFSIZE to include/lwip/opt.h.
+ * opt.h: Add above new options.
+
+ 2006-08-18 Christiaan Simons
+ * tcp_{in,out}.c: added SNMP counters.
+ * ipv4/ip.c: added SNMP counters.
+ * ipv4/ip_frag.c: added SNMP counters.
+
+ 2006-08-08 Christiaan Simons
+ * etharp.{c,h}: added etharp_find_addr() to read
+ (stable) ethernet/IP address pair from ARP table
+
+ 2006-07-14 Christiaan Simons
+ * mib_structs.c: added
+ * include/lwip/snmp_structs.h: added
+ * netif.{c,h}, netif/ethernetif.c: added SNMP statistics to netif struct
+
+ 2006-07-06 Christiaan Simons
+ * snmp/asn1_{enc,dec}.c added
+ * snmp/mib2.c added
+ * snmp/msg_{in,out}.c added
+ * include/lwip/snmp_asn1.h added
+ * include/lwip/snmp_msg.h added
+ * doc/snmp_agent.txt added
+
+ 2006-03-29 Christiaan Simons
+ * inet.c, inet.h: Added platform byteswap support.
+ Added LWIP_PLATFORM_BYTESWAP define (defaults to 0) and
+ optional LWIP_PLATFORM_HTONS(), LWIP_PLATFORM_HTONL() macros.
+
+ ++ Bug fixes:
+
+ 2006-11-30 Christiaan Simons
+ * dhcp.c: Fixed false triggers of request_timeout.
+
+ 2006-11-28 Christiaan Simons
+ * netif.c: In netif_add() fixed missing clear of ip_addr, netmask, gw and flags.
+
+ 2006-10-11 Christiaan Simons
+ * api_lib.c etharp.c, ip.c, memp.c, stats.c, sys.{c,h} tcp.h:
+ Partially accepted patch #5449 for ANSI C compatibility / build fixes.
+ * ipv4/lwip/ip.h ipv6/lwip/ip.h: Corrected UDP-Lite protocol
+ identifier from 170 to 136 (bug #17574).
+
+ 2006-10-10 Christiaan Simons
+ * api_msg.c: Fixed Nagle algorithm as reported by Bob Grice.
+
+ 2006-08-17 Christiaan Simons
+ * udp.c: Fixed bug #17200, added check for broadcast
+ destinations for PCBs bound to a unicast address.
+
+ 2006-08-07 Christiaan Simons
+ * api_msg.c: Flushing TCP output in do_close() (bug #15926).
+
+ 2006-06-27 Christiaan Simons
+ * api_msg.c: Applied patch for cold case (bug #11135).
+ In accept_function() ensure newconn->callback is always initialized.
+
+ 2006-06-15 Christiaan Simons
+ * mem.h: added MEM_SIZE_F alias to fix an ancient cold case (bug #1748),
+ facilitate printing of mem_size_t and u16_t statistics.
+
+ 2006-06-14 Christiaan Simons
+ * api_msg.c: Applied patch #5146 to handle allocation failures
+ in accept() by Kevin Lawson.
+
+ 2006-05-26 Christiaan Simons
+ * api_lib.c: Removed conn->sem creation and destruction
+ from netconn_write() and added sys_sem_new to netconn_new_*.
+
+(STABLE-1_1_1)
+
+ 2006-03-03 Christiaan Simons
+ * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap
+ access and added pbuf_alloc() return value checks.
+
+ 2006-01-01 Leon Woestenberg
+ * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is
+ now handled by the checksum routine properly.
+
+ 2006-02-27 Leon Woestenberg
+ * pbuf.c: Fix alignment; pbuf_init() would not work unless
+ pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.)
+
+ 2005-12-20 Leon Woestenberg
+ * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch
+ submitted by Mitrani Hiroshi.
+
+ 2005-12-15 Christiaan Simons
+ * inet.c: Disabled the added summing routine to preserve code space.
+
+ 2005-12-14 Leon Woestenberg
+ * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson.
+ Added Curt McDowell's optimized checksumming routine for future
+ inclusion. Need to create test case for unaliged, aligned, odd,
+ even length combination of cases on various endianess machines.
+
+ 2005-12-09 Christiaan Simons
+ * inet.c: Rewrote standard checksum routine in proper portable C.
+
+ 2005-11-25 Christiaan Simons
+ * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only.
+ * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t,
+ u32_t, s32_t typedefs. This solves most debug word-length assumes.
+
+ 2005-07-17 Leon Woestenberg
+ * inet.c: Fixed unaligned 16-bit access in the standard checksum
+ routine by Peter Jolasson.
+ * slipif.c: Fixed implementation assumption of single-pbuf datagrams.
+
+ 2005-02-04 Leon Woestenberg
+ * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch.
+ * tcp_{out|in}.c: Applied patch fixing unaligned access.
+
+ 2005-01-04 Leon Woestenberg
+ * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement.
+
+ 2005-01-03 Leon Woestenberg
+ * udp.c: UDP pcb->recv() was called even when it was NULL.
+
+(STABLE-1_1_0)
+
+ 2004-12-28 Leon Woestenberg