Fix CSVWriter output for multiple channels

Author: dramninjasUMD

CSVWriter.h

@@ -159,6 +159,7 @@ namespace DRAMSim {
 		{
 			if (!finalized)
 			{
+//				cout <<"Adding "<<name<<endl;
 				fieldNames.push_back(string(name));
 			}
 			return *this; 
@@ -177,11 +178,22 @@ namespace DRAMSim {
 		{
 			if (!finalized)
 			{
+//				cout <<"Adding "<<indexedName.str<<endl;
 				fieldNames.push_back(indexedName.str);
 			}
 			return *this; 
 		}
-
+		
+		bool isFinalized()
+		{
+//			printf("obj=%p", this); 
+			return finalized; 
+		}
+		
+		ostream &getOutputStream()
+		{
+			return output; 
+		}
 		// Insertion operators for value types 
 		// All of the other types just need to pass through to the underlying
 		// ofstream, so just write this small wrapper function to make the
@@ -203,9 +215,15 @@ namespace DRAMSim {
 	ADD_TYPE(uint64_t);
 	ADD_TYPE(float);
 	ADD_TYPE(double);
+
+	//disable copy constructor and assignment operator
+	private:
+		CSVWriter(const CSVWriter &); 
+		CSVWriter &operator=(const CSVWriter &);
+		
 	}; // class CSVWriter
 
 
-} // namespace BOBSim
+} // namespace DRAMSim
 
 #endif // _CSV_WRITER_H_

MemoryController.cpp

@@ -43,21 +43,17 @@
 
 using namespace DRAMSim;
 
-MemoryController::MemoryController(MemorySystem *parent, std::ofstream *outfile, ostream &dramsim_log_) :
+MemoryController::MemoryController(MemorySystem *parent, CSVWriter &csvOut_, ostream &dramsim_log_) :
 		dramsim_log(dramsim_log_),
 		bankStates(NUM_RANKS, vector<BankState>(NUM_BANKS, dramsim_log)),
 		commandQueue(bankStates, dramsim_log_),
 		poppedBusPacket(NULL),
-		csvOut(*outfile),
+		csvOut(csvOut_),
 		totalTransactions(0),
 		refreshRank(0)
 {
 	//get handle on parent
 	parentMemorySystem = parent;
-	if (VIS_FILE_OUTPUT)
-	{
-		visDataOut = outfile; 
-	}
 
 
 	//bus related fields
@@ -744,31 +740,6 @@ void MemoryController::update()
 
 	commandQueue.step();
 
-	//print stats if we're at the end of an epoch
-	if (currentClockCycle % EPOCH_LENGTH == 0)
-	{
-		this->printStats();
-
-		totalTransactions = 0;
-		for (size_t i=0;i<NUM_RANKS;i++)
-		{
-			for (size_t j=0; j<NUM_BANKS; j++)
-			{
-				//XXX: this means the bank list won't be printed for partial epochs
-				grandTotalBankAccesses[SEQUENTIAL(i,j)] += totalReadsPerBank[SEQUENTIAL(i,j)] + totalWritesPerBank[SEQUENTIAL(i,j)];
-				totalReadsPerBank[SEQUENTIAL(i,j)] = 0;
-				totalWritesPerBank[SEQUENTIAL(i,j)] = 0;
-				totalEpochLatency[SEQUENTIAL(i,j)] = 0;
-			}
-
-			burstEnergy[i] = 0;
-			actpreEnergy[i] = 0;
-			refreshEnergy[i] = 0;
-			backgroundEnergy[i] = 0;
-			totalReadsPerRank[i] = 0;
-			totalWritesPerRank[i] = 0;
-		}
-	}
 }
 
 bool MemoryController::WillAcceptTransaction()
@@ -791,14 +762,31 @@ bool MemoryController::addTransaction(Transaction *trans)
 	}
 }
 
+void MemoryController::resetStats()
+{
+	for (size_t i=0; i<NUM_RANKS; i++)
+	{
+		for (size_t j=0; j<NUM_BANKS; j++)
+		{
+			//XXX: this means the bank list won't be printed for partial epochs
+			grandTotalBankAccesses[SEQUENTIAL(i,j)] += totalReadsPerBank[SEQUENTIAL(i,j)] + totalWritesPerBank[SEQUENTIAL(i,j)];
+			totalReadsPerBank[SEQUENTIAL(i,j)] = 0;
+			totalWritesPerBank[SEQUENTIAL(i,j)] = 0;
+			totalEpochLatency[SEQUENTIAL(i,j)] = 0;
+		}
 
+		burstEnergy[i] = 0;
+		actpreEnergy[i] = 0;
+		refreshEnergy[i] = 0;
+		backgroundEnergy[i] = 0;
+		totalReadsPerRank[i] = 0;
+		totalWritesPerRank[i] = 0;
+	}
+}
 //prints statistics at the end of an epoch or  simulation
 void MemoryController::printStats(bool finalStats)
 {
 	unsigned myChannel = parentMemorySystem->systemID;
-	//skip the print on the first cycle, it's pretty useless
-	if (currentClockCycle == 0)
-		return;
 
 	//if we are not at the end of the epoch, make sure to adjust for the actual number of cycles elapsed
 
@@ -843,11 +831,6 @@ void MemoryController::printStats(bool finalStats)
 	PRINTN( "   Total Return Transactions : " << totalTransactions );
 	PRINT( " ("<<totalBytesTransferred <<" bytes) aggregate average bandwidth "<<totalBandwidth<<"GB/s");
 
-	// only the first memory channel should print the timestamp
-	if (VIS_FILE_OUTPUT && myChannel == 0)
-	{
-		csvOut << "ms" <<currentClockCycle * tCK * 1E-6; 
-	}
 	double totalAggregateBandwidth = 0.0;	
 	for (size_t r=0;r<NUM_RANKS;r++)
 	{
@@ -883,6 +866,7 @@ void MemoryController::printStats(bool finalStats)
 
 		if (VIS_FILE_OUTPUT)
 		{
+		//	cout << "c="<<myChannel<< " r="<<r<<"writing to csv out on cycle "<< currentClockCycle<<endl;
 			// write the vis file output
 			csvOut << CSVWriter::IndexedName("Background_Power",myChannel,r) <<backgroundPower[r];
 			csvOut << CSVWriter::IndexedName("ACT_PRE_Power",myChannel,r) << actprePower[r];
@@ -904,7 +888,6 @@ void MemoryController::printStats(bool finalStats)
 	{
 		csvOut << CSVWriter::IndexedName("Aggregate_Bandwidth",myChannel) << totalAggregateBandwidth;
 		csvOut << CSVWriter::IndexedName("Average_Bandwidth",myChannel) << totalAggregateBandwidth / (NUM_RANKS*NUM_BANKS);
-		csvOut.finalize(); 
 	}
 
 	// only print the latency histogram at the end of the simulation since it clogs the output too much to print every epoch
@@ -914,7 +897,7 @@ void MemoryController::printStats(bool finalStats)
 		PRINT( "       [lat] : #");
 		if (VIS_FILE_OUTPUT)
 		{
-			(*visDataOut) << "!!HISTOGRAM_DATA"<<endl;
+			csvOut.getOutputStream() << "!!HISTOGRAM_DATA"<<endl;
 		}
 
 		map<unsigned,unsigned>::iterator it; //
@@ -923,7 +906,7 @@ void MemoryController::printStats(bool finalStats)
 			PRINT( "       ["<< it->first <<"-"<<it->first+(HISTOGRAM_BIN_SIZE-1)<<"] : "<< it->second );
 			if (VIS_FILE_OUTPUT)
 			{
-				(*visDataOut) << it->first <<"="<< it->second << endl;
+				csvOut.getOutputStream() << it->first <<"="<< it->second << endl;
 			}
 		}
 		if (currentClockCycle % EPOCH_LENGTH == 0)
@@ -952,6 +935,8 @@ void MemoryController::printStats(bool finalStats)
 #ifdef LOG_OUTPUT
 	dramsim_log.flush();
 #endif
+
+	resetStats();
 }
 MemoryController::~MemoryController()
 {

MemoryController.h

@@ -57,7 +57,7 @@ class MemoryController : public SimulatorObject
 
 public:
 	//functions
-	MemoryController(MemorySystem* ms, std::ofstream *outfile, ostream &dramsim_log_);
+	MemoryController(MemorySystem* ms, CSVWriter &csvOut_, ostream &dramsim_log_);
 	virtual ~MemoryController();
 
 	bool addTransaction(Transaction *trans);
@@ -67,6 +67,7 @@ class MemoryController : public SimulatorObject
 	void attachRanks(vector<Rank *> *ranks);
 	void update();
 	void printStats(bool finalStats = false);
+	void resetStats(); 
 
 
 	//fields
@@ -93,8 +94,7 @@ class MemoryController : public SimulatorObject
 	vector<Rank *> *ranks;
 
 	//output file
-	std::ofstream *visDataOut;
-	CSVWriter csvOut; 
+	CSVWriter &csvOut; 
 
 	// these packets are counting down waiting to be transmitted on the "bus"
 	BusPacket *outgoingCmdPacket;

MemorySystem.cpp

@@ -52,12 +52,12 @@ namespace DRAMSim {
 
 powerCallBack_t MemorySystem::ReportPower = NULL;
 
-MemorySystem::MemorySystem(unsigned id, unsigned int megsOfMemory, ofstream &visDataOut_, ostream &dramsim_log_) :
+MemorySystem::MemorySystem(unsigned id, unsigned int megsOfMemory, CSVWriter &csvOut_, ostream &dramsim_log_) :
 		dramsim_log(dramsim_log_),
 		ReturnReadData(NULL),
 		WriteDataDone(NULL),
 		systemID(id),
-		visDataOut(visDataOut_)
+		csvOut(csvOut_)
 {
 	currentClockCycle = 0;
 
@@ -128,7 +128,7 @@ MemorySystem::MemorySystem(unsigned id, unsigned int megsOfMemory, ofstream &vis
 	DEBUG("CH. " <<systemID<<" TOTAL_STORAGE : "<< TOTAL_STORAGE << "MB | "<<NUM_RANKS<<" Ranks | "<< NUM_DEVICES <<" Devices per rank");
 
 
-	memoryController = new MemoryController(this, &visDataOut, dramsim_log);
+	memoryController = new MemoryController(this, csvOut, dramsim_log);
 
 	// TODO: change to other vector constructor?
 	ranks = new vector<Rank *>();
@@ -198,14 +198,9 @@ bool MemorySystem::addTransaction(Transaction *trans)
 }
 
 //prints statistics
-void MemorySystem::printStats()
+void MemorySystem::printStats(bool finalStats)
 {
-	memoryController->printStats(true);
-}
-
-void MemorySystem::printStats(bool)
-{
-	printStats();
+	memoryController->printStats(finalStats);
 }
 
 

MemorySystem.h

@@ -44,6 +44,7 @@
 #include "Rank.h"
 #include "Transaction.h"
 #include "Callback.h"
+#include "CSVWriter.h"
 #include <deque>
 
 namespace DRAMSim
@@ -54,13 +55,12 @@ class MemorySystem : public SimulatorObject
 	ostream &dramsim_log;
 public:
 	//functions
-	MemorySystem(unsigned id, unsigned megsOfMemory, ofstream &visDataOut, ostream &dramsim_log_);
+	MemorySystem(unsigned id, unsigned megsOfMemory, CSVWriter &csvOut_, ostream &dramsim_log_);
 	virtual ~MemorySystem();
 	void update();
 	bool addTransaction(Transaction *trans);
 	bool addTransaction(bool isWrite, uint64_t addr);
-	void printStats();
-	void printStats(bool unused);
+	void printStats(bool finalStats);
 	bool WillAcceptTransaction();
 	void RegisterCallbacks(
 	    Callback_t *readDone,
@@ -81,7 +81,7 @@ class MemorySystem : public SimulatorObject
 	unsigned systemID;
 
 private:
-	ofstream &visDataOut; 
+	CSVWriter &csvOut;
 };
 }
 

MultiChannelMemorySystem.cpp

@@ -47,7 +47,8 @@ MultiChannelMemorySystem::MultiChannelMemorySystem(const string &deviceIniFilena
 	:megsOfMemory(megsOfMemory_), deviceIniFilename(deviceIniFilename_),
 	systemIniFilename(systemIniFilename_), traceFilename(traceFilename_),
 	pwd(pwd_), visFilename(visFilename_), 
-	clockDomainCrosser(new ClockDomain::Callback<MultiChannelMemorySystem, void>(this, &MultiChannelMemorySystem::actual_update))
+	clockDomainCrosser(new ClockDomain::Callback<MultiChannelMemorySystem, void>(this, &MultiChannelMemorySystem::actual_update)),
+	csvOut(new CSVWriter(visDataOut))
 {
 	currentClockCycle=0; 
 	if (visFilename)
@@ -93,10 +94,9 @@ MultiChannelMemorySystem::MultiChannelMemorySystem(const string &deviceIniFilena
 		ERROR("Zero channels"); 
 		abort(); 
 	}
-
 	for (size_t i=0; i<NUM_CHANS; i++)
 	{
-		MemorySystem *channel = new MemorySystem(i, megsOfMemory/NUM_CHANS, visDataOut, dramsim_log);
+		MemorySystem *channel = new MemorySystem(i, megsOfMemory/NUM_CHANS, (*csvOut), dramsim_log);
 		channels.push_back(channel);
 	}
 	// for compatibility with the old marss code which assumed an sg15 part with a
@@ -383,10 +383,22 @@ void MultiChannelMemorySystem::actual_update()
 		DEBUG("DRAMSim2 Clock Frequency ="<<clockDomainCrosser.clock1<<"Hz, CPU Clock Frequency="<<clockDomainCrosser.clock2<<"Hz"); 
 	}
 
+	if (currentClockCycle % EPOCH_LENGTH == 0)
+	{
+		(*csvOut) << "ms" <<currentClockCycle * tCK * 1E-6; 
+		for (size_t i=0; i<NUM_CHANS; i++)
+		{
+			channels[i]->printStats(false); 
+		}
+		csvOut->finalize();
+	}
+	
 	for (size_t i=0; i<NUM_CHANS; i++)
 	{
 		channels[i]->update(); 
 	}
+
+
 	currentClockCycle++; 
 }
 unsigned MultiChannelMemorySystem::findChannelNumber(uint64_t addr)
@@ -468,13 +480,16 @@ bool MultiChannelMemorySystem::willAcceptTransaction()
 
 
 
-void MultiChannelMemorySystem::printStats() {
+void MultiChannelMemorySystem::printStats(bool finalStats) {
+
+	(*csvOut) << "ms" <<currentClockCycle * tCK * 1E-6; 
 	for (size_t i=0; i<NUM_CHANS; i++)
 	{
 		PRINT("==== Channel ["<<i<<"] ====");
-		channels[i]->printStats(); 
+		channels[i]->printStats(finalStats); 
 		PRINT("//// Channel ["<<i<<"] ////");
 	}
+	csvOut->finalize();
 }
 void MultiChannelMemorySystem::RegisterCallbacks( 
 		TransactionCompleteCB *readDone,

MultiChannelMemorySystem.h

@@ -33,6 +33,7 @@
 #include "MemorySystem.h"
 #include "IniReader.h"
 #include "ClockDomain.h"
+#include "CSVWriter.h"
 
 
 namespace DRAMSim {
@@ -50,7 +51,7 @@ class MultiChannelMemorySystem : public SimulatorObject
 			bool willAcceptTransaction(); 
 			bool willAcceptTransaction(uint64_t addr); 
 			void update();
-			void printStats();
+			void printStats(bool finalStats=false);
 			ostream &getLogFile();
 			void RegisterCallbacks( 
 				TransactionCompleteCB *readDone,
@@ -77,6 +78,8 @@ class MultiChannelMemorySystem : public SimulatorObject
 		ClockDomain::ClockDomainCrosser clockDomainCrosser; 
 		static void mkdirIfNotExist(string path);
 		static bool fileExists(string path); 
+		CSVWriter *csvOut; 
+
 
 	};
 }

TraceBasedSim.cpp

@@ -604,7 +604,7 @@ int main(int argc, char **argv)
 	}
 
 	traceFile.close();
-	(*memorySystem).printStats();
+	memorySystem->printStats(true);
 	// make valgrind happy
 	if (trans)
 	{