Moved Vdd to ini file, added megsOfStorage computation for TraceBasedSim, updated some system.ini defaults

Author: dramninjasUMD

IniReader.cpp

@@ -35,14 +35,14 @@ using namespace std;
 
 uint64_t TOTAL_STORAGE;
 uint NUM_BANKS;
-uint NUM_RANKS;
 uint NUM_CHANS;
 uint NUM_ROWS;
 uint NUM_COLS;
 uint DEVICE_WIDTH;
 
 uint REFRESH_PERIOD;
 float tCK;
+float Vdd;
 uint CL;
 uint AL;
 uint BL;
@@ -79,7 +79,7 @@ uint IDD7;
 
 
 //in bytes
-uint CACHE_LINE_SIZE; //4
+uint CACHE_LINE_SIZE;
 
 uint JEDEC_DATA_BUS_WIDTH;
 
@@ -162,9 +162,8 @@ static ConfigMap configMap[] =
 	DEFINE_UINT_PARAM(IDD6,DEV_PARAM),
 	DEFINE_UINT_PARAM(IDD6L,DEV_PARAM),
 	DEFINE_UINT_PARAM(IDD7,DEV_PARAM),
+	DEFINE_FLOAT_PARAM(Vdd,DEV_PARAM),
 
-	//DEFINE_UINT64_PARAM(TOTAL_STORAGE,SYS_PARAM),
-	DEFINE_UINT_PARAM(NUM_RANKS,SYS_PARAM),
 	DEFINE_UINT_PARAM(NUM_CHANS,SYS_PARAM),
 	DEFINE_UINT_PARAM(CACHE_LINE_SIZE,SYS_PARAM),
 	DEFINE_UINT_PARAM(JEDEC_DATA_BUS_WIDTH,SYS_PARAM),
@@ -187,7 +186,6 @@ static ConfigMap configMap[] =
 	DEFINE_BOOL_PARAM(DEBUG_BUS,SYS_PARAM),
 	DEFINE_BOOL_PARAM(DEBUG_BANKS,SYS_PARAM),
 	DEFINE_BOOL_PARAM(DEBUG_POWER,SYS_PARAM),
-	//modelsim output mode?
 	DEFINE_BOOL_PARAM(VERIFICATION_OUTPUT,SYS_PARAM),
 	{"", NULL, UINT, SYS_PARAM, false} // tracer value to signify end of list; if you delete it, epic fail will result
 };
@@ -601,21 +599,4 @@ void IniReader::InitEnumsFromStrings()
 
 }
 
-#if 0
-// Wrote it, but did not use it -- might be handy in the future
-void IniReader::Trim(string &str)
-{
-	size_t begin,end;
-	if ((begin = str.find_first_not_of(" ")) == string::npos)
-	{
-		begin = 0;
-	}
-	if ((end = str.find_last_not_of(" ")) == string::npos)
-	{
-		end = str.size()-1;
-	}
-	str = str.substr(begin,end-begin+1);
-}
-#endif
-
-}
+} // namespace DRAMSim

IniReader.h

@@ -68,8 +68,6 @@ class IniReader
 	static void InitEnumsFromStrings();
 	static bool CheckIfAllSet();
 	static void WriteValuesOut(std::ofstream &visDataOut);
-private:
-	static void Trim(string &str);
 };
 }
 

MemoryController.cpp

@@ -90,11 +90,6 @@ MemoryController::MemoryController(MemorySystem *parent, std::ofstream *outfile)
 	*********************/
 	//TODO: 
 
-	//uint64_t total_storage64 = (uint64_t)TOTAL_STORAGE;
-	//NUM_DEVICES = (total_storage64*8) / (NUM_ROWS * NUM_COLS * DEVICE_WIDTH * NUM_BANKS);
-	NUM_DEVICES = ((TOTAL_STORAGE * 8) / ((long)NUM_ROWS * NUM_COLS * DEVICE_WIDTH * NUM_BANKS))/NUM_RANKS;
-
-	DEBUG ("NUM DEVICES="<<NUM_DEVICES);
 
 	//bus related fields
 	outgoingCmdPacket = NULL;
@@ -1038,9 +1033,6 @@ void MemoryController::printStats(bool finalStats)
 	if (currentClockCycle == 0)
 		return;
 
-//TODO: move Vdd to config file
-	float Vdd = 1.9;
-
 	//if we are not at the end of the epoch, make sure to adjust for the actual number of cycles elapsed
 
 	uint64_t cyclesElapsed = (currentClockCycle % EPOCH_COUNT == 0) ? EPOCH_COUNT : currentClockCycle % EPOCH_COUNT;

MemoryController.h

@@ -123,7 +123,6 @@ class MemoryController : public SimulatorObject
 
 	uint refreshRank;
 
-	uint NUM_DEVICES;
 };
 }
 

MemorySystem.cpp

@@ -41,6 +41,9 @@ using namespace std;
 
 ofstream cmd_verify_out; //used in Rank.cpp and MemoryController.cpp if VERIFICATION_OUTPUT is set
 
+unsigned NUM_DEVICES;
+unsigned NUM_RANKS;
+
 namespace DRAMSim {
 #ifdef LOG_OUTPUT
 ofstream dramsim_log;
@@ -89,7 +92,7 @@ MemorySystem::MemorySystem(uint id, string deviceIniFilename, string systemIniFi
 	//calculate the total storage based on the devices the user selected and the number of
 
 	// number of bytes per rank
-	unsigned long megsOfStoragePerRank = (((NUM_ROWS * (NUM_COLS * DEVICE_WIDTH) * NUM_BANKS) * (JEDEC_DATA_BUS_WIDTH / DEVICE_WIDTH)) / 8) >> 20;
+	unsigned long megsOfStoragePerRank = ((((long)NUM_ROWS * (NUM_COLS * DEVICE_WIDTH) * NUM_BANKS) * ((long)JEDEC_DATA_BUS_WIDTH / DEVICE_WIDTH)) / 8) >> 20;
 
 	// If this is set, effectively override the number of ranks
 	if (megsOfMemory != 0)
@@ -102,9 +105,10 @@ MemorySystem::MemorySystem(uint id, string deviceIniFilename, string systemIniFi
 		}
 	}
 
-	TOTAL_STORAGE = (NUM_RANKS * megsOfStoragePerRank) << 10; 
+	NUM_DEVICES = 64/DEVICE_WIDTH;
+	TOTAL_STORAGE = (NUM_RANKS * megsOfStoragePerRank); 
 
-	DEBUG("TOTAL_STORAGE : "<<TOTAL_STORAGE);
+	DEBUG("TOTAL_STORAGE : "<< TOTAL_STORAGE << "MB | "<<NUM_RANKS<<" Ranks | "<< NUM_DEVICES <<" Devices per rank");
 
 	IniReader::InitEnumsFromStrings();
 	if (!IniReader::CheckIfAllSet())
@@ -284,7 +288,7 @@ string MemorySystem::SetOutputFileName(string traceFilename)
 	}
 
 	/* I really don't see how "the C++ way" is better than snprintf()  */
-	out << (TOTAL_STORAGE>>30) << "GB." << NUM_CHANS << "Ch." << NUM_RANKS <<"R." <<ADDRESS_MAPPING_SCHEME<<"."<<ROW_BUFFER_POLICY<<"."<< TRANS_QUEUE_DEPTH<<"TQ."<<CMD_QUEUE_DEPTH<<"CQ."<<sched<<"."<<queue;
+	out << (TOTAL_STORAGE>>10) << "GB." << NUM_CHANS << "Ch." << NUM_RANKS <<"R." <<ADDRESS_MAPPING_SCHEME<<"."<<ROW_BUFFER_POLICY<<"."<< TRANS_QUEUE_DEPTH<<"TQ."<<CMD_QUEUE_DEPTH<<"CQ."<<sched<<"."<<queue;
 	if (sim_description)
 	{
 		out << "." << sim_description;

SystemConfiguration.h

@@ -45,6 +45,7 @@
 extern std::ofstream cmd_verify_out; //used by BusPacket.cpp if VERIFICATION_OUTPUT is enabled
 //extern std::ofstream visDataOut;
 
+//TODO: namespace these to DRAMSim:: 
 extern bool VERIFICATION_OUTPUT; // output suitable to feed to modelsim
 
 extern bool DEBUG_TRANS_Q;
@@ -104,6 +105,8 @@ extern uint IDD5;
 extern uint IDD6;
 extern uint IDD6L;
 extern uint IDD7;
+extern float Vdd; 
+extern unsigned NUM_DEVICES;
 
 //same bank
 #define READ_TO_PRE_DELAY (AL+BL/2+max(((int)tRTP),2)-2)
@@ -115,7 +118,7 @@ extern uint IDD7;
 #define WRITE_TO_READ_DELAY_R (WL+BL/2+tRTRS-RL) //interrank
 
 //in bytes
-extern uint CACHE_LINE_SIZE; //4
+extern uint CACHE_LINE_SIZE; 
 
 extern uint JEDEC_DATA_BUS_WIDTH;
 

TraceBasedSim.cpp

@@ -54,6 +54,7 @@ void usage()
 	cout << "\t-q, --quiet \t\t\tflag to suppress simulation output (except final stats) [default=no]"<<endl;
 	cout << "\t-o, --option=OPTION_A=234\t\t\toverwrite any ini file option from the command line"<<endl;
 	cout << "\t-p, --pwd=DIRECTORY\t\tSet the working directory (i.e. usually DRAMSim directory where ini/ and results/ are)"<<endl;
+	cout << "\t-S, --size=# \t\t\tSize of the memory system in megabytes"<<endl;
 }
 #endif
 
@@ -241,14 +242,15 @@ int main(int argc, char **argv)
 	string systemIniFilename = "ini/system.ini";
 	string deviceIniFilename = "";
 	string pwdString = "";
+	unsigned megsOfMemory=2048;
 
 	bool overrideOpt = false;
 	string overrideKey = "";
 	string overrideVal = "";
 	string tmp = "";
 	size_t equalsign;
 
-	uint numCycles=30;
+	uint numCycles=100;
 	//getopt stuff
 	while (1)
 	{
@@ -262,10 +264,11 @@ int main(int argc, char **argv)
 			{"option",  required_argument,	0, 'o'},
 			{"quiet",  no_argument, &SHOW_SIM_OUTPUT, 'q'},
 			{"help", no_argument, 0, 'h'},
+			{"size", required_argument, 0, 'S'},
 			{0, 0, 0, 0}
 		};
 		int option_index=0; //for getopt
-		c = getopt_long (argc, argv, "t:s:c:d:o:p:bkq", long_options, &option_index);
+		c = getopt_long (argc, argv, "t:s:c:d:o:p:S:bkq", long_options, &option_index);
 		if (c == -1)
 		{
 			break;
@@ -301,6 +304,9 @@ int main(int argc, char **argv)
 		case 'c':
 			numCycles = atoi(optarg);
 			break;
+		case 'S':
+			megsOfMemory=atoi(optarg);
+			break;
 		case 'p':
 			pwdString = string(optarg);
 			break;
@@ -366,8 +372,7 @@ int main(int argc, char **argv)
 	string line;
 
 
-	MemorySystem *memorySystem;
-	memorySystem = new MemorySystem(0, deviceIniFilename, systemIniFilename, pwdString, traceFileName, 0);
+	MemorySystem *memorySystem = new MemorySystem(0, deviceIniFilename, systemIniFilename, pwdString, traceFileName, megsOfMemory);
 
 	uint64_t addr;
 	uint64_t clockCycle=0;

ini/DDR2_micron_16M_8b_x8_sg3E.ini

@@ -46,4 +46,4 @@ IDD5=215;
 IDD6=7;
 IDD6L=5;
 IDD7=280;
-
+Vdd=1.8 ; TODO: double check this

ini/DDR2_micron_32M_4B_x4_sg3E.ini

@@ -55,3 +55,4 @@ IDD7=240;
 ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP)
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
+Vdd=1.8 ; TODO: double check this

ini/DDR2_micron_32M_8B_x4_sg25E.ini

@@ -55,3 +55,4 @@ IDD7=335;
 ;WRITE_AUTOPRE_DELAY=(WL+BL/2+tWR+tRP)
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
+Vdd=1.8 ; TODO: double check this

ini/DDR3_micron_16M_8B_x8_sg15.ini

@@ -55,3 +55,4 @@ IDD7=490;
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
 
+Vdd=1.5 ; TODO: double check this

ini/DDR3_micron_32M_8B_x4_sg125.ini

@@ -57,3 +57,4 @@ IDD7=400 ; this is unused
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
 
+Vdd=1.5 ; TODO: double check this

ini/DDR3_micron_32M_8B_x4_sg15.ini

@@ -55,3 +55,4 @@ IDD7=315;
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
 
+Vdd=1.5 ; TODO: double check this

ini/DDR3_micron_32M_8B_x8_sg15.ini

@@ -55,3 +55,4 @@ IDD7=460;
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
 
+Vdd=1.5 ; TODO: double check this

ini/DDR3_micron_32M_8B_x8_sg25E.ini

@@ -55,3 +55,4 @@ IDD7=400;
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
 
+Vdd=1.5 ; TODO: double check this

ini/DDR3_micron_64M_8B_x4_sg15.ini

@@ -55,3 +55,4 @@ IDD7=415;
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
 
+Vdd=1.5 ; TODO: double check this

ini/DDR3_micron_8M_8B_x16_sg15.ini

@@ -55,3 +55,4 @@ IDD7=420;
 ;WRITE_TO_READ_DELAY_B=(WL+BL/2+tWTR);interbank
 ;WRITE_TO_READ_DELAY_R=(WL+BL/2+tRTRS-RL);interrank
 
+Vdd=1.5 ; TODO: double check this

system.ini.example

@@ -1,15 +1,14 @@
 ; COPY THIS FILE AND MODIFY IT TO SUIT YOUR NEEDS
 
-NUM_RANKS=2
 NUM_CHANS=1								; we haven't tested a whole lot with CHANS>1 so use at your own peril 
 JEDEC_DATA_BUS_WIDTH=64 			; will never change for DDR parts
-CACHE_LINE_SIZE=8						; should never change for a normal CPU (in bytes)
-TRANS_QUEUE_DEPTH=8					; transaction queue ex: READ 0xbeef
-CMD_QUEUE_DEPTH=8						; command queue ex: RAS 4
+CACHE_LINE_SIZE=64						; should never change for a normal CPU (in bytes)
+TRANS_QUEUE_DEPTH=512					; transaction queue ex: READ 0xbeef
+CMD_QUEUE_DEPTH=512						; command queue ex: RAS 4
 EPOCH_COUNT=100000						; length of an epoch in cycles (granularity of simulation)
 ROW_BUFFER_POLICY=open_page 		; close_page or open_page
-ADDRESS_MAPPING_SCHEME=scheme2	;valid schemes 1-4
-SCHEDULING_POLICY=rank_then_bank_round_robin  ; rank_then_bank_round_robin or rank_then_bank_round_robin 
+ADDRESS_MAPPING_SCHEME=scheme2	;valid schemes 1-6
+SCHEDULING_POLICY=rank_then_bank_round_robin  ; bank_then_rank_round_robin or rank_then_bank_round_robin 
 QUEUING_STRUCTURE=per_rank			;per_rank or per_rank_per_bank
 
 ;for true/false, please use all lowercase