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- DRAMSim2
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- ----------------------------------------
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+ DRAMSim2: A cycle accurate DRAM Simulator
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+ ================================================================================
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Elliott Cooper-Balis
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Paul Rosenfeld
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+ Bruce Jacob
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University of Maryland
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dramninjas [at] gmail [dot] com
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- ----------------------------------------
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-
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- 1 About DRAMSim2
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+ 1 About DRAMSim2 --------------------------------------------------------------------------------
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DRAMSim2 is a cycle accurate model of a DRAM memory controller, the DRAM modules which comprise
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system storage, and the buses by which they communicate.
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section 4.2). This core has no external run time or build time dependencies and has been tested with g++ on
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Linux as well as g++ on Cygwin on Windows.
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-
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- 2 Getting DRAMSim2 ------------------
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+ 2 Getting DRAMSim2--------------------------------------------------------------------------------
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DRAMSim2 is available on github. If you have git installed you can clone our repository by typing:
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- $ git clone http ://github.com/dramninjasUMD/DRAMSim2.git
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+ $ git clone git ://github.com/dramninjasUMD/DRAMSim2.git
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- 3 Building DRAMSim2 ------------------
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+ 3 Building DRAMSim2-------------------------------------------------------------- ------------------
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To build an optimized standalone trace-based simulator called DRAMSim simply type:
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$ make
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$ make libdramsim.so
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- 4 Running DRAMSim2 -------------------
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+ 4 Running DRAMSim2------------------------------------------------------------- -------------------
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- 4.1 Trace-Based Simulation -----------
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+ 4.1 Trace-Based Simulation--------------------------------------------------------------------- -----------
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In standalone mode, DRAMSim2 can simulate memory system traces. While traces are not as accurate as a
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real CPU model driving the memory model, they are convenient since they can be generated in a number of
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different ways (instrumentation, hardware traces, CPU simulation, etc.) and reused.
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The prefix of the filename determines which type of trace this function will use (ex: k6 foo.trc) will use the k6
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format in parseTraceFileLine().
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- 4.2 Library Interface
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+ 4.2 Library Interface--------------------------------------------------------------------------------
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In addition to simulating memory traces, DRAMSim2 can also be built as a dynamic shared library which
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is convenient for connecting it to CPU simulators or other custom front ends. A MemorySystem object
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directory. At this time we have plans to provide code to integrate DRAMSim2 into MARSSx86, SST, and
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(eventually) M5.
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- 5 Example Output --------------------------------------
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-
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The verbosity of the DRAMSim2 can be customized in the system.ini file by turning the various debug flags on
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or off.
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Below, we have provided a detailed explanation of the simulator output. With all DEBUG flags enabled, the
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Banks can be in many states, including idle, row active (shown with the row that is active), refreshing, or
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precharging. These states will update based on the commands being sent by the controller.
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- 6 Results Output ---------------------------------
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+ 6 Results Output----------------------------------------------- ---------------------------------
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In addition to printing memory statistics and debug information to standard out, DRAMSim2 also produces a
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'vis' file in the results/ directory. A vis file is essentially a summary of relevant statistics that is generated per
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- epoch (the number of cycles per epoch can be set by changing the EPOCHCOUNT parameter in the system.ini
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+ epoch (the number of cycles per epoch can be set by changing the EPOCH_COUNT parameter in the system.ini
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file).
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We are currently working on DRAMVis, which is a cross-platform viewer which parses the vis file and generates
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graphs that can be used to analyze and compare results.
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