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Paul Rosenfeld
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Initial import for release
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‎.gitignore

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results/

‎Bank.cpp

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//Bank.cpp
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//
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//Class file for bank object
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//
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#include "Bank.h"
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#include "BusPacket.h"
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using namespace std;
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using namespace DRAMSim;
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Bank::Bank():
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rowEntries(NUM_COLS)
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{}
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/* The bank class is just a glorified sparse storage data structure
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* that keeps track of written data in case the simulator wants a
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* function DRAM model
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*
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* A vector of size NUM_COLS keeps a linked list of rows and their
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* associated values.
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*
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* write() adds an entry to the proper linked list or replaces the
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* value in a row that was already written
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*
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* read() searches for a node with the right row value, if not found
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* returns the tracer value 0xDEADBEEF
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*/
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Bank::DataStruct *Bank::searchForRow(uint row, DataStruct *head)
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{
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while(head != NULL)
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{
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if(head->row == row)
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{
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//found it
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return head;
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}
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//keep looking
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head = head->next;
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}
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//if we get here, didn't find it
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return NULL;
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}
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void Bank::read(BusPacket &busPacket)
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{
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DataStruct *rowHeadNode = rowEntries[busPacket.column];
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DataStruct *foundNode = NULL;
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if ((foundNode = Bank::searchForRow(busPacket.row, rowHeadNode)) == NULL)
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{
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// the row hasn't been written before, so it isn't in the list
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//if(SHOW_SIM_OUTPUT) DEBUG("== Warning - Read from previously unwritten row " << busPacket.row);
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void *garbage = calloc(BL * JEDEC_DATA_BUS_WIDTH,1);
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((long *)garbage)[0] = 0xdeadbeef; // tracer value
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busPacket.data = garbage;
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}
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else // found it
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{
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busPacket.data = foundNode->data;
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}
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//the return packet should be a data packet, not a read packet
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busPacket.busPacketType = DATA;
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}
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void Bank::write(const BusPacket &busPacket)
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{
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//TODO: move all the error checking to BusPacket so once we have a bus packet,
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// we know the fields are all legal
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if (busPacket.column >= NUM_COLS)
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{
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ERROR("== Error - Bus Packet column "<< busPacket.column <<" out of bounds");
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exit(-1);
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}
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// head of the list we need to search
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DataStruct *rowHeadNode = rowEntries[busPacket.column];
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DataStruct *foundNode = NULL;
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if ((foundNode = Bank::searchForRow(busPacket.row, rowHeadNode)) == NULL)
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{
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//not found
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DataStruct *newRowNode = (DataStruct *)malloc(sizeof(DataStruct));
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//insert at the head for speed
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//TODO: Optimize this data structure for speedier lookups?
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newRowNode->row = busPacket.row;
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newRowNode->data = busPacket.data;
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newRowNode->next = rowHeadNode;
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rowEntries[busPacket.column] = newRowNode;
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}
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else
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{
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// found it, just plaster in the new data
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foundNode->data = busPacket.data;
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if (DEBUG_BANKS) {
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PRINTN(" -- Bank "<<busPacket.bank<<" writing to physical address 0x" << hex << busPacket.physicalAddress<<dec<<":");
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BusPacket::printData(busPacket.data);
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PRINT("");
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}
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}
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}
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‎Bank.h

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#ifndef BANK_H
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#define BANK_H
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//Bank.h
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//
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//Header file for bank class
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//
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#include "SystemConfiguration.h"
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#include "SimulatorObject.h"
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#include "BankState.h"
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#include "BusPacket.h"
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namespace DRAMSim
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{
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class Bank
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{
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typedef struct _DataStruct
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{
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uint row;
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void *data;
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struct _DataStruct *next;
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} DataStruct;
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public:
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//functions
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Bank();
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void read(BusPacket &busPacket);
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void write(const BusPacket &busPacket);
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//fields
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BankState currentState;
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private:
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// private member
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std::vector<DataStruct *> rowEntries;
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static DataStruct *searchForRow(uint row, DataStruct *head);
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};
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}
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#endif
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‎BankState.cpp

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//BankState.cpp
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//
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//Class file for bank state object
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//
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#include "BankState.h"
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using namespace std;
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using namespace DRAMSim;
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//All banks start precharged
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BankState::BankState():
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currentBankState(Idle),
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openRowAddress(0),
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nextRead(0),
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nextWrite(0),
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nextActivate(0),
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nextPrecharge(0),
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nextPowerUp(0),
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lastCommand(READ),
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stateChangeCountdown(0)
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{}
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void BankState::print()
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{
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PRINT(" == Bank State ");
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if(currentBankState == Idle)
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{
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PRINT(" State : Idle" );
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}
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else if(currentBankState == RowActive)
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{
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PRINT(" State : Active" );
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}
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else if(currentBankState == Refreshing)
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{
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PRINT(" State : Refreshing" );
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}
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else if(currentBankState == PowerDown)
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{
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PRINT(" State : Power Down" );
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}
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PRINT(" OpenRowAddress : " << openRowAddress );
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PRINT(" nextRead : " << nextRead );
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PRINT(" nextWrite : " << nextWrite );
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PRINT(" nextActivate : " << nextActivate );
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PRINT(" nextPrecharge : " << nextPrecharge );
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PRINT(" nextPowerUp : " << nextPowerUp );
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}

‎BankState.h

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#ifndef BANKSTATE_H
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#define BANKSTATE_H
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//BankState.h
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//
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//Header file for bank state class
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//
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#include "SystemConfiguration.h"
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#include "BusPacket.h"
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namespace DRAMSim
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{
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enum CurrentBankState
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{
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Idle,
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RowActive,
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Precharging,
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Refreshing,
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PowerDown
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};
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class BankState
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{
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public:
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//Fields
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CurrentBankState currentBankState;
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uint openRowAddress;
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uint64_t nextRead;
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uint64_t nextWrite;
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uint64_t nextActivate;
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uint64_t nextPrecharge;
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uint64_t nextPowerUp;
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BusPacketType lastCommand;
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uint stateChangeCountdown;
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//Functions
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BankState();
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void print();
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};
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}
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#endif
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‎BusPacket.cpp

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//BusPacket.cpp
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//
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//Class file for bus packet object
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//
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#include "BusPacket.h"
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using namespace DRAMSim;
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using namespace std;
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BusPacket::BusPacket(BusPacketType packtype, uint64_t physicalAddr, uint col, uint rw, uint r, uint b, void *dat)
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{
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physicalAddress = physicalAddr;
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busPacketType = packtype;
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data = dat;
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rank = r;
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bank = b;
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column = col;
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row = rw;
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}
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BusPacket::BusPacket() {}
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void BusPacket::print(uint64_t currentClockCycle, bool dataStart)
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{
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if (this == NULL) {
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return;
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}
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if (VERIFICATION_OUTPUT)
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{
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switch(busPacketType)
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{
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case READ:
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cmd_verify_out << currentClockCycle << ": read ("<<rank<<","<<bank<<","<<column<<",0);"<<endl;
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break;
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case READ_P:
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cmd_verify_out << currentClockCycle << ": read ("<<rank<<","<<bank<<","<<column<<",1);"<<endl;
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break;
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case WRITE:
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cmd_verify_out << currentClockCycle << ": write ("<<rank<<","<<bank<<","<<column<<",0 , 0, 'h0);"<<endl;
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break;
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case WRITE_P:
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cmd_verify_out << currentClockCycle << ": write ("<<rank<<","<<bank<<","<<column<<",1, 0, 'h0);"<<endl;
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break;
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case ACTIVATE:
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cmd_verify_out << currentClockCycle <<": activate (" << rank << "," << bank << "," << row <<");"<<endl;
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break;
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case PRECHARGE:
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cmd_verify_out << currentClockCycle <<": precharge (" << rank << "," << bank << "," << row <<");"<<endl;
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break;
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case REFRESH:
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cmd_verify_out << currentClockCycle <<": refresh (" << rank << ");"<<endl;
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break;
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case DATA:
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//TODO: data verification?
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break;
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default:
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ERROR("Trying to print unknown kind of bus packet");
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exit(-1);
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}
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}
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}
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void BusPacket::print()
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{
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if (this == NULL) //pointer use makes this a necessary precaution
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{
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return;
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}
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else {
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switch(busPacketType)
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{
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case READ:
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PRINT("BP [READ] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"]");
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break;
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case READ_P:
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PRINT("BP [READ_P] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"]");
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break;
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case WRITE:
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PRINT("BP [WRITE] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"]");
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break;
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case WRITE_P:
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PRINT("BP [WRITE_P] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"]");
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break;
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case ACTIVATE:
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PRINT("BP [ACT] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"]");
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break;
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case PRECHARGE:
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PRINT("BP [PRE] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"]");
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break;
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case REFRESH:
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PRINT("BP [REF] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"]");
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break;
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case DATA:
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PRINTN("BP [DATA] pa[0x"<<hex<<physicalAddress<<dec<<"] r["<<rank<<"] b["<<bank<<"] row["<<row<<"] col["<<column<<"] data["<<data<<"]=");
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BusPacket::printData(data);
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PRINT("");
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break;
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default:
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ERROR("Trying to print unknown kind of bus packet");
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exit(-1);
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}
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}
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}
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void BusPacket::printData(const void *data)
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{
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if (data == NULL)
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{
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PRINTN("NO DATA");
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return;
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}
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PRINTN("'" << hex);
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for (int i=0; i < 4; i++)
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{
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PRINTN(((uint64_t *)data)[i]);
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}
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PRINTN("'" << dec);
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}

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