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cpu.cpp
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cpu.cpp
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#include "cpu.h"
#include "comm.h"
#include "disassembler.h"
#include "mem.h"
#include "state.h"
#include <mutex>
#include "console.h"
#include <thread>
extern nc1020_states_t nc1020_states;
static uint32_t& cycles = nc1020_states.cycles;
static bool& should_irq = nc1020_states.should_irq;
static bool& timer0_toggle = nc1020_states.timer0_toggle;
static uint32_t& timer0_cycles = nc1020_states.timer0_cycles;
static uint32_t& timer1_cycles = nc1020_states.timer1_cycles;
static bool& should_wake_up = nc1020_states.should_wake_up;
static uint16_t& reg_pc = nc1020_states.cpu.reg_pc;
static uint8_t& reg_a = nc1020_states.cpu.reg_a;
static uint8_t& reg_ps = nc1020_states.cpu.reg_ps;
static uint8_t& reg_x = nc1020_states.cpu.reg_x;
static uint8_t& reg_y = nc1020_states.cpu.reg_y;
static uint8_t& reg_sp = nc1020_states.cpu.reg_sp;
double speed_multiplier=1.0;
void reset_cpu_states(){
nc1020_states.should_irq = false;
nc1020_states.cycles = 0;
nc1020_states.cpu.reg_a = 0;
nc1020_states.cpu.reg_ps = 0x24;
nc1020_states.cpu.reg_x = 0;
nc1020_states.cpu.reg_y = 0;
nc1020_states.cpu.reg_sp = 0xFF;
nc1020_states.cpu.reg_pc = PeekW(RESET_VEC);
nc1020_states.timer0_cycles = CYCLES_TIMER0;
nc1020_states.timer1_cycles = CYCLES_TIMER1;
}
void AdjustTime(){
uint8_t* clock_buff = nc1020_states.clock_buff;
if (++ clock_buff[0] >= 60) {
clock_buff[0] = 0;
if (++ clock_buff[1] >= 60) {
clock_buff[1] = 0;
if (++ clock_buff[2] >= 24) {
clock_buff[2] &= 0xC0;
++ clock_buff[3];
}
}
}
}
bool IsCountDown(){
uint8_t* clock_buff = nc1020_states.clock_buff;
uint8_t& clock_flags = nc1020_states.clock_flags;
if (!(clock_buff[10] & 0x02) ||
!(clock_flags & 0x02)) {
return false;
}
return (
((clock_buff[7] & 0x80) && !(((clock_buff[7] ^ clock_buff[2])) & 0x1F)) ||
((clock_buff[6] & 0x80) && !(((clock_buff[6] ^ clock_buff[1])) & 0x3F)) ||
((clock_buff[5] & 0x80) && !(((clock_buff[5] ^ clock_buff[0])) & 0x3F))
);
}
void inject(){
for(int i=0;i<8;i++){
for(int j=0;j<=0xFE;j+=2){
ram_b[0x100*i+j]=j;
ram_b[0x100*i+j+1]=i;
}
}
for(int i=0;i<16;i++){
printf("<%x>",ram_b[i]);
}
printf("\n");
memcpy(nc1020_states.ext_ram, inject_code.c_str(), inject_code.size());
ram_io[0x00]=0x80;
ram_io[0x0a]=0x80;
//Peek16(0xe3)=0x40;
//ram_io[0x0d]&=0x5d;
super_switch();
//Peek16(0x280)=0xFF;
//Peek16(0x281)=0xFF;
//Peek16(0x282)=0xFF;
//Peek16(0x283)=0xFF;
//Peek16(0xe3)=0x40;
//Peek16(0xe4)=0xb2;
//nc1020_states.ext_ram[0x17]=0x58;
reg_pc=0x4018;
}
void cpu_run(){
string msg=get_message();
if(!msg.empty()){
handle_cmd(msg);
}
tick++;
//if(tick%100000000==0) printf("tick=%lld\n",tick);
//#ifdef DEBUG
// if (executed_insts == 2792170) {
// printf("debug start!\n");
// }
// if (executed_insts >= debug_logs.insts_start &&
// executed_insts < debug_logs.insts_start + debug_logs.insts_count) {
// log_rec_t& log = debug_logs.logs[executed_insts - debug_logs.insts_start];
// string debug_info;
// if (log.reg_pc != reg_pc) {
// debug_info += " pc ";
// }
// if (log.reg_a != reg_a) {
// debug_info += " a ";
// }
// if (log.reg_ps != reg_ps) {
// debug_info += " ps ";
// }
// if (log.reg_x != reg_x) {
// debug_info += " x ";
// }
// if (log.reg_y != reg_y) {
// debug_info += " y ";
// }
// if (log.reg_sp != reg_sp) {
// debug_info += " sp ";
// }
// if (debug_logs.peek_addr != -1) {
// if (log.peeked != Peek((uint16_t)debug_logs.peek_addr)) {
// debug_info += " mem ";
// }
// } else {
// if (log.peeked != Peek(reg_pc)) {
// debug_info += " op ";
// }
// }
// if (debug_info.length()) {
// printf("%d: %s\n", executed_insts, debug_info.c_str());
// exit(-1);
// }
// }
// if (executed_insts >= debug_logs.insts_start + debug_logs.insts_count) {
// printf("ok\n");
// }
//#endif
//if(tick>8525000) wanna_inject=true;
if(enable_inject&& tick>60000000) wanna_inject=true;
if(wanna_inject&& !injected){
inject();
printf("injected!!!");
wanna_inject=false;
injected=true;
}
//if(tick>=6012850) enable_debug_pc=true;
//if(injected && reg_pc==0x2000) enable_debug_pc=true;
if(enable_debug_pc||enable_dyn_debug){
unsigned char buf[10];
buf[0]=Peek16(reg_pc);
buf[1]=Peek16(reg_pc+1);
buf[2]=Peek16(reg_pc+2);
buf[3]=0;
printf("tick=%lld ",tick /*, reg_pc*/);
printf("%02x %02x %02x %02x; ",Peek16(reg_pc), Peek16(reg_pc+1),Peek16(reg_pc+2),Peek16(reg_pc+3));
printf("bs=%02x roa_bbs=%02x ramb=%02x zp=%02x reg=%02x,%02x,%02x,%02x,%03o pc=%s",ram_io[0x00], ram_io[0x0a], ram_io[0x0d], ram_io[0x0f],reg_a,reg_x,reg_y,reg_sp,reg_ps,disassemble_next(buf,reg_pc).c_str());
printf("\n");
//getchar();
}
if(injected && tick%1==0){
//printf("bs=%x roa_bbs=%x pc=%x %x %x %x %x \n",ram_io[0x00], ram_io[0x0a], reg_pc, Peek16(reg_pc), Peek16(reg_pc+1),Peek16(reg_pc+2),Peek16(reg_pc+3));
//getchar();
}
switch (Peek16(reg_pc++)) {
case 0x00: {
reg_pc++;
stack[reg_sp--] = reg_pc >> 8;
stack[reg_sp--] = reg_pc & 0xFF;
reg_ps |= 0x10;
stack[reg_sp--] = reg_ps;
reg_ps |= 0x04;
reg_pc = PeekW(IRQ_VEC);
cycles += 7;
}
break;
case 0x01: {
uint16_t addr = PeekW((Peek16(reg_pc++) + reg_x) & 0xFF);
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 6;
}
break;
case 0x02: {
//reg_pc+=1;
}
break;
case 0x03: {
}
break;
case 0x04: {
}
break;
case 0x05: {
uint16_t addr = Peek16(reg_pc++);
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 3;
}
break;
case 0x06: {
uint16_t addr = Peek16(reg_pc++);
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 >> 7);
tmp1 <<= 1;
reg_ps |= (tmp1 & 0x80) | (!tmp1 << 1);
Store(addr, tmp1);
cycles += 5;
}
break;
case 0x07: {
}
break;
case 0x08: {
stack[reg_sp--] = reg_ps;
cycles += 3;
}
break;
case 0x09: {
uint16_t addr = reg_pc++;
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 2;
}
break;
case 0x0A: {
reg_ps &= 0x7C;
reg_ps |= reg_a >> 7;
reg_a <<= 1;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 2;
}
break;
case 0x0B: {
}
break;
case 0x0C: {
}
break;
case 0x0D: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x0E: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 >> 7);
tmp1 <<= 1;
reg_ps |= (tmp1 & 0x80) | (!tmp1 << 1);
Store(addr, tmp1);
cycles += 6;
}
break;
case 0x0F: {
}
break;
case 0x10: {
int8_t tmp4 = (int8_t) (Peek16(reg_pc++));
uint16_t addr = reg_pc + tmp4;
if (!(reg_ps & 0x80)) {
cycles += !((reg_pc ^ addr) & 0xFF00) << 1;
reg_pc = addr;
}
cycles += 2;
}
break;
case 0x11: {
uint16_t addr = PeekW(Peek16(reg_pc));
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc++;
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 5;
}
break;
case 0x12: {
}
break;
case 0x13: {
}
break;
case 0x14: {
}
break;
case 0x15: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x16: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 >> 7);
tmp1 <<= 1;
reg_ps |= (tmp1 & 0x80) | (!tmp1 << 1);
Store(addr, tmp1);
cycles += 6;
}
break;
case 0x17: {
}
break;
case 0x18: {
reg_ps &= 0xFE;
cycles += 2;
}
break;
case 0x19: {
uint16_t addr = PeekW(reg_pc);
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc += 2;
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x1A: {
}
break;
case 0x1B: {
}
break;
case 0x1C: {
}
break;
case 0x1D: {
uint16_t addr = PeekW(reg_pc);
cycles += !!(((addr & 0xFF) + reg_x) & 0xFF00);
addr += reg_x;
reg_pc += 2;
reg_a |= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x1E: {
uint16_t addr = PeekW(reg_pc);
addr += reg_x;
reg_pc += 2;
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 >> 7);
tmp1 <<= 1;
reg_ps |= (tmp1 & 0x80) | (!tmp1 << 1);
Store(addr, tmp1);
cycles += 6;
}
break;
case 0x1F: {
}
break;
case 0x20: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
reg_pc--;
stack[reg_sp--] = reg_pc >> 8;
stack[reg_sp--] = reg_pc & 0xFF;
reg_pc = addr;
cycles += 6;
}
break;
case 0x21: {
uint16_t addr = PeekW((Peek16(reg_pc++) + reg_x) & 0xFF);
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 6;
}
break;
case 0x22: {
}
break;
case 0x23: {
}
break;
case 0x24: {
uint16_t addr = Peek16(reg_pc++);
uint8_t tmp1 = Load(addr);
reg_ps &= 0x3D;
reg_ps |= (!(reg_a & tmp1) << 1) | (tmp1 & 0xC0);
cycles += 3;
}
break;
case 0x25: {
uint16_t addr = Peek16(reg_pc++);
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 3;
}
break;
case 0x26: {
uint16_t addr = Peek16(reg_pc++);
uint8_t tmp1 = Load(addr);
uint8_t tmp2 = (tmp1 << 1) | (reg_ps & 0x01);
reg_ps &= 0x7C;
reg_ps |= (tmp2 & 0x80) | (!tmp2 << 1) | (tmp1 >> 7);
Store(addr, tmp2);
cycles += 5;
}
break;
case 0x27: {
}
break;
case 0x28: {
reg_ps = stack[++reg_sp];
cycles += 4;
}
break;
case 0x29: {
uint16_t addr = reg_pc++;
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 2;
}
break;
case 0x2A: {
uint8_t tmp1 = reg_a;
reg_a = (reg_a << 1) | (reg_ps & 0x01);
reg_ps &= 0x7C;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1) | (tmp1 >> 7);
cycles += 2;
}
break;
case 0x2B: {
}
break;
case 0x2C: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
uint8_t tmp1 = Load(addr);
reg_ps &= 0x3D;
reg_ps |= (!(reg_a & tmp1) << 1) | (tmp1 & 0xC0);
cycles += 4;
}
break;
case 0x2D: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x2E: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
uint8_t tmp1 = Load(addr);
uint8_t tmp2 = (tmp1 << 1) | (reg_ps & 0x01);
reg_ps &= 0x7C;
reg_ps |= (tmp2 & 0x80) | (!tmp2 << 1) | (tmp1 >> 7);
Store(addr, tmp2);
cycles += 6;
}
break;
case 0x2F: {
}
break;
case 0x30: {
int8_t tmp4 = (int8_t) (Peek16(reg_pc++));
uint16_t addr = reg_pc + tmp4;
if ((reg_ps & 0x80)) {
cycles += !((reg_pc ^ addr) & 0xFF00) << 1;
reg_pc = addr;
}
cycles += 2;
}
break;
case 0x31: {
uint16_t addr = PeekW(Peek16(reg_pc));
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc++;
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 5;
}
break;
case 0x32: {
}
break;
case 0x33: {
}
break;
case 0x34: {
}
break;
case 0x35: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x36: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
uint8_t tmp1 = Load(addr);
uint8_t tmp2 = (tmp1 << 1) | (reg_ps & 0x01);
reg_ps &= 0x7C;
reg_ps |= (tmp2 & 0x80) | (!tmp2 << 1) | (tmp1 >> 7);
Store(addr, tmp2);
cycles += 6;
}
break;
case 0x37: {
}
break;
case 0x38: {
reg_ps |= 0x01;
cycles += 2;
}
break;
case 0x39: {
uint16_t addr = PeekW(reg_pc);
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc += 2;
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x3A: {
}
break;
case 0x3B: {
}
break;
case 0x3C: {
}
break;
case 0x3D: {
uint16_t addr = PeekW(reg_pc);
cycles += !!(((addr & 0xFF) + reg_x) & 0xFF00);
addr += reg_x;
reg_pc += 2;
reg_a &= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x3E: {
uint16_t addr = PeekW(reg_pc);
addr += reg_x;
reg_pc += 2;
uint8_t tmp1 = Load(addr);
uint8_t tmp2 = (tmp1 << 1) | (reg_ps & 0x01);
reg_ps &= 0x7C;
reg_ps |= (tmp2 & 0x80) | (!tmp2 << 1) | (tmp1 >> 7);
Store(addr, tmp2);
cycles += 6;
}
break;
case 0x3F: {
}
break;
case 0x40: {
reg_ps = stack[++reg_sp];
reg_pc = stack[++reg_sp];
reg_pc |= stack[++reg_sp] << 8;
cycles += 6;
}
break;
case 0x41: {
uint16_t addr = PeekW((Peek16(reg_pc++) + reg_x) & 0xFF);
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 6;
}
break;
case 0x42: {
}
break;
case 0x43: {
}
break;
case 0x44: {
}
break;
case 0x45: {
uint16_t addr = Peek16(reg_pc++);
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 3;
}
break;
case 0x46: {
uint16_t addr = Peek16(reg_pc++);
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 & 0x01);
tmp1 >>= 1;
reg_ps |= (!tmp1 << 1);
Store(addr, tmp1);
cycles += 5;
}
break;
case 0x47: {
}
break;
case 0x48: {
stack[reg_sp--] = reg_a;
cycles += 3;
}
break;
case 0x49: {
uint16_t addr = reg_pc++;
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 2;
}
break;
case 0x4A: {
reg_ps &= 0x7C;
reg_ps |= reg_a & 0x01;
reg_a >>= 1;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 2;
}
break;
case 0x4B: {
}
break;
case 0x4C: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
reg_pc = addr;
cycles += 3;
}
break;
case 0x4D: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x4E: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 & 0x01);
tmp1 >>= 1;
reg_ps |= (!tmp1 << 1);
Store(addr, tmp1);
cycles += 6;
}
break;
case 0x4F: {
}
break;
case 0x50: {
int8_t tmp4 = (int8_t) (Peek16(reg_pc++));
uint16_t addr = reg_pc + tmp4;
if (!(reg_ps & 0x40)) {
cycles += !((reg_pc ^ addr) & 0xFF00) << 1;
reg_pc = addr;
}
cycles += 2;
}
break;
case 0x51: {
uint16_t addr = PeekW(Peek16(reg_pc));
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc++;
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 5;
}
break;
case 0x52: {
}
break;
case 0x53: {
}
break;
case 0x54: {
}
break;
case 0x55: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x56: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 & 0x01);
tmp1 >>= 1;
reg_ps |= (!tmp1 << 1);
Store(addr, tmp1);
cycles += 6;
}
break;
case 0x57: {
}
break;
case 0x58: {
reg_ps &= 0xFB;
cycles += 2;
}
break;
case 0x59: {
uint16_t addr = PeekW(reg_pc);
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc += 2;
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x5A: {
}
break;
case 0x5B: {
}
break;
case 0x5C: {
}
break;
case 0x5D: {
uint16_t addr = PeekW(reg_pc);
cycles += !!(((addr & 0xFF) + reg_x) & 0xFF00);
addr += reg_x;
reg_pc += 2;
reg_a ^= Load(addr);
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x5E: {
uint16_t addr = PeekW(reg_pc);
addr += reg_x;
reg_pc += 2;
uint8_t tmp1 = Load(addr);
reg_ps &= 0x7C;
reg_ps |= (tmp1 & 0x01);
tmp1 >>= 1;
reg_ps |= (!tmp1 << 1);
Store(addr, tmp1);
cycles += 6;
}
break;
case 0x5F: {
}
break;
case 0x60: {
reg_pc = stack[++reg_sp];
reg_pc |= (stack[++reg_sp] << 8);
reg_pc++;
cycles += 6;
}
break;
case 0x61: {
uint16_t addr = PeekW((Peek16(reg_pc++) + reg_x) & 0xFF);
uint8_t tmp1 = Load(addr);
int16_t tmp2 = reg_a + tmp1 + (reg_ps & 0x01);
uint8_t tmp3 = tmp2 & 0xFF;
reg_ps &= 0x3C;
reg_ps |= (tmp3 & 0x80) | (!tmp3 << 1) | (tmp2 > 0xFF)
| (((reg_a ^ tmp1 ^ 0x80) & (reg_a ^ tmp3) & 0x80) >> 1);
reg_a = tmp3;
cycles += 6;
}
break;
case 0x62: {
}
break;
case 0x63: {
}
break;
case 0x64: {
}
break;
case 0x65: {
uint16_t addr = Peek16(reg_pc++);
uint8_t tmp1 = Load(addr);
int16_t tmp2 = reg_a + tmp1 + (reg_ps & 0x01);
uint8_t tmp3 = tmp2 & 0xFF;
reg_ps &= 0x3C;
reg_ps |= (tmp3 & 0x80) | (!tmp3 << 1) | (tmp2 > 0xFF)
| (((reg_a ^ tmp1 ^ 0x80) & (reg_a ^ tmp3) & 0x80) >> 1);
reg_a = tmp3;
cycles += 3;
}
break;
case 0x66: {
uint16_t addr = Peek16(reg_pc++);
uint8_t tmp1 = Load(addr);
uint8_t tmp2 = (tmp1 >> 1) | ((reg_ps & 0x01) << 7);
reg_ps &= 0x7C;
reg_ps |= (tmp2 & 0x80) | (!tmp2 << 1) | (tmp1 & 0x01);
Store(addr, tmp2);
cycles += 5;
}
break;
case 0x67: {
}
break;
case 0x68: {
reg_a = stack[++reg_sp];
reg_ps &= 0x7D;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1);
cycles += 4;
}
break;
case 0x69: {
uint16_t addr = reg_pc++;
uint8_t tmp1 = Load(addr);
int16_t tmp2 = reg_a + tmp1 + (reg_ps & 0x01);
uint8_t tmp3 = tmp2 & 0xFF;
reg_ps &= 0x3C;
reg_ps |= (tmp3 & 0x80) | (!tmp3 << 1) | (tmp2 > 0xFF)
| (((reg_a ^ tmp1 ^ 0x80) & (reg_a ^ tmp3) & 0x80) >> 1);
reg_a = tmp3;
cycles += 2;
}
break;
case 0x6A: {
uint8_t tmp1 = reg_a;
reg_a = (reg_a >> 1) | ((reg_ps & 0x01) << 7);
reg_ps &= 0x7C;
reg_ps |= (reg_a & 0x80) | (!reg_a << 1) | (tmp1 & 0x01);
cycles += 2;
}
break;
case 0x6B: {
}
break;
case 0x6C: {
uint16_t addr = PeekW(PeekW(reg_pc));
reg_pc += 2;
reg_pc = addr;
cycles += 6;
}
break;
case 0x6D: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
uint8_t tmp1 = Load(addr);
int16_t tmp2 = reg_a + tmp1 + (reg_ps & 0x01);
uint8_t tmp3 = tmp2 & 0xFF;
reg_ps &= 0x3C;
reg_ps |= (tmp3 & 0x80) | (!tmp3 << 1) | (tmp2 > 0xFF)
| (((reg_a ^ tmp1 ^ 0x80) & (reg_a ^ tmp3) & 0x80) >> 1);
reg_a = tmp3;
cycles += 4;
}
break;
case 0x6E: {
uint16_t addr = PeekW(reg_pc);
reg_pc += 2;
uint8_t tmp1 = Load(addr);
uint8_t tmp2 = (tmp1 >> 1) | ((reg_ps & 0x01) << 7);
reg_ps &= 0x7C;
reg_ps |= (tmp2 & 0x80) | (!tmp2 << 1) | (tmp1 & 0x01);
Store(addr, tmp2);
cycles += 6;
}
break;
case 0x6F: {
}
break;
case 0x70: {
int8_t tmp4 = (int8_t) (Peek16(reg_pc++));
uint16_t addr = reg_pc + tmp4;
if ((reg_ps & 0x40)) {
cycles += !((reg_pc ^ addr) & 0xFF00) << 1;
reg_pc = addr;
}
cycles += 2;
}
break;
case 0x71: {
uint16_t addr = PeekW(Peek16(reg_pc));
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc++;
uint8_t tmp1 = Load(addr);
int16_t tmp2 = reg_a + tmp1 + (reg_ps & 0x01);
uint8_t tmp3 = tmp2 & 0xFF;
reg_ps &= 0x3C;
reg_ps |= (tmp3 & 0x80) | (!tmp3 << 1) | (tmp2 > 0xFF)
| (((reg_a ^ tmp1 ^ 0x80) & (reg_a ^ tmp3) & 0x80) >> 1);
reg_a = tmp3;
cycles += 5;
}
break;
case 0x72: {
}
break;
case 0x73: {
}
break;
case 0x74: {
}
break;
case 0x75: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
uint8_t tmp1 = Load(addr);
int16_t tmp2 = reg_a + tmp1 + (reg_ps & 0x01);
uint8_t tmp3 = tmp2 & 0xFF;
reg_ps &= 0x3C;
reg_ps |= (tmp3 & 0x80) | (!tmp3 << 1) | (tmp2 > 0xFF)
| (((reg_a ^ tmp1 ^ 0x80) & (reg_a ^ tmp3) & 0x80) >> 1);
reg_a = tmp3;
cycles += 4;
}
break;
case 0x76: {
uint16_t addr = (Peek16(reg_pc++) + reg_x) & 0xFF;
uint8_t tmp1 = Load(addr);
uint8_t tmp2 = (tmp1 >> 1) | ((reg_ps & 0x01) << 7);
reg_ps &= 0x7C;
reg_ps |= (tmp2 & 0x80) | (!tmp2 << 1) | (tmp1 & 0x01);
Store(addr, tmp2);
cycles += 6;
}
break;
case 0x77: {
}
break;
case 0x78: {
reg_ps |= 0x04;
cycles += 2;
}
break;
case 0x79: {
uint16_t addr = PeekW(reg_pc);
cycles += !!(((addr & 0xFF) + reg_y) & 0xFF00);
addr += reg_y;
reg_pc += 2;
uint8_t tmp1 = Load(addr);
int16_t tmp2 = reg_a + tmp1 + (reg_ps & 0x01);
uint8_t tmp3 = tmp2 & 0xFF;
reg_ps &= 0x3C;
reg_ps |= (tmp3 & 0x80) | (!tmp3 << 1) | (tmp2 > 0xFF)
| (((reg_a ^ tmp1 ^ 0x80) & (reg_a ^ tmp3) & 0x80) >> 1);
reg_a = tmp3;
cycles += 4;
}
break;