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invproc/vicuna (press backspace or delete to remove)

Hi, I am working with this processor lately and already can do some stuff with it, but when start using vector operations they are not recognized. For example when I tried run the Test.c code: #include ...
  • AlfredoRodrigues4
  • 1
  • Opened 
    on Jan 16
  • #124

Upon executing the test code example given in the Simulation - Vicuna documentation (https://vicuna.readthedocs.io/en/latest/01_user/simulation.html), although I am able to get the outputs, I am getting ...
  • deeplearner92
  • 1
  • Opened 
    on Sep 12, 2024
  • #123

hi @moimfeld I am currently working with the conv_3x3 function in the RISC-V assembly code, and I have a question regarding the incorporation of bias into the convolution operation. Specifically, I want ...
  • Haleski47
  • Opened 
    on Jul 30, 2024
  • #122

I m running some applications with these configurations make -f ../sim/Makefile ICACHE_SZ=16384 ICACHE_LINE_W=128 DCACHE_SZ=16384 DCACHE_LINE_W=128 CORE=cv32e40x TARGET_TECH=fpga VMEM_W=32 VREG_W=1024 ...
  • maheshejs
  • 1
  • Opened 
    on Jan 4, 2024
  • #121

I tried executing some matrix multiplication algorithms on verilated model of Vicuna. The algorithms are able to successfully execute with compact configuration but not with dual and triple pipeline configuration. ...
  • AnjaliVerma1314
  • Opened 
    on Nov 28, 2023
  • #119

Unable to get the cycle count by reading a machine mode CSR (mcycle) on verilated model of Vicuna with Ibex host core. The machine mode CSRs seem to be not accessible with Ibex host core on Vicuna s verilator. ...
  • AnjaliVerma1314
  • 2
  • Opened 
    on Nov 28, 2023
  • #118

Verilator version: 5.016 LLVM version: 14.0.0 Branch: main Steps taken: 1) Copied following C code to file as directed in the documentation in the folder temp wthin the repo. // vicuna/temp/test.c ...
  • latifbhatti
  • 1
  • Opened 
    on Oct 19, 2023
  • #115

Fatal: Unexpected signal: 11. /# //wsl.localhost/Ubuntu-20.04/home/aqdas/vicuna/sim/../rtl/vproc_mul_block.sv(1): Vopt Compiler exiting
  • aaqdas
  • Opened 
    on Jul 26, 2023
  • #114

Hello Vicuna community, I have run into issues executing vsext.vf2 and vzext.vf2 functions with a destination LMUL=8. When attempting to execute these, an Illegal Instruction exception is thrown. I believe ...
  • ParkerJones567
  • Opened 
    on Jul 3, 2023
  • #112

Hello @michael-platzer and vicuna community, I am trying to run the demo version of vicuna using cv32e40x as a scalar core. While generating the bitstream (Genesys2 Target) for the same I am getting following ...
  • Nikhil-311293
  • 4
  • Opened 
    on May 5, 2023
  • #111
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