No output generated for D-Flip Flop Positive Edge Triggered

[kanurusubhash]

When we click on Simulate button,graph gets generated but the output is a straight line instead of postive edge trigger output of D Flip Flop.

Expected Output:
Similar to D-Flip Flop negative edge triggered simulation output graph, Input should have both high and low signals and output line should show rectangular areas at negative edge of clock based on input at that time.

Environment :
OS: Windows 7,
Browsers: Firefox-43.0.4
Bandwidth : 40Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

@khushpreet-kaur
Submitted by : (Team -7) Subhash Kanuru ,Somya, Simran

[khushpreet-kaur]

@kanurusubhash Are you logging this issue as part of your test cases? or you need any clarification from my side? Why did you mention me in this issue? Please specify in more detail.

[kanurusubhash]

@khushpreet-kaur I am logging the issue for failed test cases as part software engineering project-1

[khushpreet-kaur]

@kanurusubhash Ok. So no need to mention me in every issue.