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Currently, PVM relies on PTI is enabled inside VM. This means each process inside guest has 2 cr3, and there are 2 PGD in SPT of PVM.
PVM implements a hypercall (PVM_HC_LOAD_PGTBL) to change pagetable of SPT. And PVM is maintaining a pair of process usr/sys CR3s and switch flags, so that PVM could do direct switch to speed up guest process usr/sys switch without return to hypervisor.
We can speed up sys to usr switch by preloading the user pgd in PVM_HC_LOAD_PGTBL.
Here are some lmbench context switch case test results. Using preload user pgd feature, context switch latency could reduce 10%+, if we apply the enlarge the SPT LRU cache patch set, we can speed up context switching in multiprocess environment.
process num 2 3
w/o preload 3.952 5.344
w/ preload 3.555 4.517
The text was updated successfully, but these errors were encountered:
Currently, PVM relies on PTI is enabled inside VM. This means each process inside guest has 2 cr3, and there are 2 PGD in SPT of PVM.
PVM implements a hypercall (PVM_HC_LOAD_PGTBL) to change pagetable of SPT. And PVM is maintaining a pair of process usr/sys CR3s and switch flags, so that PVM could do direct switch to speed up guest process usr/sys switch without return to hypervisor.
We can speed up sys to usr switch by preloading the user pgd in PVM_HC_LOAD_PGTBL.
Here are some lmbench context switch case test results. Using preload user pgd feature, context switch latency could reduce 10%+, if we apply the enlarge the SPT LRU cache patch set, we can speed up context switching in multiprocess environment.
The text was updated successfully, but these errors were encountered: