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Multi-KVM (reference): Allow PVM to coexist with VMX/SVM.
User-return MSR.
Perf callback.
VPID (per pCPU VPID).
ASI: Handle PVM VMExit events without switching hardware CR3 to kernel CR3.
KVM shared TLB for different vCPUs in the same VM & pCPU (context_id & generation).
Permission clone on non-final SPTes when guest CR0.WP is set (allow PVM hypervisor to share shadowed user page tables for guest kernel/user CR3).
PMU Refactor
Create separate kernel modules for pmu_intel.c and pmu_amd.c. This allows PVM to select the appropriate module based on the vendor.
PVM Hypervisor
Analyze and mitigate hypervisor/guest side-channel attacks.
Direct #PF Injection
Inject #PF into the guest in the switcher based on the error code. Fetch all GPTes during SP allocation and set the SPTE as reserved if the associated GPTE is present. For NP (Not Present) faults, inject directly into the guest. See commit c7addb902054195b995114df154e061c7d604f69. Note: This method may fail under PV MMU, as there will be no TLB flushing when the guest modifies a GPTE.
Post Interrupt Emulation
Inject hardware interrupts directly into the guest. Emulating full APIC logic in the switcher might be complex. Consider allowing the guest kernel to handle passthrough hardware interrupts directly using user interrupts.
PerVM Mapping Space for PVCS (PGD Granularity)
Current PVCS relies on PFN cache (KVM_USE_GUEST_USAGE), but it has been dropped from the mainline. Consider dynamically mapping guest vCPU PVCS pages to a VA range under a fixed, unused PGD.
PMU
PMU virtualization should support separate statistics for kernel and user modes, as both the guest kernel and userspace run in hardware CPL3.
Remove non-PVM mode when VMM/guest supports 64-bit-only.
PV Optimization
SMP PV Booting (Doing)
Allow the secondary CPU to boot directly into 64-bit mode. This might also eliminate the need for non-PVM mode (requires specification change). Note:
We have a functional internal implementation, but we would like a more general implementation, possibly in accordance with the TDX booting specification. We need to discuss this.
PV MMIO Write ✅
Use a hypercall to emulate MMIO write directly (may require extra PVOPS).
MMU Optimization
PV MMU (Doing)
Remove write protection from guest page tables. Allow the guest to notify the hypervisor of GPTE changes using PVOPS to synchronize SPTE. Full design details are in PV MMU Design #13 . Note:
We have a functional internal implementation, but we would like a more general implementation that is also available for nested TDP MMU. We need to discuss this.
Direct Page Table (Xen-like)?
Finer-Grained TLB Flushing
Move TLB flushing outside of MMU lock (TLB flushing delay).
Specification
Guest
Host Kernel
Host KVM
pmu_intel.c
andpmu_amd.c
. This allows PVM to select the appropriate module based on the vendor.PVM Hypervisor
c7addb902054195b995114df154e061c7d604f69
. Note: This method may fail under PV MMU, as there will be no TLB flushing when the guest modifies a GPTE.KVM_USE_GUEST_USAGE
), but it has been dropped from the mainline. Consider dynamically mapping guest vCPU PVCS pages to a VA range under a fixed, unused PGD.PV Optimization
SMP PV Booting (Doing)
Note:
We have a functional internal implementation, but we would like a more general implementation, possibly in accordance with the TDX booting specification. We need to discuss this.
PV MMIO Write ✅
MMU Optimization
Note:
We have a functional internal implementation, but we would like a more general implementation that is also available for nested TDP MMU. We need to discuss this.
VMM
Migration
Testing
Debug Tools
pvm_get_exit_info()
.perf-kvm
to analyze PVM exit reasons.The text was updated successfully, but these errors were encountered: