diff --git a/.github/workflows/nightly_test.yml b/.github/workflows/nightly_test.yml
index 78118e0781..dc6ab3e296 100644
--- a/.github/workflows/nightly_test.yml
+++ b/.github/workflows/nightly_test.yml
@@ -65,9 +65,8 @@ jobs:
           - {test: "vtr_reg_strong",             cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                                         extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON",                          extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
-          - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""} 
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                     extra_pkgs: ""}
+          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DSYNLIG_SYSTEMVERILOG=ON",                                    extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
index 0f0dbf3231..142c0870c5 100644
--- a/.github/workflows/test.yml
+++ b/.github/workflows/test.yml
@@ -97,7 +97,7 @@ jobs:
       run: ./dev/${{ matrix.script }}
 
 
-  UniTests:
+  UnitTests:
     name: 'U: C++ Unit Tests'
     runs-on: ubuntu-24.04
     steps:
@@ -366,6 +366,38 @@ jobs:
           ./.github/scripts/build.sh
           ./run_reg_test.py parmys_reg_basic -show_failures -j${{ steps.cpu-cores.outputs.count }}
 
+  SystemVerilog:
+    name: 'System Verilog Regression'
+    runs-on: ubuntu-24.04
+    steps:
+
+    - uses: actions/setup-python@v5
+      with:
+        python-version: 3.12.3
+
+    # NOTE: This is using recursive on purpose. In order to use the System
+    #       Verilog feature, need submodules inside of a submodule.
+    - uses: actions/checkout@v4
+      with:
+        submodules: 'recursive'
+
+    - name: Get number of CPU cores
+      uses: SimenB/github-actions-cpu-cores@v2
+      id: cpu-cores
+
+    - name: Install dependencies
+      run: ./.github/scripts/install_dependencies.sh
+
+    - uses: hendrikmuhs/ccache-action@v1.2
+
+    - name: Test
+      env:
+        CMAKE_PARAMS: '-DSYNLIG_SYSTEMVERILOG=ON'
+        NUM_PROC: ${{ steps.cpu-cores.outputs.count }}
+      run: |
+        export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
+        ./.github/scripts/build.sh
+        ./run_reg_test.py vtr_reg_system_verilog -show_failures -j${{ steps.cpu-cores.outputs.count}}
 
   ODINII:
     name: 'ODIN-II Basic Test'
@@ -508,11 +540,12 @@ jobs:
     needs:
       - Build
       - Format
-      - UniTests
+      - UnitTests
       - Warnings
       - Regression
       - Sanitized
       - Parmys
+      - SystemVerilog
       - ODINII
       - VQM2BLIF
       - Compatibility