diff --git a/Makefile b/Makefile
index 5e524e3..9905cc7 100644
--- a/Makefile
+++ b/Makefile
@@ -34,7 +34,7 @@ DRIVER_FLAGS ?= -j 0 --quiet --rerun
 SCENARIOS ?= --vlt --vltmt --dist
 
 test:
-	t/bootstrap.pl $(DRIVER_FLAGS) $(SCENARIOS) t/t_*.pl
+	t/vltest_bootstrap.py $(DRIVER_FLAGS) $(SCENARIOS) t/t_*.py
 
 ######################################################################
 
diff --git a/docs/README.md b/docs/README.md
index ced589e..806625d 100644
--- a/docs/README.md
+++ b/docs/README.md
@@ -21,7 +21,7 @@ Run an individual test:
 ```
 export VERILATOR_ROOT=location  # if your shell is bash
 setenv VERILATOR_ROOT location  # if your shell is csh
-t/t_a_hello.pl
+t/t_a_hello.py
 ```
 
 Automatically run these tests as part of normal Verilator "make test"
@@ -39,7 +39,7 @@ make clean
 
 # Adding additional tests
 
-To add additional tests, add a `t/t_{name}.pl` file.  See the Verilator
+To add additional tests, add a `t/t_{name}.py` file.  See the Verilator
 internals documentation for instructions on the test file format.
 
 To be accepted in this package, an external submodule tested here must:
diff --git a/t/bootstrap.pl b/t/bootstrap.pl
deleted file mode 100755
index c1aaa7a..0000000
--- a/t/bootstrap.pl
+++ /dev/null
@@ -1,28 +0,0 @@
-#!/usr/bin/perl
-# DESCRIPTION: Verilator: Verilog Test driver bootstrapper
-#
-# Copyright 2008 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-# This is exec'ed by every test that is run standalone (called from the
-# shell as ./t_test_name.pl)
-
-use FindBin;
-use Cwd qw(chdir);
-
-$ENV{VERILATOR_ROOT} or die "%Error: VERILATOR_ROOT required for site tests,";
-
-$ENV{VERILATOR_TESTS_SITE} ||= '';
-$ENV{VERILATOR_TESTS_SITE} .= ':' if $ENV{VERILATOR_TESTS_SITE};
-$ENV{VERILATOR_TESTS_SITE} .= $FindBin::Bin;
-
-my @args = @ARGV;
-#chdir("$ENV{VERILATOR_ROOT}/test_regress");
-
-@args = map { s!.*/!!; $_; } @args;
-
-print "cd $ENV{PWD} && $ENV{VERILATOR_ROOT}/test_regress/driver.pl ",join(' ',@args),"\n";
-exec("$ENV{VERILATOR_ROOT}/test_regress/driver.pl", @args);
-die;
diff --git a/t/t_a_hello.pl b/t/t_a_hello.pl
deleted file mode 100755
index 4d4c974..0000000
--- a/t/t_a_hello.pl
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-scenarios(vlt => 1);
-
-compile(
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
diff --git a/t/t_a_hello.py b/t/t_a_hello.py
new file mode 100755
index 0000000..89aa3d9
--- /dev/null
+++ b/t/t_a_hello.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile()
+
+test.execute(check_finished=True)
+
+test.passes()
diff --git a/t/t_bench_synmul.pl b/t/t_bench_synmul.pl
deleted file mode 100755
index 3380cfe..0000000
--- a/t/t_bench_synmul.pl
+++ /dev/null
@@ -1,30 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-scenarios(simulator => 1);
-
-top_filename("t/t_math_synmul.v");
-
-$Self->{cycles} = $Self->{benchmark}||0;
-$Self->{cycles} = 100 if $Self->{cycles}<100;
-
-$Self->{sim_time} = $Self->{cycles}*100;
-
-compile(
-    v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",
-                 "--stats",
-                 "-Wno-UNOPTTHREADS"],
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
diff --git a/t/t_bench_synmul.py b/t/t_bench_synmul.py
new file mode 100755
index 0000000..38e5d6a
--- /dev/null
+++ b/t/t_bench_synmul.py
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+test.top_filename = "t/t_math_synmul.v"
+
+cycles = 100
+test.sim_time = cycles * 100
+
+test.compile(v_flags2=[
+    "+define+SIM_CYCLES=" + str(cycles), "--stats", "-Wno-UNOPTTHREADS"
+], )
+
+test.execute(check_finished=True)
+
+test.passes()
diff --git a/t/t_bench_wallace.pl b/t/t_bench_wallace.pl
deleted file mode 100755
index a49afaa..0000000
--- a/t/t_bench_wallace.pl
+++ /dev/null
@@ -1,27 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-scenarios(simulator => 1);
-
-top_filename("t_math_wallace.v");
-
-my $cycles = $Self->{benchmark}||0;
-$cycles = 100 if $cycles<100;
-
-$Self->{sim_time} = $cycles*100;
-
-compile (
-    v_flags2 => ["+define+SIM_CYCLES=${cycles}"],
-    );
-
-execute (
-    check_finished=>1,
-    );
-
-ok(1);
-1;
diff --git a/t/t_bench_wallace.py b/t/t_bench_wallace.py
new file mode 100755
index 0000000..714ee5c
--- /dev/null
+++ b/t/t_bench_wallace.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios("simulator")
+test.top_filename = "t/t_math_wallace.v"
+
+cycles = 100
+test.sim_time = cycles * 100
+
+test.compile(v_flags2=["+define+SIM_CYCLES=" + str(cycles)])
+
+test.execute(check_finished=True)
+
+test.passes()
diff --git a/t/t_cores_eh2_cmark.pl b/t/t_cores_eh2_cmark.pl
deleted file mode 100755
index b978481..0000000
--- a/t/t_cores_eh2_cmark.pl
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-setenv('RV_ROOT', File::Spec->rel2abs($Self->{t_dir}."/../submodules/Cores-SweRV-EH2"));
-setenv('VERILATOR', "$ENV{VERILATOR_ROOT}/bin/verilator");
-
-# Find compiler flag needed
-my $fc = $Self->file_contents("$ENV{VERILATOR_ROOT}/include/verilated.mk");
-$fc =~ /CFG_CXXFLAGS_STD_NEWEST = (\S+)/ or die;
-my $CFG_CXXFLAGS_STD_NEWEST = $1;
-
-# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
-# toolchain on your path), from ICCM but otherwise using the default core
-# configuration. Running from ICCM is faster and hopefully more exciting.
-# Note the build happens in $Self->{obj_dir} as the SweRV build system can
-# find everything via RV_ROOT. This leaves the submodule clean.
-run(cmd => ["make -j4 -C $Self->{obj_dir} -f $ENV{RV_ROOT}/tools/Makefile",
-            ("VERILATOR='$ENV{VERILATOR} --debug-check -Wno-IMPLICITSTATIC --stats --timing "
-             . join(' ',$Self->driver_verilator_flags())
-             . "'"),
-            # Because Cores-SweRV-EH2/tools/Makefile has -std=c++11 which is too old
-            # Unfortunately it's too late in the Makefile to pass in VERILATOR above
-            "VERILATOR_DEBUG='-CFLAGS $CFG_CXXFLAGS_STD_NEWEST'",
-            "CONF_PARAMS=-iccm_enable=1",
-            "GCC_PREFIX=none TEST=cmark_iccm",
-            "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"],
-    logfile => "$Self->{obj_dir}/sim.log",
-    );
-
-file_grep("$Self->{obj_dir}/sim.log", qr/.*\nTEST_PASSED\n/is);
-
-ok(1);
-1;
diff --git a/t/t_cores_el2_cmark.pl b/t/t_cores_el2_cmark.pl
deleted file mode 100755
index 4905489..0000000
--- a/t/t_cores_el2_cmark.pl
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-setenv('RV_ROOT', File::Spec->rel2abs($Self->{t_dir}."/../submodules/Cores-SweRV-EL2"));
-setenv('VERILATOR', "$ENV{VERILATOR_ROOT}/bin/verilator");
-
-# Find compiler flag needed
-my $fc = $Self->file_contents("$ENV{VERILATOR_ROOT}/include/verilated.mk");
-$fc =~ /CFG_CXXFLAGS_STD_NEWEST = (\S+)/ or die;
-my $CFG_CXXFLAGS_STD_NEWEST = $1;
-
-# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
-# toolchain on your path), from ICCM but otherwise using the default core
-# configuration. Running from ICCM is faster and hopefully more exciting.
-# Note the build happens in $Self->{obj_dir} as the SweRV build system can
-# find everything via RV_ROOT. This leaves the submodule clean.
-run(cmd => ["make -j4 -C $Self->{obj_dir} -f $ENV{RV_ROOT}/tools/Makefile",
-            "VERILATOR='$ENV{VERILATOR} --debug-check -Wno-IMPLICITSTATIC "
-            .join(' ',$Self->driver_verilator_flags()),"'",
-            # Because Cores-SweRV-EH2/tools/Makefile has -std=c++11 which is too old
-            # Unfortunately it's too late in the Makefile to pass in VERILATOR above
-            "VERILATOR_DEBUG='-CFLAGS $CFG_CXXFLAGS_STD_NEWEST'",
-            "CONF_PARAMS=-iccm_enable=1",
-            "GCC_PREFIX=none TEST=cmark_iccm",
-            "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"],
-    logfile => "$Self->{obj_dir}/sim.log",
-    );
-
-file_grep("$Self->{obj_dir}/sim.log", qr/.*\nTEST_PASSED\n/is);
-
-ok(1);
-1;
diff --git a/t/t_cores_swerv_cmark.pl b/t/t_cores_swerv_cmark.pl
deleted file mode 100755
index d1dec26..0000000
--- a/t/t_cores_swerv_cmark.pl
+++ /dev/null
@@ -1,46 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-setenv('RV_ROOT', File::Spec->rel2abs($Self->{t_dir}."/../submodules/Cores-SweRV"));
-setenv('VERILATOR', "$ENV{VERILATOR_ROOT}/bin/verilator");
-
-# Find compiler flag needed
-my $fc = $Self->file_contents("$ENV{VERILATOR_ROOT}/include/verilated.mk");
-$fc =~ /CFG_CXXFLAGS_STD_NEWEST = (\S+)/ or die;
-my $CFG_CXXFLAGS_STD_NEWEST = $1;
-
-# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
-# toolchain on your path), from ICCM but otherwise using the default core
-# configuration. Running from ICCM is faster and hopefully more exciting.
-# Note the build happens in $Self->{obj_dir} as the SweRV build system can
-# find everything via RV_ROOT. This leaves the submodule clean.
-run(cmd => ["make -j4 -C $Self->{obj_dir} -f $ENV{RV_ROOT}/tools/Makefile",
-            "VERILATOR='$ENV{VERILATOR} --debug-check -Wno-IMPLICITSTATIC "
-            .join(' ',$Self->driver_verilator_flags()),"'",
-            # Because Cores-SweRV-EH2/tools/Makefile has -std=c++11 which is too old
-            # Unfortunately it's too late in the Makefile to pass in VERILATOR above
-            "VERILATOR_DEBUG='-CFLAGS $CFG_CXXFLAGS_STD_NEWEST'",
-            "CONF_PARAMS=-iccm_enable=1",
-            "GCC_PREFIX=none TEST=cmark_iccm",
-            "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"],
-    logfile => "$Self->{obj_dir}/sim.log",
-    );
-
-file_grep("$Self->{obj_dir}/sim.log", qr/.*\nTEST_PASSED\n/is);
-
-# Profiling:
-#  add to cmd: --debug-check --prof-cfuncs -CFLAGS -pg -LDFLAGS -pg
-#  cd /svaha/wsnyder/SandBox/homecvs/v4/verilator_ext_tests/obj_vlt/t_cores_swerv_cmark
-#  gprof
-
-ok(1);
-1;
diff --git a/t/t_cores_swerv_cmark.py b/t/t_cores_swerv_cmark.py
new file mode 100755
index 0000000..0f52ec8
--- /dev/null
+++ b/t/t_cores_swerv_cmark.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.setenv('RV_ROOT',
+            os.path.abspath(test.t_dir + "/../submodules/Cores-SweRV"))
+test.setenv('VERILATOR', os.environ["VERILATOR_ROOT"] + "/bin/verilator")
+
+# Find compiler flag needed
+fc = test.file_contents(os.environ["VERILATOR_ROOT"] + "/include/verilated.mk")
+m = re.search(r'CFG_CXXFLAGS_STD_NEWEST = (\S+)', fc)
+if not m:
+    test.error("Couldn't determine CFG_CXXFLAGS_STD_NEWEST")
+CFG_CXXFLAGS_STD_NEWEST = m.group(1)
+
+# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
+# toolchain on your path), from ICCM but otherwise using the default core
+# configuration. Running from ICCM is faster and hopefully more exciting.
+# Note the build happens in test.obj_dir as the SweRV build system can
+# find everything via RV_ROOT. This leaves the submodule clean.
+test.run(
+    cmd=[
+        "make -j4 -C " + test.obj_dir + " -f " + os.environ["RV_ROOT"] +
+        "/tools/Makefile",
+        ("VERILATOR='" + os.environ["VERILATOR"] +
+         " --debug-check -Wno-IMPLICITSTATIC --stats " +
+         ' '.join(test.driver_verilator_flags) + "'"),
+        # Because Cores-SweRV-EH2/tools/Makefile has -std=c++11 which is too old
+        # Unfortunately it's too late in the Makefile to pass in VERILATOR above
+        "VERILATOR_DEBUG='-CFLAGS " + CFG_CXXFLAGS_STD_NEWEST + "'",  #
+        "CONF_PARAMS=-iccm_enable=1",  #
+        "GCC_PREFIX=none TEST=cmark_iccm",  #
+        "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"
+    ],  #
+    logfile=test.obj_dir + "/sim.log")
+
+test.file_grep(test.obj_dir + "/sim.log", r'\nTEST_PASSED\n')
+
+test.passes()
diff --git a/t/t_cores_swerv_eh2_cmark.py b/t/t_cores_swerv_eh2_cmark.py
new file mode 100755
index 0000000..05001e4
--- /dev/null
+++ b/t/t_cores_swerv_eh2_cmark.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.setenv('RV_ROOT',
+            os.path.abspath(test.t_dir + "/../submodules/Cores-SweRV-EH2"))
+test.setenv('VERILATOR', os.environ["VERILATOR_ROOT"] + "/bin/verilator")
+
+# Find compiler flag needed
+fc = test.file_contents(os.environ["VERILATOR_ROOT"] + "/include/verilated.mk")
+m = re.search(r'CFG_CXXFLAGS_STD_NEWEST = (\S+)', fc)
+if not m:
+    test.error("Couldn't determine CFG_CXXFLAGS_STD_NEWEST")
+CFG_CXXFLAGS_STD_NEWEST = m.group(1)
+
+# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
+# toolchain on your path), from ICCM but otherwise using the default core
+# configuration. Running from ICCM is faster and hopefully more exciting.
+# Note the build happens in test.obj_dir as the SweRV build system can
+# find everything via RV_ROOT. This leaves the submodule clean.
+test.run(
+    cmd=[
+        "make -j4 -C " + test.obj_dir + " -f " + os.environ["RV_ROOT"] +
+        "/tools/Makefile",
+        ("VERILATOR='" + os.environ["VERILATOR"] +
+         " --debug-check -Wno-IMPLICITSTATIC --stats --timing " +
+         ' '.join(test.driver_verilator_flags) + "'"),
+        # Because Cores-SweRV-EH2/tools/Makefile has -std=c++11 which is too old
+        # Unfortunately it's too late in the Makefile to pass in VERILATOR above
+        "VERILATOR_DEBUG='-CFLAGS " + CFG_CXXFLAGS_STD_NEWEST + "'",  #
+        "CONF_PARAMS=-iccm_enable=1",  #
+        "GCC_PREFIX=none TEST=cmark_iccm",  #
+        "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"
+    ],  #
+    logfile=test.obj_dir + "/sim.log")
+
+test.file_grep(test.obj_dir + "/sim.log", r'\nTEST_PASSED\n')
+
+test.passes()
diff --git a/t/t_cores_swerv_el2_cmark.py b/t/t_cores_swerv_el2_cmark.py
new file mode 100755
index 0000000..3554a20
--- /dev/null
+++ b/t/t_cores_swerv_el2_cmark.py
@@ -0,0 +1,49 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.setenv('RV_ROOT',
+            os.path.abspath(test.t_dir + "/../submodules/Cores-SweRV-EL2"))
+test.setenv('VERILATOR', os.environ["VERILATOR_ROOT"] + "/bin/verilator")
+
+# Find compiler flag needed
+fc = test.file_contents(os.environ["VERILATOR_ROOT"] + "/include/verilated.mk")
+m = re.search(r'CFG_CXXFLAGS_STD_NEWEST = (\S+)', fc)
+if not m:
+    test.error("Couldn't determine CFG_CXXFLAGS_STD_NEWEST")
+CFG_CXXFLAGS_STD_NEWEST = m.group(1)
+
+# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
+# toolchain on your path), from ICCM but otherwise using the default core
+# configuration. Running from ICCM is faster and hopefully more exciting.
+# Note the build happens in test.obj_dir as the SweRV build system can
+# find everything via RV_ROOT. This leaves the submodule clean.
+test.run(
+    cmd=[
+        "make -j4 -C " + test.obj_dir + " -f " + os.environ["RV_ROOT"] +
+        "/tools/Makefile",
+        "VERILATOR='" + os.environ["VERILATOR"] +
+        " --debug-check -Wno-IMPLICITSTATIC " +
+        ' '.join(test.driver_verilator_flags),
+        "'",
+        # Because Cores-SweRV-EH2/tools/Makefile has -std=c++11 which is too old
+        # Unfortunately it's too late in the Makefile to pass in VERILATOR above
+        "VERILATOR_DEBUG='-CFLAGS " + CFG_CXXFLAGS_STD_NEWEST + "'",  #
+        "CONF_PARAMS=-iccm_enable=1",  #
+        "GCC_PREFIX=none TEST=cmark_iccm",  #
+        "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"
+    ],  #
+    logfile=test.obj_dir + "/sim.log")
+
+test.file_grep(test.obj_dir + "/sim.log", r'\nTEST_PASSED\n')
+
+test.passes()
diff --git a/t/t_cores_veer_eh1_cmark.pl b/t/t_cores_veer_eh1_cmark.pl
deleted file mode 100755
index 6ce071c..0000000
--- a/t/t_cores_veer_eh1_cmark.pl
+++ /dev/null
@@ -1,46 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-setenv('RV_ROOT', File::Spec->rel2abs($Self->{t_dir}."/../submodules/Cores-VeeR-EH1"));
-setenv('VERILATOR', "$ENV{VERILATOR_ROOT}/bin/verilator");
-
-# Find compiler flag needed
-my $fc = $Self->file_contents("$ENV{VERILATOR_ROOT}/include/verilated.mk");
-$fc =~ /CFG_CXXFLAGS_STD_NEWEST = (\S+)/ or die;
-my $CFG_CXXFLAGS_STD_NEWEST = $1;
-
-# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
-# toolchain on your path), from ICCM but otherwise using the default core
-# configuration. Running from ICCM is faster and hopefully more exciting.
-# Note the build happens in $Self->{obj_dir} as the VeeR build system can
-# find everything via RV_ROOT. This leaves the submodule clean.
-run(cmd => ["make -j4 -C $Self->{obj_dir} -f $ENV{RV_ROOT}/tools/Makefile",
-            "VERILATOR='$ENV{VERILATOR} --debug-check -Wno-IMPLICITSTATIC "
-            .join(' ',$Self->driver_verilator_flags()),"'",
-            # Because Cores-VeeR-EH2/tools/Makefile has -std=c++11 which is too old
-            # Unfortunately it's too late in the Makefile to pass in VERILATOR above
-            "VERILATOR_DEBUG='-CFLAGS $CFG_CXXFLAGS_STD_NEWEST'",
-            "CONF_PARAMS=-iccm_enable=1",
-            "GCC_PREFIX=none TEST=cmark_iccm",
-            "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"],
-    logfile => "$Self->{obj_dir}/sim.log",
-    );
-
-file_grep("$Self->{obj_dir}/sim.log", qr/.*\nTEST_PASSED\n/is);
-
-# Profiling:
-#  add to cmd: --debug-check --prof-cfuncs -CFLAGS -pg -LDFLAGS -pg
-#  cd /svaha/wsnyder/SandBox/homecvs/v4/verilator_ext_tests/obj_vlt/t_cores_swerv_cmark
-#  gprof
-
-ok(1);
-1;
diff --git a/t/t_cores_veer_eh1_cmark.py b/t/t_cores_veer_eh1_cmark.py
new file mode 100755
index 0000000..9d112d1
--- /dev/null
+++ b/t/t_cores_veer_eh1_cmark.py
@@ -0,0 +1,53 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.setenv('RV_ROOT',
+            os.path.abspath(test.t_dir + "/../submodules/Cores-VeeR-EH1"))
+test.setenv('VERILATOR', os.environ["VERILATOR_ROOT"] + "/bin/verilator")
+
+# Find compiler flag needed
+fc = test.file_contents(os.environ["VERILATOR_ROOT"] + "/include/verilated.mk")
+m = re.search(r'CFG_CXXFLAGS_STD_NEWEST = (\S+)', fc)
+if not m:
+    test.error("Couldn't determine CFG_CXXFLAGS_STD_NEWEST")
+CFG_CXXFLAGS_STD_NEWEST = m.group(1)
+
+# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
+# toolchain on your path), from ICCM but otherwise using the default core
+# configuration. Running from ICCM is faster and hopefully more exciting.
+# Note the build happens in test.obj_dir as the VeeR build system can
+# find everything via RV_ROOT. This leaves the submodule clean.
+test.run(
+    cmd=[
+        "make -j4 -C " + test.obj_dir + " -f " + os.environ["RV_ROOT"] +
+        "/tools/Makefile",
+        ("VERILATOR='" + os.environ["VERILATOR"] +
+         " --debug-check -Wno-IMPLICITSTATIC " +
+         ' '.join(test.driver_verilator_flags) + "'"),
+        # Because Cores-VeeR-EH2/tools/Makefile has -std=c++11 which is too old
+        # Unfortunately it's too late in the Makefile to pass in VERILATOR above
+        "VERILATOR_DEBUG='-CFLAGS " + CFG_CXXFLAGS_STD_NEWEST + "'",  #
+        "CONF_PARAMS=-iccm_enable=1",
+        "GCC_PREFIX=none TEST=cmark_iccm",
+        "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"
+    ],
+    logfile=test.obj_dir + "/sim.log")
+
+test.file_grep(test.obj_dir + "/sim.log", r'\nTEST_PASSED\n')
+
+# Profiling:
+#  add to cmd: --debug-check --prof-cfuncs -CFLAGS -pg -LDFLAGS -pg
+#  cd /svaha/wsnyder/SandBox/homecvs/v4/verilator_ext_tests/obj_vlt/t_cores_swerv_cmark
+#  gprof
+
+test.passes()
diff --git a/t/t_cores_veer_eh2_cmark.pl b/t/t_cores_veer_eh2_cmark.pl
deleted file mode 100755
index 55c9ee6..0000000
--- a/t/t_cores_veer_eh2_cmark.pl
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-setenv('RV_ROOT', File::Spec->rel2abs($Self->{t_dir}."/../submodules/Cores-VeeR-EH2"));
-setenv('VERILATOR', "$ENV{VERILATOR_ROOT}/bin/verilator");
-
-# Find compiler flag needed
-my $fc = $Self->file_contents("$ENV{VERILATOR_ROOT}/include/verilated.mk");
-$fc =~ /CFG_CXXFLAGS_STD_NEWEST = (\S+)/ or die;
-my $CFG_CXXFLAGS_STD_NEWEST = $1;
-
-# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
-# toolchain on your path), from ICCM but otherwise using the default core
-# configuration. Running from ICCM is faster and hopefully more exciting.
-# Note the build happens in $Self->{obj_dir} as the VeeR build system can
-# find everything via RV_ROOT. This leaves the submodule clean.
-run(cmd => ["make -j4 -C $Self->{obj_dir} -f $ENV{RV_ROOT}/tools/Makefile",
-            ("VERILATOR='$ENV{VERILATOR} --debug-check -Wno-IMPLICITSTATIC --stats --timing "
-             . join(' ',$Self->driver_verilator_flags())
-             . "'"),
-            # Because Cores-VeeR-EH2/tools/Makefile has -std=c++11 which is too old
-            # Unfortunately it's too late in the Makefile to pass in VERILATOR above
-            "VERILATOR_DEBUG='-CFLAGS $CFG_CXXFLAGS_STD_NEWEST'",
-            "CONF_PARAMS=-iccm_enable=1",
-            "GCC_PREFIX=none TEST=cmark_iccm",
-            "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"],
-    logfile => "$Self->{obj_dir}/sim.log",
-    );
-
-file_grep("$Self->{obj_dir}/sim.log", qr/.*\nTEST_PASSED\n/is);
-
-ok(1);
-1;
diff --git a/t/t_cores_veer_eh2_cmark.py b/t/t_cores_veer_eh2_cmark.py
new file mode 100755
index 0000000..ee37c51
--- /dev/null
+++ b/t/t_cores_veer_eh2_cmark.py
@@ -0,0 +1,53 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.setenv('RV_ROOT',
+            os.path.abspath(test.t_dir + "/../submodules/Cores-VeeR-EH2"))
+test.setenv('VERILATOR', os.environ["VERILATOR_ROOT"] + "/bin/verilator")
+
+# Find compiler flag needed
+fc = test.file_contents(os.environ["VERILATOR_ROOT"] + "/include/verilated.mk")
+m = re.search(r'CFG_CXXFLAGS_STD_NEWEST = (\S+)', fc)
+if not m:
+    test.error("Couldn't determine CFG_CXXFLAGS_STD_NEWEST")
+CFG_CXXFLAGS_STD_NEWEST = m.group(1)
+
+# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
+# toolchain on your path), from ICCM but otherwise using the default core
+# configuration. Running from ICCM is faster and hopefully more exciting.
+# Note the build happens in test.obj_dir as the VeeR build system can
+# find everything via RV_ROOT. This leaves the submodule clean.
+test.run(
+    cmd=[
+        "make -j4 -C " + test.obj_dir + " -f " + os.environ["RV_ROOT"] +
+        "/tools/Makefile",
+        ("VERILATOR='" + os.environ["VERILATOR"] +
+         " --debug-check -Wno-IMPLICITSTATIC --stats --timing" +
+         ' '.join(test.driver_verilator_flags) + "'"),
+        # Because Cores-VeeR-EH2/tools/Makefile has -std=c++11 which is too old
+        # Unfortunately it's too late in the Makefile to pass in VERILATOR above
+        "VERILATOR_DEBUG='-CFLAGS " + CFG_CXXFLAGS_STD_NEWEST + "'",  #
+        "CONF_PARAMS=-iccm_enable=1",
+        "GCC_PREFIX=none TEST=cmark_iccm",
+        "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"
+    ],
+    logfile=test.obj_dir + "/sim.log")
+
+test.file_grep(test.obj_dir + "/sim.log", r'\nTEST_PASSED\n')
+
+# Profiling:
+#  add to cmd: --debug-check --prof-cfuncs -CFLAGS -pg -LDFLAGS -pg
+#  cd /svaha/wsnyder/SandBox/homecvs/v4/verilator_ext_tests/obj_vlt/t_cores_swerv_cmark
+#  gprof
+
+test.passes()
diff --git a/t/t_cores_veer_el2_cmark.pl b/t/t_cores_veer_el2_cmark.pl
deleted file mode 100755
index 92e20ff..0000000
--- a/t/t_cores_veer_el2_cmark.pl
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-setenv('RV_ROOT', File::Spec->rel2abs($Self->{t_dir}."/../submodules/Cores-VeeR-EL2"));
-setenv('VERILATOR', "$ENV{VERILATOR_ROOT}/bin/verilator");
-
-# Find compiler flag needed
-my $fc = $Self->file_contents("$ENV{VERILATOR_ROOT}/include/verilated.mk");
-$fc =~ /CFG_CXXFLAGS_STD_NEWEST = (\S+)/ or die;
-my $CFG_CXXFLAGS_STD_NEWEST = $1;
-
-# This will run the canned CoreMark (even if you have a riscv64-unknown-elf
-# toolchain on your path), from ICCM but otherwise using the default core
-# configuration. Running from ICCM is faster and hopefully more exciting.
-# Note the build happens in $Self->{obj_dir} as the VeeR build system can
-# find everything via RV_ROOT. This leaves the submodule clean.
-$Self->skip("cores-VeeR-EL2 has unfixed mason dependency");
-#run(cmd => ["make -j4 -C $Self->{obj_dir} -f $ENV{RV_ROOT}/tools/Makefile",
-#            "VERILATOR='$ENV{VERILATOR} --debug-check -Wno-IMPLICITSTATIC "
-#            .join(' ',$Self->driver_verilator_flags()),"'",
-#            # Because Cores-VeeR-EH2/tools/Makefile has -std=c++11 which is too old
-#            # Unfortunately it's too late in the Makefile to pass in VERILATOR above
-#            "VERILATOR_DEBUG='-CFLAGS $CFG_CXXFLAGS_STD_NEWEST'",
-#            "CONF_PARAMS=-iccm_enable=1",
-#            "GCC_PREFIX=none TEST=cmark_iccm",
-#            "VERILATOR_MAKE_FLAGS=VM_PARALLEL_BUILDS=1 verilator"],
-#    logfile => "$Self->{obj_dir}/sim.log",
-#    );
-#
-#file_grep("$Self->{obj_dir}/sim.log", qr/.*\nTEST_PASSED\n/is);
-
-ok(1);
-1;
diff --git a/t/t_cores_veer_el2_cmark.py b/t/t_cores_veer_el2_cmark.py
new file mode 100755
index 0000000..726735f
--- /dev/null
+++ b/t/t_cores_veer_el2_cmark.py
@@ -0,0 +1,14 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.skip("cores-VeeR-EL2 has unfixed mason dependency")
+
+test.passes()
diff --git a/t/t_coverage_example.pl b/t/t_coverage_example.pl
deleted file mode 100755
index a4e495b..0000000
--- a/t/t_coverage_example.pl
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-setenv('VERILATOR', "$ENV{VERILATOR_ROOT}/bin/verilator");
-
-run(cmd => ["make -j4 -C submodules/example-systemverilog"],
-    logfile => "$Self->{obj_dir}/sim.log",
-    );
-
-file_grep("$Self->{obj_dir}/sim.log", qr/.*\n-- DONE --/is);
-
-ok(1);
-1;
diff --git a/t/t_coverage_example.py b/t/t_coverage_example.py
new file mode 100755
index 0000000..3e9dd88
--- /dev/null
+++ b/t/t_coverage_example.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.setenv('VERILATOR', os.environ['VERILATOR_ROOT'] + "/bin/verilator")
+
+test.run(cmd=["make -j4 -C submodules/example-systemverilog"],
+         logfile=test.obj_dir + "/sim.log")
+
+test.file_grep(test.obj_dir + "/sim.log", r'.*\n-- DONE --')
+
+test.passes()
diff --git a/t/t_dump_json_astsee.pl b/t/t_dump_json_astsee.pl
deleted file mode 100755
index 595861c..0000000
--- a/t/t_dump_json_astsee.pl
+++ /dev/null
@@ -1,33 +0,0 @@
-#!/usr/bin/env perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-# test whether json dumps don't "crash" astsee
-
-scenarios(vlt => 1);
-
-{
-    my $cmd = qq{astsee_verilator -h >/dev/null 2>&1};
-    print "\t$cmd\n" if $::Debug;
-    system($cmd) and do { skip("No astsee installed\n"); return 1 }
-}
-
-top_filename("$ENV{VERILATOR_ROOT}/test_regress/t/t_dump.v");
-
-lint(
-    v_flags => ["--lint-only --dump-tree-json"],
-    );
-
-
-run(cmd => ["cd $Self->{obj_dir} && astsee_verilator *001*.json > astsee.log"],
-    logfile => "$Self->{obj_dir}/astsee.log");
-
-ok(1);
-
-1;
diff --git a/t/t_dump_json_astsee.py b/t/t_dump_json_astsee.py
new file mode 100755
index 0000000..958b30e
--- /dev/null
+++ b/t/t_dump_json_astsee.py
@@ -0,0 +1,26 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = os.environ["VERILATOR_ROOT"] + "/test_regress/t/t_dump.v"
+
+out = test.run_capture("astsee_verilator -h 2>&1", check=False)
+if 'not found' in out:
+    test.skip("No astsee installed\n")
+
+test.lint(v_flags=["--lint-only --dump-tree-json"])
+
+test.run(cmd=[
+    "cd " + test.obj_dir + " && astsee_verilator *001*.json > astsee.log"
+],
+         logfile=test.obj_dir + "/astsee.log")
+
+test.passes()
diff --git a/t/t_gdb_jtree.pl b/t/t_gdb_jtree.pl
deleted file mode 100755
index 6282cfb..0000000
--- a/t/t_gdb_jtree.pl
+++ /dev/null
@@ -1,33 +0,0 @@
-#!/usr/bin/env perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-# test whether jtree gdb command doesn't crash
-
-scenarios(vlt => 1);
-
-{
-    my $cmd = qq{astsee_verilator -h >/dev/null 2>&1};
-    print "\t$cmd\n" if $::Debug;
-    system($cmd) and do { skip("No astsee installed\n"); return 1 }
-}
-
-setenv("VERILATOR_GDB", "gdb --return-child-result"
-                        . ($::Debug ? " --batch" : " --batch-silent --quiet")
-                        . ' -init-eval-command "set auto-load no"'
-                        . " --command $ENV{VERILATOR_ROOT}/src/.gdbinit"
-                        . " --command $Self->{t_dir}/t_gdb_jtree.gdb");
-
-top_filename("t/t_dump.v");
-
-lint(v_flags => ["--gdb", "--debug"]);
-
-ok(1);
-
-1;
diff --git a/t/t_gdb_jtree.py b/t/t_gdb_jtree.py
new file mode 100755
index 0000000..524a62d
--- /dev/null
+++ b/t/t_gdb_jtree.py
@@ -0,0 +1,28 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+test.top_filename = "t/t_dump.v"
+
+out = test.run_capture("astsee_verilator -h 2>&1", check=False)
+if 'not found' in out:
+    test.skip("No astsee installed\n")
+
+test.setenv(
+    "VERILATOR_GDB", "gdb --return-child-result" +
+    (" --batch-silent --quiet" if test.verbose else " --batch") +
+    ' -init-eval-command "set auto-load no"' + " --command " +
+    os.environ["VERILATOR_ROOT"] + "/src/.gdbinit" + " --command " +
+    test.t_dir + "/t_gdb_jtree.gdb")
+
+test.lint(v_flags=["--gdb", "--debug"])
+
+test.passes()
diff --git a/t/t_gtkwave_diff.pl b/t/t_gtkwave_diff.pl
deleted file mode 100755
index a05a5c7..0000000
--- a/t/t_gtkwave_diff.pl
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2019 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-sub check {
-    my ($a, $b, $basename) = @_;
-    my $cmd = "diff -u $a/$basename $b/$basename 2>&1";
-    print "\t$cmd\n" if $Self->{verbose};
-    my $out = `$cmd`;
-    if ($? || $o) {
-        print $out;
-        $Self->error("Differences in $basename");
-        $Self->copy_if_golden("$a/$basename", "$b/$basename");
-    }
-}
-
-scenarios(dist => 1);
-
-if (!$ENV{VERILATOR_TEST_UPSTREAM}) {
-    skip("Skipping due to no VERILATOR_TEST_UPSTREAM");
-} else {
-    print `pwd`;
-    my $g = "submodules/gtkwave";
-    my $v = $ENV{VERILATOR_ROOT} || "submodules/verilator";
-
-    check("$g/src/helpers", "$v/include/gtkwave", "wavealloca.h");
-    check("$g/lib/libfst", "$v/include/gtkwave", "fastlz.h");
-    check("$g/lib/libfst", "$v/include/gtkwave", "fastlz.c");
-    check("$g/lib/libfst", "$v/include/gtkwave", "fstapi.h");
-    check("$g/lib/libfst", "$v/include/gtkwave", "fstapi.c");
-    check("$g/lib/libfst", "$v/include/gtkwave", "lz4.h");
-    check("$g/lib/libfst", "$v/include/gtkwave", "lz4.c");
-
-    ok(1);
-}
-
-1;
diff --git a/t/t_gtkwave_diff.py b/t/t_gtkwave_diff.py
new file mode 100755
index 0000000..2ce5996
--- /dev/null
+++ b/t/t_gtkwave_diff.py
@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('dist')
+
+
+def check(a, b, basename):
+    cmd = "diff -u " + a + "/" + basename + " " + b + "/" + basename + " 2>&1"
+    if test.verbose:
+        print("\t" + cmd)
+    out = test.run_capture(cmd, check=False)
+    if out != "":
+        print(out)
+        test.error_keep_going("Differences in " + basename)
+        test.copy_if_golden(a + "/" + basename, b + "/" + basename)
+
+
+if 'VERILATOR_TEST_UPSTREAM' not in os.environ:
+    test.skip("Skipping due to no VERILATOR_TEST_UPSTREAM")
+
+print(os.getcwd)
+g = "submodules/gtkwave"
+v = os.environ['VERILATOR_ROOT']
+
+check(g + "/src/helpers", v + "/include/gtkwave", "wavealloca.h")
+check(g + "/lib/libfst", v + "/include/gtkwave", "fastlz.h")
+check(g + "/lib/libfst", v + "/include/gtkwave", "fastlz.c")
+check(g + "/lib/libfst", v + "/include/gtkwave", "fstapi.h")
+check(g + "/lib/libfst", v + "/include/gtkwave", "fstapi.c")
+check(g + "/lib/libfst", v + "/include/gtkwave", "lz4.h")
+check(g + "/lib/libfst", v + "/include/gtkwave", "lz4.c")
+
+test.passes()
diff --git a/t/t_math_synmul.pl b/t/t_math_synmul.pl
deleted file mode 100755
index a256a52..0000000
--- a/t/t_math_synmul.pl
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-scenarios(simulator => 1);
-
-compile(
-    verilator_flags2 => ["-Wno-UNOPTTHREADS"],
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
diff --git a/t/t_math_synmul.py b/t/t_math_synmul.py
new file mode 100755
index 0000000..153317c
--- /dev/null
+++ b/t/t_math_synmul.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["-Wno-UNOPTTHREADS"])
+
+test.execute(check_finished=True)
+
+test.passes()
diff --git a/t/t_math_wallace.pl b/t/t_math_wallace.pl
deleted file mode 100755
index 1f6e80c..0000000
--- a/t/t_math_wallace.pl
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-scenarios(simulator => 1);
-
-compile(
-    );
-
-execute(
-    check_finished=>1,
-    );
-
-ok(1);
-1;
diff --git a/t/t_math_wallace.py b/t/t_math_wallace.py
new file mode 100755
index 0000000..f64ff6a
--- /dev/null
+++ b/t/t_math_wallace.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute(check_finished=True)
+
+test.passes()
diff --git a/t/t_uvm_parse.pl b/t/t_uvm_parse.pl
deleted file mode 100755
index 4ca7906..0000000
--- a/t/t_uvm_parse.pl
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-
-use File::Spec;
-
-scenarios(vlt => 1);
-
-my $uvm_root = File::Spec->rel2abs($Self->{t_dir}."/../submodules/uvm");
-
-lint(
-    v_flags2 => ["+incdir+${uvm_root}/src",
-                 "-Wall -Wno-DECLFILENAME -Wno-VARHIDDEN -Wno-CONSTRAINTIGN -Wno-MISINDENT",
-                 "--debug-exit-uvm",
-    ],
-    );
-
-ok(1);
-1;
diff --git a/t/t_uvm_parse.py b/t/t_uvm_parse.py
new file mode 100755
index 0000000..d43a13a
--- /dev/null
+++ b/t/t_uvm_parse.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+uvm_root = os.path.abspath(test.t_dir + "/../submodules/uvm")
+
+test.lint(v_flags=[
+    "+incdir+" + uvm_root + "/src",
+    "-Wall -Wno-DECLFILENAME -Wno-VARHIDDEN -Wno-CONSTRAINTIGN -Wno-MISINDENT",
+    "--debug-exit-uvm"
+])
+
+test.passes()
diff --git a/t/t_wbuart32.pl b/t/t_wbuart32.pl
deleted file mode 100755
index b299246..0000000
--- a/t/t_wbuart32.pl
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/usr/bin/perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you can
-# redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
-
-scenarios(vlt => 1);
-
-run(cmd => ["make -C submodules/wbuart32",
-            "VERILATOR='$ENV{VERILATOR_ROOT}/bin/verilator --debug-check ".join(' ',$Self->driver_verilator_flags())."'",
-            "test"],
-    logfile => "$Self->{obj_dir}/sim.log",
-    );
-
-file_grep("$Self->{obj_dir}/sim.log", qr/.*\nPASS!\n.*\nPASS\n.*\nPASS!\n/is);
-
-# profiling:
-#   (cd submodules/wbuart32/bench/cpp ; gprof linetest > gprof.log )
-
-ok(1);
-1;
diff --git a/t/t_wbuart32.py b/t/t_wbuart32.py
new file mode 100755
index 0000000..7f73932
--- /dev/null
+++ b/t/t_wbuart32.py
@@ -0,0 +1,26 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.run(cmd=[
+    "make -C submodules/wbuart32", "VERILATOR='" +
+    os.environ['VERILATOR_ROOT'] + "/bin/verilator --debug-check " +
+    ' '.join(test.driver_verilator_flags) + "'", "test"
+],
+         logfile=test.obj_dir + "/sim.log")
+
+test.file_grep(test.obj_dir + "/sim.log", r'PASS!')
+
+# profiling:
+#   (cd submodules/wbuart32/bench/cpp ; gprof linetest > gprof.log )
+
+test.passes()
diff --git a/t/vltest_bootstrap.py b/t/vltest_bootstrap.py
new file mode 100755
index 0000000..9d53224
--- /dev/null
+++ b/t/vltest_bootstrap.py
@@ -0,0 +1,27 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import os
+import re
+import sys
+
+if 'VERILATOR_ROOT' not in os.environ:
+    sys.exit("%Error: setenv VERILATOR_ROOT required for site tests")
+
+if 'VERILATOR_TESTS_SITE' not in os.environ:
+    os.environ['VERILATOR_TESTS_SITE'] = ''
+else:
+    os.environ['VERILATOR_TESTS_SITE'] += ':'
+os.environ['VERILATOR_TESTS_SITE'] += os.path.dirname(
+    os.path.realpath(__file__))
+
+os.environ['PWD'] = os.getcwd()
+args = list(map(lambda arg: re.sub(r'.*/test_regress/', '', arg), sys.argv))
+os.execl(os.environ['VERILATOR_ROOT'] + "/test_regress/driver.py",
+         "--bootstrapped", *args)