.gitmodules

[submodule "submodules/verilator"]
	path = submodules/verilator
	url = https://github.com/verilator/verilator.git
[submodule "submodules/example-systemverilog"]
	path = submodules/example-systemverilog
	url = https://github.com/verilator/example-systemverilog.git
[submodule "submodules/Cores-SweRV"]
	path = submodules/Cores-SweRV
	url = https://github.com/chipsalliance/Cores-SweRV.git
[submodule "submodules/Cores-SweRV-EH2"]
	path = submodules/Cores-SweRV-EH2
	url = https://github.com/chipsalliance/Cores-SweRV-EH2.git
[submodule "submodules/Cores-SweRV-EL2"]
	path = submodules/Cores-SweRV-EL2
	url = https://github.com/chipsalliance/Cores-SweRV-EL2.git
[submodule "submodules/gtkwave"]
	path = submodules/gtkwave
	url = https://github.com/gtkwave/gtkwave.git
[submodule "submodules/wbuart32"]
	path = submodules/wbuart32
	url = https://github.com/ZipCPU/wbuart32.git
[submodule "submodules/uvm"]
	path = submodules/uvm
	url = https://github.com/chipsalliance/uvm-verilator.git
[submodule "submodules/Cores-VeeR-EL2"]
	path = submodules/Cores-VeeR-EL2
	url = https://github.com/chipsalliance/Cores-VeeR-EL2.git
[submodule "submodules/Cores-VeeR-EH2"]
	path = submodules/Cores-VeeR-EH2
	url = https://github.com/chipsalliance/Cores-VeeR-EH2.git
[submodule "submodules/Cores-VeeR-EH1"]
	path = submodules/Cores-VeeR-EH1
	url = https://github.com/chipsalliance/Cores-VeeR-EH1.git
[submodule "submodules/astsee"]
	path = submodules/astsee
	url = https://github.com/antmicro/astsee.git