diff --git a/alu_u32/src/lt/mod.rs b/alu_u32/src/lt/mod.rs
index 59f2aba..3aee13b 100644
--- a/alu_u32/src/lt/mod.rs
+++ b/alu_u32/src/lt/mod.rs
@@ -150,7 +150,7 @@ where
         let mut imm: Option<Word<u8>> = None;
         let read_addr_1 = (state.cpu().fp as i32 + ops.b()) as u32;
         let write_addr = (state.cpu().fp as i32 + ops.a()) as u32;
-        let src1 = if ops.d() == 1 {
+        let src1: Word<u8> = if ops.d() == 1 {
             let b = (ops.b() as u32).into();
             imm = Some(b);
             b
@@ -159,7 +159,7 @@ where
                 .mem_mut()
                 .read(clk, read_addr_1, true, pc, opcode, 0, "")
         };
-        let src2 = if ops.is_imm() == 1 {
+        let src2: Word<u8> = if ops.is_imm() == 1 {
             let c = (ops.c() as u32).into();
             imm = Some(c);
             c
@@ -199,7 +199,7 @@ where
         let mut imm: Option<Word<u8>> = None;
         let read_addr_1 = (state.cpu().fp as i32 + ops.b()) as u32;
         let write_addr = (state.cpu().fp as i32 + ops.a()) as u32;
-        let src1 = if ops.d() == 1 {
+        let src1: Word<u8> = if ops.d() == 1 {
             let b = (ops.b() as u32).into();
             imm = Some(b);
             b
@@ -208,7 +208,7 @@ where
                 .mem_mut()
                 .read(clk, read_addr_1, true, pc, opcode, 0, "")
         };
-        let src2 = if ops.is_imm() == 1 {
+        let src2: Word<u8> = if ops.is_imm() == 1 {
             let c = (ops.c() as u32).into();
             imm = Some(c);
             c