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==============================================================================
XRT Build Version: 2.13.466 (2022.1)
Build Date: 2022-04-14 17:45:07
Hash ID: f5505e402c2ca1ffe45eb6d3a9399b23a0dc8776
==============================================================================
xclbin Information
------------------
Generated by: v++ (2022.1) on 2022-04-13-17:42:45
Version: 2.13.466
Kernels: vadd
Signature:
Content: Bitstream
UUID (xclbin): 9c0e5a15-2727-ca3f-e014-ddad06e6b458
UUID (IINTF): 16e2362f82d2feab35529da27134b76d
Sections: DEBUG_IP_LAYOUT, BITSTREAM, MEM_TOPOLOGY, IP_LAYOUT,
CONNECTIVITY, CLOCK_FREQ_TOPOLOGY, BUILD_METADATA,
EMBEDDED_METADATA, SYSTEM_METADATA,
PARTITION_METADATA, GROUP_CONNECTIVITY, GROUP_TOPOLOGY
==============================================================================
Hardware Platform (Shell) Information
-------------------------------------
Vendor: xilinx
Board: u50
Name: gen3x16_xdma_5
Version: 202210.1
Generated Version: Vivado 2022.1 (SW Build: 3481164)
Created: Thu Mar 3 20:48:35 2022
FPGA Device: xcu50
Board Vendor: xilinx.com
Board Name: xilinx.com:au50:1.1
Board Part: xilinx.com:au50:part0:1.1
Platform VBNV: xilinx_u50_gen3x16_xdma_5_202210_1
Static UUID: 00000000-0000-0000-0000-000000000000
Feature ROM TimeStamp: 0
Scalable Clocks
------
Name: hbm_aclk
Index: 0
Type: SYSTEM
Frequency: 450 MHz
Name: KERNEL_CLK
Index: 1
Type: KERNEL
Frequency: 500 MHz
Name: DATA_CLK
Index: 2
Type: DATA
Frequency: 300 MHz
System Clocks
------
Name: ulp_ucs_aclk_kernel_00
Type: SCALABLE
Default Freq: 300 MHz
Requested Freq: 300 MHz
Achieved Freq: 300 MHz
Name: ulp_ucs_aclk_kernel_01
Type: SCALABLE
Default Freq: 500 MHz
Requested Freq: 500 MHz
Achieved Freq: 500 MHz
Name: _bd_top_blp_s_aclk_freerun_ref_00
Type: FIXED
Default Freq: 100 MHz
Memory Configuration
--------------------
Name: HBM[0]
Index: 0
Type: MEM_HBM
Base Address: 0x0
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[1]
Index: 1
Type: MEM_DRAM
Base Address: 0x10000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[2]
Index: 2
Type: MEM_DRAM
Base Address: 0x20000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[3]
Index: 3
Type: MEM_DRAM
Base Address: 0x30000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[4]
Index: 4
Type: MEM_DRAM
Base Address: 0x40000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[5]
Index: 5
Type: MEM_DRAM
Base Address: 0x50000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[6]
Index: 6
Type: MEM_DRAM
Base Address: 0x60000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[7]
Index: 7
Type: MEM_DRAM
Base Address: 0x70000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[8]
Index: 8
Type: MEM_DRAM
Base Address: 0x80000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[9]
Index: 9
Type: MEM_DRAM
Base Address: 0x90000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[10]
Index: 10
Type: MEM_DRAM
Base Address: 0xa0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[11]
Index: 11
Type: MEM_DRAM
Base Address: 0xb0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[12]
Index: 12
Type: MEM_DRAM
Base Address: 0xc0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[13]
Index: 13
Type: MEM_DRAM
Base Address: 0xd0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[14]
Index: 14
Type: MEM_DRAM
Base Address: 0xe0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[15]
Index: 15
Type: MEM_DRAM
Base Address: 0xf0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[16]
Index: 16
Type: MEM_DRAM
Base Address: 0x100000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[17]
Index: 17
Type: MEM_DRAM
Base Address: 0x110000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[18]
Index: 18
Type: MEM_DRAM
Base Address: 0x120000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[19]
Index: 19
Type: MEM_DRAM
Base Address: 0x130000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[20]
Index: 20
Type: MEM_DRAM
Base Address: 0x140000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[21]
Index: 21
Type: MEM_DRAM
Base Address: 0x150000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[22]
Index: 22
Type: MEM_DRAM
Base Address: 0x160000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[23]
Index: 23
Type: MEM_DRAM
Base Address: 0x170000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[24]
Index: 24
Type: MEM_DRAM
Base Address: 0x180000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[25]
Index: 25
Type: MEM_DRAM
Base Address: 0x190000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[26]
Index: 26
Type: MEM_DRAM
Base Address: 0x1a0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[27]
Index: 27
Type: MEM_DRAM
Base Address: 0x1b0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[28]
Index: 28
Type: MEM_DRAM
Base Address: 0x1c0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[29]
Index: 29
Type: MEM_DRAM
Base Address: 0x1d0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[30]
Index: 30
Type: MEM_DRAM
Base Address: 0x1e0000000
Address Size: 0x10000000
Bank Used: Yes
Name: HBM[31]
Index: 31
Type: MEM_DRAM
Base Address: 0x1f0000000
Address Size: 0x10000000
Bank Used: Yes
Name: PLRAM[0]
Index: 32
Type: MEM_DRAM
Base Address: 0x0
Address Size: 0x0
Bank Used: No
Name: PLRAM[1]
Index: 33
Type: MEM_DRAM
Base Address: 0x0
Address Size: 0x0
Bank Used: No
Name: PLRAM[2]
Index: 34
Type: MEM_DRAM
Base Address: 0x0
Address Size: 0x0
Bank Used: No
Name: PLRAM[3]
Index: 35
Type: MEM_DRAM
Base Address: 0x0
Address Size: 0x0
Bank Used: No
Name: HOST[0]
Index: 36
Type: MEM_DRAM
Base Address: 0x0
Address Size: 0x0
Bank Used: No
==============================================================================
Kernel: vadd
Definition
----------
Signature: vadd (void* in1, void* in2, void* out, unsigned int dsize, unsigned int kernel_loop, unsigned int addRandom)
Ports
-----
Port: M_AXI_GMEM0
Mode: master
Range (bytes): 0xFFFFFFFF
Data Width: 512 bits
Port Type: addressable
Port: M_AXI_GMEM1
Mode: master
Range (bytes): 0xFFFFFFFF
Data Width: 512 bits
Port Type: addressable
Port: M_AXI_GMEM2
Mode: master
Range (bytes): 0xFFFFFFFF
Data Width: 512 bits
Port Type: addressable
Port: S_AXI_CONTROL
Mode: slave
Range (bytes): 0x4C
Data Width: 32 bits
Port Type: addressable
--------------------------
Instance: vadd_1
Base Address: 0x1400000
Argument: in1
Register Offset: 0x10
Port: M_AXI_GMEM0
Memory: HBM[0] (MEM_HBM)
Memory: HBM[1] (MEM_DRAM)
Memory: HBM[2] (MEM_DRAM)
Memory: HBM[3] (MEM_DRAM)
Memory: HBM[4] (MEM_DRAM)
Memory: HBM[5] (MEM_DRAM)
Memory: HBM[6] (MEM_DRAM)
Memory: HBM[7] (MEM_DRAM)
Memory: HBM[8] (MEM_DRAM)
Memory: HBM[9] (MEM_DRAM)
Memory: HBM[10] (MEM_DRAM)
Memory: HBM[11] (MEM_DRAM)
Memory: HBM[12] (MEM_DRAM)
Memory: HBM[13] (MEM_DRAM)
Memory: HBM[14] (MEM_DRAM)
Memory: HBM[15] (MEM_DRAM)
Memory: HBM[16] (MEM_DRAM)
Memory: HBM[17] (MEM_DRAM)
Memory: HBM[18] (MEM_DRAM)
Memory: HBM[19] (MEM_DRAM)
Memory: HBM[20] (MEM_DRAM)
Memory: HBM[21] (MEM_DRAM)
Memory: HBM[22] (MEM_DRAM)
Memory: HBM[23] (MEM_DRAM)
Memory: HBM[24] (MEM_DRAM)
Memory: HBM[25] (MEM_DRAM)
Memory: HBM[26] (MEM_DRAM)
Memory: HBM[27] (MEM_DRAM)
Memory: HBM[28] (MEM_DRAM)
Memory: HBM[29] (MEM_DRAM)
Memory: HBM[30] (MEM_DRAM)
Memory: HBM[31] (MEM_DRAM)
Argument: in2
Register Offset: 0x1C
Port: M_AXI_GMEM1
Memory: HBM[0] (MEM_HBM)
Memory: HBM[1] (MEM_DRAM)
Memory: HBM[2] (MEM_DRAM)
Memory: HBM[3] (MEM_DRAM)
Memory: HBM[4] (MEM_DRAM)
Memory: HBM[5] (MEM_DRAM)
Memory: HBM[6] (MEM_DRAM)
Memory: HBM[7] (MEM_DRAM)
Memory: HBM[8] (MEM_DRAM)
Memory: HBM[9] (MEM_DRAM)
Memory: HBM[10] (MEM_DRAM)
Memory: HBM[11] (MEM_DRAM)
Memory: HBM[12] (MEM_DRAM)
Memory: HBM[13] (MEM_DRAM)
Memory: HBM[14] (MEM_DRAM)
Memory: HBM[15] (MEM_DRAM)
Memory: HBM[16] (MEM_DRAM)
Memory: HBM[17] (MEM_DRAM)
Memory: HBM[18] (MEM_DRAM)
Memory: HBM[19] (MEM_DRAM)
Memory: HBM[20] (MEM_DRAM)
Memory: HBM[21] (MEM_DRAM)
Memory: HBM[22] (MEM_DRAM)
Memory: HBM[23] (MEM_DRAM)
Memory: HBM[24] (MEM_DRAM)
Memory: HBM[25] (MEM_DRAM)
Memory: HBM[26] (MEM_DRAM)
Memory: HBM[27] (MEM_DRAM)
Memory: HBM[28] (MEM_DRAM)
Memory: HBM[29] (MEM_DRAM)
Memory: HBM[30] (MEM_DRAM)
Memory: HBM[31] (MEM_DRAM)
Argument: out
Register Offset: 0x28
Port: M_AXI_GMEM2
Memory: HBM[0] (MEM_HBM)
Memory: HBM[1] (MEM_DRAM)
Memory: HBM[2] (MEM_DRAM)
Memory: HBM[3] (MEM_DRAM)
Memory: HBM[4] (MEM_DRAM)
Memory: HBM[5] (MEM_DRAM)
Memory: HBM[6] (MEM_DRAM)
Memory: HBM[7] (MEM_DRAM)
Memory: HBM[8] (MEM_DRAM)
Memory: HBM[9] (MEM_DRAM)
Memory: HBM[10] (MEM_DRAM)
Memory: HBM[11] (MEM_DRAM)
Memory: HBM[12] (MEM_DRAM)
Memory: HBM[13] (MEM_DRAM)
Memory: HBM[14] (MEM_DRAM)
Memory: HBM[15] (MEM_DRAM)
Memory: HBM[16] (MEM_DRAM)
Memory: HBM[17] (MEM_DRAM)
Memory: HBM[18] (MEM_DRAM)
Memory: HBM[19] (MEM_DRAM)
Memory: HBM[20] (MEM_DRAM)
Memory: HBM[21] (MEM_DRAM)
Memory: HBM[22] (MEM_DRAM)
Memory: HBM[23] (MEM_DRAM)
Memory: HBM[24] (MEM_DRAM)
Memory: HBM[25] (MEM_DRAM)
Memory: HBM[26] (MEM_DRAM)
Memory: HBM[27] (MEM_DRAM)
Memory: HBM[28] (MEM_DRAM)
Memory: HBM[29] (MEM_DRAM)
Memory: HBM[30] (MEM_DRAM)
Memory: HBM[31] (MEM_DRAM)
Argument: dsize
Register Offset: 0x34
Port: S_AXI_CONTROL
Memory: <not applicable>
Argument: kernel_loop
Register Offset: 0x3C
Port: S_AXI_CONTROL
Memory: <not applicable>
Argument: addRandom
Register Offset: 0x44
Port: S_AXI_CONTROL
Memory: <not applicable>
==============================================================================
Generated By
------------
Command: v++
Version: 2022.1 - 2022-04-13-17:42:45 (SW BUILD: 3524075)
Command Line: v++ --config ../vadd.cfg --connectivity.nk vadd:1:vadd_1 --connectivity.sp vadd_1.in1:HBM[0:31] --connectivity.sp vadd_1.in2:HBM[0:31] --connectivity.sp vadd_1.out:HBM[0:31] --debug --input_files _x.hw.xilinx_u50_gen3x16_xdma_5_202210_1/vadd.xo --link --optimize 0 --platform xilinx_u50_gen3x16_xdma_5_202210_1 --profile.data all:all:all --report_level 0 --save-temps --target hw --temp_dir ./_x.hw.xilinx_u50_gen3x16_xdma_5_202210_1 --vivado.impl.jobs -o./build_dir.hw.xilinx_u50_gen3x16_xdma_5_202210_1/vadd.link.xclbin --vivado.synth.jobs 8
Options: --config ../vadd.cfg
--connectivity.nk vadd:1:vadd_1
--connectivity.sp vadd_1.in1:HBM[0:31]
--connectivity.sp vadd_1.in2:HBM[0:31]
--connectivity.sp vadd_1.out:HBM[0:31]
--debug
--input_files _x.hw.xilinx_u50_gen3x16_xdma_5_202210_1/vadd.xo
--link
--optimize 0
--platform xilinx_u50_gen3x16_xdma_5_202210_1
--profile.data all:all:all
--report_level 0
--save-temps
--target hw
--temp_dir ./_x.hw.xilinx_u50_gen3x16_xdma_5_202210_1
--vivado.impl.jobs
-o./build_dir.hw.xilinx_u50_gen3x16_xdma_5_202210_1/vadd.link.xclbin
--vivado.synth.jobs 8
==============================================================================
User Added Key Value Pairs
--------------------------
<empty>
==============================================================================