to confirm whether the change of nvseq and nvlreq is right

[gxlong1983]

Hi,

When we change the value of the parameter HwachaNVectorRegs and HwachaNSRAMRFEntries into 32, we found that the nvsreq and nvlreq in hwacha.scala are not satisfied and an error is reported as follows.
firrtl.passes.CheckWidths$BitsWidthException: @[dcc-mem.scala 613:33:[email protected]]: [module VLU] High bit 9 in bits operator is larger than input width 5 in bits(_T_1675, 9, 0).
firrtl.passes.PassException: 4 errors detected!

after we change the nvsreq and nvlreq as below, there is no error.

val nvsreq = math.max(p(HwachaNVectorRegs), p(HwachaNSRAMRFEntries)) * p(HwachaBankWidth) / p(HwachaRegLen)
val nvlreq = math.max(p(HwachaNVectorRegs), p(HwachaNSRAMRFEntries)) * p(HwachaBankWidth) / p(HwachaRegLen)

Could you please confirm whether the change for nvsreq and nvlreq is right? thanks.

--gao