Potential issue with Ring[T].zero for Complex

[shunshou]

Not really sure what's going on and I found a way around it -- but I was getting non-synthesizable node errors by directly assigning Complex to Ring[T].zero where T <: Data:RealBits.

Just making a note for the future.

Workaround was to individually assign real/imag to Lits.

Also, this wasn't a problem with FixedPoint, only with DspReal.

[shunshou]

@chick

val zero = Ring[DspComplex[T]].zero

Gives

 java.lang.IllegalArgumentException: requirement failed: can't create Mux with non-equivalent types dsptools.numbers.DspComplex@c1 and dsptools.numbers.DspComplex@9d

When I mux the zero in.