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Releases: ucb-bar/chiseltest
Releases · ucb-bar/chiseltest
v0.1.3
v0.1.2
v0.1.1
v0.1.0
190904
190730: Merge pull request #51 from ucb-bar/fix-no-printf-with-verilator
Snapshot pushed to sonatype. Note, this relies on the latest version of Chisel and FIRRTL, which were published as snapshots a few days back.
- Added Verilator support, by porting the backend from old testers. Further improvements are planned, for example, reducing IPC cost using JNI.
- Add experimental with-Option for test(...)
- Add experimental support for poke and peek operations on clocks
- Update usage of Chisel and FIRRTL APIs, including Stage / Phase
- Bump sbt to 1.2.8
- Improved documentation
190311
Snapshot pushed to sonatype
- Add RawTester to allow top-level test instantiation and execution outside a ScalaTest environment, eg for use in the jupyter notebook
- Properly clean up things when tests fails, with a finally block on exceptions
- Remaining threads should be killed without causing exceptions
- Fix VCDs not dumping on test failure
- Add implicit clock resolution stubs into master, which will exception out when invoked, but allow code dependent on it to compile
- Fix false combinational paths across BlackBoxes (which broke rocket AsyncQueue), with new treadle API
- Fix .withClock deprecations by deleting experimental imports
190218
Snapshot pushed to sonatype
- Blocking regions removed, and threads may not change regions (thread region is set on spawn)
- Introduce a
.joinAndStep(clk)construct on threads, to allow joining on threads in a later region while making the time advance explicit - Most DecoupledDriver operations happen in the Monitor region
Note: the AsyncReset fixes are not included with this release since they depend on a treadle change that has not been pushed to sonatype
190207
Snapshot pushed to sonatype.
Major changes:
- Implement regions (beta - semantics subject to change), and DecoupledDriver enqueue/dequeue operations refactored to use regions so they can operate on a passthrough Decoupled interface from different threads.
- Add default timeout of 1000 clock cycles of inactivity (meaning, pokes that aren't no-ops) on the main clock. Can be overridden with eg
c.clock.setTimeout(numCcyles). - Added the async reset reg Treadle greybox model to chisel3.tester.experimental. See the AsyncResetReg tests for an usage example. Should be compatible with the rocket-chip AsyncResetReg. Note: this will be deprecated and/ore removed once we have native async support in Chisel.
- Should fix binary compatibility with recent Chisel snapshots.
- Bugfix: maintain thread ordering through joins.
New features for library builders:
- Add setVar/getVar to access a per-test global mutable map.
- Add ClockResolutionUtils, which use setVar/getVar to tag a implicit clock on a wire. This provides the manual way of doing for implicit clock resolution, which is a feature that's still in development. Check out the DecoupledDriver implementation for an example.
181206
Snapshot pushed to sonatype.
Major changes:
- VCD dumping disabled by default, but can be passed in from the command line, eg in sbt:
testOnly chisel3.tests.BasicTest -- -DwriteVcd=1(for large designs, VCD dumping would cause significant performance degradation) - Folder names in test_run_dir are now taken from the ScalaTest names
- Poking outputs will error