From 3c31faef7b96eedd502a28b16891c58ec709d114 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 23 May 2024 12:50:20 -0700 Subject: [PATCH] Add GCD IOBinders examples --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + .../chipyard/src/main/scala/iobinders/IOBinders.scala | 9 +++++++++ generators/chipyard/src/main/scala/iobinders/Ports.scala | 2 ++ 3 files changed, 12 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 77a998e699..11d70982c5 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -59,6 +59,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithNICIOPunchthrough ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithUARTTSIPunchthrough ++ + new chipyard.iobinders.WithGCDBusyPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index e00f43a4ac..61f347443c 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -39,6 +39,7 @@ import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig} import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule} +import chipyard.example.{CanHavePeripheryGCD} import scala.reflect.{ClassTag} @@ -540,3 +541,11 @@ class WithNMITiedOff extends ComposeIOBinder({ (Nil, Nil) } }) + +class WithGCDBusyPunchthrough extends OverrideIOBinder({ + (system: CanHavePeripheryGCD) => system.gcd_busy.map { busy => + val io_gcd_busy = IO(Output(Bool())) + io_gcd_busy := busy + (Seq(GCDBusyPort(() => io_gcd_busy)), Nil) + }.getOrElse((Nil, Nil)) +}) diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala index a9ea0a2d45..dfe9c58fa1 100644 --- a/generators/chipyard/src/main/scala/iobinders/Ports.scala +++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala @@ -109,3 +109,5 @@ case class JTAGResetPort (val getIO: () => Reset) case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle]) extends Port[HeterogeneousBag[TLBundle]] +case class GCDBusyPort (val getIO: () => Bool) + extends Port[Bool]