From 2507ac9d87bc20651d74b3615bd4a188b02f88b5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 20 Dec 2024 16:03:57 -0800 Subject: [PATCH] Disable FPU model optimizations (temporarily) --- generators/firechip/chip/src/main/scala/FireSim.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/firechip/chip/src/main/scala/FireSim.scala b/generators/firechip/chip/src/main/scala/FireSim.scala index ff2169bf4..77ccfac2d 100644 --- a/generators/firechip/chip/src/main/scala/FireSim.scala +++ b/generators/firechip/chip/src/main/scala/FireSim.scala @@ -125,7 +125,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) - r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) + // TODO: currently, fpu mem. model optimizations are broken with model multi-threading so disable for now + //r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) } case b: BoomTile => { val core = b.module.core