From afff9c4243371af924904b02a0b8ead4b19da956 Mon Sep 17 00:00:00 2001 From: joonho hwangbo Date: Wed, 15 May 2024 23:56:06 -0700 Subject: [PATCH 01/29] Misc configs | rocketchip bump (#1877) * Misc configs | rocketchip bump * Add NoTraceIOBridge * Nit * Remove useless configs * FireSim NoC config --- .../src/main/scala/config/NoCConfigs.scala | 23 +++++++++++++++++++ .../src/main/scala/config/RocketConfigs.scala | 4 ++++ .../src/main/scala/TargetConfigs.scala | 8 ++++++- generators/rocket-chip | 2 +- 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index a5acc1e0a6..ac24d85c56 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -267,3 +267,26 @@ class SbusMeshNoCConfig extends Config( new chipyard.config.AbstractConfig ) +class QuadRocketSbusRingNoCConfig extends Config( + new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( + constellation.protocol.DiplomaticNetworkNodeMapping( + inNodeMapping = ListMap( + "Core 0 " -> 0, + "Core 1 " -> 1, + "Core 2 " -> 2, + "Core 3 " -> 3, + "serial_tl" -> 4), + outNodeMapping = ListMap( + "system[0]" -> 5, + "system[1]" -> 6, + "system[2]" -> 7, + "system[3]" -> 8, + "pbus" -> 4)), // TSI is on the pbus, so serial-tl and pbus should be on the same node + nocParams = NoCParams( + topology = UnidirectionalTorus1D(9), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), + routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2)) + )) ++ + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ + new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index d3f2158436..680129a385 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -12,6 +12,10 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) +class DualRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ + new chipyard.config.AbstractConfig) + class TinyRocketConfig extends Config( new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports new testchipip.soc.WithNoScratchpads ++ // All memory is the Rocket TCMs diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 8533d80bd0..42f0b1d84d 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -371,10 +371,16 @@ class FireSimLargeBoomCospikeConfig extends Config( new WithFireSimConfigTweaks++ new chipyard.LargeBoomV3Config) +class FireSimQuadRocketSbusRingNoCConfig extends Config( + new chipyard.config.WithNoTraceIO ++ + new WithDefaultFireSimBridges ++ + new WithFireSimConfigTweaks++ + new chipyard.QuadRocketSbusRingNoCConfig) + class FireSimLargeBoomSV39CospikeConfig extends Config( new firesim.firesim.WithCospikeBridge ++ new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks++ new chipyard.config.WithSV39 ++ - new chipyard.LargeBoomV3Config) + new chipyard.LargeBoomV3Config) \ No newline at end of file diff --git a/generators/rocket-chip b/generators/rocket-chip index c10ce93fd1..e79ecc100b 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit c10ce93fd1a4187599ea926603e8ce10d04f77d7 +Subproject commit e79ecc100b5d20cc32ce426d0d7440bbfaf29e61 From c60d0475b64f7fa6822dd5b476572c4afa5ce7f6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:46:06 -0700 Subject: [PATCH 02/29] remove redundant CLASSPATH_TARGETS (this is always the same as CLASSPATH) --- common.mk | 10 +++++----- variables.mk | 3 --- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/common.mk b/common.mk index a0f3e6ac26..8aa41ca7c1 100644 --- a/common.mk +++ b/common.mk @@ -119,13 +119,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) +$(CHIPYARD_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) $(CHECK_SUBMODULES_COMMAND) mkdir -p $(dir $@) $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS) +$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -133,7 +133,7 @@ $(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) # verilog generation pipeline ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile -$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS) +$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) (set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ @@ -242,12 +242,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs TOP_MACROCOMPILER_MODE ?= --mode synflops -$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF) +$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(TOP_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) MODEL_MACROCOMPILER_MODE = --mode synflops -$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) +$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(MODEL_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) diff --git a/variables.mk b/variables.mk index 58cc85c4cd..e58e7f73a3 100644 --- a/variables.mk +++ b/variables.mk @@ -162,9 +162,6 @@ endif CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar -# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix) -CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH)) -TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH)) # chisel generated outputs FIRRTL_FILE ?= $(build_dir)/$(long_name).fir From 9737d62635bd24208d3049f56b8a3b5946b76531 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:50:36 -0700 Subject: [PATCH 03/29] Add comments on what CHIPYARD_CLASSPATH and TAPEOUT_CLASSPATH contain --- variables.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index e58e7f73a3..9c7d159a69 100644 --- a/variables.mk +++ b/variables.mk @@ -160,7 +160,9 @@ endif # classpaths CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache -CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar +# The chipyard classpath must contain the Generator main +CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar +# The tapeout classpath must contain MacroCompiler TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar # chisel generated outputs From 0c3ede15af603c2e6a6e5e3a777a206a6cc04546 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:51:40 -0700 Subject: [PATCH 04/29] Rename CHIPYARD_CLASSPATH to GENERATOR_CLASSPATH This name better reflects that this classpath must contain a Generator main, but does not have to necessarily be the chipyard project in build.sbt --- common.mk | 10 +++++----- variables.mk | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/common.mk b/common.mk index 8aa41ca7c1..04d1374e2a 100644 --- a/common.mk +++ b/common.mk @@ -119,13 +119,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) +$(GENERATOR_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) $(CHECK_SUBMODULES_COMMAND) mkdir -p $(dir $@) - $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) + $(call run_sbt_assembly,$(SBT_PROJECT),$(GENERATOR_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH) +$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(GENERATOR_CLASSPATH) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -133,9 +133,9 @@ $(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEO # verilog generation pipeline ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile -$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH) $(EXTRA_GENERATOR_REQS) +$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(GENERATOR_CLASSPATH) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) - (set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ + (set -o pipefail && $(call run_jar_scala_main,$(GENERATOR_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ --name $(long_name) \ --top-module $(MODEL_PACKAGE).$(MODEL) \ diff --git a/variables.mk b/variables.mk index 9c7d159a69..8fadc08469 100644 --- a/variables.mk +++ b/variables.mk @@ -160,8 +160,8 @@ endif # classpaths CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache -# The chipyard classpath must contain the Generator main -CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar +# The generator classpath must contain the Generator main +GENERATOR_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar # The tapeout classpath must contain MacroCompiler TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar From 3cf3d815dc6a88113637be022e3aa0fda3a14763 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:53:48 -0700 Subject: [PATCH 05/29] Rename fpga_platforms to chipyard_fpga --- build.sbt | 2 +- docs/Prototyping/General.rst | 2 +- fpga/Makefile | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/build.sbt b/build.sbt index dd245a6f2a..fb38ee68bf 100644 --- a/build.sbt +++ b/build.sbt @@ -324,6 +324,6 @@ lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val fpga_platforms = (project in file("./fpga")) +lazy val chipyard_fpga = (project in file("./fpga")) .dependsOn(chipyard, fpga_shells) .settings(commonSettings) diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index 051cbcf8fd..17ef417362 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -30,7 +30,7 @@ For example: # converts to - make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream + make SBT_PROJECT=chipyard_fpga MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. diff --git a/fpga/Makefile b/fpga/Makefile index ebf55a9776..22f7ce18cc 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -17,7 +17,7 @@ sim_name := none SUB_PROJECT ?= vcu118 ifeq ($(SUB_PROJECT),vc707) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= VC707FPGATestHarness VLOG_MODEL ?= VC707FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vc707 @@ -31,7 +31,7 @@ ifeq ($(SUB_PROJECT),vc707) endif ifeq ($(SUB_PROJECT),vcu118) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= VCU118FPGATestHarness VLOG_MODEL ?= VCU118FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vcu118 @@ -45,7 +45,7 @@ ifeq ($(SUB_PROJECT),vcu118) endif ifeq ($(SUB_PROJECT),nexysvideo) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= NexysVideoHarness VLOG_MODEL ?= NexysVideoHarness MODEL_PACKAGE ?= chipyard.fpga.nexysvideo @@ -60,7 +60,7 @@ endif ifeq ($(SUB_PROJECT),arty35t) # TODO: Fix with Arty - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= Arty35THarness VLOG_MODEL ?= Arty35THarness MODEL_PACKAGE ?= chipyard.fpga.arty @@ -74,7 +74,7 @@ ifeq ($(SUB_PROJECT),arty35t) endif ifeq ($(SUB_PROJECT),arty100t) # TODO: Fix with Arty - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= Arty100THarness VLOG_MODEL ?= Arty100THarness MODEL_PACKAGE ?= chipyard.fpga.arty100t From 2f2cde8748d1dbc38dcfc5c76dd93435571a3f06 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 17 May 2024 12:13:44 -0700 Subject: [PATCH 06/29] Bump rocket-chip --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index e79ecc100b..a235684242 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit e79ecc100b5d20cc32ce426d0d7440bbfaf29e61 +Subproject commit a2356842423c884863140745f686ec81d3544d07 From 5c57d8733bbd8eb437c3d41d876294e2db7cce35 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 17 May 2024 12:47:17 -0700 Subject: [PATCH 07/29] Bump shuttle/boom --- generators/boom | 2 +- generators/shuttle | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 506c11c99c..41c8fc9bdf 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 506c11c99ca9f6015d14fdc02c45c1e22983d06f +Subproject commit 41c8fc9bdfe68d0e30295cbaf764f2e69c36dbb8 diff --git a/generators/shuttle b/generators/shuttle index b75fada257..4792a1aba4 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit b75fada257c576de5c9968dbbf5a09302b53b1de +Subproject commit 4792a1aba4e9f2d70e6f84587913f78c9e4c0340 From 3a6677bc3012f47e94b8914ebab6e789c9e949e3 Mon Sep 17 00:00:00 2001 From: Nayiri <38256927+nayiri-k@users.noreply.github.com> Date: Sun, 19 May 2024 17:54:47 -0700 Subject: [PATCH 08/29] Fix clock name and macro paths for Sky130 VLSI flow (#1882) --- vlsi/example-asap7.yml | 2 +- vlsi/example-design.yml | 2 +- vlsi/example-designs/sky130-commercial.yml | 2 +- .../sky130-openroad-rockettile.yml | 5 ++-- vlsi/example-designs/sky130-openroad.yml | 23 ++++++------------- vlsi/example-designs/sky130-rocket.yml | 2 +- vlsi/example-sky130.yml | 12 +++++----- 7 files changed, 20 insertions(+), 28 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 6fc819aadd..ab0d6c8e6d 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_uncore", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index 3f46a4438e..80f338a9e9 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_uncore", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml index fb1f8407fb..1ec4a08ffe 100644 --- a/vlsi/example-designs/sky130-commercial.yml +++ b/vlsi/example-designs/sky130-commercial.yml @@ -2,7 +2,7 @@ # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"} + {name: "clock_uncore", period: "30ns", uncertainty: "2ns"} ] # Placement Constraints diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index 4a6b664cda..cfc4c5bb52 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore" vlsi.inputs.clocks: [ {name: "clock", period: "30ns", uncertainty: "3ns"} ] @@ -22,7 +22,7 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # data cache + # data cache - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 @@ -47,3 +47,4 @@ vlsi.inputs.placement_constraints: x: 50 y: 2100 orientation: r90 + diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index 3b95d9823c..a686fbba4f 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -3,7 +3,7 @@ # Specify clock signals # Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"} + {name: "clock_uncore", period: "50ns", uncertainty: "2ns"} ] # Flow parameters that yield a routable design with reasonable timing @@ -54,36 +54,27 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + # data cache + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 y: 50 orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro x: 50 - y: 450 - orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 850 - orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 1250 + y: 800 orientation: r90 # tag array - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro x: 50 y: 1600 orientation: r90 # instruction cache - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 y: 2100 diff --git a/vlsi/example-designs/sky130-rocket.yml b/vlsi/example-designs/sky130-rocket.yml index 2e7c7a5bb4..7e95e331ed 100644 --- a/vlsi/example-designs/sky130-rocket.yml +++ b/vlsi/example-designs/sky130-rocket.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore" vlsi.inputs.clocks: [ {name: "clock", period: "5ns", uncertainty: "1ns"} ] diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 1e3faf1c5a..3f45bd3d26 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"} + {name: "clock_uncore", period: "20ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow @@ -42,27 +42,27 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # data cache - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + # data cache + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 y: 50 orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro x: 50 y: 800 orientation: r90 # tag array - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro x: 50 y: 1600 orientation: r90 # instruction cache - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 y: 2100 From 16bc0531e9ca3af5001b1e2fc8fa857aeb9aeac1 Mon Sep 17 00:00:00 2001 From: bartender Date: Mon, 20 May 2024 01:29:10 +0000 Subject: [PATCH 09/29] [cd] Bump CIRCT from firtool-1.66.0 to firtool-1.75.0 This is an automated commit generated by the `circt/update-circt` GitHub Action. (cherry picked from commit 0a4a055f375bec7620ab38e2704261d73385cfd7) --- conda-reqs/circt.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conda-reqs/circt.json b/conda-reqs/circt.json index 1eb54a4391..020fe373a3 100644 --- a/conda-reqs/circt.json +++ b/conda-reqs/circt.json @@ -1,3 +1,3 @@ { - "version": "firtool-1.66.0" + "version": "firtool-1.75.0" } From 3c31faef7b96eedd502a28b16891c58ec709d114 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 23 May 2024 12:50:20 -0700 Subject: [PATCH 10/29] Add GCD IOBinders examples --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + .../chipyard/src/main/scala/iobinders/IOBinders.scala | 9 +++++++++ generators/chipyard/src/main/scala/iobinders/Ports.scala | 2 ++ 3 files changed, 12 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 77a998e699..11d70982c5 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -59,6 +59,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithNICIOPunchthrough ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithUARTTSIPunchthrough ++ + new chipyard.iobinders.WithGCDBusyPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index e00f43a4ac..61f347443c 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -39,6 +39,7 @@ import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig} import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule} +import chipyard.example.{CanHavePeripheryGCD} import scala.reflect.{ClassTag} @@ -540,3 +541,11 @@ class WithNMITiedOff extends ComposeIOBinder({ (Nil, Nil) } }) + +class WithGCDBusyPunchthrough extends OverrideIOBinder({ + (system: CanHavePeripheryGCD) => system.gcd_busy.map { busy => + val io_gcd_busy = IO(Output(Bool())) + io_gcd_busy := busy + (Seq(GCDBusyPort(() => io_gcd_busy)), Nil) + }.getOrElse((Nil, Nil)) +}) diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala index a9ea0a2d45..dfe9c58fa1 100644 --- a/generators/chipyard/src/main/scala/iobinders/Ports.scala +++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala @@ -109,3 +109,5 @@ case class JTAGResetPort (val getIO: () => Reset) case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle]) extends Port[HeterogeneousBag[TLBundle]] +case class GCDBusyPort (val getIO: () => Bool) + extends Port[Bool] From 9a5673ddef7e5dd925a3a0d352553b85f1e973c9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 5 May 2023 11:26:27 -0700 Subject: [PATCH 11/29] Add singleclock broadcast clockbinder --- .../main/scala/clocking/ClockBinders.scala | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index d075fcbbea..3582ba08d6 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -102,6 +102,42 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ } }) +// Broadcasts a single clock IO to all clock domains +class WithSingleClockBroadcastClockGenerator extends OverrideLazyIOBinder({ + (system: HasChipyardPRCI) => { + implicit val p = GetSystemParameters(system) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + InModuleBody { + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + } + + val clockGroupsAggregateNode = ClockGroupAggregateNode("single_clock") + val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + system.allClockGroupsNode :*= clockGroupsAggregateNode := clockGroupsSourceNode + + InModuleBody { + val clock_wire = Wire(Input(new ClockWithFreq(100))) + val reset_wire = Wire(Input(AsyncReset())) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) + val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) + + clockGroupsSourceNode.out.foreach { case (bundle, edge) => + bundle.member.data.foreach { b => + b.clock := clock_io.clock + b.reset := reset_io + } + } + (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) + } + } +}) + class WithClockTapIOCells extends OverrideIOBinder({ (system: CanHaveClockTap) => { system.clockTapIO.map { tap => From 17f784bfd331cc7335dae49e5b26054342a1c252 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 28 May 2024 12:26:18 -0700 Subject: [PATCH 12/29] Add example clocking configs and SingleClockBroadcast option --- .../main/scala/clocking/ClockBinders.scala | 26 +++++--------- .../main/scala/config/ClockingConfigs.scala | 34 +++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) create mode 100644 generators/chipyard/src/main/scala/config/ClockingConfigs.scala diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 3582ba08d6..bcf2fb4907 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -72,7 +72,7 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr } } }) - + // This passes all clocks through to the TestHarness class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { @@ -102,38 +102,28 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ } }) -// Broadcasts a single clock IO to all clock domains -class WithSingleClockBroadcastClockGenerator extends OverrideLazyIOBinder({ +// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies +class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } - val clockGroupsAggregateNode = ClockGroupAggregateNode("single_clock") + val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock")) val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - system.allClockGroupsNode :*= clockGroupsAggregateNode := clockGroupsSourceNode + system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode InModuleBody { - val clock_wire = Wire(Input(new ClockWithFreq(100))) + val clock_wire = Wire(Input(Clock())) val reset_wire = Wire(Input(AsyncReset())) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) clockGroupsSourceNode.out.foreach { case (bundle, edge) => bundle.member.data.foreach { b => - b.clock := clock_io.clock + b.clock := clock_io b.reset := reset_io } } - (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) + (Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell) } } }) diff --git a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala new file mode 100644 index 0000000000..0d3197ea65 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala @@ -0,0 +1,34 @@ +package chipyard + +import org.chipsalliance.cde.config.{Config} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem.{MBUS, SBUS} +import testchipip.soc.{OBUS} + +//================================================== +// This file contains examples of the different ways +// clocks can be generated for chiypard designs +//================================================== + +// The default constructs IOs for all requested clocks in the chiptopClockGroupsNode +// Note: This is what designs inheriting from AbstractConfig do by default +class DefaultClockingRocketConfig extends Config( + new chipyard.clocking.WithPassthroughClockGenerator ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// This is a more physically realistic approach, normally we can't punch out a separate +// pin for each clock domain. The standard "test chip" approach is to punch a few slow clock +// inputs, integrate a PLL, and generate an array of selectors/dividers to configure the +// clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info +class ChipLikeClockingRocketConfig extends Config( + new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single +// clock input pin. +class SingleClockBroadcastRocketConfig extends Config( + new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) From 385c055ef78df44a61812149942af5f2d233704d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Feb 2024 16:20:10 -0800 Subject: [PATCH 13/29] Add rerocc submodule --- .gitmodules | 4 +++- generators/rerocc | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) create mode 160000 generators/rerocc diff --git a/.gitmodules b/.gitmodules index cc56bc35f5..c24ded763c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -142,4 +142,6 @@ [submodule "tools/midas-targetutils"] path = tools/midas-targetutils url = https://github.com/firesim/midas-targetutils.git - +[submodule "generators/rerocc"] + path = generators/rerocc + url = https://github.com/ucb-bar/rerocc.git diff --git a/generators/rerocc b/generators/rerocc new file mode 160000 index 0000000000..78a29b0f88 --- /dev/null +++ b/generators/rerocc @@ -0,0 +1 @@ +Subproject commit 78a29b0f885deef1a99fb071dd6feeb7b65702b9 From e8eeaad36d71666b2a95365319956f6079134433 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Feb 2024 16:20:46 -0800 Subject: [PATCH 14/29] Add rerocc to check-commit CI --- .github/scripts/check-commit.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 570a6ee599..1b859414f8 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,8 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy") + +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc") dir="generators" branches=("master" "main" "dev") search From fdb47267704d4022ef2a14763ccd2cbf6d71cdf8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Feb 2024 16:21:34 -0800 Subject: [PATCH 15/29] Add rerocc to build.sbt --- build.sbt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index f240389fd8..4bb7c4c6b1 100644 --- a/build.sbt +++ b/build.sbt @@ -173,7 +173,7 @@ lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache, dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress, barf, shuttle, caliptra_aes) + constellation, mempress, barf, shuttle, caliptra_aes, rerocc) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -253,6 +253,11 @@ lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +lazy val rerocc = (project in file("generators/rerocc")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) From 13dda467644e6baeb3d20f98005d93be5b7b62fb Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 5 Feb 2024 11:11:59 -0800 Subject: [PATCH 16/29] Integrate rerocc --- build.sbt | 2 +- .../chipyard/src/main/scala/DigitalTop.scala | 1 + .../scala/config/RoCCAcceleratorConfigs.scala | 19 +++++++++++++++++++ .../config/fragments/RoCCFragments.scala | 14 ++++++++++++++ generators/rerocc | 2 +- 5 files changed, 36 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 4bb7c4c6b1..36bf77420f 100644 --- a/build.sbt +++ b/build.sbt @@ -254,7 +254,7 @@ lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc")) .settings(commonSettings) lazy val rerocc = (project in file("generators/rerocc")) - .dependsOn(rocketchip) + .dependsOn(rocketchip, constellation, boom) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index e0f6939266..c4fa17aafa 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -39,6 +39,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect + with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators { override lazy val module = new DigitalTopModule(this) } diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 184afaa75f..91ee7c15ce 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -48,3 +48,22 @@ class AES256ECBRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.WithSystemBusWidth(256) ++ new chipyard.config.AbstractConfig) + +class ReRoCCTestConfig extends Config( + new rerocc.WithReRoCC ++ + new chipyard.config.WithCharacterCountRoCC ++ // rerocc tile4 is charcnt + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile3 is accum + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile2 is accum + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile1 is accum + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile0 is accum + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +class ReRoCCManyGemminiConfig extends Config( + new rerocc.WithReRoCC ++ + new gemmini.LeanGemminiConfig ++ // rerocc tile3 is gemmini + new gemmini.LeanGemminiConfig ++ // rerocc tile2 is gemmini + new gemmini.LeanGemminiConfig ++ // rerocc tile1 is gemmini + new gemmini.LeanGemminiConfig ++ // rerocc tile0 is gemmini + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // 4 rocket cores + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index 5ef76b7567..c29b05d381 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -43,3 +43,17 @@ class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( })) } }) + +class WithAccumulatorRoCC(op: OpcodeSet = OpcodeSet.custom1) extends Config((site, here, up) => { + case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => { + val accumulator = LazyModule(new AccumulatorExample(op, n = 4)(p)) + accumulator + }) +}) + +class WithCharacterCountRoCC(op: OpcodeSet = OpcodeSet.custom2) extends Config((site, here, up) => { + case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => { + val counter = LazyModule(new CharacterCountExample(op)(p)) + counter + }) +}) diff --git a/generators/rerocc b/generators/rerocc index 78a29b0f88..61751c3c23 160000 --- a/generators/rerocc +++ b/generators/rerocc @@ -1 +1 @@ -Subproject commit 78a29b0f885deef1a99fb071dd6feeb7b65702b9 +Subproject commit 61751c3c23f6f7435cc264d32757956351cdb72a From 4f1dd4e1952a8976a38f833bd3552bca11673a61 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 5 Feb 2024 11:15:22 -0800 Subject: [PATCH 17/29] Add rerocc to tests --- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 4 ++++ .github/workflows/chipyard-run-tests.yml | 24 ++++++++++++++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 124bdd3f84..d76d7a32ec 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" -grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb" +grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters" @@ -72,6 +72,7 @@ mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig" mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig" mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog" mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig" +mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig" mapping["constellation"]=" SUB_PROJECT=constellation" mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 31fea5d6c5..90fe0687a3 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -127,6 +127,10 @@ case $1 in make -C $LOCAL_CHIPYARD_DIR/tests run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 ;; + chipyard-rerocc) + make -C $LOCAL_CHIPYARD_DIR/generators/rerocc/tests + run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/rerocc/tests/rerocc.riscv LOADMEM=1 + ;; tracegen) run_tracegen ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 0b6448885f..24654306a6 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -777,6 +777,29 @@ jobs: group-key: "group-peripherals" project-key: "chipyard-llcchiplet" + chipyard-rerocc-run-tests: + name: chipyard-rerocc-run-tests + needs: prepare-chipyard-accels + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-accels" + project-key: "chipyard-rerocc" + chipyard-gemmini-run-tests: name: chipyard-gemmini-run-tests needs: prepare-chipyard-accels @@ -1143,6 +1166,7 @@ jobs: chipyard-tethered-run-tests, chipyard-symmetric-run-tests, chipyard-llcchiplet-run-tests, + chipyard-rerocc-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-prefetchers-run-tests, From e50adecd31bb797ad43e13ceff042dafd6bf02ee Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 May 2024 16:21:31 -0700 Subject: [PATCH 18/29] Bump rerocc --- generators/rerocc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rerocc b/generators/rerocc index 61751c3c23..a22dce622d 160000 --- a/generators/rerocc +++ b/generators/rerocc @@ -1 +1 @@ -Subproject commit 61751c3c23f6f7435cc264d32757956351cdb72a +Subproject commit a22dce622db350e4a159ed90cf83d00782ed8187 From 2d2abed586b27874ba425e8eaffd47a7e579fd60 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 May 2024 13:38:00 -0700 Subject: [PATCH 19/29] Name all the generated ClockDomains --- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 3 ++- generators/rocket-chip | 2 +- generators/rocket-chip-blocks | 2 +- generators/testchipip | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 9b140e2084..d4b36b5053 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -37,7 +37,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) - val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain") + val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") + .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar diff --git a/generators/rocket-chip b/generators/rocket-chip index a235684242..3cec0f0dee 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit a2356842423c884863140745f686ec81d3544d07 +Subproject commit 3cec0f0dee432d6bb2da5ce6aa1142474807ff86 diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index 2fc961f356..c667be9bb3 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit 2fc961f356b1104a34567adeefa9e3666940643f +Subproject commit c667be9bb32f25e52516e71cd1ded58290ac5993 diff --git a/generators/testchipip b/generators/testchipip index 104df6a81f..7a30dc737d 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 104df6a81fd989cd4cad69b699894664fcf93c05 +Subproject commit 7a30dc737d0d93e1e1926d56f7361d4b70ff5fe7 From 28b157c21621013a1631e70ed78acd0631a2067d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Jun 2024 17:41:44 -0700 Subject: [PATCH 20/29] Remove firesim build.sbt from our SBT dependencies We don't depend on firesim's build.sbt anymore --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index e1120061ac..ce4ee2af91 100644 --- a/common.mk +++ b/common.mk @@ -93,7 +93,7 @@ TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout) TAPEOUT_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(SCALA_EXT)) TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(VLOG_EXT)) # This assumes no SBT meta-build sources -SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) +SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### From e1f37c0d3fb72cf927e86d0a06b00466f151a1d5 Mon Sep 17 00:00:00 2001 From: Brandon Michael Whitchurch Date: Tue, 11 Jun 2024 11:32:56 -0700 Subject: [PATCH 21/29] add upper bound for python version to avoid incompatible packages --- conda-reqs/chipyard-extended.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conda-reqs/chipyard-extended.yaml b/conda-reqs/chipyard-extended.yaml index a1e87d4b3a..cf0b43202a 100644 --- a/conda-reqs/chipyard-extended.yaml +++ b/conda-reqs/chipyard-extended.yaml @@ -30,7 +30,7 @@ dependencies: - bison - flex - expat - - python>=3.9 + - python>=3.9,<3.11 - bc - unzip - patch From 4fdc224c48177eed913379f8d98eaabfee7d7faa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 11:11:27 -0700 Subject: [PATCH 22/29] Fix uniquify script for new firtool --- common.mk | 1 + scripts/uniquify-module-names.py | 8 +++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index e1120061ac..7f1b9669c4 100644 --- a/common.mk +++ b/common.mk @@ -218,6 +218,7 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ --top-hier-json $(MFC_TOP_HRCHY_JSON) \ --in-all-filelist $(MFC_FILELIST) \ + --in-bb-filelist $(MFC_BB_MODS_FILELIST) \ --dut $(TOP) \ --model $(MODEL) \ --target-dir $(GEN_COLLATERAL_DIR) \ diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index d2131c33e2..5c6a9613fb 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -11,6 +11,7 @@ parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument("--top-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') +parser.add_argument('--in-bb-filelist', type=str, required=True, help='Path to input blackbox filelist') parser.add_argument("--dut", type=str, required=True, help="Name of the DUT module.") parser.add_argument("--model", type=str, required=True, help="Name of the Model module.") parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') @@ -57,8 +58,8 @@ def get_modules_in_verilog_file(file): module_names.append(words[1].replace("(", "").replace(")", "").replace(";", "")) return module_names -def get_modules_in_filelist(verilog_module_filename, cc_filelist): - with open(args.in_all_filelist) as fl: +def get_modules_in_filelist(filelist, verilog_module_filename, cc_filelist): + with open(filelist) as fl: lines = fl.readlines() for line in lines: path = line.strip() @@ -186,7 +187,8 @@ def uniquify_modules_under_model(modules_under_model, common_modules, verilog_mo def main(): verilog_module_filename = dict() cc_filelist = list() - get_modules_in_filelist(verilog_module_filename, cc_filelist) + get_modules_in_filelist(args.in_all_filelist, verilog_module_filename, cc_filelist) + get_modules_in_filelist(args.in_bb_filelist , verilog_module_filename, cc_filelist) modules_under_model = get_modules_under_hier(args.model_hier_json, args.dut) modules_under_top = get_modules_under_hier(args.top_hier_json) From a15fb7ff3d240f4a723ec8be1a9feda5659e9bc9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 11:36:55 -0700 Subject: [PATCH 23/29] Remove unused thin-client stuff --- common.mk | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/common.mk b/common.mk index ce4ee2af91..431238d706 100644 --- a/common.mk +++ b/common.mk @@ -96,16 +96,6 @@ TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties -######################################################################################### -# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change) -######################################################################################### -$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) -ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) - cd $(base_dir) && $(SBT) "reload" - touch $@ -else - cd $(base_dir) && $(SBT) "exit" -endif ######################################################################################### # copy over bootrom files From dcb3d24b08a3ef83b4e8ae3d95c1936cb30650a0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 11:37:13 -0700 Subject: [PATCH 24/29] Log CIRCT output into a log file --- common.mk | 7 ++++--- variables.mk | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index 431238d706..fdb2bde2b5 100644 --- a/common.mk +++ b/common.mk @@ -169,7 +169,8 @@ SFC_MFC_TARGETS = \ $(MFC_MODEL_SMEMS_JSON) \ $(MFC_FILELIST) \ $(MFC_BB_MODS_FILELIST) \ - $(GEN_COLLATERAL_DIR) + $(GEN_COLLATERAL_DIR) \ + $(FIRTOOL_LOG_FILE) MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket @@ -184,7 +185,7 @@ endif $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) rm -rf $(GEN_COLLATERAL_DIR) - firtool \ + (set -o pipefail && firtool \ --format=fir \ --export-module-hierarchy \ --verify-each=true \ @@ -198,7 +199,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) --annotation-file=$(FINAL_ANNO_FILE) \ --split-verilog \ -o $(GEN_COLLATERAL_DIR) \ - $(FIRRTL_FILE) + $(FIRRTL_FILE) |& tee $(FIRTOOL_LOG_FILE)) $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it # DOC include end: FirrtlCompiler diff --git a/variables.mk b/variables.mk index ffb96d2f94..5dfee1968f 100644 --- a/variables.mk +++ b/variables.mk @@ -154,6 +154,7 @@ TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json CHISEL_LOG_FILE ?= $(build_dir)/$(long_name).chisel.log +FIRTOOL_LOG_FILE ?= $(build_dir)/$(long_name).firtool.log # chisel anno modification output MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json From eee405331baf9b035abcc7344ff754f0444c044b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 13:46:00 -0700 Subject: [PATCH 25/29] Bump CIRCT submodule --- tools/circt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/circt b/tools/circt index 9e0c1696f3..481cb60add 160000 --- a/tools/circt +++ b/tools/circt @@ -1 +1 @@ -Subproject commit 9e0c1696f3caef4059c65774ad6b8efee91d9d9e +Subproject commit 481cb60add7358934414a3c6b396f5d29ad934fe From 316c41ea522edffd189604e360a1a9535ac92769 Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 08:19:27 -0700 Subject: [PATCH 26/29] fixes for insert includes - avoid infinite loop condition - follow pep8 style guide - encapsulate some functionality to decrease visual nesting --- scripts/insert-includes.py | 174 +++++++++++++++++++++++-------------- 1 file changed, 107 insertions(+), 67 deletions(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index b939878aad..6c77bb5d13 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -1,80 +1,120 @@ #!/usr/bin/env python +""" +replaces a `include with the full include file. -# replaces a `include with the full include file. -# recursively replaces `include's until none are left -# -# args -# $1 - file to remove includes from -# $2 - file to write output to -# $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs) -# includes are found relative to this path -# this is equivalent to something like +incdir+ +args +$1 - file which has includes to be replaced +$2 - file in which output will be written +$3 - list of directories to search for includes + (note: NON-RECURSIVE must specify all dirs) + includes are found relative to this path + this is equivalent to something like +incdir+ +""" -import sys -import re import os -import tempfile +import re import shutil +import sys +import tempfile + + +def print_info(msg): + """ + Print an info message. + + Args: + msg (str): message to print + """ + print(f"[INFO] {msg}") + + +def print_error(msg, critical=True): + """ + Print an error message. + + Args: + msg (str): message to print + critical (bool): whether to exit after printing the message + """ + if critical: + sys.exit(f"[ERROR] {msg}") + else: + print(f"[ERROR] {msg}") + -inVlog = sys.argv[1] -outVlog = sys.argv[2] -print("[INFO] Replaces includes from: " + str(inVlog)) +def find_include(file_name, inc_dirs): + """ + Find the include file in the list of directories. -if inVlog == outVlog: - sys.exit("[ERROR] The input and output file cannot be the same.") + Args: + file_name (str): include file name + inc_dirs (list): list of directories to search for includes -# add directories to search list -incDirs = sys.argv[3:] -print("[INFO] Searching following dirs for includes: " + str(incDirs)) + Returns: + str: full path to the include file + """ + for d in inc_dirs: + inc_file_name = d + "/" + file_name + if os.path.exists(inc_file_name): + return inc_file_name + print_error(f"Include file {file_name} not found in {inc_dirs}") + return None -def process(inF, outF): - # open file - with open(inF, 'r') as inFile: - with open(outF, 'w') as outFile: - # for each include found, search through all dirs and replace if found, error if not - for num, line in enumerate(inFile, 1): + +def process(in_fname, out_fname, inc_dirs=None): + """ + Replace include directives in a file with the full include file. + + Args: + in_fname (str): input file name + out_fname (str): output file name + inc_dirs (list): list of directories to search for includes + """ + with open(in_fname, "r", encoding="utf-8") as in_file: + with open(out_fname, "w", encoding="utf-8") as out_file: + # for each include found, search through all dirs + # and replace if found, error if not + for num, line in enumerate(in_file, 1): match = re.match(r"^ *`include +\"(.*)\"", line) if match and match.group(1) != "uvm_macros.svh": - print("[INFO] Replacing includes for {}".format(match.group(1))) + print_info( + f"Replacing includes for {match.group(1)}" + f" at line {num}" + ) # search for include and replace - found = False - for d in incDirs: - potentialIncFileName = d + "/" + match.group(1) - if os.path.exists(potentialIncFileName): - found = True - print("[INFO] Found missing include in {}".format(potentialIncFileName)) - with open(potentialIncFileName, 'r') as incFile: - for iline in incFile: - outFile.write(iline) - break - - # must find something to include with - if not found: - sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num)) + inc_file_name = find_include(match.group(1), inc_dirs) + with open(inc_file_name, "r", encoding="utf-8") as inc_file: + out_file.writelines(inc_file) + else: - outFile.write(line) - -inF = inVlog - -while True: - # create a copy of the input - fd, temp_path = tempfile.mkstemp() - shutil.copy2(inF, temp_path) - - with open(temp_path, 'r') as inFile: - anyIncludes = False - for line in inFile: - match = re.match(r"^ *`include +\"(.*)\"", line) - if match: - anyIncludes = True - break - - if anyIncludes: - process(temp_path, outVlog) - inF = outVlog - os.remove(temp_path) - else: - os.remove(temp_path) - break - -print("[INFO] Success. Writing output to: " + str(outVlog)) + out_file.write(line) + + +def main(): + """ + Entry point for the script. + + Args: + + """ + in_vlog = sys.argv[1] + out_vlog = sys.argv[2] + + if in_vlog == out_vlog: + sys.exit("[ERROR] The input and output file cannot be the same.") + + # add directories to search list + inc_dirs = sys.argv[3:] + print("[INFO] Replaces includes from: " + str(in_vlog)) + print("[INFO] Searching following dirs for includes: " + str(inc_dirs)) + + # make a copy of the input file + _, temp_path = tempfile.mkstemp() + shutil.copy2(in_vlog, temp_path) + process(temp_path, out_vlog, inc_dirs) + + print("[INFO] Success. Output written to: " + str(out_vlog)) + + +if __name__ == "__main__": + main() From feeab6b93be81ba1665910df462a4ae8cb81edda Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 08:35:37 -0700 Subject: [PATCH 27/29] add check for duplicate include directives --- scripts/insert-includes.py | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index 6c77bb5d13..bcf39a6036 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -70,24 +70,29 @@ def process(in_fname, out_fname, inc_dirs=None): out_fname (str): output file name inc_dirs (list): list of directories to search for includes """ + replaced_includes = set() with open(in_fname, "r", encoding="utf-8") as in_file: with open(out_fname, "w", encoding="utf-8") as out_file: # for each include found, search through all dirs # and replace if found, error if not for num, line in enumerate(in_file, 1): match = re.match(r"^ *`include +\"(.*)\"", line) - if match and match.group(1) != "uvm_macros.svh": - print_info( - f"Replacing includes for {match.group(1)}" - f" at line {num}" - ) - # search for include and replace - inc_file_name = find_include(match.group(1), inc_dirs) - with open(inc_file_name, "r", encoding="utf-8") as inc_file: - out_file.writelines(inc_file) - - else: + if not match or match.group(1) == "uvm_macros.svh": + # copy the line as is out_file.write(line) + continue + if match.group(1) in replaced_includes: + print_info("Skipping duplicate include") + continue + + print_info( + f"Replacing includes for {match.group(1)}" f" at line {num}" + ) + # search for include and replace + inc_file_name = find_include(match.group(1), inc_dirs) + with open(inc_file_name, "r", encoding="utf-8") as inc_file: + out_file.writelines(inc_file) + replaced_includes.add(match.group(1)) def main(): From e4e49ef8985a76ffe2c13e0b451ba595a1d65d4a Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 09:13:05 -0700 Subject: [PATCH 28/29] use DFS to recursively search and expand includes in a single pass --- scripts/insert-includes.py | 54 ++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index bcf39a6036..d29847c27e 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -61,6 +61,36 @@ def find_include(file_name, inc_dirs): return None +def process_helper(in_fname, out_f, inc_dirs, replaced_includes): + """ + Helper function to DFS through include files and replace includes. + """ + print(f"DFS state: {replaced_includes}") + include_regex = re.compile(r"^ *`include +\"(.*)\"") + # slurp the input file. + # this avoids having a bunch of fds open during recursion + with open(in_fname, "r", encoding="utf-8") as in_file: + lines = in_file.readlines() + + for num, line in enumerate(lines, 1): + match = re.match(include_regex, line) + if not match or match.group(1) == "uvm_macros.svh": + # copy the line as is + out_f.write(line) + continue + if match.group(1) in replaced_includes: + print_info("Skipping duplicate include") + continue + + print_info( + f"Replacing includes for {match.group(1)}" f" at line {num}" + ) + # search for include and replace + inc_file_name = find_include(match.group(1), inc_dirs) + replaced_includes.add(match.group(1)) + process_helper(inc_file_name, out_f, inc_dirs, replaced_includes) + + def process(in_fname, out_fname, inc_dirs=None): """ Replace include directives in a file with the full include file. @@ -71,28 +101,8 @@ def process(in_fname, out_fname, inc_dirs=None): inc_dirs (list): list of directories to search for includes """ replaced_includes = set() - with open(in_fname, "r", encoding="utf-8") as in_file: - with open(out_fname, "w", encoding="utf-8") as out_file: - # for each include found, search through all dirs - # and replace if found, error if not - for num, line in enumerate(in_file, 1): - match = re.match(r"^ *`include +\"(.*)\"", line) - if not match or match.group(1) == "uvm_macros.svh": - # copy the line as is - out_file.write(line) - continue - if match.group(1) in replaced_includes: - print_info("Skipping duplicate include") - continue - - print_info( - f"Replacing includes for {match.group(1)}" f" at line {num}" - ) - # search for include and replace - inc_file_name = find_include(match.group(1), inc_dirs) - with open(inc_file_name, "r", encoding="utf-8") as inc_file: - out_file.writelines(inc_file) - replaced_includes.add(match.group(1)) + with open(out_fname, "w", encoding="utf-8") as out_file: + process_helper(in_fname, out_file, inc_dirs, replaced_includes) def main(): From ecd7c805a40b6aa42fcaf24b787cfbd11977b435 Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 09:18:44 -0700 Subject: [PATCH 29/29] remove debug print --- scripts/insert-includes.py | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index d29847c27e..22dd8e9d93 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -65,7 +65,6 @@ def process_helper(in_fname, out_f, inc_dirs, replaced_includes): """ Helper function to DFS through include files and replace includes. """ - print(f"DFS state: {replaced_includes}") include_regex = re.compile(r"^ *`include +\"(.*)\"") # slurp the input file. # this avoids having a bunch of fds open during recursion