From e78756704bcd2d2605bd845df6d37b41301a6dac Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Mon, 4 Dec 2023 18:14:50 -0800
Subject: [PATCH 01/31] FIX: fix vcu118 sd card frequency

---
 fpga/src/main/resources/vcu118/sdboot/sd.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c
index f1bdb61e2c..60bebbd8cb 100644
--- a/fpga/src/main/resources/vcu118/sdboot/sd.c
+++ b/fpga/src/main/resources/vcu118/sdboot/sd.c
@@ -22,7 +22,7 @@
 #error Must define TL_CLK
 #endif
 
-#define F_CLK TL_CLK
+#define F_CLK (TL_CLK)
 
 static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
 
@@ -79,7 +79,9 @@ static inline void sd_cmd_end(void)
 static void sd_poweron(void)
 {
 	long i;
-	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
+	// HACK: frequency change
+	// REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
+	REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2.5);
 	REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
 	for (i = 10; i > 0; i--) {
 		sd_dummy();
@@ -176,7 +178,9 @@ static int copy(void)
 
 	// TODO: Speed up SPI freq. (breaks between these two values)
 	//REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL);
-	REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
+	// HACK: frequency change
+	// REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
+	REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2); //  / 0.5
 	if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) {
 		sd_cmd_end();
 		return 1;

From 069a9d2999d53b26550387506097c38fc420c4a3 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Tue, 5 Dec 2023 15:07:25 -0800
Subject: [PATCH 02/31] ADD: add equation for setting certain SPI clock speed

---
 fpga/src/main/resources/vcu118/sdboot/sd.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c
index 60bebbd8cb..e8d45ba7b5 100644
--- a/fpga/src/main/resources/vcu118/sdboot/sd.c
+++ b/fpga/src/main/resources/vcu118/sdboot/sd.c
@@ -22,7 +22,14 @@
 #error Must define TL_CLK
 #endif
 
-#define F_CLK (TL_CLK)
+#define F_CLK 		(TL_CLK)
+
+// SPI SCLK frequency, in kHz
+#define SPI_CLK 	1250
+
+// SPI clock divisor value
+// @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi
+#define SPI_DIV 	(((F_CLK * 1000) / SPI_CLK) / 2 - 1)
 
 static volatile uint32_t * const spi = (void *)(SPI_CTRL_ADDR);
 
@@ -80,8 +87,8 @@ static void sd_poweron(void)
 {
 	long i;
 	// HACK: frequency change
-	// REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 300000UL);
-	REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2.5);
+
+	REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
 	REG32(spi, SPI_REG_CSMODE) = SPI_CSMODE_OFF;
 	for (i = 10; i > 0; i--) {
 		sd_dummy();
@@ -173,14 +180,10 @@ static int copy(void)
 
 	dputs("CMD18");
 
-	kprintf("LOADING 0x%xB PAYLOAD\r\n", PAYLOAD_SIZE_B);
+	kprintf("LOADING 0x%x B PAYLOAD\r\n", PAYLOAD_SIZE_B);
 	kprintf("LOADING  ");
 
-	// TODO: Speed up SPI freq. (breaks between these two values)
-	//REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 16666666UL);
-	// HACK: frequency change
-	// REG32(spi, SPI_REG_SCKDIV) = (F_CLK / 5000000UL);
-	REG32(spi, SPI_REG_SCKDIV) = (F_CLK * 2); //  / 0.5
+	REG32(spi, SPI_REG_SCKDIV) = SPI_DIV;
 	if (sd_cmd(0x52, BBL_PARTITION_START_SECTOR, 0xE1) != 0x00) {
 		sd_cmd_end();
 		return 1;

From e8f89d228ceb4e4c6311648a654157265898cf33 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 18 Dec 2023 09:31:42 -0800
Subject: [PATCH 03/31] Move CIRCT install to its own step in build-setup
 script

---
 scripts/build-setup.sh | 38 ++++++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 12 deletions(-)

diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh
index 9d79735a5e..d3a66ca6a0 100755
--- a/scripts/build-setup.sh
+++ b/scripts/build-setup.sh
@@ -29,7 +29,8 @@ usage() {
     echo "   7. FireSim pre-compile sources"
     echo "   8. FireMarshal"
     echo "   9. FireMarshal pre-compile default buildroot Linux sources"
-    echo "  10. Runs repository clean-up"
+    echo "  10. Install CIRCT"
+    echo "  11. Runs repository clean-up"
     echo ""
     echo "**See below for options to skip parts of the setup. Skipping parts of the setup is not guaranteed to be tested/working.**"
     echo ""
@@ -152,16 +153,6 @@ if run_step "1"; then
     conda activate $CYDIR/.conda-env
     exit_if_last_command_failed
 
-    # install circt into conda
-    git submodule update --init $CYDIR/tools/install-circt &&
-    $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
-        -f circt-full-shared-linux-x64.tar.gz \
-        -i $CONDA_PREFIX \
-        -v version-file \
-        -x $CYDIR/conda-reqs/circt.json \
-        -g null
-    exit_if_last_command_failed
-
     # Conda Setup
     # Provide a sourceable snippet that can be used in subshells that may not have
     # inhereted conda functions that would be brought in under a login shell that
@@ -273,8 +264,31 @@ if run_step "8"; then
     popd
 fi
 
-# do misc. cleanup for a "clean" git status
 if run_step "10"; then
+    # install circt into conda
+    if run_step "1"; then
+        PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE
+    else
+        if [ -z "$RISCV" ] ; then
+            error "ERROR: If conda initialization skipped, \$RISCV variable must be defined."
+            exit 1
+        fi
+        PREFIX=$RISCV
+    fi
+
+    git submodule update --init $CYDIR/tools/install-circt &&
+    $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
+        -f circt-full-shared-linux-x64.tar.gz \
+        -i $PREFIX \
+        -v version-file \
+        -x $CYDIR/conda-reqs/circt.json \
+        -g null
+    exit_if_last_command_failed
+fi
+
+
+# do misc. cleanup for a "clean" git status
+if run_step "11"; then
     begin_step "10" "Cleaning up repository"
     $CYDIR/scripts/repo-clean.sh
     exit_if_last_command_failed

From 733bd3e7eaadd071e6e0f9653ebcaf33ef725636 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 19 Dec 2023 12:03:50 -0800
Subject: [PATCH 04/31] Bump testchipip for more organized package

---
 generators/caliptra-aes-acc                   |  2 +-
 .../chipyard/src/main/scala/DigitalTop.scala  | 16 ++++++-------
 .../chipyard/src/main/scala/Subsystem.scala   |  2 +-
 .../main/scala/clocking/HasChipyardPRCI.scala |  3 ++-
 .../main/scala/clocking/TLClockDivider.scala  |  4 ++--
 .../main/scala/clocking/TLClockSelector.scala |  4 ++--
 .../main/scala/config/AbstractConfig.scala    | 14 ++++++-----
 .../src/main/scala/config/ChipConfigs.scala   | 24 +++++++++----------
 .../scala/config/MemorySystemConfigs.scala    |  4 ++--
 .../src/main/scala/config/NoCoreConfigs.scala |  4 ++--
 .../config/PeripheralDeviceConfigs.scala      | 22 ++++++++---------
 .../src/main/scala/config/SodorConfigs.scala  | 12 +++++-----
 .../src/main/scala/config/SpikeConfigs.scala  |  2 +-
 .../main/scala/config/TracegenConfigs.scala   |  2 +-
 .../config/fragments/ClockingFragments.scala  |  4 +---
 .../config/fragments/TileFragments.scala      |  2 +-
 .../src/main/scala/example/FlatChipTop.scala  |  2 +-
 .../main/scala/example/FlatTestHarness.scala  |  5 +++-
 .../main/scala/harness/HarnessBinders.scala   |  9 ++++++-
 .../src/main/scala/iobinders/IOBinders.scala  |  8 ++++++-
 .../src/main/scala/iobinders/Ports.scala      |  8 +++++--
 generators/testchipip                         |  2 +-
 22 files changed, 88 insertions(+), 67 deletions(-)

diff --git a/generators/caliptra-aes-acc b/generators/caliptra-aes-acc
index 15d2f85262..82fa7080f4 160000
--- a/generators/caliptra-aes-acc
+++ b/generators/caliptra-aes-acc
@@ -1 +1 @@
-Subproject commit 15d2f85262125a3ba5a674868d4bcbdfbf720df1
+Subproject commit 82fa7080f428b2e59062a55e948f507805c98ef5
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index d7263008a2..01b6626d5e 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -13,13 +13,13 @@ import freechips.rocketchip.devices.tilelink._
 
 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
-  with testchipip.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
-  with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
-  with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
-  with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
-  with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
-  with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+  with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
+  with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
+  with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register
+  with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
+  with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
+  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
   with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
   with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
@@ -40,7 +40,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
 }
 
 class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
-  with testchipip.CanHaveTraceIOModuleImp
+  with testchipip.cosim.CanHaveTraceIOModuleImp
   with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
   with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
   with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index a3ba679ec1..8654d561df 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._
 import boom.common.{BoomTile}
 
 
-import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
+import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
 
 trait CanHaveHTIF { this: BaseSubsystem =>
   // Advertise HTIF if system can communicate with fesvr
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
index 356a04329d..7aa676d5bd 100644
--- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
+++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -14,7 +14,8 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
-import testchipip.{TLTileResetCtrl, ClockGroupFakeResetSynchronizer}
+import testchipip.boot.{TLTileResetCtrl}
+import testchipip.clocking.{ClockGroupFakeResetSynchronizer}
 
 case class ChipyardPRCIControlParams(
   slaveWhere: TLBusWrapperLocation = CBUS,
diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
index 45f9374d95..a3c33561f2 100644
--- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util.ElaborationArtefacts
 
-import testchipip._
+import testchipip.clocking._
 
 // This module adds a TileLink memory-mapped clock divider to the clock graph
 // The output clock/reset pairs from this module should be synchronized later
@@ -38,7 +38,7 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
       val reg = Module(new AsyncResetRegVec(w=divBits, init=0))
 
       println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider")
-      val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
+      val divider = Module(new ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
       divider.io.clockIn := sources(i).clock
       // busReset is expected to be high for a long time, since reset will take a while to propagate
       // to the TL bus. While reset is propagating, make sure we propagate a fast, undivided clock
diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
index 2787042892..1d0a149d7c 100644
--- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util.ElaborationArtefacts
 
-import testchipip._
+import testchipip.clocking._
 
 case class ClockSelNode()(implicit valName: ValName)
   extends MixedNexusNode(ClockImp, ClockGroupImp)(
@@ -40,7 +40,7 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
       sel := reg.io.q
       println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux")
 
-      val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
+      val mux = ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
       mux.io.sel        := sel
       mux.io.resetAsync := asyncReset.asAsyncReset
       sinks(i).clock := mux.io.clockOut
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index 06f9af3b3e..cef46e0419 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -61,12 +61,14 @@ class AbstractConfig extends Config(
   new chipyard.config.WithFrontBusFrequency(500.0) ++               // Default 500 MHz fbus
   new chipyard.config.WithOffchipBusFrequency(500.0) ++             // Default 500 MHz obus
 
-  new testchipip.WithCustomBootPin ++                               // add a custom-boot-pin to support pin-driven boot address
-  new testchipip.WithBootAddrReg ++                                 // add a boot-addr-reg for configurable boot address
-  new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(        // add a serial-tilelink interface
-    client = Some(testchipip.SerialTLClientParams(idBits = 4)),     // serial-tilelink interface will master the FBUS, and support 4 idBits
-    width = 32                                                      // serial-tilelink interface with 32 lanes
-  ))) ++
+  new testchipip.boot.WithCustomBootPin ++                          // add a custom-boot-pin to support pin-driven boot address
+  new testchipip.boot.WithBootAddrReg ++                            // add a boot-addr-reg for configurable boot address
+  new testchipip.serdes.WithSerialTL(Seq(                           // add a serial-tilelink interface
+    testchipip.serdes.SerialTLParams(
+      client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
+      width = 32                                                    // serial-tilelink interface with 32 lanes
+    )
+  )) ++
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
   new chipyard.config.WithBootROM ++                                // use default bootrom
   new chipyard.config.WithUART ++                                   // add a UART
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index e3d183750f..ffcb3f7781 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -3,7 +3,7 @@ package chipyard
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.subsystem.{MBUS, SBUS}
-import testchipip.{OBUS}
+import testchipip.soc.{OBUS}
 
 // A simple config demonstrating how to set up a basic chip in Chipyard
 class ChipLikeRocketConfig extends Config(
@@ -22,16 +22,16 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   // Set up I/O
   //==================================
-  new testchipip.WithSerialTLWidth(4) ++                                                // 4bit wide Serialized TL interface to minimize IO
-  new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++                              // Configure the off-chip memory accessible over serial-tl as backing memory
+  new testchipip.serdes.WithSerialTLWidth(4) ++                                         // 4bit wide Serialized TL interface to minimize IO
+  new testchipip.serdes.WithSerialTLMem(size = (1 << 30) * 4L) ++                       // Configure the off-chip memory accessible over serial-tl as backing memory
   new freechips.rocketchip.subsystem.WithNoMemPort ++                                   // Remove axi4 mem port
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++                          // 1 memory channel
 
   //==================================
   // Set up buses
   //==================================
-  new testchipip.WithOffchipBusClient(MBUS) ++                                          // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
-  new testchipip.WithOffchipBus ++                                                      // attach a offchip bus, since the serial-tl will master some external tilelink memory
+  new testchipip.soc.WithOffchipBusClient(MBUS) ++                                      // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
+  new testchipip.soc.WithOffchipBus ++                                                  // attach a offchip bus, since the serial-tl will master some external tilelink memory
 
   //==================================
   // Set up clock./reset
@@ -60,17 +60,17 @@ class ChipBringupHostConfig extends Config(
   //=============================
   // Setup the SerialTL side on the bringup device
   //=============================
-  new testchipip.WithSerialTLWidth(4) ++                                       // match width with the chip
-  new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L,               // accessible memory of the chip that doesn't come from the tethered host
-                                 idBits = 4, isMainMemory = false) ++          // This assumes off-chip mem starts at 0x8000_0000
-  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
+  new testchipip.serdes.WithSerialTLWidth(4) ++                                // match width with the chip
+  new testchipip.serdes.WithSerialTLMem(base = 0x0, size = 0x80000000L,        // accessible memory of the chip that doesn't come from the tethered host
+                                        idBits = 4, isMainMemory = false) ++   // This assumes off-chip mem starts at 0x8000_0000
+  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
 
   //============================
   // Setup bus topology on the bringup system
   //============================
-  new testchipip.WithOffchipBusClient(SBUS,                                    // offchip bus hangs off the SBUS
+  new testchipip.soc.WithOffchipBusClient(SBUS,                                // offchip bus hangs off the SBUS
     blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accessed directly
-  new testchipip.WithOffchipBus ++                                             // offchip bus
+  new testchipip.soc.WithOffchipBus ++                                         // offchip bus
 
   //=============================
   // Set up memory on the bringup system
@@ -80,7 +80,7 @@ class ChipBringupHostConfig extends Config(
   //=============================
   // Generate the TSI-over-UART side of the bringup system
   //=============================
-  new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++           // nonstandard baud rate to improve performance
+  new testchipip.tsi.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++       // nonstandard baud rate to improve performance
 
   //=============================
   // Set up clocks of the bringup system
diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
index aab7fb7f60..c49f85eea2 100644
--- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
@@ -19,14 +19,14 @@ class GB1MemoryRocketConfig extends Config(
 
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadOnlyRocketConfig extends Config(
-  new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
+  new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: mbusscratchpadrocket
 
 class SbusScratchpadRocketConfig extends Config(
-  new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
+  new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
index 19e9a7e0ed..4f70f9ee09 100644
--- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -4,8 +4,8 @@ import org.chipsalliance.cde.config.{Config}
 
 // A empty config with no cores. Useful for testing
 class NoCoresConfig extends Config(
-  new testchipip.WithNoBootAddrReg ++
-  new testchipip.WithNoCustomBootPin ++
+  new testchipip.boot.WithNoBootAddrReg ++
+  new testchipip.boot.WithNoCustomBootPin ++
   new chipyard.config.WithNoCLINT ++
   new chipyard.config.WithNoBootROM ++
   new chipyard.config.WithBroadcastManager ++
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
index 5473b99e16..9940074306 100644
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -22,13 +22,13 @@ class SmallSPIFlashRocketConfig extends Config(
 
 class SimBlockDeviceRocketConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++                // drive block-device IOs with SimBlockDevice
-  new testchipip.WithBlockDevice ++                         // add block-device module to peripherybus
+  new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to peripherybus
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
   new chipyard.harness.WithBlockDeviceModel ++              // drive block-device IOs with a BlockDeviceModel
-  new testchipip.WithBlockDevice ++                         // add block-device module to periphery bus
+  new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to periphery bus
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
@@ -53,10 +53,10 @@ class MMIORocketConfig extends Config(
 
 class LBWIFRocketConfig extends Config(
   new chipyard.config.WithOffchipBusFrequency(500) ++
-  new testchipip.WithOffchipBusClient(MBUS) ++
-  new testchipip.WithOffchipBus ++
-  new testchipip.WithSerialTLMem(isMainMemory=true) ++      // set lbwif memory base to DRAM_BASE, use as main memory
-  new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove AXI4 backing memory
+  new testchipip.soc.WithOffchipBusClient(MBUS) ++
+  new testchipip.soc.WithOffchipBus ++
+  new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
+  new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove AXI4 backing memory
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
@@ -69,10 +69,10 @@ class dmiRocketConfig extends Config(
 // DOC include end: DmiRocket
 
 class ManyPeripheralsRocketConfig extends Config(
-  new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
-  new testchipip.WithOffchipBusClient(MBUS) ++               // OBUS provides backing memory to the MBUS
-  new testchipip.WithOffchipBus ++                           // OBUS must exist for serial-tl to master off-chip memory
-  new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
+  new testchipip.iceblk.WithBlockDevice ++                   // add block-device module to peripherybus
+  new testchipip.soc.WithOffchipBusClient(MBUS) ++           // OBUS provides backing memory to the MBUS
+  new testchipip.soc.WithOffchipBus ++                       // OBUS must exist for serial-tl to master off-chip memory
+  new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
   new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
   new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
   new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
@@ -84,7 +84,7 @@ class ManyPeripheralsRocketConfig extends Config(
 
 class UARTTSIRocketConfig extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.config.WithMemoryBusFrequency(10) ++
   new chipyard.config.WithFrontBusFrequency(10) ++
   new chipyard.config.WithPeripheryBusFrequency(10) ++
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index 4181083cbc..7d7c7ac34d 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.{Config}
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -16,7 +16,7 @@ class Sodor1StageConfig extends Config(
 class Sodor2StageConfig extends Config(
   // Create a Sodor 2-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -25,7 +25,7 @@ class Sodor2StageConfig extends Config(
 class Sodor3StageConfig extends Config(
   // Create a Sodor 1-stage core with two ports
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -34,7 +34,7 @@ class Sodor3StageConfig extends Config(
 class Sodor3StageSinglePortConfig extends Config(
   // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -43,7 +43,7 @@ class Sodor3StageSinglePortConfig extends Config(
 class Sodor5StageConfig extends Config(
   // Create a Sodor 5-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -52,7 +52,7 @@ class Sodor5StageConfig extends Config(
 class SodorUCodeConfig extends Config(
   // Construct a Sodor microcode-based single-bus core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
index 4c1fc30322..6f4c6ab733 100644
--- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
@@ -43,7 +43,7 @@ class SpikeUltraFastDevicesConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++
   new chipyard.harness.WithLoopbackNIC ++
   new icenet.WithIceNIC ++
-  new testchipip.WithBlockDevice ++
+  new testchipip.iceblk.WithBlockDevice ++
 
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index 55cce1b818..4235bf1e3f 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -43,6 +43,6 @@ class NonBlockingTraceGenL2Config extends Config(
 
 class NonBlockingTraceGenL2RingConfig extends Config(
   new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
-  new testchipip.WithRingSystemBus ++
+  new testchipip.soc.WithRingSystemBus ++
   new freechips.rocketchip.subsystem.WithInclusiveCache ++
   new AbstractTraceGenConfig)
diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
index 9191bc0cc9..f86254c45b 100644
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -13,9 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}
 
 import chipyard._
 import chipyard.clocking._
-import testchipip.{OffchipBusKey}
-
-import testchipip.{OffchipBusKey}
+import testchipip.soc.{OffchipBusKey}
 
 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index 6262fbcdd4..92d8fc6fb6 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -11,7 +11,7 @@ import boom.common.{BoomTileAttachParams}
 import cva6.{CVA6TileAttachParams}
 import sodor.common.{SodorTileAttachParams}
 import ibex.{IbexTileAttachParams}
-import testchipip._
+import testchipip.cosim.{TracePortKey, TracePortParams}
 import barf.{TilePrefetchingMasterPortParams}
 
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
index 24fcad8e2b..96139ef538 100644
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -14,7 +14,7 @@ import chipyard.harness.{BuildTop}
 import chipyard.clocking._
 import chipyard.iobinders._
 import barstools.iocell.chisel._
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 class WithFlatChipTop extends Config((site, here, up) => {
   case BuildTop => (p: Parameters) => new FlatChipTop()(p)
diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
index 5f6c69f199..304c58a363 100644
--- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
+++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala
@@ -11,7 +11,10 @@ import freechips.rocketchip.util.{PlusArg}
 import freechips.rocketchip.subsystem.{CacheBlockBytes}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import freechips.rocketchip.jtag.{JTAGIO}
-import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI}
+import testchipip.serdes.{SerialTLKey}
+import testchipip.uart.{UARTAdapter}
+import testchipip.dram.{SimDRAM}
+import testchipip.tsi.{TSIHarness, SimTSI}
 import chipyard.harness.{BuildTop}
 
 // A "flat" TestHarness that doesn't use IOBinders
diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 943215060e..9748f597a8 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -12,7 +12,14 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import barstools.iocell.chisel._
-import testchipip._
+import testchipip.dram.{SimDRAM}
+import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
+import testchipip.soc.{TestchipSimDTM}
+import testchipip.spi.{SimSPIFlashModel}
+import testchipip.uart.{UARTAdapter}
+import testchipip.serdes.{UARTToSerial, SerialWidthAdapter}
+import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel}
+import testchipip.cosim.{SpikeCosim}
 import icenet.{NicLoopback, SimNetwork}
 import chipyard._
 import chipyard.clocking.{HasChipyardPRCI}
diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 7894ba513b..45f726410e 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -23,7 +23,13 @@ import tracegen.{TraceGenSystemModuleImp}
 
 import barstools.iocell.chisel._
 
-import testchipip._
+import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
+import testchipip.spi.{SPIChipIO}
+import testchipip.boot.{CanHavePeripheryCustomBootPin}
+import testchipip.util.{ClockedIO}
+import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
+import testchipip.cosim.{CanHaveTraceIOModuleImp, TraceOutputTop, SpikeCosimConfig}
+import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
 
diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala
index c5c9f19eb8..ba14cc3963 100644
--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -4,9 +4,13 @@ import chisel3._
 import chisel3.experimental.{Analog}
 import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.spi.{SPIFlashParams, SPIPortIO}
-import sifive.blocks.devices.i2c.{I2CPort}
 import sifive.blocks.devices.gpio.{GPIOPortIO}
-import testchipip._
+import testchipip.util.{ClockedIO}
+import testchipip.serdes.{TLSerdesser, SerialIO, SerialTLParams}
+import testchipip.spi.{SPIChipIO}
+import testchipip.cosim.{TraceOutputTop, SpikeCosimConfig}
+import testchipip.iceblk.{BlockDeviceIO, BlockDeviceConfig}
+import testchipip.tsi.{UARTTSIIO}
 import icenet.{NICIOvonly, NICConfig}
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}
diff --git a/generators/testchipip b/generators/testchipip
index 50a05b0782..171095445e 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 50a05b078295f91798bee9d506a47a4e967dd493
+Subproject commit 171095445e15bb8f002fbb3ec8b0f0b26dfcc5fe

From 1e5ebf192ad8686c6ec02ceb1ab9cd69cac2aae5 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 19 Dec 2023 12:11:12 -0800
Subject: [PATCH 05/31] Update firesim/firechip with new testchipip packaging

---
 .../src/main/scala/BridgeBinders.scala        |  2 +-
 .../src/main/scala/TargetConfigs.scala        | 21 ++++++++++---------
 sims/firesim                                  |  2 +-
 3 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index ad643deb1f..954c104cfb 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import sifive.blocks.devices.uart._
 
-import testchipip._
+import testchipip.tsi.{SerialRAM}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 
 import junctions.{NastiKey, NastiParameters}
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 944fe9cf09..9f5f7ef6a3 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -13,7 +13,8 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
 import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams}
+import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
+import testchipip.cosim.{TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 
@@ -101,7 +102,7 @@ class WithFireSimDesignTweaks extends Config(
   // Required: Bake in the default FASED memory model
   new WithDefaultMemModel ++
   // Optional: reduce the width of the Serial TL interface
-  new testchipip.WithSerialTLWidth(4) ++
+  new testchipip.serdes.WithSerialTLWidth(4) ++
   // Required*: Scale default baud rate with periphery bus frequency
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
   // Optional: Adds IO to attach tracerV bridges
@@ -109,7 +110,7 @@ class WithFireSimDesignTweaks extends Config(
   // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
   // Optional: Removing this will require using an initramfs under linux
-  new testchipip.WithBlockDevice
+  new testchipip.iceblk.WithBlockDevice
 )
 
 // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
@@ -151,7 +152,7 @@ class WithFireSimConfigTweaks extends Config(
 class WithMinimalFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithMbusScratchpad ++
+  new testchipip.soc.WithMbusScratchpad ++
   new WithMinimalFireSimDesignTweaks
 )
 
@@ -161,8 +162,8 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config(
 class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
-  new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
-  new testchipip.WithBlockDevice(true) ++ // add in block device
+  new testchipip.soc.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
+  new testchipip.iceblk.WithBlockDevice(true) ++ // add in block device
   new WithMinimalFireSimDesignTweaks
 )
 
@@ -257,11 +258,11 @@ class FireSimSmallSystemConfig extends Config(
   new WithoutClockGating ++
   new WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
-  new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(
-    client = Some(testchipip.SerialTLClientParams(idBits = 4)),
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
+    client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
     width = 32
   ))) ++
-  new testchipip.WithBlockDevice ++
+  new testchipip.iceblk.WithBlockDevice ++
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
   new chipyard.RocketConfig)
@@ -339,7 +340,7 @@ class FireSim16LargeBoomConfig extends Config(
 class FireSimNoMemPortConfig extends Config(
   new WithDefaultFireSimBridges ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithMbusScratchpad ++
+  new testchipip.soc.WithMbusScratchpad ++
   new WithFireSimConfigTweaks ++
   new chipyard.RocketConfig)
 
diff --git a/sims/firesim b/sims/firesim
index 73fe6a51b2..e975893595 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 73fe6a51b28a2dbbe3f307bdbc6ba2407b311a27
+Subproject commit e975893595129c2682a72fb7e5898273fcc2d071

From 604cb6358f559cac8220a59a9539a084ae11413d Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 19 Dec 2023 12:17:00 -0800
Subject: [PATCH 06/31] Bump fpga-platforms to new organized testchipip

---
 docs/Customization/Memory-Hierarchy.rst           |   2 +-
 fpga/bootrom.rv32.img                             | Bin 0 -> 192 bytes
 fpga/bootrom.rv64.img                             | Bin 0 -> 192 bytes
 fpga/src/main/scala/arty/Configs.scala            |   4 ++--
 fpga/src/main/scala/arty100t/Configs.scala        |   6 +++---
 fpga/src/main/scala/arty100t/HarnessBinders.scala |   2 --
 fpga/src/main/scala/nexysvideo/Configs.scala      |   6 +++---
 .../main/scala/nexysvideo/HarnessBinders.scala    |   2 --
 fpga/src/main/scala/vc707/Configs.scala           |   2 +-
 fpga/src/main/scala/vcu118/Configs.scala          |   2 +-
 fpga/src/main/scala/vcu118/bringup/Configs.scala  |   2 +-
 .../scala/vcu118/bringup/CustomOverlays.scala     |   2 +-
 .../main/scala/vcu118/bringup/DigitalTop.scala    |   2 +-
 .../scala/vcu118/bringup/HarnessBinders.scala     |   2 +-
 .../src/main/scala/vcu118/bringup/IOBinders.scala |   2 +-
 .../main/scala/vcu118/bringup/TestHarness.scala   |   3 ++-
 variables.mk                                      |   2 +-
 17 files changed, 19 insertions(+), 22 deletions(-)
 create mode 100755 fpga/bootrom.rv32.img
 create mode 100755 fpga/bootrom.rv64.img

diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst
index 62ccf68454..ecb666d1f9 100644
--- a/docs/Customization/Memory-Hierarchy.rst
+++ b/docs/Customization/Memory-Hierarchy.rst
@@ -94,7 +94,7 @@ memory channel.
 
 Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
 and remove the off-chip link. This is done by adding a fragment like
-``testchipip.WithScratchpad`` to your configuration and removing the
+``testchipip.soc.WithScratchpad`` to your configuration and removing the
 memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
diff --git a/fpga/bootrom.rv32.img b/fpga/bootrom.rv32.img
new file mode 100755
index 0000000000000000000000000000000000000000..fbab5033ab69b24d54a0175d735a0f2cf21f5364
GIT binary patch
literal 192
zcmdna%D_~t>hLj{g_R+np@Chv&6Qy?n*f8d!ZikAHaCW5wPXJu&tm(R&v1Z^0Sgdk
zWnd6yW&Kku5NhyQNx)$8B_+qnpM)5aTbLM%1q=*?SsQ?~t3j~>t3feCfI$9-`~Q)R
z$^Rh#r+E=8!{d2O|Aa+V88)+SWl&zg%3$uwz`(4^3e+oV0&?GUpgogYTN#Df7&wXz
N*nnm!7zhIm0s!cFEFk~@

literal 0
HcmV?d00001

diff --git a/fpga/bootrom.rv64.img b/fpga/bootrom.rv64.img
new file mode 100755
index 0000000000000000000000000000000000000000..8d4fea0554d5c5f953b25cfe015ae3c9bd3b1189
GIT binary patch
literal 192
zcmdna%D_~t>hLj{g_R+np@Chv&6Qy?n*f8d!ZikAHaCW5wPXJu&tm(R&v1Z^0Sgdk
zWnd6yW&Kku5NhyQNx)$8B_+qnpM)5aTbLM%1q=*?SsQ?~t3j~>t3feCfI$9-`~Q)R
z$^Rh#r+E=8!{d2O|Aa+V88)+SWl&zg%3$uwz`$(E3e+oV0&?GUpgogYTN#Df7&wXz
N*nnm!7zhIm0s!i%EHMB8

literal 0
HcmV?d00001

diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index 1bf2b64318..eeb26b6061 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -11,7 +11,7 @@ import freechips.rocketchip.tile._
 
 import sifive.blocks.devices.uart._
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -30,7 +30,7 @@ class WithArtyTweaks extends Config(
   new chipyard.config.WithFrontBusFrequency(32) ++
   new chipyard.config.WithControlBusFrequency(32) ++
   new chipyard.config.WithPeripheryBusFrequency(32) ++
-  new testchipip.WithNoSerialTL
+  new testchipip.serdes.WithNoSerialTL
 )
 
 class TinyRocketArtyConfig extends Config(
diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 213425f57b..c9892aa86f 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
 import sifive.blocks.devices.uart._
 import sifive.fpgashells.shell.{DesignKey}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -25,7 +25,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
   new WithNoDesignKey ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
   new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
@@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config(
 class BringupArty100TConfig extends Config(
   new WithArty100TSerialTLToGPIO ++
   new WithArty100TTweaks(freqMHz = 50) ++
-  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
+  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
   new chipyard.ChipBringupHostConfig)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 4c82197081..dd7c1a352d 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -20,8 +20,6 @@ import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._
 
-import testchipip._
-
 class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala
index 01b095fa51..fe53b96d8a 100644
--- a/fpga/src/main/scala/nexysvideo/Configs.scala
+++ b/fpga/src/main/scala/nexysvideo/Configs.scala
@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
 import sifive.blocks.devices.uart._
 import sifive.fpgashells.shell.{DesignKey}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -26,7 +26,7 @@ class WithNexysVideoTweaks extends Config(
   new WithNexysVideoUARTTSI ++
   new WithNexysVideoDDRTL ++
   new WithNoDesignKey ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
   new chipyard.config.WithMemoryBusFrequency(50.0) ++
@@ -53,7 +53,7 @@ class WithTinyNexysVideoTweaks extends Config(
   new WithNexysVideoUARTTSI ++
   new WithNoDesignKey ++
   new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
   new chipyard.config.WithMemoryBusFrequency(50.0) ++
diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
index 4027cbcf2a..e6865effc4 100644
--- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
+++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
@@ -12,8 +12,6 @@ import sifive.blocks.devices.uart.{UARTParams}
 
 import chipyard._
 import chipyard.harness._
-
-import testchipip._
 import chipyard.iobinders._
 
 class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
index 124920d78d..4842434e37 100644
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem, ExtTLMem}
 import chipyard.harness._
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index 32dc3c2c0c..3f99fdb967 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard._
 import chipyard.harness._
diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala
index 65a23a1fba..0760fa72b7 100644
--- a/fpga/src/main/scala/vcu118/bringup/Configs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
-import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
+import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
 
 import chipyard.{BuildSystem}
 
diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
index 4b9604f9ab..a52a1b5ec3 100644
--- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.clocks._
 import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
 
-import testchipip.{TSIHostWidgetIO}
+import testchipip.tsi.{TSIHostWidgetIO}
 
 import chipyard.fpga.vcu118.{FMCPMap}
 
diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
index c5401d320b..e4efbdc7e1 100644
--- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
+++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
@@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule}
 
 class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
   with sifive.blocks.devices.i2c.HasPeripheryI2C
-  with testchipip.HasPeripheryTSIHostWidget
+  with testchipip.tsi.HasPeripheryTSIHostWidget
 {
   override lazy val module = new BringupVCU118DigitalTopModule(this)
 }
diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
index d60de62049..c130a697f8 100644
--- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
@@ -11,7 +11,7 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
 import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
 
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.harness._
 import chipyard.iobinders._
diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
index 155f264747..24b7aa9a7b 100644
--- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
 import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
 
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
 
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 12398d8fdb..94d282580c 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._
 import sifive.blocks.devices.i2c._
 import sifive.blocks.devices.gpio._
 
-import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
+import testchipip.util.{TLSinkSetter}
 
 import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
 
diff --git a/variables.mk b/variables.mk
index fcda57effb..65f493d2e6 100644
--- a/variables.mk
+++ b/variables.mk
@@ -97,7 +97,7 @@ ifeq ($(SUB_PROJECT),testchipip)
 	VLOG_MODEL        ?= $(MODEL)
 	MODEL_PACKAGE     ?= chipyard.unittest
 	CONFIG            ?= TestChipUnitTestConfig
-	CONFIG_PACKAGE    ?= testchipip
+	CONFIG_PACKAGE    ?= testchipip.test
 	GENERATOR_PACKAGE ?= chipyard
 	TB                ?= TestDriver
 	TOP               ?= UnitTestSuite

From b7176b3c29b8437e7ec85ceeb518891a88c2de28 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 19 Dec 2023 15:14:39 -0800
Subject: [PATCH 07/31] Bump testchipip

---
 .../chipyard/src/main/scala/harness/HarnessBinders.scala      | 4 ++--
 generators/testchipip                                         | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
index 9748f597a8..6710696d9c 100644
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -16,8 +16,8 @@ import testchipip.dram.{SimDRAM}
 import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
 import testchipip.soc.{TestchipSimDTM}
 import testchipip.spi.{SimSPIFlashModel}
-import testchipip.uart.{UARTAdapter}
-import testchipip.serdes.{UARTToSerial, SerialWidthAdapter}
+import testchipip.uart.{UARTAdapter, UARTToSerial}
+import testchipip.serdes.{SerialWidthAdapter}
 import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel}
 import testchipip.cosim.{SpikeCosim}
 import icenet.{NicLoopback, SimNetwork}
diff --git a/generators/testchipip b/generators/testchipip
index 171095445e..70e198313a 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 171095445e15bb8f002fbb3ec8b0f0b26dfcc5fe
+Subproject commit 70e198313a7e467f9219e4caba0158a96f851503

From 81a2857ec77a93c424012e7a5f1d98ba896cbc5f Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 19 Dec 2023 15:45:20 -0800
Subject: [PATCH 08/31] Add arty100t harness binder to map UART to PMOD JD

---
 fpga/src/main/scala/arty100t/Configs.scala    |  4 ++-
 fpga/src/main/scala/arty100t/Harness.scala    |  3 --
 .../main/scala/arty100t/HarnessBinders.scala  | 33 ++++++++++++++++++-
 3 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 213425f57b..fce9177dc6 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -21,7 +21,10 @@ class WithNoDesignKey extends Config((site, here, up) => {
   case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
 })
 
+// By default, this uses the on-board USB-UART for the TSI-over-UART link
+// The PMODUART HarnessBinder maps the actual UART device to JD pin
 class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
+  new WithArty100TPMODUART ++
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
   new WithNoDesignKey ++
@@ -37,7 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.config.WithNoDebug ++ // no jtag
-  new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
   new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
   new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
   new freechips.rocketchip.subsystem.WithoutTLMonitors)
diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index a535e65f88..577bd1b2bc 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -33,9 +33,6 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
 
   harnessSysPLLNode := clockOverlay.overlayOutput.node
 
-  val io_uart_bb = BundleBridgeSource(() => new UARTPortIO(dp(PeripheryUARTKey).headOption.getOrElse(UARTParams(0))))
-  val uartOverlay = dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
-
   val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRArtyPlacedOverlay]
   val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
     name = "chip_ddr",
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 4c82197081..6ad8defdf2 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -25,7 +25,17 @@ import testchipip._
 class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
-    ath.io_uart_bb.bundle <> port.io.uart
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi")
+    harnessIO <> port.io
+    val packagePinsWithPackageIOs = Seq(
+      ("A9" , IOPin(harnessIO.uart.rxd)),
+      ("D10", IOPin(harnessIO.uart.txd)))
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addIOB(io)
+    } }
+
     ath.other_leds(1) := port.io.dropped
     ath.other_leds(9) := port.io.tsi2tl_state(0)
     ath.other_leds(10) := port.io.tsi2tl_state(1)
@@ -34,6 +44,7 @@ class WithArty100TUARTTSI extends HarnessBinder({
   }
 })
 
+
 class WithArty100TDDRTL extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: TLMemPort) => {
     val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
@@ -83,3 +94,23 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
     artyTh.xdc.clockDedicatedRouteFalse(clkIO)
   }
 })
+
+// Maps the UART device to the on-board USB-UART
+class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: UARTPort) => {
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
+    harnessIO <> port.io
+    val packagePinsWithPackageIOs = Seq(
+      (rxdPin, IOPin(harnessIO.rxd)),
+      (txdPin, IOPin(harnessIO.txd)))
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addIOB(io)
+    } }
+  }
+})
+
+// Maps the UART device to PMOD JD pins 3/7
+class WithArty100TPMODUART extends WithArty100TUART("E2", "F4")

From 902d33ebd1448ef80c6596b8ffe887a8e8b412ed Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 20 Dec 2023 08:43:35 -0800
Subject: [PATCH 09/31] Add Arty100T JTAG

---
 fpga/src/main/scala/arty100t/Configs.scala    |  2 +-
 .../main/scala/arty100t/HarnessBinders.scala  | 25 ++++++++++++++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index fce9177dc6..df29d5af03 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -27,6 +27,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new WithArty100TPMODUART ++
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
+  new WithArty100TJTAG ++
   new WithNoDesignKey ++
   new testchipip.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
@@ -39,7 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.config.WithNoDebug ++ // no jtag
   new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
   new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
   new freechips.rocketchip.subsystem.WithoutTLMonitors)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 6ad8defdf2..64676584f4 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -113,4 +113,27 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha
 })
 
 // Maps the UART device to PMOD JD pins 3/7
-class WithArty100TPMODUART extends WithArty100TUART("E2", "F4")
+class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
+
+class WithArty100TJTAG extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
+    harnessIO <> port.io
+
+    ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
+    ath.sdc.addGroup(clocks = Seq("JTCK"))
+    ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
+    val packagePinsWithPackageIOs = Seq(
+      ("F4", IOPin(harnessIO.TCK)),
+      ("D2", IOPin(harnessIO.TMS)),
+      ("E2", IOPin(harnessIO.TDI)),
+      ("D4", IOPin(harnessIO.TDO))
+    )
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addPullup(io)
+    } }
+  }
+})

From 516ecf9d9e61fd3ee2cedb1681947bd0bcf6a12c Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Wed, 20 Dec 2023 22:16:15 -0800
Subject: [PATCH 10/31] ADD: increase frequency to maximum

---
 fpga/src/main/resources/vcu118/sdboot/sd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c
index e8d45ba7b5..c89f155685 100644
--- a/fpga/src/main/resources/vcu118/sdboot/sd.c
+++ b/fpga/src/main/resources/vcu118/sdboot/sd.c
@@ -25,7 +25,7 @@
 #define F_CLK 		(TL_CLK)
 
 // SPI SCLK frequency, in kHz
-#define SPI_CLK 	1250
+#define SPI_CLK 	25000 // 1250
 
 // SPI clock divisor value
 // @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi

From c32de04b5d0535df406cccc25109311fb08c49ff Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Wed, 20 Dec 2023 22:25:05 -0800
Subject: [PATCH 11/31] ADD: add inline docs

---
 fpga/src/main/resources/vcu118/sdboot/sd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/fpga/src/main/resources/vcu118/sdboot/sd.c b/fpga/src/main/resources/vcu118/sdboot/sd.c
index c89f155685..bc1a68e8b8 100644
--- a/fpga/src/main/resources/vcu118/sdboot/sd.c
+++ b/fpga/src/main/resources/vcu118/sdboot/sd.c
@@ -25,7 +25,9 @@
 #define F_CLK 		(TL_CLK)
 
 // SPI SCLK frequency, in kHz
-#define SPI_CLK 	25000 // 1250
+// We are using the 25MHz High Speed mode. If this speed is not supported by the
+// SD card, consider changing to the Default Speed mode (12.5 MHz).
+#define SPI_CLK 	25000
 
 // SPI clock divisor value
 // @see https://ucb-bar.gitbook.io/baremetal-ide/baremetal-ide/using-peripheral-devices/sifive-ips/serial-peripheral-interface-spi

From 5a96abeb146c5a2993654ccef8f24e4664c9af93 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Thu, 21 Dec 2023 21:09:39 -0800
Subject: [PATCH 12/31] FIX: fix conda-lock version, >1.4.0 does not work!

---
 docs/Chipyard-Basics/Initial-Repo-Setup.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
index 9f31624e4d..948b7e2ee0 100644
--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -46,7 +46,7 @@ This is done by the following:
 
 .. code-block:: shell
 
-    conda install -n base conda-lock=1.4
+    conda install -n base conda-lock==1.4.0
     conda activate base
 
 

From 77c3b65fc93b23fd6336858b55b3b20297eaefd7 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 26 Dec 2023 09:39:08 -0800
Subject: [PATCH 13/31] Don't punch out uart2tsi debug io

---
 fpga/src/main/scala/arty100t/HarnessBinders.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 64676584f4..bbb966bb63 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -25,11 +25,11 @@ import testchipip._
 class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
-    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart_tsi")
-    harnessIO <> port.io
+    val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
+    harnessIO <> port.io.uart
     val packagePinsWithPackageIOs = Seq(
-      ("A9" , IOPin(harnessIO.uart.rxd)),
-      ("D10", IOPin(harnessIO.uart.txd)))
+      ("A9" , IOPin(harnessIO.rxd)),
+      ("D10", IOPin(harnessIO.txd)))
     packagePinsWithPackageIOs foreach { case (pin, io) => {
       ath.xdc.addPackagePin(io, pin)
       ath.xdc.addIOStandard(io, "LVCMOS33")

From 638d40e988e5b39f02614b9ea03f1fe373580b17 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 27 Dec 2023 12:53:38 -0800
Subject: [PATCH 14/31] Remove esp-conda-env from CI conda envs

This was unused
---
 .github/actions/create-conda-env/action.yml | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/.github/actions/create-conda-env/action.yml b/.github/actions/create-conda-env/action.yml
index e29a06e948..b9fd606690 100644
--- a/.github/actions/create-conda-env/action.yml
+++ b/.github/actions/create-conda-env/action.yml
@@ -11,7 +11,6 @@ runs:
           echo "Creating a conda environment for each toolchain with the toolchain installed"
           conda activate base
           conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools ./conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
-          conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools ./conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
           conda deactivate
 
           echo "Add extra toolchain collateral + CIRCT to RISC-V install area"
@@ -25,14 +24,5 @@ runs:
               -x ./conda-reqs/circt.json \
               -g ${{ github.token }}
           conda deactivate
-          conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools
-          ./scripts/build-toolchain-extra.sh esp-tools -p $CONDA_PREFIX/esp-tools
-          ./tools/install-circt/bin/download-release-or-nightly-circt.sh \
-              -f circt-full-shared-linux-x64.tar.gz \
-              -i $CONDA_PREFIX \
-              -v version-file \
-              -x ./conda-reqs/circt.json \
-              -g ${{ github.token }}
-          conda deactivate
         fi
       shell: bash -leo pipefail {0}

From 81fd8edb066124ea1c5cb0286b269c68e37f5ac9 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Fri, 29 Dec 2023 15:35:35 -0800
Subject: [PATCH 15/31] ADD: add scratchpad

---
 fpga/src/main/scala/arty100t/Configs.scala | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index d5c83af37a..03ab2b1efd 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -46,6 +46,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
 
 class RocketArty100TConfig extends Config(
   new WithArty100TTweaks ++
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // use rocket l1 DCache scratchpad as base phys mem
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.RocketConfig)
 

From 0ba5c62b30fb50f4e87331c3c7942909a0053def Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Fri, 29 Dec 2023 16:15:59 -0800
Subject: [PATCH 16/31] FIX: fix scratchpad description

---
 fpga/src/main/scala/arty100t/Configs.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 03ab2b1efd..140df42bc2 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -46,7 +46,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
 
 class RocketArty100TConfig extends Config(
   new WithArty100TTweaks ++
-  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // use rocket l1 DCache scratchpad as base phys mem
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // add on-chip scratchpad for small programs
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.RocketConfig)
 

From 9529c13610bd1f698c51bd00bc868543669b346c Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 29 Dec 2023 18:01:14 -0800
Subject: [PATCH 17/31] Add generators/ submodule status check

---
 common.mk | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/common.mk b/common.mk
index f525b526a8..d52af1a0f9 100644
--- a/common.mk
+++ b/common.mk
@@ -118,7 +118,7 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 #########################################################################################
 # compile scala jars
 #########################################################################################
-$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
+$(CHIPYARD_CLASSPATH_TARGETS) &: check-submodule-status $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
 	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
 
@@ -451,6 +451,15 @@ find-config-fragments:
 help:
 	@for line in $(HELP_LINES); do echo "$$line"; done
 
+#########################################################################################
+# Check submodule status
+#########################################################################################
+
+.PHONY: check-submodule-status
+check-submodule-status:
+	echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed"
+	! git submodule status $(base_dir)/generators | grep ^-
+
 #########################################################################################
 # Implicit rule handling
 #########################################################################################

From 07a7f30b3bcce63b2c634006e649188b98aa3a11 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Fri, 29 Dec 2023 19:21:10 -0800
Subject: [PATCH 18/31] ADD: set scratchpad as default config

---
 fpga/src/main/scala/arty100t/Configs.scala                     | 1 -
 generators/chipyard/src/main/scala/config/AbstractConfig.scala | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 140df42bc2..d5c83af37a 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -46,7 +46,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
 
 class RocketArty100TConfig extends Config(
   new WithArty100TTweaks ++
-  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 128 * 1024) ++ // add on-chip scratchpad for small programs
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.RocketConfig)
 
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index cef46e0419..ace2a110d2 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -72,6 +72,7 @@ class AbstractConfig extends Config(
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
   new chipyard.config.WithBootROM ++                                // use default bootrom
   new chipyard.config.WithUART ++                                   // add a UART
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 64 * 1024) ++ // add 64 KiB on-chip scratchpad
   new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
   new chipyard.config.WithNoSubsystemDrivenClocks ++                // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
   new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set

From c2175f45004d5aab5d7384419c751b513f1af397 Mon Sep 17 00:00:00 2001
From: Tynan McAuley <tynan@niobiummicrosystems.com>
Date: Fri, 29 Dec 2023 21:22:34 -0800
Subject: [PATCH 19/31] Reduce CDE lookups for IOBinders

---
 generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 45f726410e..7695be7024 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -116,7 +116,10 @@ object GetSystemParameters {
 }
 
 class IOBinder[T](composer: Seq[IOBinderFunction] => Seq[IOBinderFunction])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
-  case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> composer(up(IOBinders, site)(tag.runtimeClass.toString)))
+  case IOBinders => {
+    val upMap = up(IOBinders)
+    upMap + (tag.runtimeClass.toString -> composer(upMap(tag.runtimeClass.toString)))
+  }
 })
 
 class ConcreteIOBinder[T](composes: Boolean, fn: T => IOBinderTuple)(implicit tag: ClassTag[T]) extends IOBinder[T](

From 0fa09da5c1a1687fb620018f5e8650fadb88a9da Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Sat, 30 Dec 2023 06:29:05 -0800
Subject: [PATCH 20/31] Remove MBus spad from configs that do not support it

---
 fpga/src/main/scala/arty/Configs.scala                      | 3 ++-
 .../chipyard/src/main/scala/config/AbstractConfig.scala     | 3 ++-
 generators/chipyard/src/main/scala/config/NoCConfigs.scala  | 4 ++--
 .../chipyard/src/main/scala/config/NoCoreConfigs.scala      | 1 +
 .../chipyard/src/main/scala/config/RocketConfigs.scala      | 4 +++-
 .../chipyard/src/main/scala/config/SodorConfigs.scala       | 6 ++++++
 generators/testchipip                                       | 2 +-
 7 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index eeb26b6061..e86140eb68 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -30,7 +30,8 @@ class WithArtyTweaks extends Config(
   new chipyard.config.WithFrontBusFrequency(32) ++
   new chipyard.config.WithControlBusFrequency(32) ++
   new chipyard.config.WithPeripheryBusFrequency(32) ++
-  new testchipip.serdes.WithNoSerialTL
+  new testchipip.serdes.WithNoSerialTL ++
+  new testchipip.soc.WithNoScratchpads
 )
 
 class TinyRocketArtyConfig extends Config(
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index ace2a110d2..775ecb5861 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -69,10 +69,11 @@ class AbstractConfig extends Config(
       width = 32                                                    // serial-tilelink interface with 32 lanes
     )
   )) ++
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000,          // add 64 KiB on-chip scratchpad
+                                        size = 64 * 1024) ++
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
   new chipyard.config.WithBootROM ++                                // use default bootrom
   new chipyard.config.WithUART ++                                   // add a UART
-  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 64 * 1024) ++ // add 64 KiB on-chip scratchpad
   new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
   new chipyard.config.WithNoSubsystemDrivenClocks ++                // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
   new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set
diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index 66cb1aa2af..4288fa847e 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -146,7 +146,7 @@ class MultiNoCConfig extends Config(
  * L2 3   | MI  | Cache[3]   |    6
  * DRAM 0 | MO  | system[0]  |    3
  * DRAM 1 | MO  | system[1]  |    5
- * extram | MO  | serial_tl_0  |    9
+ * spad   | MO  | ram[0]     |    9
  */
 // DOC include start: SharedNoCConfig
 class SharedNoCConfig extends Config(
@@ -169,7 +169,7 @@ class SharedNoCConfig extends Config(
         "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
       outNodeMapping = ListMap(
         "system[0]" -> 3, "system[1]" -> 5,
-        "serial_tl_0" -> 9))
+        "ram[0]" -> 9))
   )) ++
   new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(
diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
index 4f70f9ee09..6647e51639 100644
--- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -4,6 +4,7 @@ import org.chipsalliance.cde.config.{Config}
 
 // A empty config with no cores. Useful for testing
 class NoCoresConfig extends Config(
+  new testchipip.soc.WithNoScratchpads ++
   new testchipip.boot.WithNoBootAddrReg ++
   new testchipip.boot.WithNoCustomBootPin ++
   new chipyard.config.WithNoCLINT ++
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 929e8c5940..216cb53e0a 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -12,7 +12,8 @@ class RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class TinyRocketConfig extends Config(
-  new chipyard.harness.WithDontTouchChipTopPorts(false) ++         // TODO FIX: Don't dontTouch the ports
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++        // TODO FIX: Don't dontTouch the ports
+  new testchipip.soc.WithNoScratchpads ++                         // All memory is the Rocket TCMs
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
   new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
   new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
@@ -36,6 +37,7 @@ class RV32RocketConfig extends Config(
 // DOC include start: l1scratchpadrocket
 class ScratchpadOnlyRocketConfig extends Config(
   new chipyard.config.WithL2TLBs(0) ++
+  new testchipip.soc.WithNoScratchpads ++                      // remove subsystem scratchpads, confusingly named, does not remove the L1D$ scratchpads
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // remove offchip mem port
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 DCache scratchpad as base phys mem
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index 7d7c7ac34d..2edda3ce97 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -7,6 +7,7 @@ import org.chipsalliance.cde.config.{Config}
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -16,6 +17,7 @@ class Sodor1StageConfig extends Config(
 class Sodor2StageConfig extends Config(
   // Create a Sodor 2-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -25,6 +27,7 @@ class Sodor2StageConfig extends Config(
 class Sodor3StageConfig extends Config(
   // Create a Sodor 1-stage core with two ports
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -34,6 +37,7 @@ class Sodor3StageConfig extends Config(
 class Sodor3StageSinglePortConfig extends Config(
   // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -43,6 +47,7 @@ class Sodor3StageSinglePortConfig extends Config(
 class Sodor5StageConfig extends Config(
   // Create a Sodor 5-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -52,6 +57,7 @@ class Sodor5StageConfig extends Config(
 class SodorUCodeConfig extends Config(
   // Construct a Sodor microcode-based single-bus core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
diff --git a/generators/testchipip b/generators/testchipip
index 70e198313a..c13b8f658b 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 70e198313a7e467f9219e4caba0158a96f851503
+Subproject commit c13b8f658b955f9f61a52caefcd6388e034b0575

From 561e3fca68c4bd2717509d9160d6cabf206656b1 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 2 Jan 2024 12:51:27 -0800
Subject: [PATCH 21/31] [ci skip] Add makefile help text for
 check-submodule-status

---
 common.mk | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/common.mk b/common.mk
index d52af1a0f9..c4ae8548e8 100644
--- a/common.mk
+++ b/common.mk
@@ -57,7 +57,8 @@ HELP_COMMANDS += \
 "   firrtl                      = generate intermediate firrtl files from chisel elaboration" \
 "   run-tests                   = run all assembly and benchmark tests" \
 "   launch-sbt                  = start sbt terminal" \
-"   find-config-fragments       = list all config. fragments"
+"   find-config-fragments       = list all config. fragments" \
+"   check-submodule-status      = check that all submodules in generators/ have been initialized"
 
 #########################################################################################
 # include additional subproject make fragments

From 0a42dd1ca1bc83d12de40ab7d5b6ebe28630bb81 Mon Sep 17 00:00:00 2001
From: Tynan McAuley <tynan@niobiummicrosystems.com>
Date: Wed, 3 Jan 2024 16:22:51 -0800
Subject: [PATCH 22/31] Update deprecated APIs to prepare for Chisel 5

- `IO` was moved from `chisel3.experimental` to `chisel3`
- `DataMirror` was moved from `chisel3.experimental` to `chisel3.reflect`
---
 generators/chipyard/src/main/scala/SpikeTile.scala             | 2 +-
 .../chipyard/src/main/scala/clocking/ClockGroupCombiner.scala  | 2 +-
 .../chipyard/src/main/scala/clocking/TileClockGater.scala      | 2 +-
 .../chipyard/src/main/scala/clocking/TileResetSetter.scala     | 2 +-
 generators/chipyard/src/main/scala/iobinders/IOBinders.scala   | 3 ++-
 5 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index fc822c2272..777b373116 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{IntParam, StringParam, IO}
+import chisel3.experimental.{IntParam, StringParam}
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
index e52368049b..9b53cbefd6 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
index e299d0a9f4..c92e05bc32 100644
--- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
index 53dd36d09a..88916d17b3 100644
--- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 7695be7024..f67ea81fb3 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -1,7 +1,8 @@
 package chipyard.iobinders
 
 import chisel3._
-import chisel3.experimental.{Analog, IO, DataMirror}
+import chisel3.reflect.DataMirror
+import chisel3.experimental.Analog
 
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._

From 9ab9132c8b30753450518f9ca3f4ab03719b3b92 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 4 Jan 2024 13:34:53 -0800
Subject: [PATCH 23/31] Fix missing childClock/childReset in Arty100THarness

---
 fpga/src/main/scala/arty100t/Harness.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index 577bd1b2bc..30a382e1b0 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -76,6 +76,9 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
     def referenceReset = dutClock.in.head._1.reset
     def success = { require(false, "Unused"); false.B }
 
+    childClock := harnessBinderClock
+    childReset := harnessBinderReset
+
     ddrOverlay.mig.module.clock := harnessBinderClock
     ddrOverlay.mig.module.reset := harnessBinderReset
     ddrBlockDuringReset.module.clock := harnessBinderClock

From bb23af97be037af80ef1710034eaa1d3b4785fcd Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 4 Jan 2024 12:10:36 -0800
Subject: [PATCH 24/31] Add clearer --skip flags to build-setup

---
 scripts/build-setup.sh | 28 +++++++++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh
index d3a66ca6a0..a55b10fdd7 100755
--- a/scripts/build-setup.sh
+++ b/scripts/build-setup.sh
@@ -38,12 +38,20 @@ usage() {
     echo "  --help -h               : Display this message"
 
     echo "  --force -f              : Skip all prompts and checks"
-    echo "  --skip-validate         : DEPRECATED: Same functionality as --force"
     echo "  --verbose -v            : Verbose printout"
 
     echo "  --use-unpinned-deps -ud : Use unpinned conda environment"
 
     echo "  --skip -s N             : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')."
+    echo "  --skip-conda            : Skip Conda initialization (step 1)"
+    echo "  --skip-submodules       : Skip submodule initialization (step 2)"
+    echo "  --skip-toolchain        : Skip toolchain collateral (step 3)"
+    echo "  --skip-ctags            : Skip ctags (step 4)"
+    echo "  --skip-precompile       : Skip precompiling sources (steps 5/7)"
+    echo "  --skip-firesim          : Skip Firesim initialization (steps 6/7)"
+    echo "  --skip-marshal          : Skip firemarshal initialization (steps 8/9)"
+    echo "  --skip-circt            : Skip CIRCT install (step 10)"
+    echo "  --skip-clean            : Skip repository clean-up (step 11)"
 
     exit "$1"
 }
@@ -73,6 +81,24 @@ do
         --skip | -s)
             shift
             SKIP_LIST+=(${1}) ;;
+        --skip-conda)
+            SKIP_LIST+=(1) ;;
+        --skip-submodules)
+            SKIP_LIST+=(2) ;;
+        --skip-toolchain)
+            SKIP_LIST+=(3) ;;
+        --skip-ctags)
+            SKIP_LIST+=(4) ;;
+        --skip-precompile)
+            SKIP_LIST+=(5 6) ;;
+        --skip-firesim)
+            SKIP_LIST+=(6 7) ;;
+        --skip-marshal)
+            SKIP_LIST+=(8 9) ;;
+        --skip-circt)
+            SKIP_LIST+=(10) ;;
+        --skip-clean)
+            SKIP_LIST+=(11) ;;
         * )
             error "invalid option $1"
             usage 1 ;;

From 7c1357476920dbccc2065827e3f3457e096d4fec Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 4 Jan 2024 14:09:54 -0800
Subject: [PATCH 25/31] Rename cache/blocks submodules to match new
 chipsalliance ownership

---
 .github/scripts/check-commit.sh                |  2 +-
 .gitmodules                                    | 12 ++++++------
 build.sbt                                      | 12 ++++++------
 docs/Chipyard-Basics/Chipyard-Components.rst   |  6 +++---
 docs/Customization/Custom-Chisel.rst           |  2 +-
 docs/Customization/Memory-Hierarchy.rst        |  8 ++++----
 ...nerators.rst => Rocket-Chip-Generators.rst} | 18 +++++++++---------
 docs/Generators/Rocket-Chip.rst                |  4 ++--
 docs/Generators/Rocket.rst                     |  2 +-
 docs/Generators/index.rst                      |  2 +-
 fpga/Makefile                                  |  2 +-
 .../{sifive-blocks => rocket-chip-blocks}      |  0
 ...ifive-cache => rocket-chip-inclusive-cache} |  0
 scripts/tutorial-patches/build.sbt.patch       |  2 +-
 sims/firesim                                   |  2 +-
 15 files changed, 37 insertions(+), 37 deletions(-)
 rename docs/Generators/{SiFive-Generators.rst => Rocket-Chip-Generators.rst} (73%)
 rename generators/{sifive-blocks => rocket-chip-blocks} (100%)
 rename generators/{sifive-cache => rocket-chip-inclusive-cache} (100%)

diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
index d3b856c87e..a4a95611d4 100755
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -45,7 +45,7 @@ search () {
     done
 }
 
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
 dir="generators"
 branches=("master" "main" "dev")
 search
diff --git a/.gitmodules b/.gitmodules
index e1768873f7..b047c8388b 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,9 +13,6 @@
 [submodule "generators/boom"]
 	path = generators/boom
 	url = https://github.com/riscv-boom/riscv-boom.git
-[submodule "generators/sifive-blocks"]
-	path = generators/sifive-blocks
-	url = https://github.com/chipsalliance/rocket-chip-blocks.git
 [submodule "generators/hwacha"]
 	path = generators/hwacha
 	url = https://github.com/ucb-bar/hwacha.git
@@ -25,9 +22,6 @@
 [submodule "generators/icenet"]
 	path = generators/icenet
 	url = https://github.com/firesim/icenet.git
-[submodule "generators/block-inclusivecache-sifive"]
-	path = generators/sifive-cache
-	url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
 [submodule "tools/dsptools"]
 	path = tools/dsptools
 	url = https://github.com/ucb-bar/dsptools.git
@@ -145,3 +139,9 @@
 [submodule "toolchains/riscv-tools/riscv-spike-devices"]
 	path = toolchains/riscv-tools/riscv-spike-devices
 	url = https://github.com/ucb-bar/spike-devices.git
+[submodule "generators/rocket-chip-blocks"]
+	path = generators/rocket-chip-blocks
+	url = https://github.com/chipsalliance/rocket-chip-blocks.git
+[submodule "generators/rocket-chip-inclusive-cache"]
+	path = generators/rocket-chip-inclusive-cache
+	url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
diff --git a/build.sbt b/build.sbt
index c3be6161ef..51fd6b09ce 100644
--- a/build.sbt
+++ b/build.sbt
@@ -141,12 +141,12 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
 
 lazy val testchipip = (project in file("generators/testchipip"))
-  .dependsOn(rocketchip, sifive_blocks)
+  .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
 lazy val chipyard = (project in file("generators/chipyard"))
-  .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+  .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
@@ -180,7 +180,7 @@ lazy val fft_generator = (project in file("generators/fft-generator"))
   .settings(commonSettings)
 
 lazy val tracegen = (project in file("generators/tracegen"))
-  .dependsOn(testchipip, rocketchip, sifive_cache, boom)
+  .dependsOn(testchipip, rocketchip, rocketchip_inclusive_cache, boom)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -279,12 +279,12 @@ lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocke
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
+lazy val rocketchip_blocks = (project in file("generators/rocket-chip-blocks"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sifive_cache = (project in file("generators/sifive-cache"))
+lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-inclusive-cache"))
   .settings(
     commonSettings,
     Compile / scalaSource := baseDirectory.value / "design/craft")
@@ -304,7 +304,7 @@ lazy val firechip = (project in file("generators/firechip"))
     Test / testOptions += Tests.Argument("-oF")
   )
 lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
-  .dependsOn(rocketchip, sifive_blocks)
+  .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst
index 8f8e90455f..222d37df37 100644
--- a/docs/Chipyard-Basics/Chipyard-Components.rst
+++ b/docs/Chipyard-Basics/Chipyard-Components.rst
@@ -53,9 +53,9 @@ System Components:
 **icenet**
   A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.
 
-**sifive-blocks**
-  System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
-  These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
+**rocket-chip-blocks**
+  System components originally implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
+  Now maintained by Chips Alliance. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
 
 **AWL (Analog Widget Library)**
   Digital components required for integration with high speed serial links.
diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst
index 121ca712e3..a3b4ef72c3 100644
--- a/docs/Customization/Custom-Chisel.rst
+++ b/docs/Customization/Custom-Chisel.rst
@@ -59,7 +59,7 @@ should look something like this:
 .. code-block:: scala
 
     lazy val chipyard = (project in file("generators/chipyard"))
-        .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+        .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
             sha3, dsptools, `rocket-dsp-utils`,
             gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
             yourproject, // <- added to the middle of the list for simplicity
diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst
index ecb666d1f9..11bc132ba5 100644
--- a/docs/Customization/Memory-Hierarchy.rst
+++ b/docs/Customization/Memory-Hierarchy.rst
@@ -46,17 +46,17 @@ agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, but
 a network-on-chip-based implementation can be generated using Constellation.
 See :ref:`Customization/NoC-SoCs:SoCs with NoC-based Interconnects` for more.
 
-The SiFive L2 Cache
--------------------
+The Inclusive Last-Level Cache
+---------------------------------
 
-The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's
+The default ``RocketConfig`` provided in the Chipyard example project uses the Rocket-Chip
 InclusiveCache generator to produce a shared L2 cache. In the default
 configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way
 set-associativity. However, you can change these parameters to obtain your
 desired cache configuration. The main restriction is that the number of ways
 and the number of banks must be powers of 2.
 
-Refer to the ``CacheParameters`` object defined in sifive-cache for
+Refer to the ``CacheParameters`` object defined in ``rocket-chip-inclusive-cache`` for
 customization options.
 
 The Broadcast Hub
diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/Rocket-Chip-Generators.rst
similarity index 73%
rename from docs/Generators/SiFive-Generators.rst
rename to docs/Generators/Rocket-Chip-Generators.rst
index d6b174ef58..66dd66a020 100644
--- a/docs/Generators/SiFive-Generators.rst
+++ b/docs/Generators/Rocket-Chip-Generators.rst
@@ -1,19 +1,19 @@
-SiFive Generators
+Rocket-Chip Generators
 ==================
 
-Chipyard includes several open-source generators developed and maintained by `SiFive <https://www.sifive.com/>`__.
-These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``.
+Chipyard includes several open-source generators developed by `SiFive <https://www.sifive.com/>`__, and now openly maintained as part of Chips Alliance.
+These are currently organized within two submodules named ``rocket-chip-blocks`` and ``rocket-chip-inclusive-cache``.
 
 Last-Level Cache Generator
 -----------------------------
 
-``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
+``rocket-chip-inclusive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
 To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
 
 
 Peripheral Devices Overview
 ----------------------------
-``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
+``rocket-chip-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
 
 These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
 All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device.
@@ -34,7 +34,7 @@ Finally, you add the relevant config fragment to the SoC config. For example:
 General Purpose I/Os (GPIO) Device
 ----------------------------------
 
-GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
+GPIO device is a periphery device provided by ``rocket-chip-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
 
 
 GPIO main features
@@ -78,7 +78,7 @@ Including GPIO in the SoC
 Universal Asynchronous Receiver/Transmitter (UART) Device
 ----------------------------------------------------------
 
-UART device is a periphery device provided by ``sifive-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
+UART device is a periphery device provided by ``rocket-chip-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
 
 
 UART main features
@@ -125,7 +125,7 @@ Including UART in the SoC
 Inter-Integrated Circuit (I2C) Interface Device
 -------------------------------------------------
 
-I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
+I2C device is a periphery device provided by ``rocket-chip-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
 
 
 I2C main features
@@ -169,7 +169,7 @@ Including I2C in the SoC
 Serial Peripheral Interface (SPI) Device
 -------------------------------------------------
 
-SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
+SPI device is a periphery device provided by ``rocket-chip-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
 
 The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device.
 
diff --git a/docs/Generators/Rocket-Chip.rst b/docs/Generators/Rocket-Chip.rst
index 856d01e154..3e40493932 100644
--- a/docs/Generators/Rocket-Chip.rst
+++ b/docs/Generators/Rocket-Chip.rst
@@ -1,8 +1,8 @@
 Rocket Chip
 ===========
 
-Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
-`SiFive <https://www.sifive.com>`__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
+Rocket Chip generator is an SoC generator developed at Berkeley and SiFive, and now maintained openly in Chips Alliance.
+Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
 
 `Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
 Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip
diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst
index 6c55b76140..536d699141 100644
--- a/docs/Generators/Rocket.rst
+++ b/docs/Generators/Rocket.rst
@@ -1,7 +1,7 @@
 Rocket Core
 ====================================
 
-`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive <https://www.sifive.com/>`__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
+`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and `SiFive <https://www.sifive.com/>`__, and now maintained by Chips Alliance. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
 
 The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
 It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst
index c2bf3719d6..651a6bae9e 100644
--- a/docs/Generators/index.rst
+++ b/docs/Generators/index.rst
@@ -26,7 +26,7 @@ so changes to the generators themselves will automatically be used when building
    Gemmini
    IceNet
    TestChipIP
-   SiFive-Generators
+   Rocket-Chip-Generators
    SHA3
    CVA6
    Ibex
diff --git a/fpga/Makefile b/fpga/Makefile
index cfe760f4a0..a4d3bf99f8 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -137,7 +137,7 @@ include $(base_dir)/common.mk
 # copy from other directory
 #########################################################################################
 all_vsrcs := \
-	$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
+	$(base_dir)/generators/rocket-chip-blocks/vsrc/SRLatch.v
 
 #########################################################################################
 # vivado rules
diff --git a/generators/sifive-blocks b/generators/rocket-chip-blocks
similarity index 100%
rename from generators/sifive-blocks
rename to generators/rocket-chip-blocks
diff --git a/generators/sifive-cache b/generators/rocket-chip-inclusive-cache
similarity index 100%
rename from generators/sifive-cache
rename to generators/rocket-chip-inclusive-cache
diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch
index e47fbbf6b8..b64d7a4393 100644
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -5,7 +5,7 @@ index c3be6161..2a6d7160 100644
 @@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
  
  lazy val chipyard = (project in file("generators/chipyard"))
-   .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+   .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +    //sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, rocket_dsp_utils,
diff --git a/sims/firesim b/sims/firesim
index e975893595..0443e53fcb 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit e975893595129c2682a72fb7e5898273fcc2d071
+Subproject commit 0443e53fcbf5dad4a51bcbdcf6c7556e86e81deb

From 46585a5114f521dc45e4b0c31f374105afaaeee4 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 5 Jan 2024 11:14:38 -0800
Subject: [PATCH 26/31] Fix check-submodule-status forcing rebuilds

---
 common.mk | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/common.mk b/common.mk
index c4ae8548e8..3763584ff1 100644
--- a/common.mk
+++ b/common.mk
@@ -84,6 +84,8 @@ endif
 # Returns a list of files in directories $1 with *any* of the file extensions in $2
 lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type)))
 
+CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep ^-
+
 SCALA_EXT = scala
 VLOG_EXT = sv v
 CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
@@ -119,7 +121,8 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 #########################################################################################
 # compile scala jars
 #########################################################################################
-$(CHIPYARD_CLASSPATH_TARGETS) &: check-submodule-status $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
+$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
+	$(CHECK_SUBMODULES_COMMAND)
 	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
 
@@ -458,8 +461,7 @@ help:
 
 .PHONY: check-submodule-status
 check-submodule-status:
-	echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed"
-	! git submodule status $(base_dir)/generators | grep ^-
+	$(CHECK_SUBMODULES_COMMAND)
 
 #########################################################################################
 # Implicit rule handling

From 9f45c49f04979f352035770d60e948edd720d9b7 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 5 Jan 2024 11:51:17 -0800
Subject: [PATCH 27/31] Fix docs

---
 docs/Generators/Rocket-Chip-Generators.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Generators/Rocket-Chip-Generators.rst b/docs/Generators/Rocket-Chip-Generators.rst
index 66dd66a020..435fa1ddd3 100644
--- a/docs/Generators/Rocket-Chip-Generators.rst
+++ b/docs/Generators/Rocket-Chip-Generators.rst
@@ -1,5 +1,5 @@
 Rocket-Chip Generators
-==================
+======================
 
 Chipyard includes several open-source generators developed by `SiFive <https://www.sifive.com/>`__, and now openly maintained as part of Chips Alliance.
 These are currently organized within two submodules named ``rocket-chip-blocks`` and ``rocket-chip-inclusive-cache``.

From 2f1ee6bb326451e9eb95675019e97cb76fd7d850 Mon Sep 17 00:00:00 2001
From: Tynan McAuley <tynan@niobiummicrosystems.com>
Date: Fri, 5 Jan 2024 12:15:48 -0800
Subject: [PATCH 28/31] Allow sed override in uniquify-module-names.py

On macOS, this can be set to `gsed` to allow use of the `-i` flag.
---
 scripts/uniquify-module-names.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py
index 237054f270..0ddea49f6b 100755
--- a/scripts/uniquify-module-names.py
+++ b/scripts/uniquify-module-names.py
@@ -21,6 +21,7 @@
 args = parser.parse_args()
 
 MODEL_SFX=args.model + "_UNIQUIFIED"
+SED=os.environ.get("SED", "sed")
 
 
 def bash(cmd):
@@ -109,7 +110,7 @@ def generate_copy(c, sfx):
   new_file = os.path.join(args.gcpath, new_file)
 
   shutil.copy(cur_file, new_file)
-  bash(f"sed -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
+  bash(f"{SED} -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
   return new_file
 
 def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
@@ -136,7 +137,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
         new_file = generate_copy(cur_file, MODEL_SFX)
         if parent is not None and ((parent, mod) not in updated_submodule):
           parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
-          bash(f"sed -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
+          bash(f"{SED} -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
           updated_submodule.add((parent, mod))
 
         # add the uniquified module to the verilog_modul_filename dict

From ba560002dc87ce988881ead81154781de108b745 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Sat, 6 Jan 2024 18:23:02 -0800
Subject: [PATCH 29/31] Add Baremetal IDE support (#1534)

---
 .gitmodules            | 3 +++
 software/baremetal-ide | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 software/baremetal-ide

diff --git a/.gitmodules b/.gitmodules
index e1768873f7..ac7a790ef5 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -64,6 +64,9 @@
 [submodule "software/nvdla-workload"]
 	path = software/nvdla-workload
 	url = https://github.com/ucb-bar/nvdla-workload.git
+[submodule "software/baremetal-ide"]
+	path = software/baremetal-ide
+	url = https://github.com/ucb-bar/Baremetal-IDE.git
 [submodule "generators/riscv-sodor"]
 	path = generators/riscv-sodor
 	url = https://github.com/ucb-bar/riscv-sodor.git
diff --git a/software/baremetal-ide b/software/baremetal-ide
new file mode 160000
index 0000000000..f488090a7f
--- /dev/null
+++ b/software/baremetal-ide
@@ -0,0 +1 @@
+Subproject commit f488090a7f37da43610bd5017ee401526bf40fb2

From 3a00005d8977096e683918f985e0813622ebf295 Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Sat, 6 Jan 2024 21:58:22 -0800
Subject: [PATCH 30/31] ADD: add information on Baremetal-IDE

---
 docs/Chipyard-Basics/Chipyard-Components.rst | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst
index 8f8e90455f..72735e164d 100644
--- a/docs/Chipyard-Basics/Chipyard-Components.rst
+++ b/docs/Chipyard-Basics/Chipyard-Components.rst
@@ -106,6 +106,9 @@ Software
   FireMarshal is the default workload generation tool that Chipyard uses to create software to run on its platforms.
   See :ref:`fire-marshal` for more information.
 
+**Baremetal-IDE**
+  Baremetal-IDE is an all-in-one tool for baremetal-level C/C++ program developments. See `Tutorial <https://ucb-bar.gitbook.io/chipyard/baremetal-ide/getting-started-with-baremetal-ide/>`_ for more information.
+
 Sims
 -------------------------------------------
 

From 33c96703868430589fc463172ef6fd5c3314567c Mon Sep 17 00:00:00 2001
From: "-T.K.-" <t_k_233@outlook.com>
Date: Sat, 6 Jan 2024 22:16:39 -0800
Subject: [PATCH 31/31] Update docs/Chipyard-Basics/Chipyard-Components.rst

Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>
---
 docs/Chipyard-Basics/Chipyard-Components.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst
index 72735e164d..34e983b3d2 100644
--- a/docs/Chipyard-Basics/Chipyard-Components.rst
+++ b/docs/Chipyard-Basics/Chipyard-Components.rst
@@ -107,7 +107,7 @@ Software
   See :ref:`fire-marshal` for more information.
 
 **Baremetal-IDE**
-  Baremetal-IDE is an all-in-one tool for baremetal-level C/C++ program developments. See `Tutorial <https://ucb-bar.gitbook.io/chipyard/baremetal-ide/getting-started-with-baremetal-ide/>`_ for more information.
+  Baremetal-IDE is an all-in-one tool for baremetal-level C/C++ program development. See `Tutorial <https://ucb-bar.gitbook.io/chipyard/baremetal-ide/getting-started-with-baremetal-ide/>`_ for more information.
 
 Sims
 -------------------------------------------