From 7c1357476920dbccc2065827e3f3457e096d4fec Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 4 Jan 2024 14:09:54 -0800 Subject: [PATCH 1/2] Rename cache/blocks submodules to match new chipsalliance ownership --- .github/scripts/check-commit.sh | 2 +- .gitmodules | 12 ++++++------ build.sbt | 12 ++++++------ docs/Chipyard-Basics/Chipyard-Components.rst | 6 +++--- docs/Customization/Custom-Chisel.rst | 2 +- docs/Customization/Memory-Hierarchy.rst | 8 ++++---- ...nerators.rst => Rocket-Chip-Generators.rst} | 18 +++++++++--------- docs/Generators/Rocket-Chip.rst | 4 ++-- docs/Generators/Rocket.rst | 2 +- docs/Generators/index.rst | 2 +- fpga/Makefile | 2 +- .../{sifive-blocks => rocket-chip-blocks} | 0 ...ifive-cache => rocket-chip-inclusive-cache} | 0 scripts/tutorial-patches/build.sbt.patch | 2 +- sims/firesim | 2 +- 15 files changed, 37 insertions(+), 37 deletions(-) rename docs/Generators/{SiFive-Generators.rst => Rocket-Chip-Generators.rst} (73%) rename generators/{sifive-blocks => rocket-chip-blocks} (100%) rename generators/{sifive-cache => rocket-chip-inclusive-cache} (100%) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index d3b856c87e..a4a95611d4 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils") dir="generators" branches=("master" "main" "dev") search diff --git a/.gitmodules b/.gitmodules index e1768873f7..b047c8388b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,9 +13,6 @@ [submodule "generators/boom"] path = generators/boom url = https://github.com/riscv-boom/riscv-boom.git -[submodule "generators/sifive-blocks"] - path = generators/sifive-blocks - url = https://github.com/chipsalliance/rocket-chip-blocks.git [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git @@ -25,9 +22,6 @@ [submodule "generators/icenet"] path = generators/icenet url = https://github.com/firesim/icenet.git -[submodule "generators/block-inclusivecache-sifive"] - path = generators/sifive-cache - url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git [submodule "tools/dsptools"] path = tools/dsptools url = https://github.com/ucb-bar/dsptools.git @@ -145,3 +139,9 @@ [submodule "toolchains/riscv-tools/riscv-spike-devices"] path = toolchains/riscv-tools/riscv-spike-devices url = https://github.com/ucb-bar/spike-devices.git +[submodule "generators/rocket-chip-blocks"] + path = generators/rocket-chip-blocks + url = https://github.com/chipsalliance/rocket-chip-blocks.git +[submodule "generators/rocket-chip-inclusive-cache"] + path = generators/rocket-chip-inclusive-cache + url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git diff --git a/build.sbt b/build.sbt index c3be6161ef..51fd6b09ce 100644 --- a/build.sbt +++ b/build.sbt @@ -141,12 +141,12 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies) lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") lazy val testchipip = (project in file("generators/testchipip")) - .dependsOn(rocketchip, sifive_blocks) + .dependsOn(rocketchip, rocketchip_blocks) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, + .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, @@ -180,7 +180,7 @@ lazy val fft_generator = (project in file("generators/fft-generator")) .settings(commonSettings) lazy val tracegen = (project in file("generators/tracegen")) - .dependsOn(testchipip, rocketchip, sifive_cache, boom) + .dependsOn(testchipip, rocketchip, rocketchip_inclusive_cache, boom) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) @@ -279,12 +279,12 @@ lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocke .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sifive_blocks = (project in file("generators/sifive-blocks")) +lazy val rocketchip_blocks = (project in file("generators/rocket-chip-blocks")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val sifive_cache = (project in file("generators/sifive-cache")) +lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-inclusive-cache")) .settings( commonSettings, Compile / scalaSource := baseDirectory.value / "design/craft") @@ -304,7 +304,7 @@ lazy val firechip = (project in file("generators/firechip")) Test / testOptions += Tests.Argument("-oF") ) lazy val fpga_shells = (project in file("./fpga/fpga-shells")) - .dependsOn(rocketchip, sifive_blocks) + .dependsOn(rocketchip, rocketchip_blocks) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 8f8e90455f..222d37df37 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -53,9 +53,9 @@ System Components: **icenet** A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. -**sifive-blocks** - System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator. - These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. +**rocket-chip-blocks** + System components originally implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator. + Now maintained by Chips Alliance. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. **AWL (Analog Widget Library)** Digital components required for integration with high speed serial links. diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst index 121ca712e3..a3b4ef72c3 100644 --- a/docs/Customization/Custom-Chisel.rst +++ b/docs/Customization/Custom-Chisel.rst @@ -59,7 +59,7 @@ should look something like this: .. code-block:: scala lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, + .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, sha3, dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, yourproject, // <- added to the middle of the list for simplicity diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index ecb666d1f9..11bc132ba5 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -46,17 +46,17 @@ agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, but a network-on-chip-based implementation can be generated using Constellation. See :ref:`Customization/NoC-SoCs:SoCs with NoC-based Interconnects` for more. -The SiFive L2 Cache -------------------- +The Inclusive Last-Level Cache +--------------------------------- -The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's +The default ``RocketConfig`` provided in the Chipyard example project uses the Rocket-Chip InclusiveCache generator to produce a shared L2 cache. In the default configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way set-associativity. However, you can change these parameters to obtain your desired cache configuration. The main restriction is that the number of ways and the number of banks must be powers of 2. -Refer to the ``CacheParameters`` object defined in sifive-cache for +Refer to the ``CacheParameters`` object defined in ``rocket-chip-inclusive-cache`` for customization options. The Broadcast Hub diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/Rocket-Chip-Generators.rst similarity index 73% rename from docs/Generators/SiFive-Generators.rst rename to docs/Generators/Rocket-Chip-Generators.rst index d6b174ef58..66dd66a020 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/Rocket-Chip-Generators.rst @@ -1,19 +1,19 @@ -SiFive Generators +Rocket-Chip Generators ================== -Chipyard includes several open-source generators developed and maintained by `SiFive `__. -These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``. +Chipyard includes several open-source generators developed by `SiFive `__, and now openly maintained as part of Chips Alliance. +These are currently organized within two submodules named ``rocket-chip-blocks`` and ``rocket-chip-inclusive-cache``. Last-Level Cache Generator ----------------------------- -``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration. +``rocket-chip-inclusive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration. To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section. Peripheral Devices Overview ---------------------------- -``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more. +``rocket-chip-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more. These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device. @@ -34,7 +34,7 @@ Finally, you add the relevant config fragment to the SoC config. For example: General Purpose I/Os (GPIO) Device ---------------------------------- -GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers. +GPIO device is a periphery device provided by ``rocket-chip-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers. GPIO main features @@ -78,7 +78,7 @@ Including GPIO in the SoC Universal Asynchronous Receiver/Transmitter (UART) Device ---------------------------------------------------------- -UART device is a periphery device provided by ``sifive-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers. +UART device is a periphery device provided by ``rocket-chip-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers. UART main features @@ -125,7 +125,7 @@ Including UART in the SoC Inter-Integrated Circuit (I2C) Interface Device ------------------------------------------------- -I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+). +I2C device is a periphery device provided by ``rocket-chip-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+). I2C main features @@ -169,7 +169,7 @@ Including I2C in the SoC Serial Peripheral Interface (SPI) Device ------------------------------------------------- -SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol. +SPI device is a periphery device provided by ``rocket-chip-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol. The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device. diff --git a/docs/Generators/Rocket-Chip.rst b/docs/Generators/Rocket-Chip.rst index 856d01e154..3e40493932 100644 --- a/docs/Generators/Rocket-Chip.rst +++ b/docs/Generators/Rocket-Chip.rst @@ -1,8 +1,8 @@ Rocket Chip =========== -Rocket Chip generator is an SoC generator developed at Berkeley and now supported by -`SiFive `__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC. +Rocket Chip generator is an SoC generator developed at Berkeley and SiFive, and now maintained openly in Chips Alliance. +Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC. `Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator. Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst index 6c55b76140..536d699141 100644 --- a/docs/Generators/Rocket.rst +++ b/docs/Generators/Rocket.rst @@ -1,7 +1,7 @@ Rocket Core ==================================== -`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive `__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`. +`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and `SiFive `__, and now maintained by Chips Alliance. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`. The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language. It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index c2bf3719d6..651a6bae9e 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -26,7 +26,7 @@ so changes to the generators themselves will automatically be used when building Gemmini IceNet TestChipIP - SiFive-Generators + Rocket-Chip-Generators SHA3 CVA6 Ibex diff --git a/fpga/Makefile b/fpga/Makefile index cfe760f4a0..a4d3bf99f8 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -137,7 +137,7 @@ include $(base_dir)/common.mk # copy from other directory ######################################################################################### all_vsrcs := \ - $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v + $(base_dir)/generators/rocket-chip-blocks/vsrc/SRLatch.v ######################################################################################### # vivado rules diff --git a/generators/sifive-blocks b/generators/rocket-chip-blocks similarity index 100% rename from generators/sifive-blocks rename to generators/rocket-chip-blocks diff --git a/generators/sifive-cache b/generators/rocket-chip-inclusive-cache similarity index 100% rename from generators/sifive-cache rename to generators/rocket-chip-inclusive-cache diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index e47fbbf6b8..b64d7a4393 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -5,7 +5,7 @@ index c3be6161..2a6d7160 100644 @@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell, + .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches + //sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, rocket_dsp_utils, diff --git a/sims/firesim b/sims/firesim index e975893595..0443e53fcb 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e975893595129c2682a72fb7e5898273fcc2d071 +Subproject commit 0443e53fcbf5dad4a51bcbdcf6c7556e86e81deb From 9f45c49f04979f352035770d60e948edd720d9b7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 5 Jan 2024 11:51:17 -0800 Subject: [PATCH 2/2] Fix docs --- docs/Generators/Rocket-Chip-Generators.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Generators/Rocket-Chip-Generators.rst b/docs/Generators/Rocket-Chip-Generators.rst index 66dd66a020..435fa1ddd3 100644 --- a/docs/Generators/Rocket-Chip-Generators.rst +++ b/docs/Generators/Rocket-Chip-Generators.rst @@ -1,5 +1,5 @@ Rocket-Chip Generators -================== +====================== Chipyard includes several open-source generators developed by `SiFive `__, and now openly maintained as part of Chips Alliance. These are currently organized within two submodules named ``rocket-chip-blocks`` and ``rocket-chip-inclusive-cache``.