From 1527f981ec94d9818b0f3a52375a072969f79a03 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 26 Oct 2023 16:41:04 -0700 Subject: [PATCH] Fix port to port.io --- generators/firechip/src/main/scala/BridgeBinders.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 8c351246a9..8500edee81 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -89,8 +89,8 @@ class WithDMIBridge extends HarnessBinder({ // If FASED bridge is attached, loadmem widget is present val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx))) - val nDMIAddrBits = port.dmi.req.bits.addr.getWidth - DMIBridge(th.harnessBinderClock, port, mainMemoryName, th.harnessBinderReset.asBool, nDMIAddrBits) + val nDMIAddrBits = port.io.dmi.req.bits.addr.getWidth + DMIBridge(th.harnessBinderClock, port.io, mainMemoryName, th.harnessBinderReset.asBool, nDMIAddrBits) } })