From 127a7596296cea636dd891226f1c4544bcc31f62 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Fri, 20 Oct 2023 15:07:18 -0700
Subject: [PATCH] Bump rocket-chip
---
.../chipyard/src/main/scala/config/AbstractConfig.scala | 2 +-
.../chipyard/src/main/scala/config/TracegenConfigs.scala | 3 ++-
generators/rocket-chip | 2 +-
generators/tracegen/src/main/scala/System.scala | 6 ++++--
4 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index 140f74fb7..bc09862ef 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -53,7 +53,7 @@ class AbstractConfig extends Config(
// By default, punch out IOs to the Harness
new chipyard.clocking.WithPassthroughClockGenerator ++
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index 78c815fb9..77408a96e 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -12,10 +12,11 @@ class AbstractTraceGenConfig extends Config(
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
new chipyard.clocking.WithPassthroughClockGenerator ++
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++
new chipyard.config.WithTracegenSystem ++
new chipyard.config.WithNoSubsystemClockIO ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
+ new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 8881ccd1c..0e88fc066 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 8881ccd1cab941ed0a0981c00361b1415027f8ce
+Subproject commit 0e88fc066e293b0da45da7360afd4cd3e6399678
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index b25225c7d..488054d37 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -23,11 +23,13 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
case t: BoomTraceGenTile => t.statusNode.makeSink()
}
+ lazy val fakeClockDomain = sbus.generateSynchronousDomain
+
lazy val clintOpt = None
lazy val debugOpt = None
lazy val plicOpt = None
- lazy val clintDomainOpt = None
- lazy val plicDomainOpt = None
+ lazy val clintDomainOpt = Some(fakeClockDomain)
+ lazy val plicDomainOpt = Some(fakeClockDomain)
override lazy val module = new TraceGenSystemModuleImp(this)
}