From 0de940b6a0d6acb8199f1159da98ebd97408ee2e Mon Sep 17 00:00:00 2001 From: Mihai Tudor Date: Sat, 16 Sep 2023 19:48:59 -0700 Subject: [PATCH] Updated docs on waveform generation --- docs/Simulation/Software-RTL-Simulation.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 580a5d2e09..86d8a07c56 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -177,8 +177,8 @@ A special target that automatically generates the waveform file for a specific t For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. An open-source vcd-capable waveform viewer is `GTKWave `__. -For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. -If you have Synopsys licenses, we recommend using the DVE waveform viewer. +For a VCS simulation, this will generate an fsdb file (fast signal database, a proprietary waveform representation format developed by Novas Software, later acquired by Synopsys) that can be loaded to fsdb-supported waveform viewers. +If you have Synopsys licenses, we recommend using the Verdi waveform viewer. Visualizing Chipyard SoCs --------------------------