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b/OA/bag3_analog/tia_term/symbol/thumbnail_128x128.png new file mode 100644 index 0000000..88feed7 Binary files /dev/null and b/OA/bag3_analog/tia_term/symbol/thumbnail_128x128.png differ diff --git a/src/bag3_analog/layout/tia/buf_cmos_cell.py b/src/bag3_analog/layout/tia/buf_cmos_cell.py new file mode 100644 index 0000000..08e74a7 --- /dev/null +++ b/src/bag3_analog/layout/tia/buf_cmos_cell.py @@ -0,0 +1,515 @@ +## SPDX-License-Identifier: BSD-3-Clause AND Apache-2.0 +# Copyright 2018 Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +"""This module contains layout generators for pseudo differential inverters.""" + +from typing import Any, Dict, Type, Optional, List, Sequence + +from pybag.enum import MinLenMode, RoundMode + +from bag.typing import TrackType +from bag.util.immutable import Param +from bag.layout.template import TemplateDB +from bag.layout.routing.base import TrackID, WireArray +from bag.design.module import Module + +from xbase.layout.enum import MOSWireType, SubPortMode +from xbase.layout.mos.base import MOSBasePlaceInfo, MOSBase +from xbase.layout.mos.guardring import GuardRing + +from bag3_digital.layout.stdcells.gates import InvCore + +from bag.layout.enum import DrawTaps +from ...schematic.buf_cmos_cell import bag3_analog__buf_cmos_cell + +from .util import max_conn_wires + + +class BufCMOS(MOSBase): + """The core of the pseudo differential inverters + """ + + def __init__(self, temp_db: TemplateDB, params: Param, **kwargs: Any) -> None: + MOSBase.__init__(self, temp_db, params, **kwargs) + + @classmethod + def get_schematic_class(cls) -> Optional[Type[Module]]: + return bag3_analog__buf_cmos_cell + + @classmethod + def get_params_info(cls) -> Dict[str, str]: + return dict( + pinfo='The MOSBasePlaceInfo object.', + seg_p='segments of pmos', + seg_n='segments of nmos', + w_p='pmos width.', + w_n='nmos width.', + ridx_p='pmos row index.', + ridx_n='nmos row index.', + show_pins='True to show pins', + flip_tile='True to flip all tiles', + draw_taps='LEFT or RIGHT or BOTH or NONE', + sig_locs='Signal locations for top horizontal metal layer pins', + ndum='number of dummy at one side, need even number' + ) + + @classmethod + def get_default_param_values(cls) -> Dict[str, Any]: + return dict( + seg_p=-1, + seg_n=-1, + w_p=0, + w_n=0, + ridx_p=-1, + ridx_n=0, + show_pins=False, + flip_tile=False, + draw_taps='NONE', + sig_locs={}, + ndum=0, + ) + + def draw_layout(self) -> None: + pinfo = MOSBasePlaceInfo.make_place_info(self.grid, self.params['pinfo']) + self.draw_base(pinfo, flip_tile=self.params['flip_tile']) + + seg_p: int = self.params['seg_p'] + seg_n: int = self.params['seg_n'] + ridx_p: int = self.params['ridx_p'] + ridx_n: int = self.params['ridx_n'] + ndum: int = self.params['ndum'] + draw_taps: DrawTaps = DrawTaps[self.params['draw_taps']] + sig_locs: Dict[str, TrackType] = self.params['sig_locs'] + + for val in [seg_p, seg_n, ndum]: + if val % 2: + raise ValueError(f'This generator does not support odd number of segments ') + + tr_manager = self.tr_manager + hm_layer = self.conn_layer + 1 + vm_layer = hm_layer + 1 + xm_layer = vm_layer + 1 + + inv_params = self.params.copy(append=dict(is_guarded=True, show_pins=False, vertical_out=False)) + inv_master = self.new_template(InvCore, params=inv_params) + inv_ncol = inv_master.num_cols + + # taps + sub_sep = self.sub_sep_col + 2 + sup_info = self.get_supply_column_info(xm_layer) + num_taps = 0 + tap_offset = 0 + tap_left = tap_right = False + if draw_taps in DrawTaps.RIGHT | DrawTaps.BOTH: + num_taps += 1 + tap_right = True + if draw_taps in DrawTaps.LEFT | DrawTaps.BOTH: + num_taps += 1 + tap_offset += sup_info.ncol + sub_sep // 2 + tap_left = True + + # set total number of columns + # Total width can be limited by either transistor size or by vertical metal size + seg_max = 2 * max(seg_p, seg_n) + seg_tot = seg_max + (sup_info.ncol + sub_sep // 2) * num_taps + 2 * ndum + + + # --- Placement --- # + cur_col = tap_offset + if ndum > 0: + nmos_dum_p = self.add_mos(ridx_n, cur_col, ndum, tile_idx=0) + pmos_dum_p = self.add_mos(ridx_p, cur_col, ndum, tile_idx=0) + cur_col += ndum + inst_p = self.add_tile(inv_master, 0, cur_col) + cur_col += 2 * inv_ncol + mid_idx = self.arr_info.col_to_track(vm_layer, cur_col - inv_ncol, mode=RoundMode.NEAREST) + inst_n = self.add_tile(inv_master, 0, cur_col, flip_lr=True) + if ndum > 0: + cur_col += ndum + nmos_dum_n = self.add_mos(ridx_n, cur_col, ndum, tile_idx=0, flip_lr=True) + pmos_dum_n = self.add_mos(ridx_p, cur_col, ndum, tile_idx=0, flip_lr=True) + # add taps + lay_range = range(self.conn_layer, xm_layer + 1) + vdd_table: Dict[int, List[WireArray]] = {lay: [] for lay in lay_range} + vss_table: Dict[int, List[WireArray]] = {lay: [] for lay in lay_range} + if tap_left: + self.add_supply_column(sup_info, 0, vdd_table, vss_table) + if tap_right: + self.add_supply_column(sup_info, seg_tot, vdd_table, vss_table, flip_lr=True) + self.set_mos_size() + + # --- Routing --- # + # 1. supplies + vdd_table[hm_layer].append(inst_p.get_pin('VDD', layer=hm_layer)) + vdd_table[hm_layer].append(inst_n.get_pin('VDD', layer=hm_layer)) + self.add_pin('VDD_conn', vdd_table[self.conn_layer], hide=True) + self.add_pin('VDD_hm', vdd_table[hm_layer], hide=True) + self.add_pin('VDD_vm', vdd_table[vm_layer], hide=True) + self.add_pin('VDDA', self.connect_wires(vdd_table[xm_layer])) + + vss_table[hm_layer].append(inst_p.get_pin('VSS', layer=hm_layer)) + vss_table[hm_layer].append(inst_n.get_pin('VSS', layer=hm_layer)) + self.add_pin('VSS_conn', vss_table[self.conn_layer], hide=True) + self.add_pin('VSS_hm', vss_table[hm_layer], hide=True) + self.add_pin('VSS_vm', vss_table[vm_layer], hide=True) + self.add_pin('VSS', self.connect_wires(vss_table[xm_layer])) + + vdd = self.connect_wires(vdd_table[hm_layer])[0] + vss = self.connect_wires(vss_table[hm_layer])[0] + tr_w_h = self.tr_manager.get_width(hm_layer, 'sig') + tr_w_v = self.tr_manager.get_width(vm_layer, 'sig') + if ndum > 0: + # connect dummy + pmos_port, nmos_port = [], [] + for pmos, nmos in zip([pmos_dum_n, pmos_dum_p], [nmos_dum_n, nmos_dum_p]): + pmos_port += [pmos.s] + nmos_port += [nmos.s] + self.connect_to_track_wires(pmos_port, vdd) + self.connect_to_track_wires(nmos_port, vss) + # connect g&d to VDD/VSS with M3 + nout_tidx = sig_locs.get('nout', self.get_track_index(ridx_n, MOSWireType.DS_GATE, + wire_name='sig', wire_idx=-1)) + pout_tidx = sig_locs.get('pout', self.get_track_index(ridx_p, MOSWireType.DS_GATE, + wire_name='sig', wire_idx=0)) + nout_tid = TrackID(hm_layer, nout_tidx, tr_w_h) + pout_tid = TrackID(hm_layer, pout_tidx, tr_w_h) + # left (p) + pmos_p_hm = self.connect_to_tracks([pmos_dum_p.g, pmos_dum_p.d], pout_tid, min_len_mode=MinLenMode.LOWER) + nmos_p_hm = self.connect_to_tracks([nmos_dum_p.g, nmos_dum_p.d], nout_tid, min_len_mode=MinLenMode.LOWER) + tidx_p_vm = self.grid.coord_to_track(vm_layer, pmos_p_hm.lower, mode=RoundMode.NEAREST) + self.connect_to_tracks([pmos_p_hm, vdd], TrackID(vm_layer, tidx_p_vm, width=tr_w_v)) + self.connect_to_tracks([nmos_p_hm, vss], TrackID(vm_layer, tidx_p_vm, width=tr_w_v)) + pmos_n_hm = self.connect_to_tracks([pmos_dum_n.g, pmos_dum_n.d], pout_tid, min_len_mode=MinLenMode.UPPER) + nmos_n_hm = self.connect_to_tracks([nmos_dum_n.g, nmos_dum_n.d], nout_tid, min_len_mode=MinLenMode.UPPER) + tidx_n_vm = self.grid.coord_to_track(vm_layer, pmos_n_hm.upper, mode=RoundMode.NEAREST) + self.connect_to_tracks([pmos_n_hm, vdd], TrackID(vm_layer, tidx_n_vm, width=tr_w_v)) + self.connect_to_tracks([nmos_n_hm, vss], TrackID(vm_layer, tidx_n_vm, width=tr_w_v)) + + # 2. export inp, inn + inp_vm = inst_p.get_pin('in') + inn_vm = inst_n.get_pin('in') + self.add_pin('vip', inp_vm) + self.add_pin('vin', inn_vm) + + # 3. export von, vop and connect to multiple wires on vm_layer + von_upper_idx = tr_manager.get_next_track(vm_layer, mid_idx, 'sig', 'sig', up=False) + von_upper = self.grid.track_to_coord(vm_layer, von_upper_idx) + + von_hm = inst_p.get_all_port_pins('out') + von_lower_idx = tr_manager.get_next_track(vm_layer, inp_vm.track_id.base_index, 'sig', 'sig', up=True) + von_lower = self.grid.track_to_coord(vm_layer, von_lower_idx) + von_vm_idx = tr_manager.get_next_track(vm_layer, inp_vm.track_id.base_index, 'sig', 'sig', up=False) + try: von_vm = max_conn_wires(self, tr_manager, 'sig', von_hm, start_coord=von_lower, end_coord=von_upper) + except: von_vm = self.connect_to_tracks(von_hm, TrackID(vm_layer, von_vm_idx, width=tr_w_v)) + vop_upper_idx = tr_manager.get_next_track(vm_layer, inn_vm.track_id.base_index, 'sig', 'sig', up=False) + vop_upper = self.grid.track_to_coord(vm_layer, vop_upper_idx) + vop_lower_idx = tr_manager.get_next_track(vm_layer, mid_idx, 'sig', 'sig', up=True) + vop_lower = self.grid.track_to_coord(vm_layer, vop_lower_idx) + vop_hm = inst_n.get_all_port_pins('out') + vop_vm_idx = tr_manager.get_next_track(vm_layer, inn_vm.track_id.base_index, 'sig', 'sig', up=True) + try: vop_vm = max_conn_wires(self, tr_manager, 'sig', vop_hm, start_coord=vop_lower, end_coord=vop_upper) + except: vop_vm = self.connect_to_tracks(vop_hm, TrackID(vm_layer, vop_vm_idx, width=tr_w_v)) + + self.add_pin('von', von_vm) + self.add_pin('vop', vop_vm) + sch_params = inv_master.sch_params + w_n = sch_params['w_n'] + w_p = sch_params['w_p'] + lch = sch_params['lch'] + if ndum > 0: + dum_info = [(('nch', w_n, lch, sch_params['th_n'], 'VSS', 'VSS'), ndum * 2), + (('pch', w_p, lch, sch_params['th_p'], 'VDDA', 'VDDA'), ndum * 2)] + sch_params = sch_params.copy(append=dict(dum_info=dum_info)) + # set + + + + + + self.sch_params = sch_params + + +class BufCMOSRow(MOSBase): + """The core of the pseudo differential inverters + """ + + def __init__(self, temp_db: TemplateDB, params: Param, **kwargs: Any) -> None: + MOSBase.__init__(self, temp_db, params, **kwargs) + + @classmethod + def get_schematic_class(cls) -> Optional[Type[Module]]: + return bag3_analog__buf_cmos_cell + + @classmethod + def get_params_info(cls) -> Dict[str, str]: + return dict( + pinfo='The MOSBasePlaceInfo object.', + seg_p='segments of pmos', + seg_n='segments of nmos', + w_p='pmos width.', + w_n='nmos width.', + ridx_p='pmos row index.', + ridx_n='nmos row index.', + show_pins='True to show pins', + flip_tile='True to flip all tiles', + sig_locs='Signal locations for top horizontal metal layer pins', + ndum='number of dummy at one side, need even number' + ) + + @classmethod + def get_default_param_values(cls) -> Dict[str, Any]: + return dict( + seg_p=-1, + seg_n=-1, + w_p=0, + w_n=0, + ridx_p=-1, + ridx_n=0, + show_pins=False, + flip_tile=False, + sig_locs={}, + ndum=0, + ) + + def draw_layout(self) -> None: + pinfo = MOSBasePlaceInfo.make_place_info(self.grid, self.params['pinfo']) + self.draw_base(pinfo, flip_tile=self.params['flip_tile']) + + # core_tile + _pinfo = self.get_tile_pinfo(tile_idx=1) + + seg_p: int = self.params['seg_p'] + seg_n: int = self.params['seg_n'] + w_p: int = self.params['w_p'] + w_n: int = self.params['w_n'] + ridx_p: int = self.params['ridx_p'] + ridx_n: int = self.params['ridx_n'] + ndum: int = self.params['ndum'] + sig_locs: Dict[str, TrackType] = self.params['sig_locs'] + + for val in (seg_p, seg_n, ndum): + if val % 2: + raise ValueError(f'This generator does not support odd number of segments ') + + hm_layer = self.conn_layer + 1 + vm_layer = hm_layer + 1 + xm_layer = vm_layer + 1 + + inv_params = self.params.copy(append=dict(is_guarded=True, show_pins=False, vertical_sup=True, + vertical_out=False), + remove=['pinfo']) + inv_master = self.new_template(InvCore, params=dict(pinfo=_pinfo, **inv_params)) + inv_ncol = inv_master.num_cols + + # set total number of columns + seg_max = 2 * max(seg_p, seg_n) + seg_tot = seg_max + 2 * ndum + + # taps + sub_vss = self.add_substrate_contact(0, 0, tile_idx=0, seg=seg_tot, port_mode=SubPortMode.BOTH) + sub_vdd = self.add_substrate_contact(0, 0, tile_idx=2, seg=seg_tot, port_mode=SubPortMode.BOTH) + + # --- Placement --- # + cur_col = 0 + if ndum > 0: + nmos_dum_p = self.add_mos(ridx_n, cur_col, ndum, tile_idx=1, w=w_n) + pmos_dum_p = self.add_mos(ridx_p, cur_col, ndum, tile_idx=1, w=w_p) + cur_col += ndum + inst_p = self.add_tile(inv_master, 1, cur_col) + cur_col += 2 * inv_ncol + mid_idx = self.arr_info.col_to_track(vm_layer, cur_col - inv_ncol, mode=RoundMode.NEAREST) + inst_n = self.add_tile(inv_master, 1, cur_col, flip_lr=True) + if ndum > 0: + cur_col += ndum + nmos_dum_n = self.add_mos(ridx_n, cur_col, ndum, tile_idx=1, flip_lr=True, w=w_n) + pmos_dum_n = self.add_mos(ridx_p, cur_col, ndum, tile_idx=1, flip_lr=True, w=w_p) + + # set size + self.set_mos_size() + + # --- Routing --- # + tr_manager = self.tr_manager + hm_layer = self.conn_layer + 1 + # 1. supplies + vdd_tidx = self.get_track_index(0, MOSWireType.DS, wire_name='sup', wire_idx=-1, tile_idx=2) + vss_tidx = self.get_track_index(0, MOSWireType.DS, wire_name='sup', wire_idx=-1, tile_idx=0) + w_sup_hm = tr_manager.get_width(hm_layer, 'sup') + + inst_vss, inst_vdd = [sub_vss], [sub_vdd] + for inst in (inst_p, inst_n): + inst_vss.extend(inst.get_all_port_pins('VSS', layer=self.conn_layer)) + inst_vdd.extend(inst.get_all_port_pins('VDD', layer=self.conn_layer)) + if ndum > 0: + # connect dummy + for pmos, nmos in zip([pmos_dum_n, pmos_dum_p], [nmos_dum_n, nmos_dum_p]): + inst_vdd.extend([pmos.g, pmos.d, pmos.s]) + inst_vss.extend([nmos.g, nmos.d, nmos.s]) + self.connect_wires(inst_vss) + self.connect_wires(inst_vdd) + vss = self.connect_to_tracks([sub_vss[0::2]], TrackID(hm_layer, vss_tidx, width=w_sup_hm), min_len_mode=MinLenMode.MIDDLE) + vdd = self.connect_to_tracks([sub_vdd[0::2]], TrackID(hm_layer, vdd_tidx, width=w_sup_hm), min_len_mode=MinLenMode.MIDDLE) + self.add_pin('VDDA', vdd, connect=True) + self.add_pin('VSS', vss, connect=True) + + # 2. export inp, inn + inp_vm = inst_p.get_pin('in') + inn_vm = inst_n.get_pin('in') + self.add_pin('vip', inp_vm) + self.add_pin('vin', inn_vm) + + # 3. export von, vop and connect to multiple wires on vm_layer + # mid_idx = self.grid.coord_to_track(vm_layer, inst_p.bound_box.xh, mode=RoundMode.NEAREST) + von_upper_idx = tr_manager.get_next_track(vm_layer, mid_idx, 'sig', 'sig', up=False) + von_upper = self.grid.track_to_coord(vm_layer, von_upper_idx) + vop_lower_idx = tr_manager.get_next_track(vm_layer, mid_idx, 'sig', 'sig', up=True) + vop_lower = self.grid.track_to_coord(vm_layer, vop_lower_idx) + von_hm = inst_p.get_all_port_pins('out') + von_lower_idx = tr_manager.get_next_track(vm_layer, inp_vm.track_id.base_index, 'sig', 'sig', up=True) + von_lower = self.grid.track_to_coord(vm_layer, von_lower_idx) + von_vm = max_conn_wires(self, tr_manager, 'sig', von_hm, start_coord=von_lower, end_coord=von_upper) + vop_upper_idx = tr_manager.get_next_track(vm_layer, inn_vm.track_id.base_index, 'sig', 'sig', up=False) + vop_upper = self.grid.track_to_coord(vm_layer, vop_upper_idx) + vop_hm = inst_n.get_all_port_pins('out') + vop_vm = max_conn_wires(self, tr_manager, 'sig', vop_hm, start_coord=vop_lower, end_coord=vop_upper) + + self.add_pin('von', von_vm) + self.add_pin('vop', vop_vm) + sch_params = dict(**inv_master.sch_params) + lch = sch_params['lch'] + if ndum > 0: + dum_info = [(('nch', sch_params['w_n'], lch, sch_params['th_n'], 'VSS', 'VSS'), ndum * 2), + (('pch', sch_params['w_p'], lch, sch_params['th_p'], 'VDDA', 'VDDA'), ndum * 2)] + sch_params['dum_info'] = dum_info + # set properties + self.sch_params = sch_params + + +class BufCMOSGR(GuardRing): + def __init__(self, temp_db: TemplateDB, params: Param, **kwargs: Any) -> None: + GuardRing.__init__(self, temp_db, params, **kwargs) + + @classmethod + def get_params_info(cls) -> Dict[str, str]: + ans = BufCMOS.get_params_info() + ans.update( + pmos_gr='pmos guard ring tile name.', + nmos_gr='nmos guard ring tile name.', + edge_ncol='Number of columns on guard ring edge. Use 0 for default.', + ) + return ans + + @classmethod + def get_default_param_values(cls) -> Dict[str, Any]: + ans = BufCMOSV1.get_default_param_values() + ans.update( + pmos_gr='pgr', + nmos_gr='ngr', + edge_ncol=0, + ) + return ans + + def get_layout_basename(self) -> str: + return self.__class__.__name__ + + def draw_layout(self) -> None: + params = self.params + pmos_gr: str = params['pmos_gr'] + nmos_gr: str = params['nmos_gr'] + edge_ncol: int = params['edge_ncol'] + + core_params = params.copy(remove=['pmos_gr', 'nmos_gr', 'edge_ncol']) + master = self.new_template(BufCMOSV1, params=core_params) + + sub_sep = master.sub_sep_col + gr_sub_sep = master.gr_sub_sep_col + sep_ncol_left = sep_ncol_right = sub_sep + draw_taps: DrawTaps = DrawTaps[params['draw_taps']] + if draw_taps in DrawTaps.RIGHT | DrawTaps.BOTH: + sep_ncol_right = gr_sub_sep - sub_sep // 2 + if draw_taps in DrawTaps.LEFT | DrawTaps.BOTH: + sep_ncol_left = gr_sub_sep - sub_sep // 2 + sep_ncol = (sep_ncol_left, sep_ncol_right) + + inst, sup_list = self.draw_guard_ring(master, pmos_gr, nmos_gr, sep_ncol, edge_ncol) + vdd_hm_list, vss_hm_list = [], [] + for (vss_list, vdd_list) in sup_list: + vss_hm_list.extend(vss_list) + vdd_hm_list.extend(vdd_list) + + self.connect_to_track_wires(vss_hm_list, inst.get_all_port_pins('VSS_vm')) + self.connect_to_track_wires(vdd_hm_list, inst.get_all_port_pins('VDD_vm')) + + +class BufCMOSRowGR(GuardRing): + def __init__(self, temp_db: TemplateDB, params: Param, **kwargs: Any) -> None: + GuardRing.__init__(self, temp_db, params, **kwargs) + + @classmethod + def get_params_info(cls) -> Dict[str, str]: + ans = BufCMOSV1Row.get_params_info() + ans.update( + pmos_gr='pmos guard ring tile name.', + nmos_gr='nmos guard ring tile name.', + edge_ncol='Number of columns on guard ring edge. Use 0 for default.', + ) + return ans + + @classmethod + def get_default_param_values(cls) -> Dict[str, Any]: + ans = BufCMOSV1Row.get_default_param_values() + ans.update( + pmos_gr='pgr', + nmos_gr='ngr', + edge_ncol=0, + ) + return ans + + def get_layout_basename(self) -> str: + return self.__class__.__name__ + + def draw_layout(self) -> None: + params = self.params + pmos_gr: str = params['pmos_gr'] + nmos_gr: str = params['nmos_gr'] + edge_ncol: int = params['edge_ncol'] + + core_params = params.copy(remove=['pmos_gr', 'nmos_gr', 'edge_ncol']) + master = self.new_template(BufCMOSV1Row, params=core_params) + + gr_sub_sep = master.gr_sub_sep_col + sep_ncol_left = sep_ncol_right = gr_sub_sep + sep_ncol = (sep_ncol_left, sep_ncol_right) + + inst, sup_list = self.draw_guard_ring(master, pmos_gr, nmos_gr, sep_ncol, edge_ncol) + vdd_hm_list, vss_hm_list = [], [] + for (vss_list, vdd_list) in sup_list: + vss_hm_list.extend(vss_list) + vdd_hm_list.extend(vdd_list) + + self.add_pin('VSS', vss_hm_list, connect=True) + self.add_pin('VDDA', vdd_hm_list, connect=True) diff --git a/src/bag3_analog/layout/tia/tia.py b/src/bag3_analog/layout/tia/tia.py new file mode 100644 index 0000000..0325480 --- /dev/null +++ b/src/bag3_analog/layout/tia/tia.py @@ -0,0 +1,403 @@ +"""This module defines delay_res_unit.""" + +from typing import Mapping, Any, Optional, Type, cast, Dict + +from bag.util.immutable import Param +from bag.design.module import Module +from bag.design.database import ModuleDB +from bag.layout.template import TemplateDB, TemplateBase +from bag.layout.routing.base import TrackID, WireArray + +from pybag.enum import RoundMode, Orientation, Direction +from pybag.core import Transform, BBox + +from xbase.layout.res.base import ResBasePlaceInfo, ResArrayBase +from xbase.layout.mos.top import GenericWrapper +from xbase.layout.array.top import ArrayBaseWrapper +from xbase.layout.cap.core import MOMCapCore +from bag3_analog.layout.res.termination import Termination +from .buf_cmos_cell import BufCMOSGR, BufCMOS +from ...schematic.tia_res import bag3_analog__tia_res + +import numpy as np +from .util import round_to_blk_pitch, draw_stack_wire, extend_matching_wires + +class TIARes(ResArrayBase): + def __init__(self, temp_db: TemplateDB, params: Param, **kwargs: Any) -> None: + ResArrayBase.__init__(self, temp_db, params, **kwargs) + + @classmethod + def get_schematic_class(cls) -> Optional[Type[Module]]: + return bag3_analog__tia_res + + @classmethod + def get_params_info(cls) -> Mapping[str, str]: + return dict( + pinfo='The ResBasePlaceInfo object.', + nx_dum='Number of dummies on each side, X direction', + ny_dum='Number of dummies on each side, Y direction', + ) + + @classmethod + def get_default_param_values(cls) -> Mapping[str, Any]: + return dict(nx_dum=0, ny_dum=0) + + def draw_layout(self) -> None: + pinfo = cast(ResBasePlaceInfo, ResBasePlaceInfo.make_place_info(self.grid, self.params['pinfo'])) + self.draw_base(pinfo) + + sub_type = pinfo.res_config['sub_type_default'] + if sub_type != 'ntap': + raise ValueError(f'This generator does not support sub_type={sub_type}. Only ntap is supported.') + + # Get hm_layer and vm_layer WireArrays + warrs, bulk_warrs = self.connect_hm_vm() + + # Connect all dummies + self.connect_dummies(warrs, bulk_warrs) + + # Supply connections on xm_layer + self.connect_bulk_xm(bulk_warrs) + + unit_params = dict( + w=pinfo.w_res, + l=pinfo.l_res, + intent=pinfo.res_type, + ) + nx, ny = pinfo.nx, pinfo.ny + nx_dum: int = self.params['nx_dum'] + ny_dum: int = self.params['ny_dum'] + npar = nx - 2 * nx_dum + nser = ny - 2 * ny_dum + num_dum = nx * ny - npar * nser + + # --- Routing of unit resistors --- # + hm_layer = self.conn_layer + 1 + vm_layer = hm_layer + 1 + xm_layer = vm_layer + 1 + r_bot, r_top = self.connect_units(warrs, nx_dum, nx - nx_dum, ny_dum, ny - ny_dum) + + # connect top vm_layers to xm_layer + w_xm_sig = self.tr_manager.get_width(xm_layer, 'sig') + xm_idx0 = self.grid.coord_to_track(xm_layer, r_top.middle, RoundMode.NEAREST) + xm_tid0 = TrackID(xm_layer, xm_idx0, w_xm_sig) + xm_idx1 = self.grid.coord_to_track(xm_layer, r_bot.middle, RoundMode.NEAREST) + xm_tid1 = TrackID(xm_layer, xm_idx1, w_xm_sig) + self.add_pin('PLUS', self.connect_to_tracks(r_top, xm_tid0)) + self.add_pin('MINUS', self.connect_to_tracks(r_bot, xm_tid1)) + + self.sch_params = dict( + res_params=dict( + unit_params=unit_params, + nser=nser, + npar=npar, + ), + dum_params=dict( + unit_params=unit_params, + nser=1, + npar=num_dum, + ), + sub_type=sub_type, + ) + + +class TIA(TemplateBase): + def __init__(self, temp_db: TemplateDB, params: Param, **kwargs: Any) -> None: + TemplateBase.__init__(self, temp_db, params, **kwargs) + self._sup_wire = {} + self._decap_w = 0 + + @property + def sup_wire(self) -> Dict[WireArray, Any]: + return self._sup_wire + + @property + def decap_w(self) -> int: + return self._decap_w + + def get_schematic_class_inst(self) -> Optional[Type[Module]]: + if self.params['res_term_params']: + # noinspection PyTypeChecker + return ModuleDB.get_schematic_class('bag3_analog', 'tia_term') + else: + # noinspection PyTypeChecker + return ModuleDB.get_schematic_class('bag3_analog', 'tia') + + + @classmethod + def get_params_info(cls) -> Mapping[str, str]: + return dict( + buf_params='Parameters for buffer', + res_params='Parameters for feedback resistor', + cap_params='Parameters for mom cap, if not specified, removed the mom cap', + res_term_params='Parameters for termination resistor', + decap_params='Parameters for DC decoupling cap', + do_power_fill='True to do power fill from M4 to M6', + guard_ring='True to draw guard ring', + ) + + @classmethod + def get_default_param_values(cls) -> Dict[str, Any]: + return dict( + do_power_fill=False, + cap_params=None, + res_term_params=None, + decap_params=None, + guard_ring=True, + ) + + def draw_layout(self) -> None: + do_power_fill = self.params['do_power_fill'] + # make masters + buf_params: Mapping[str, Any] = self.params['buf_params'] + guard_ring: bool = self.params['guard_ring'] + + buf_gen = BufCMOSGR if guard_ring else BufCMOS + buf_master = self.new_template(GenericWrapper, params=dict(cls_name=buf_gen.get_qualified_name(), + params=buf_params)) + + res_params: Mapping[str, Any] = self.params['res_params'] + res_master = self.new_template(ArrayBaseWrapper, params=dict(cls_name=TIARes.get_qualified_name(), + params=res_params)) + + cap_params: Optional[Mapping[str, Any]] = self.params.get('cap_params', None) + if cap_params: + cap_master = self.new_template(MOMCapCore, params=cap_params) + + res_term_params: Optional[Mapping[str, Any]] = self.params.get('res_term_params', None) + if res_term_params: + res_term_master = self.new_template(ArrayBaseWrapper, params=dict(cls_name=Termination.get_qualified_name(), + params=res_term_params)) + + decap_params: Optional[Mapping[str, Any]] = self.params.get('decap_params', None) + if decap_params: + decap_master = self.new_template(MOMCapCore, params=decap_params) + + # --- Placement --- # + w_blk, h_blk = self.grid.get_block_size(buf_master.size[0]) + buf_w, buf_h = buf_master.bound_box.w, buf_master.bound_box.h + res_w, res_h = res_master.bound_box.w, res_master.bound_box.h + if cap_params: + cap_w, cap_h = cap_master.bound_box.w, cap_master.bound_box.h + else: + cap_w, cap_h = 0, 0 + + if res_term_params: + res_term_w, res_term_h = res_term_master.bound_box.w, res_term_master.bound_box.h + else: + res_term_w, res_term_h = 0, 0 + + if decap_params: + decap_w, decap_h = decap_master.bound_box.w, decap_master.bound_box.h + else: + decap_w, decap_h = 0, 0 + + self._decap_w = decap_w + + tot_w = max(buf_w + 2 * res_w, 2 * cap_w + res_term_w) + decap_w + tot_h = max(cap_h + max(buf_h, res_h) + res_term_h, decap_h) + + buf_xl = (tot_w - buf_w + decap_w) // 2 + buf_yl = cap_h + res_term_h + buf_xl, buf_yl = round_to_blk_pitch(buf_xl, buf_yl, w_blk, h_blk) + buf_inst = self.add_instance(buf_master, xform=Transform(dx=buf_xl, dy=buf_yl)) + tr_manager = buf_master.core.tr_manager + + res_xl = buf_xl - res_w + res_yl = cap_h + (max(buf_h, res_h) - res_h) // 2 + res_term_h + res_xl, res_yl = round_to_blk_pitch(res_xl, res_yl, w_blk, h_blk) + resp_inst = self.add_instance(res_master, xform=Transform(dx=res_xl, dy=res_yl)) + resn_inst = self.add_instance(res_master, xform=Transform(dx=res_xl + res_w + buf_w, dy=res_yl)) + + if cap_params: + cap_xl = (tot_w - 2 * cap_w + decap_w) // 2 + cap_yh = cap_h + cap_xl, cap_yh = round_to_blk_pitch(cap_xl, cap_yh, w_blk, h_blk) + capp_inst = self.add_instance(cap_master, xform=Transform(dx=cap_xl + cap_w, dy=cap_yh, mode=Orientation.R180)) + capn_inst = self.add_instance(cap_master, xform=Transform(dx=cap_xl + cap_w, dy=cap_yh, mode=Orientation.MX)) + + if res_term_params: + res_term_xl = (tot_w - res_term_w + decap_w) // 2 + res_term_yl = 0 + res_term_xl, res_term_yl = round_to_blk_pitch(res_term_xl, res_term_yl, w_blk, h_blk) + res_term_inst = self.add_instance(res_term_master, xform=Transform(dx=res_term_xl, dy=res_term_yl)) + + if decap_params: + decap_xl = decap_w + decap_yl = 0 + decap_xl, decap_yl = round_to_blk_pitch(decap_xl, decap_yl, w_blk, h_blk) + decap_inst = self.add_instance(decap_master, xform=Transform(dx=decap_xl, dy=decap_yl, mode=Orientation.MY),) + + # # --- Routing --- # + xm_layer = resp_inst.get_pin('MINUS').layer_id + ym_layer = xm_layer + 1 + zm_layer = ym_layer + 1 + w_sig_xm = tr_manager.get_width(xm_layer, 'sig') + w_sig_ym = tr_manager.get_width(ym_layer, 'sig') + + # vip/ vin + if cap_params: + self.reexport(capp_inst.get_port('minus'), net_name='vip') + self.reexport(capn_inst.get_port('minus'), net_name='vin') + if res_term_params: + # export to zm_layer + stack = draw_stack_wire(self, res_term_inst.get_pin('PLUS'), zm_layer, tr_list=[1, 4], sp_list=[3, 4]) + vip_zm = stack[-1] + stack = draw_stack_wire(self, res_term_inst.get_pin('MINUS'), zm_layer, tr_list=[1, 4], sp_list=[3, 4]) + vin_zm = stack[-1] + stack = draw_stack_wire(self, res_term_inst.get_pin('MID'), zm_layer, tr_list=[1, 4], sp_list=[3, 4]) + mid_zm = stack[-1] + vdd_res = res_term_inst.get_all_port_pins('VDD', xm_layer) + vdd_zm = [] + for vdd in vdd_res: + stack = draw_stack_wire(self, vdd, zm_layer, tr_list=[1, 4], sp_list=[3, 4]) + vdd_zm += stack[-1] + + self.add_pin('VDD', vdd_zm, connect=True) + # mid + mid_xm = [res_term_inst.get_pin('MID')] + if decap_params: + mid_ym_tidx = decap_inst.get_pin('plus', layer=ym_layer).track_id.base_index + mid_ym_tidx = tr_manager.get_next_track(ym_layer, mid_ym_tidx, 'sig', 'sig') + mid_ym_tidx = tr_manager.get_next_track(ym_layer, mid_ym_tidx, 'sig', 'sig') + mid_ym_tidx = tr_manager.get_next_track(ym_layer, mid_ym_tidx, 'sig', 'sig') + mid_xm += decap_inst.get_all_port_pins('plus', xm_layer) + self.connect_to_tracks(mid_xm + mid_zm, TrackID(ym_layer, mid_ym_tidx, width=w_sig_ym)) + self.add_pin('VDD', decap_inst.get_all_port_pins('minus', zm_layer), connect=True) + + # vip_m/ vin_m + + vlay = (buf_inst.get_port('vip').get_single_layer(), 'drawing') + vdir = Direction.LOWER + vip_m_buf = buf_inst.get_pin('vip') + vin_m_buf = buf_inst.get_pin('vin') + vip_m_res = resp_inst.get_pin('MINUS') + vin_m_res = resn_inst.get_pin('MINUS') + + vm_layer = xm_layer - 1 + ym_layer = xm_layer + 1 + vip_passive =[vip_m_res] + vin_passive =[vin_m_res] + if cap_params: + vip_m_cap_xm, vip_m_cap_vm, vip_m_cap_ym = capp_inst.get_all_port_pins('plus', xm_layer)[0], \ + capp_inst.get_all_port_pins('plus', vm_layer)[0],\ + capp_inst.get_all_port_pins('plus', ym_layer)[0] + vin_m_cap_xm, vin_m_cap_vm, vin_m_cap_ym = capn_inst.get_all_port_pins('plus', xm_layer)[0], \ + capn_inst.get_all_port_pins('plus', vm_layer)[0], \ + capn_inst.get_all_port_pins('plus', ym_layer)[0] + + vip_xm_idx = tr_manager.get_next_track(xm_layer, vip_m_cap_xm.track_id.base_index, 'sig', 'sig', up=True) + vip_xm_idx = tr_manager.get_next_track(xm_layer, vip_xm_idx, 'sig', 'sig', up=True) + vin_xm_idx = tr_manager.get_next_track(xm_layer, vin_m_cap_xm.track_id.base_index, 'sig', 'sig', up=True) + vin_xm_idx = tr_manager.get_next_track(xm_layer, vin_xm_idx, 'sig', 'sig', up=True) + vip_m_cap = self.connect_to_tracks([vip_m_cap_vm, vip_m_cap_ym], TrackID(xm_layer, vip_xm_idx, width=w_sig_xm)) + vin_m_cap = self.connect_to_tracks([vin_m_cap_vm, vin_m_cap_ym], TrackID(xm_layer, vin_xm_idx, width=w_sig_xm)) + vip_passive += [vip_m_cap] + vin_passive += [vin_m_cap] + vip_m = self.connect_bbox_to_track_wires(vdir, vlay, vip_m_buf, vip_passive) + vin_m = self.connect_bbox_to_track_wires(vdir, vlay, vin_m_buf, vin_passive) + vip_name = 'vip_m' if cap_params else 'vip' + vin_name = 'vin_m' if cap_params else 'vin' + + + # connect vip/ vin on M7 + if res_term_params: + stack_p = draw_stack_wire(self, vip_m[0], zm_layer, tr_list=[1, 4], sp_list=[3, 4]) + stack_n = draw_stack_wire(self, vin_m[0], zm_layer, tr_list=[1, 4], sp_list=[3, 4]) + buf_vip = stack_p[-1] + buf_vin = stack_n[-1] + # vip_m7_tidx = self.grid.coord_to_track(zm_layer + 1, buf_vip[0].middle, mode=RoundMode.GREATER) + # vin_m7_tidx = self.grid.coord_to_track(zm_layer + 1, buf_vin[0].middle, mode=RoundMode.LESS_EQ) + # vip_m7 = self.connect_to_tracks(buf_vip + vip_zm, TrackID(zm_layer + 1, vip_m7_tidx, width=1)) + # vin_m7 = self.connect_to_tracks(buf_vin + vin_zm, TrackID(zm_layer + 1, vin_m7_tidx, width=1)) + # vip_m7, vin_m7 = extend_matching_wires(self,[vip_m7, vin_m7]) + self.add_pin(vip_name, buf_vip + vip_zm, connect=True) + self.add_pin(vin_name, buf_vin + vin_zm, connect=True) + else: + self.add_pin(vip_name, vip_m) + self.add_pin(vin_name, vin_m) + + + # vop/ von + vop_m_buf = buf_inst.get_all_port_pins('vop') + von_m_buf = buf_inst.get_all_port_pins('von') + vop_m_res = resn_inst.get_pin('PLUS') + von_m_res = resp_inst.get_pin('PLUS') + for bbox in vop_m_buf: + vop = self.connect_bbox_to_track_wires(vdir, vlay, bbox, vop_m_res) + for bbox in von_m_buf: + von = self.connect_bbox_to_track_wires(vdir, vlay, bbox, von_m_res) + self.add_pin('vop', vop_m_res) + self.add_pin('von', von_m_res) + + # VDD/VSS + vdd_xm_buf = buf_inst.get_all_port_pins('VDDA') + vdd_xm_left = resp_inst.get_all_port_pins('VDD') + vdd_xm_right = resn_inst.get_all_port_pins('VDD') + vdd_xm = vdd_xm_buf + vdd_xm_left + vdd_xm_right + vss_xm = buf_inst.get_all_port_pins('VSS') + top_idx = np.argmax([vdd.track_id.base_index for vdd in vdd_xm]) + sup_xm = vdd_xm + vss_xm + bot_idx = np.argmin([vdd.track_id.base_index for vdd in sup_xm]) + # self._sup_wire.update(top_wire=vdd_xm[top_idx], bot_wire=sup_xm[bot_idx], left_wire=vdd_xm[1], right_wire=vdd_xm[-1]) + self._sup_wire.update(top_wire=vdd_xm[top_idx], bot_wire=sup_xm[bot_idx]) + + # set size + xm_layer = vdd_xm[0].layer_id + ym_layer = xm_layer + 1 + zm_layer = ym_layer + 1 + self.set_size_from_bound_box(zm_layer, BBox(0, 0, tot_w, tot_h)) + + if not do_power_fill: + self.add_pin('VDD_xm_buf', vdd_xm_buf, label='VDD:') + self.add_pin('VDD_xm_right', vdd_xm_right, label='VDD:') + self.add_pin('VDD_xm_left', vdd_xm_left, label='VDD:') + self.add_pin('VSS_xm', vss_xm, label='VSS:') + else: + sup_w_xm = tr_manager.get_width(xm_layer, 'sup') + bbox = self.bound_box + bb_xl, bb_xh, bb_yl, bb_yh = bbox.xl, bbox.xh, bbox.yl, bbox.yh + + # M5 + sup_w_ym = tr_manager.get_width(ym_layer, 'sup') + wl, wh = self.grid.get_wire_bounds(ym_layer, 0, width=sup_w_ym) + w_ym = int((wh - wl) / 2) + via_ext_xm, via_ext_ym = self.grid.get_via_extensions(Direction.LOWER, xm_layer, sup_w_xm, sup_w_ym) + dx =via_ext_xm + w_ym + # dy = self.bound_box.yl - vss_xm[0].bound_box.yl + via_ext_ym + bb = BBox(xl=bb_xl - dx, xh=bb_xh - dx, yl=capp_inst.bound_box.yh, yh=bb_yh + via_ext_ym) + vdd_ym, vss_ym = self.do_power_fill(ym_layer, tr_manager, vdd_xm, vss_xm, bound_box=bb) + # self.add_pin('VDD_ym', vdd_ym, label='VDD:') + # self.add_pin('VSS_ym', vss_ym, label='VSS:') + + # M6 + sup_w_zm = tr_manager.get_width(zm_layer, 'sup') + wl, wh = self.grid.get_wire_bounds(zm_layer, 0, width=sup_w_zm) + w_zm = int((wh - wl) / 2) + via_ext_zm, via_ext_zm_x = self.grid.get_via_extensions(Direction.LOWER, ym_layer, sup_w_ym, sup_w_zm) + dx = self.bound_box.xl - vss_ym[0].bound_box.xl + via_ext_zm_x + bb = bb.expand(dy=- via_ext_zm - w_zm, dx=dx) + vdd_zm, vss_zm = self.do_power_fill(zm_layer, tr_manager, vdd_ym, vss_ym, bound_box=bb) + self.add_pin('VDD_zm', vdd_zm, label='VDD:') + self.add_pin('VSS_zm', vss_zm, label='VSS:') + + # set size + self.set_size_from_bound_box(6, BBox(0, 0, tot_w, tot_h)) + + # set schematic parameters + if res_term_params: + self.sch_params = dict( + buf_cmos_cell_params=buf_master.sch_params, + res_params=res_master.sch_params, + res_term_params=res_term_master.sch_params, + decap_params=decap_master.sch_params, + + ) + else: + + self.sch_params = dict( + buf_cmos_cell_params=buf_master.sch_params, + res_params=res_master.sch_params, + cap_params=cap_master.sch_params if cap_params else None, + with_cap=True if cap_params else False, + ) diff --git a/src/bag3_analog/layout/tia/util.py b/src/bag3_analog/layout/tia/util.py new file mode 100644 index 0000000..74cd093 --- /dev/null +++ b/src/bag3_analog/layout/tia/util.py @@ -0,0 +1,404 @@ +from __future__ import (absolute_import, division, + print_function, unicode_literals) +# noinspection PyUnresolvedReferences,PyCompatibility +from builtins import * + +from typing import Any, Set, Dict, Optional, Union, List, Tuple + +from bag.layout.routing import TrackID, WireArray +from pybag.enum import RoundMode, MinLenMode, Orient2D, Direction + +from bag.layout.template import TemplateDB +from bag.layout.util import BBox +from bag.util.math import HalfInt + +from xbase.layout.mos.base import MOSBasePlaceInfo, MOSBase, TrackManager +from bag.layout.template import TemplateBase +import math + + +def via_maker(template, l1, l2, object, coordx, coordy, width): + base = object + layers = [] + width = [0]*l1+ width + for i in range(l1, l2): + if (i + 1) % 2 == 0: + out_track = TrackID(i + 1, template.grid.coord_to_nearest_track(i + 1, coordy, half_track=True, mode=0, + unit_mode=True), width=width[i]) + else: + out_track = TrackID(i + 1, template.grid.coord_to_nearest_track(i + 1, coordx, half_track=True, mode=0, + unit_mode=True), width=width[i]) + layers.append(template.connect_to_tracks([base], out_track, min_len_mode=0)) + base = layers[-1] + + return layers + + +def get_mos_conn_layer(self): + return self.grid.tech_info.tech_params['layout']['mos_tech_class'].get_mos_conn_layer() + + +def max_conn_wires(self, tr_manager, wire_type, wire_list, start_coord=None, end_coord=None): + max_coord, min_coord = 0, math.inf + for w in wire_list: + max_coord = max_coord if max_coord > w.upper else w.upper + min_coord = min_coord if min_coord < w.lower else w.lower + + start_coord = start_coord if start_coord is not None else min_coord + end_coord = end_coord if end_coord is not None else max_coord + if end_coord < start_coord: + raise ValueError("[Util Error:] End points smaller than start point, please check") + conn_layer = wire_list[0].layer_id+1 + conn_w = tr_manager.get_width(conn_layer, wire_type) + cur_tidx = self.grid.coord_to_track(conn_layer, start_coord, mode=RoundMode.NEAREST) + res_wire_list = [] + while self.grid.track_to_coord(conn_layer, cur_tidx) <= end_coord: + res_wire_list.append(self.connect_to_tracks(wire_list, TrackID(conn_layer, cur_tidx, conn_w))) + cur_tidx = tr_manager.get_next_track(conn_layer, cur_tidx, wire_type, wire_type) + if len(res_wire_list) < 1: + raise ValueError("[Util Error:] Targeted connection have no effect") + return res_wire_list + + +def round_to_blk_pitch(x_loc, y_loc, blk_w, blk_h): + return (math.ceil(x_loc / blk_w) * blk_w, math.ceil(y_loc / blk_h) * blk_h) + + +def draw_stack_wire(self: TemplateBase, wire: WireArray, top_layid: int, x0: Optional[Union[int, float]] = None, + y0: Optional[Union[int, float]] = None, x1: Optional[Union[int, float]] = None, + y1: Optional[Union[int, float]] = None, tr_list: Optional[List[Union[int, float]]] = None, + sp_list: Optional[List[Union[HalfInt, int]]] = None, max_mode: bool = True, + min_len_mode: MinLenMode = MinLenMode.NONE, + mode: int = 1, sep_margin: bool = False, + sp_margin_list: Optional[List[Union[HalfInt, int]]] = None) -> List[List[WireArray]]: + """ + create WireArray from bot_layid to top_layid-1 within the given coordinates + Parameters + ---------- + self: TemplateBase + template database. + wire: WireArray + wire to be connected. + top_layid: Int + top layer id. + x0: Union[Int, float] + bottom left, x coordinate. + y0: Union[Int, float] + bottom left, y coordinate. + x1: Union[Int, float] + top right, x coordinate. + y1: Union[Int, float] + top right, y coordinate. + x_mode: Int + x direction mode. + If negative, the result wire will have width less than or equal to the given width. + If positive, the result wire will have width greater than or equal to the given width. + y_mode: Int + y direction mode. + If negative, the result wire will have width less than or equal to the given width. + If positive, the result wire will have width greater than or equal to the given width. + half_track: Bool + True to get half track. + tr_list: List[Union[Int, float]] + Wire array track list. + sp_list: List[Union[HalfInt]] + Wire array track separation list. + max_mode: Bool + True to draw wire with max width from coordinates and tr_list + track_mode: + ####### + min_len_mode: Int + Mininum length mode. See connect_to_tracks for details. + mode: Int + draw stack mode. + Returns + ------- + wire_arr_list: List[WireArray] + stack wire list. + """ + bot_layid = wire.layer_id + # get wire layer + if top_layid > bot_layid: + layer_flip = False + else: + layer_flip = True + + if tr_list is not None: + if len(tr_list) != top_layid - bot_layid: + raise ValueError('If given tr_list, its length should same as layers(top_layid-bot_layid)') + + # get coordinate + if x0 is None: + x0 = wire.bound_box.xl + if y0 is None: + y0 = wire.bound_box.yl + if x1 is None: + x1 = wire.bound_box.xh + if y1 is None: + y1 = wire.bound_box.yh + + # check coordinates + if x1 <= x0 or y1 <= y0: + raise ValueError("If given coordinates," + "we need left coord smaller than right coordinate\n" + "and bottom coordinate smaller than top coordinate") + if bot_layid == top_layid: + raise ValueError("Need top_layer != wire layer. It can be larger or smaller than it.") + + # draw stack wires + wire_arr_list = [wire] + if not layer_flip: + swp_list = list(range(bot_layid, top_layid)) + else: + swp_list = list(range(top_layid, bot_layid))[::-1] + + for i in swp_list: + if self.grid.get_direction(i + 1) == Orient2D.y: + if mode == 0: + tr, tr_w = self.grid.interval_to_track(i + 1, (x0, x1)) + if tr_w is None: + tr_w = 1 + # could specify tr from outside and choose the larger one + if tr_list is not None: + if tr_list[i - bot_layid] is not None: + if max_mode: + tr_w = max(tr_w, tr_list[i - bot_layid]) + else: + tr_w = tr_list[i - bot_layid] + + tr_tid = TrackID(i + 1, tr, width=tr_w) + wire_n = self.connect_to_tracks(wire_arr_list[-1], tr_tid, track_lower=y0, track_upper=y1, + min_len_mode=min_len_mode) + elif mode == 1: + # get wire width and space + if tr_list is not None: + w_ntr = tr_list[i - bot_layid] + else: + w_ntr = wire.bound_box.w + if sp_list is not None: + sp_ntr = sp_list[i - bot_layid] + else: + sp_ntr = self.grid.get_sep_tracks(i + 1, ntr1=w_ntr, ntr2=w_ntr) + if sp_margin_list is not None: + sp_margin_ntr = sp_margin_list[i - bot_layid] + else: + sp_margin_ntr = sp_ntr // 2 + tid_lower = self.grid.coord_to_track(i + 1, x0, mode=RoundMode.GREATER_EQ) + tid_upper = self.grid.coord_to_track(i + 1, x1, mode=RoundMode.LESS_EQ) + if tid_lower == tid_upper: + tr_idx = [tid_upper] + else: + tr_idx = self.get_available_tracks(i + 1, tid_lower, tid_upper, y0 - 170, y1 + 170, w_ntr, sep=sp_ntr, + sep_margin=sp_margin_ntr if sep_margin else None) + if tid_upper - tid_lower < w_ntr and len(tr_idx) > 0: + tr_idx = [(tid_upper + tid_lower) / 2] + wire_n = [] + for idx in tr_idx: + tr_tid = TrackID(i + 1, idx, width=w_ntr) + wire_n.append(self.connect_to_tracks(wire_arr_list[-1], tr_tid, min_len_mode=min_len_mode)) + else: + raise ValueError("For now, only support two modes.") + else: + if mode == 0: + tr, tr_w = self.grid.interval_to_track(i + 1, (y0, y1)) + if tr_w is None: + tr_w = 1 + # could specify tr from outside and choose the larger one + if tr_list is not None: + if tr_list[i - bot_layid] is not None: + if max_mode: + tr_w = max(tr_w, tr_list[i - bot_layid]) + else: + tr_w = tr_list[i - bot_layid] + tr_tid = TrackID(i + 1, tr, width=tr_w) + wire_n = self.connect_to_tracks(wire_arr_list[-1], tr_tid, track_lower=x0, track_upper=x1, + min_len_mode=min_len_mode) + elif mode == 1: + # get wire width and space + if tr_list is not None: + w_ntr = tr_list[i - bot_layid] + else: + w_ntr = wire.bound_box.w + if sp_list is not None: + sp_ntr = sp_list[i - bot_layid] + else: + sp_ntr = self.grid.get_sep_tracks(i + 1, ntr1=w_ntr, ntr2=w_ntr) + if sp_margin_list is not None: + sp_margin_ntr = sp_margin_list[i - bot_layid] + else: + sp_margin_ntr = sp_ntr // 2 + tid_lower = self.grid.coord_to_track(i + 1, y0, mode=RoundMode.GREATER_EQ) + tid_upper = self.grid.coord_to_track(i + 1, y1, mode=RoundMode.LESS_EQ) + if tid_upper == tid_lower: + tr_idx = [tid_lower] + else: + tr_idx = self.get_available_tracks(i + 1, tid_lower, tid_upper, x0 - 150, x1 + 150, w_ntr, sep=sp_ntr, + sep_margin=sp_margin_ntr if sep_margin else None) + if tid_upper - tid_lower < w_ntr and len(tr_idx) > 0: + tr_idx = [(tid_upper + tid_lower) / 2] + + + wire_n = [] + for idx in tr_idx: + tr_tid = TrackID(i + 1, idx, width=w_ntr) + wire_n.append(self.connect_to_tracks(wire_arr_list[-1], tr_tid, min_len_mode=min_len_mode, track_lower=x0, track_upper=x1)) + else: + raise ValueError("For now, only support two modes.") + + wire_arr_list.append(wire_n) + + return wire_arr_list + + + +def draw_multiple_stack_wire(self: TemplateBase, tr_manager, warr_list: List[WireArray], top_layid: int, wire_type: str, + sep_type: (str, str), y0=None, y1=None, x0=None, x1=None, stack_idx=-1): + + stack_wire = [] + cur_lay = warr_list[0].layer_id + layer_range = range(cur_lay + 1, top_layid + 1) + for warr in warr_list: + stack = draw_stack_wire(self, warr, top_layid, x0=x0, x1=x1, y0=y0, y1=y1, + tr_list=[tr_manager.get_width(lay, wire_type) for lay in layer_range], + sp_list=[tr_manager.get_sep(lay, sep_type) for lay in layer_range]) + stack_wire += stack[stack_idx] + return stack_wire + + +def extend_matching_wires(self, warrs: List[WireArray], lower: Optional[Union[int, float]]=None, + upper: Optional[Union[int, float]]=None)-> List[WireArray]: + + warr_lower = lower if lower!=None else warrs[0].lower + warr_upper = upper if upper!=None else warrs[0].upper + + lay_id = warrs[0].layer_id + width = warrs[0].track_id.width + warr_lower = warr_lower if warrs[0].lower > warr_lower else warrs[0].lower + warr_upper = warr_upper if warrs[0].upper < warr_upper else warrs[0].upper + + for warr in warrs[1:]: + # inspect layer id + assert lay_id == warr.layer_id + # find max width + width = warr.track_id.width if width < warr.track_id.width else width + # find min lower + warr_lower = warr_lower if warr.lower > warr_lower else warr.lower + # find max upper + warr_upper = warr_upper if warr.upper < warr_upper else warr.upper + + extended_warrs = [] + for warr in warrs: + new_warr = self.add_wires(lay_id, warr.track_id.base_index, warr_lower, warr_upper, width=width) + extended_warrs.append(new_warr) + + return extended_warrs + +def power_fill_helper(self, layer_id: int, tr_manager: TrackManager, + vdd_warrs: List[WireArray], vss_warrs: List[WireArray], bbox_overwrite=False, + bound_box: Optional[BBox] = None, top_wire: Optional[WireArray] = None, + bot_wire: Optional[WireArray] = None, left_wire: Optional[WireArray] = None, + right_wire: Optional[WireArray] = None, **kwargs) -> Tuple[List[WireArray], List[WireArray]]: + """Calculate via extention to do power fill. + Parameters + ---------- + layer_id: int + the layer to draw power lines + vdd_warrs: List[WireArray] + vdd wires (layer_id-1) to be connected. [] if no vdd wires + vss_warrs: List[WireArray] + vss wires (layer_id-1) to be connected. [] if no vss wires + bbox_overwrite: bool + True to overwrite with bound_box + bound_box: Optional[BBox] + The region to draw power lines + (takes the largest margin among bound_box and vdd_warrs/vss_warrs in layer_id direction + takes the smallest margin among bound_box and vdd_warrs/vss_warrs in layer_id-1 direction) + top_wire: Optional[WireArray] + The topmost wire in among vss_warrs/vdd_warrs if not specified, the last element in vdd_warrs or vss_warrs + would be assigned if vdd_warrs + vss_warrs is even or odd + bot_wire: Optional[WireArray] + The bottommost wire in among vss_warrs/vdd_warrs if not specified, the first element in vss_warrs or + vdd_warrs (if vss_warrs = []) + left_wire: Optional[WireArray] + The leftmost wire in among vss_warrs/vdd_warrs if not specified, the first element in vss_warrs or + vdd_warrs (if vss_warrs = []) + right_wire: Optional[WireArray] + The rightmost wire in among vss_warrs/vdd_warrs if not specified, the last element in vdd_warrss or vss_warrs + would be assigned if vdd_warrs + vss_warrs is even or odd + + Returns + ------- + (vdd, vss) : Tuple[List[WireArray], List[WireArray]] + list of created wires on layer_id + + """ + sup_w = tr_manager.get_width(layer_id, 'sup') + sup_w_lower = tr_manager.get_width(layer_id - 1, 'sup') + wl, wh = self.grid.get_wire_bounds(layer_id, 0, width=sup_w) + w_mid = int((wh - wl) / 2) + via_ext_lower, via_ext_cur = self.grid.get_via_extensions(Direction.LOWER, layer_id - 1, sup_w_lower, sup_w) + + is_horizontal = (self.grid.get_direction(layer_id) == 0) + num_vss = len(vss_warrs) + num_vdd = len(vdd_warrs) + if num_vdd + num_vss == 0: + raise ValueError("need at least vss_warrs or vdd_wars") + + top_wire, bot_wire, left_wire, right_wire = get_boundary_wires(self, vdd_warrs + vss_warrs) + # if not top_wire: + # top_wire = vss_warrs[-1] if ((num_vss + num_vdd) & 1) and (num_vss > 0) else vdd_warrs[-1] + # if not bot_wire: + # bot_wire = vss_warrs[0] if num_vss > 0 else vdd_warrs[0] + # if not right_wire: + # right_wire = vss_warrs[-1] if ((num_vss + num_vdd) & 1) and (num_vss > 0) else vdd_warrs[-1] + # if not left_wire: + # left_wire = vss_warrs[0] if num_vss > 0 else vdd_warrs[0] + # layer_id is horizontal + if is_horizontal: + dx = via_ext_cur + dy = - via_ext_lower - w_mid + + # layer_id is vertical + else: + dx = - via_ext_lower - w_mid + dy = via_ext_cur + xl, xh, yl, yh = left_wire.bound_box.xl, right_wire.bound_box.xh, bot_wire.bound_box.yl, top_wire.bound_box.yh + xl = xl if is_horizontal else xl - dx + xh = xh if is_horizontal else xh + dx + yl = yl if not is_horizontal else yl - dy + yh = yh if not is_horizontal else yh + dy + + xl = bound_box.xl if (bound_box and ((bound_box.xl < xl) or bbox_overwrite)) else xl + xh = bound_box.xh if (bound_box and ((bound_box.xh > xh) or bbox_overwrite)) else xh + yl = bound_box.yl if ( + bound_box and ((bound_box.yl < yl) or bbox_overwrite)) else yl + yh = bound_box.yh if ( + bound_box and ((bound_box.yh > yh) or bbox_overwrite)) else yh + # bb = bound_box.expand(dy=dy, dx=dx) + bb = BBox(xl=xl, yl=yl, xh=xh, yh=yh) + if num_vss == 0: + sup_type = 'vdd' + elif num_vdd == 0: + sup_type = 'vss' + else: + sup_type = 'both' + vdd, vss = self.do_power_fill(layer_id, tr_manager, vdd_warrs, vss_warrs, bound_box=bb, sup_type=sup_type, + **kwargs) + return vdd, vss + + +def get_boundary_wires(self, warrs: List[WireArray]) -> Tuple[WireArray, WireArray, WireArray, WireArray]: + # return topmost, bottommost, leftmost, and rightmost wire in a list of wires + # initialize + wire_top, wire_bot, wire_left, wire_right = [warrs[0]] * 4 + for wire in warrs: + if wire.bound_box.yh > wire_top.bound_box.yh: + wire_top = wire + if wire.bound_box.yl < wire_bot.bound_box.yl: + wire_bot = wire + if wire.bound_box.xl < wire_left.bound_box.xl: + wire_left = wire + if wire.bound_box.xh > wire_right.bound_box.xh: + wire_right = wire + + return wire_top, wire_bot, wire_left, wire_right diff --git a/src/bag3_analog/schematic/buf_cmos_cell.py b/src/bag3_analog/schematic/buf_cmos_cell.py new file mode 100644 index 0000000..b8a8952 --- /dev/null +++ b/src/bag3_analog/schematic/buf_cmos_cell.py @@ -0,0 +1,91 @@ +# BSD 3-Clause License +# +# Copyright (c) 2018, Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# -*- coding: utf-8 -*- + +from typing import Mapping, Any, List, Tuple + +import pkg_resources +from pathlib import Path + +from bag.design.module import Module +from bag.design.database import ModuleDB +from bag.util.immutable import Param + + +# noinspection PyPep8Naming +class bag3_analog__buf_cmos_cell(Module): + """Module for library bag3_analog cell buf_cmos_cell. + + Fill in high level description here. + """ + + yaml_file = pkg_resources.resource_filename(__name__, + str(Path('netlist_info', + 'buf_cmos_cell.yaml'))) + + def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None: + Module.__init__(self, self.yaml_file, database, params, **kwargs) + + @classmethod + def get_params_info(cls) -> Mapping[str, str]: + """Returns a dictionary from parameter names to descriptions. + + Returns + ------- + param_info : Optional[Mapping[str, str]] + dictionary from parameter names to descriptions. + """ + return dict( + lch='channel length, in meters.', + w_n='pmos/nmos width, in meters/number of fins.', + seg_n='nmos number of fingers.', + w_p='pmos/nmos width, in meters/number of fins.', + seg_p='nmos number of fingers.', + th_p='pmos transistor threshold', + th_n='nmos transistor threshold', + dum_info='dummy information', + ) + + @classmethod + def get_default_param_values(cls) -> Mapping[str, Any]: + return dict( + dum_info=None, + ) + + def design(self, lch: int, w_n: int, w_p: int, seg_n: int, seg_p: int, th_p: str, th_n: str, + dum_info: List[Tuple]) -> None: + self.instances['XN0'].design(w=w_n, l=lch, nf=seg_n, intent=th_n) + self.instances['XN1'].design(w=w_n, l=lch, nf=seg_n, intent=th_n) + self.instances['XP0'].design(w=w_p, l=lch, nf=seg_p, intent=th_p) + self.instances['XP1'].design(w=w_p, l=lch, nf=seg_p, intent=th_p) + + # dummy + self.design_dummy_transistors(dum_info, 'XDUM', 'VDDA', 'VSS') diff --git a/src/bag3_analog/schematic/netlist_info/buf_cmos_cell.symbol.yaml b/src/bag3_analog/schematic/netlist_info/buf_cmos_cell.symbol.yaml new file mode 100644 index 0000000..5151f02 --- /dev/null +++ b/src/bag3_analog/schematic/netlist_info/buf_cmos_cell.symbol.yaml @@ -0,0 +1,920 @@ +lib_name: bag3_analog +cell_name: buf_cmos_cell +view_name: symbol +bbox: + - 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180 + - -30 + - + - 160 + - -30 +instances: + {} +props: + interfaceLastChanged: + - 4 + - time_val: 1583356556 + partName: + - 3 + - tia + pin#: + - 0 + - 11 + portOrder: + - 5 + - name: ILList + bin_val: ("von" "vop" "VDD" "VSS" "vin_m" "vip_m" "vin" "vip") + vendorName: + - 3 + - "" +app_defs: + _dbLastSavedCounter: + - 0 + - 365 + _dbvCvTimeStamp: + - 0 + - 365 + cdbRevision: + - 0 + - 227612 diff --git a/src/bag3_analog/schematic/netlist_info/tia.yaml b/src/bag3_analog/schematic/netlist_info/tia.yaml new file mode 100644 index 0000000..aaa81e1 --- /dev/null +++ b/src/bag3_analog/schematic/netlist_info/tia.yaml @@ -0,0 +1,907 @@ +lib_name: bag3_analog +cell_name: tia +view_name: schematic +bbox: + - -610 + - -410 + - 600 + - 310 +terminals: + VDD: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -540 + - 180 + - R0 + bbox: + - -601 + - 154 + - -530 + - 190 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -565 + - 180 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 1 + ttype: 2 + VSS: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -540 + - 160 + - R0 + bbox: + - -601 + - 134 + - -530 + - 170 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -565 + - 160 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 2 + ttype: 2 + vin: + obj: + - 1 + - inst: + lib_name: basic + cell_name: ipin + view_name: symbol + xform: + - -540 + - 10 + - R0 + bbox: + - -597 + - -16 + - -540 + - 20 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -570 + - 10 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 0 + vin_m: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -540 + - 90 + - R0 + bbox: + - -601 + - 64 + - -530 + - 100 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -565 + - 90 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 2 + vip: + obj: + - 1 + - inst: + lib_name: basic + cell_name: ipin + view_name: symbol + xform: + - -540 + - 30 + - R0 + bbox: + - -597 + - 4 + - -540 + - 40 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -570 + - 30 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 0 + vip_m: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -540 + - 110 + - R0 + bbox: + - -601 + - 84 + - -530 + - 120 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -565 + - 110 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 2 + von: + obj: + - 1 + - inst: + lib_name: basic + cell_name: opin + view_name: symbol + xform: + - -560 + - -60 + - R0 + bbox: + - -560 + - -86 + - -503 + - -50 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -535 + - -60 + alignment: 1 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 1 + vop: + obj: + - 1 + - inst: + lib_name: basic + cell_name: opin + view_name: symbol + xform: + - -560 + - -40 + - R0 + bbox: + - -560 + - -66 + - -503 + - -30 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -535 + - -40 + alignment: 1 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 1 +shapes: + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vin_m + points: + - + - 210 + - 70 + - + - 250 + - 70 + - + - 7 + - layer: 228 + purpose: 237 + net: vin_m + origin: + - 214 + - 77 + alignment: 2 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vin_m + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vop + points: + - + - 210 + - 100 + - + - 250 + - 100 + - + - 7 + - layer: 228 + purpose: 237 + net: vop + origin: + - 214 + - 107 + alignment: 2 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vop + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 60 + - 270 + - + - 60 + - 310 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - 53 + - 274 + alignment: 2 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 5 + - layer: 228 + purpose: 4294967295 + net: von + points: + - + - -130 + - 100 + - + - -90 + - 100 + - + - 7 + - layer: 228 + purpose: 237 + net: von + origin: + - -94 + - 107 + alignment: 8 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: von + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vip_m + points: + - + - -130 + - 70 + - + - -90 + - 70 + - + - 7 + - layer: 228 + purpose: 237 + net: vip_m + origin: + - -104 + - 77 + alignment: 8 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vip_m + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VSS + points: + - + - 60 + - -150 + - + - 60 + - -110 + - + - 7 + - layer: 228 + purpose: 237 + net: VSS + origin: + - 53 + - -114 + alignment: 8 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VSS + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vip + points: + - + - -100 + - -410 + - + - -100 + - -370 + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vip_m + points: + - + - -100 + - -190 + - + - -100 + - -160 + - + - 7 + - layer: 228 + purpose: 237 + net: vip + origin: + - -107 + - -390 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vip + - + - 7 + - layer: 228 + purpose: 237 + net: vip_m + origin: + - -107 + - -170 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vip_m + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - -440 + - 90 + - + - -400 + - 90 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - -420 + - 97 + alignment: 5 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vip_m + points: + - + - -310 + - -70 + - + - -310 + - -30 + - + - 7 + - layer: 228 + purpose: 237 + net: vip_m + origin: + - -317 + - -50 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vip_m + - + - 5 + - layer: 228 + purpose: 4294967295 + net: von + points: + - + - -310 + - 210 + - + - -310 + - 250 + - + - 7 + - layer: 228 + purpose: 237 + net: von + origin: + - -317 + - 230 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: von + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vin + points: + - + - 210 + - -410 + - + - 210 + - -370 + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vin_m + points: + - + - 210 + - -190 + - + - 210 + - -150 + - + - 7 + - layer: 228 + purpose: 237 + net: vin + origin: + - 203 + - -390 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vin + - + - 7 + - layer: 228 + purpose: 237 + net: vin_m + origin: + - 203 + - -170 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vin_m + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vop + points: + - + - 470 + - 200 + - + - 470 + - 240 + - + - 7 + - layer: 228 + purpose: 237 + net: vop + origin: + - 457 + - 220 + alignment: 5 + orient: MXR90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vop + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vin_m + points: + - + - 470 + - -80 + - + - 470 + - -40 + - + - 7 + - layer: 228 + purpose: 237 + net: vin_m + origin: + - 457 + - -60 + alignment: 5 + orient: MXR90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vin_m + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 600 + - 80 + - + - 560 + - 80 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - 564 + - 87 + alignment: 8 + orient: MY + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD +instances: + XBUF: + lib_name: bag_vco + cell_name: buf_cmos_cell_v1 + view_name: symbol + xform: + - -50 + - -110 + - R0 + bbox: + - -94 + - -114 + - 214 + - 274 + connections: + VDDA: VDD + VSS: VSS + vin: vin_m + vip: vip_m + von: von + vop: vop + params: + {} + is_primitive: false + XCAP0: + lib_name: xbase + cell_name: momcap_core + view_name: symbol + xform: + - 150 + - -190 + - R270 + bbox: + - 150 + - -374 + - 270 + - -186 + connections: + minus: vin + plus: vin_m + params: + {} + is_primitive: false + XCAP1: + lib_name: xbase + cell_name: momcap_core + view_name: symbol + xform: + - -160 + - -190 + - R270 + bbox: + - -160 + - -374 + - -40 + - -186 + connections: + minus: vip + plus: vip_m + params: + {} + is_primitive: false + XRES0: + lib_name: bag_vco + cell_name: res + view_name: symbol + xform: + - 380 + - -40 + - R0 + bbox: + - 380 + - -44 + - 564 + - 204 + connections: + MINUS: vin_m + PLUS: vop + VDD: VDD + params: + {} + is_primitive: false + XRES1: + lib_name: bag_vco + cell_name: res + view_name: symbol + xform: + - -220 + - -30 + - MY + bbox: + - -404 + - -34 + - -220 + - 214 + connections: + MINUS: vip_m + PLUS: von + VDD: VDD + params: + {} + is_primitive: false +props: + connectivityLastUpdated: + - 0 + - 5517 + instance#: + - 0 + - 9 + lastSchematicExtraction: + - 4 + - time_val: 1623362357 + net#: + - 0 + - 0 + pin#: + - 0 + - 14 + schGeometryLastUpdated: + - 0 + - 5517 + schGeometryVersion: + - 3 + - sch.ds.gm.1.4 + schXtrVersion: + - 3 + - sch.10.0 +app_defs: + _dbLastSavedCounter: + - 0 + - 5517 + _dbvCvTimeStamp: + - 0 + - 5517 + cdbRevision: + - 0 + - 227612 diff --git a/src/bag3_analog/schematic/netlist_info/tia_res.symbol.yaml b/src/bag3_analog/schematic/netlist_info/tia_res.symbol.yaml new file mode 100644 index 0000000..66276ee --- /dev/null +++ b/src/bag3_analog/schematic/netlist_info/tia_res.symbol.yaml @@ -0,0 +1,255 @@ +lib_name: bag3_analog +cell_name: tia_res +view_name: symbol +bbox: + - 0 + - -4 + - 184 + - 244 +terminals: + MINUS: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 86 + - -4 + - 94 + - 4 + stype: 0 + ttype: 2 + PLUS: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 86 + - 236 + - 94 + - 244 + stype: 0 + ttype: 2 + VDD: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 176 + - 116 + - 184 + - 124 + stype: 0 + ttype: 2 +shapes: + - + - 0 + - layer: 231 + purpose: 4294967295 + net: "" + bbox: + - 40 + - 40 + - 140 + - 200 + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 90 + - 200 + - + - 90 + - 180 + - + - 60 + - 160 + - + - 120 + - 140 + - + - 60 + - 120 + - + - 120 + - 100 + - + - 60 + - 80 + - + - 90 + - 60 + - + - 90 + - 40 + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 90 + - 200 + - + - 90 + - 240 + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 90 + - 40 + - + - 90 + - 0 + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 140 + - 120 + - + - 180 + - 120 + - + - 7 + - layer: 229 + purpose: 237 + net: "" + origin: + - 80 + - 241 + alignment: 7 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: PLUS + - + - 7 + - layer: 229 + purpose: 237 + net: "" + origin: + - 80 + - 51 + alignment: 7 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: MINUS + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 180 + - 120 + - + - 140 + - 120 + - + - 0 + - layer: 236 + purpose: 4294967295 + net: "" + bbox: + - 0 + - 0 + - 180 + - 240 + - + - 7 + - layer: 229 + purpose: 237 + net: "" + origin: + - 174 + - 130 + alignment: 1 + orient: R180 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 8 + - layer: 236 + purpose: 237 + net: "" + origin: + - 0 + - 230 + alignment: 1 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: "[@instanceName]" + evaluator: cdsNLPEvalText + - + - 8 + - layer: 231 + purpose: 237 + net: "" + origin: + - 90 + - 180 + alignment: 5 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: "[@cellName]" + evaluator: cdsNLPEvalText +instances: + {} +props: + interfaceLastChanged: + - 4 + - time_val: 1623188730 + pin#: + - 0 + - 4 + portOrder: + - 5 + - name: ILList + bin_val: ("MINUS" "PLUS" "VDD") +app_defs: + _dbLastSavedCounter: + - 0 + - 131 + _dbvCvTimeStamp: + - 0 + - 131 + cdbRevision: + - 0 + - 227612 diff --git a/src/bag3_analog/schematic/netlist_info/tia_res.yaml b/src/bag3_analog/schematic/netlist_info/tia_res.yaml new file mode 100644 index 0000000..b4f6ca2 --- /dev/null +++ b/src/bag3_analog/schematic/netlist_info/tia_res.yaml @@ -0,0 +1,381 @@ +lib_name: bag3_analog +cell_name: tia_res +view_name: schematic +bbox: + - -222 + - -210 + - 130 + - 110 +terminals: + MINUS: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -150 + - 80 + - R0 + bbox: + - -211 + - 54 + - -140 + - 90 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -175 + - 80 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 2 + PLUS: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -150 + - 100 + - R0 + bbox: + - -211 + - 74 + - -140 + - 110 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -175 + - 100 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 2 + VDD: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -150 + - 60 + - R0 + bbox: + - -211 + - 34 + - -140 + - 70 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -175 + - 60 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 2 +shapes: + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 20 + - 20 + - + - 60 + - 20 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - 24 + - 27 + alignment: 2 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 5 + - layer: 228 + purpose: 4294967295 + net: MINUS + points: + - + - 0 + - -40 + - + - 0 + - 0 + - + - 7 + - layer: 228 + purpose: 237 + net: MINUS + origin: + - -7 + - -4 + alignment: 8 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: MINUS + - + - 5 + - layer: 228 + purpose: 4294967295 + net: PLUS + points: + - + - 0 + - 60 + - + - 0 + - 100 + - + - 7 + - layer: 228 + purpose: 237 + net: PLUS + origin: + - -7 + - 64 + alignment: 2 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: PLUS + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 0 + - -110 + - + - 0 + - -70 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - -7 + - -106 + alignment: 2 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 0 + - -210 + - + - 0 + - -170 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - -7 + - -174 + alignment: 8 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 20 + - -150 + - + - 60 + - -150 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - 24 + - -143 + alignment: 2 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD +instances: + XDUM: + lib_name: BAG_prim + cell_name: res_standard + view_name: symbol + xform: + - -40 + - -100 + - R0 + bbox: + - -132 + - -174 + - 130 + - -100 + connections: + BULK: VDD + MINUS: VDD + PLUS: VDD + params: + l: + - 3 + - 400n + w: + - 3 + - 400n + is_primitive: true + XRES: + lib_name: BAG_prim + cell_name: res_standard + view_name: symbol + xform: + - -40 + - 70 + - R0 + bbox: + - -132 + - -4 + - 130 + - 70 + connections: + BULK: VDD + MINUS: MINUS + PLUS: PLUS + params: + l: + - 3 + - 400n + w: + - 3 + - 400n + is_primitive: true +props: + connectivityLastUpdated: + - 0 + - 506 + instance#: + - 0 + - 1 + lastSchematicExtraction: + - 4 + - time_val: 1623188759 + net#: + - 0 + - 0 + pin#: + - 0 + - 6 + schGeometryLastUpdated: + - 0 + - 506 + schGeometryVersion: + - 3 + - sch.ds.gm.1.4 + schXtrVersion: + - 3 + - sch.10.0 +app_defs: + _dbLastSavedCounter: + - 0 + - 506 + _dbvCvTimeStamp: + - 0 + - 506 + cdbRevision: + - 0 + - 227612 diff --git a/src/bag3_analog/schematic/netlist_info/tia_term.symbol.yaml b/src/bag3_analog/schematic/netlist_info/tia_term.symbol.yaml new file mode 100644 index 0000000..aadce65 --- /dev/null +++ b/src/bag3_analog/schematic/netlist_info/tia_term.symbol.yaml @@ -0,0 +1,686 @@ +lib_name: bag3_analog +cell_name: tia_term +view_name: symbol +bbox: + - 16 + - -124 + - 224 + - 104 +terminals: + VDD: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 116 + - 96 + - 124 + - 104 + stype: 1 + ttype: 2 + VSS: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 116 + - -124 + - 124 + - -116 + stype: 2 + ttype: 2 + vin: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 16 + - -34 + - 24 + - -26 + stype: 0 + ttype: 0 + vip: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 16 + - 6 + - 24 + - 14 + stype: 0 + ttype: 0 + von: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 216 + - 6 + - 224 + - 14 + stype: 0 + ttype: 1 + vop: + obj: + - 0 + - layer: 229 + purpose: 4294967295 + net: "" + bbox: + - 216 + - -34 + - 224 + - -26 + stype: 0 + ttype: 1 +shapes: + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 20 + - 10 + - + - 60 + - 10 + - + - 7 + - layer: 229 + purpose: 237 + net: "" + origin: + - 26 + - 20 + alignment: 1 + orient: MX + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vip + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 20 + - -30 + - + - 60 + - -30 + - + - 7 + - layer: 229 + purpose: 237 + net: "" + origin: + - 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+ - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - + - 120 + - 100 + - + - 120 + - 60 + - + - 7 + - layer: 229 + purpose: 237 + net: "" + origin: + - 110 + - 94 + alignment: 1 + orient: R270 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 0 + - layer: 236 + purpose: 4294967295 + net: "" + bbox: + - 20 + - -120 + - 220 + - 100 + - + - 8 + - layer: 236 + purpose: 237 + net: "" + origin: + - 60 + - 70 + alignment: 1 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: "[@instanceName]" + evaluator: cdsNLPEvalText + - + - 8 + - layer: 231 + purpose: 237 + net: "" + origin: + - 105 + - -70 + alignment: 4 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: "[@partName]" + evaluator: cdsNLPEvalText + - + - 0 + - layer: 231 + purpose: 4294967295 + net: "" + bbox: + - 60 + - -80 + - 180 + - 60 + - + - 5 + - layer: 231 + purpose: 4294967295 + net: "" + points: + - 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0 + - 418 + _dbvCvTimeStamp: + - 0 + - 418 + cdbRevision: + - 0 + - 227612 diff --git a/src/bag3_analog/schematic/netlist_info/tia_term.yaml b/src/bag3_analog/schematic/netlist_info/tia_term.yaml new file mode 100644 index 0000000..2c97fcb --- /dev/null +++ b/src/bag3_analog/schematic/netlist_info/tia_term.yaml @@ -0,0 +1,858 @@ +lib_name: bag3_analog +cell_name: tia_term +view_name: schematic +bbox: + - -601 + - -460 + - 600 + - 310 +terminals: + VDD: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -540 + - 180 + - R0 + bbox: + - -601 + - 154 + - -530 + - 190 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -565 + - 180 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 1 + ttype: 2 + VSS: + obj: + - 1 + - inst: + lib_name: basic + cell_name: iopin + view_name: symbolr + xform: + - -540 + - 160 + - R0 + bbox: + - -601 + - 134 + - -530 + - 170 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -565 + - 160 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 2 + ttype: 2 + vin: + obj: + - 1 + - inst: + lib_name: basic + cell_name: ipin + view_name: symbol + xform: + - -540 + - 10 + - R0 + bbox: + - -597 + - -16 + - -540 + - 20 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -570 + - 10 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 0 + vip: + obj: + - 1 + - inst: + lib_name: basic + cell_name: ipin + view_name: symbol + xform: + - -540 + - 30 + - R0 + bbox: + - -597 + - 4 + - -540 + - 40 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -570 + - 30 + alignment: 7 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 0 + von: + obj: + - 1 + - inst: + lib_name: basic + cell_name: opin + view_name: symbol + xform: + - -560 + - -60 + - R0 + bbox: + - -560 + - -86 + - -503 + - -50 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -535 + - -60 + alignment: 1 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 1 + vop: + obj: + - 1 + - inst: + lib_name: basic + cell_name: opin + view_name: symbol + xform: + - -560 + - -40 + - R0 + bbox: + - -560 + - -66 + - -503 + - -30 + connections: + {} + params: + {} + is_primitive: true + attr: + layer: 229 + purpose: 237 + net: "" + origin: + - -535 + - -40 + alignment: 1 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + attr_type: 0 + format: 1 + stype: 0 + ttype: 1 +shapes: + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vin + points: + - + - 210 + - 70 + - + - 250 + - 70 + - + - 7 + - layer: 228 + purpose: 237 + net: vin + origin: + - 214 + - 77 + alignment: 2 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vin + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vop + points: + - + - 210 + - 100 + - + - 250 + - 100 + - + - 7 + - layer: 228 + purpose: 237 + net: vop + origin: + - 214 + - 107 + alignment: 2 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vop + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 60 + - 270 + - + - 60 + - 310 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - 53 + - 274 + alignment: 2 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 5 + - layer: 228 + purpose: 4294967295 + net: von + points: + - + - -130 + - 100 + - + - -90 + - 100 + - + - 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+ - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - -36 + - -293 + alignment: 2 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 7 + - layer: 228 + purpose: 237 + net: vin + origin: + - -137 + - -424 + alignment: 8 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vin + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - -440 + - 90 + - + - -400 + - 90 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - -420 + - 97 + alignment: 5 + orient: R0 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vip + points: + - + - -310 + - -70 + - + - -310 + - -30 + - + - 7 + - layer: 228 + purpose: 237 + net: vip + origin: + - -317 + - -50 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vip + - + - 5 + - layer: 228 + purpose: 4294967295 + net: von + points: + - + - -310 + - 210 + - + - -310 + - 250 + - + - 7 + - layer: 228 + purpose: 237 + net: von + origin: + - -317 + - 230 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: von + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 210 + - -420 + - + - 210 + - -380 + - + - 5 + - layer: 228 + purpose: 4294967295 + net: mid + points: + - + - 210 + - -200 + - + - 210 + - -160 + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vip + points: + - + - -130 + - -180 + - + - -130 + - -140 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - 203 + - -400 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD + - + - 7 + - layer: 228 + purpose: 237 + net: mid + origin: + - 203 + - -180 + alignment: 5 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: mid + - + - 7 + - layer: 228 + purpose: 237 + net: vip + origin: + - -137 + - -176 + alignment: 2 + orient: R90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vip + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vop + points: + - + - 470 + - 200 + - + - 470 + - 240 + - + - 7 + - layer: 228 + purpose: 237 + net: vop + origin: + - 457 + - 220 + alignment: 5 + orient: MXR90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vop + - + - 5 + - layer: 228 + purpose: 4294967295 + net: vin + points: + - + - 470 + - -80 + - + - 470 + - -40 + - + - 7 + - layer: 228 + purpose: 237 + net: vin + origin: + - 457 + - -60 + alignment: 5 + orient: MXR90 + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: vin + - + - 5 + - layer: 228 + purpose: 4294967295 + net: VDD + points: + - + - 600 + - 80 + - + - 560 + - 80 + - + - 7 + - layer: 228 + purpose: 237 + net: VDD + origin: + - 564 + - 87 + alignment: 8 + orient: MY + font: 5 + height: 10 + overbar: false + visible: true + drafting: true + text: VDD +instances: + XBUF: + lib_name: bag_vco + cell_name: buf_cmos_cell_v1 + view_name: symbol + xform: + - -50 + - -110 + - R0 + bbox: + - -94 + - -114 + - 214 + - 274 + connections: + VDDA: VDD + VSS: VSS + vin: vin + vip: vip + von: von + vop: vop + params: + {} + is_primitive: false + XDECAP: + lib_name: xbase + cell_name: momcap_core + view_name: symbol + xform: + - 150 + - -200 + - R270 + bbox: + - 150 + - -384 + - 270 + - -196 + connections: + minus: VDD + plus: mid + params: + {} + is_primitive: false + XRES0: + lib_name: bag_vco + cell_name: res + view_name: symbol + xform: + - 380 + - -40 + - R0 + bbox: + - 380 + - -44 + - 564 + - 204 + connections: + MINUS: vin + PLUS: vop + VDD: VDD + params: + {} + is_primitive: false + XRES1: + lib_name: bag_vco + cell_name: res + view_name: symbol + xform: + - -220 + - -30 + - MY + bbox: + - -404 + - -34 + - -220 + - 214 + connections: + MINUS: vip + PLUS: von + VDD: VDD + params: + {} + is_primitive: false + XTERM: + lib_name: bag3_analog + cell_name: res_termination + view_name: symbol + xform: + - -220 + - -420 + - R0 + bbox: + - -220 + - -424 + - -36 + - -176 + connections: + BULK: VDD + MINUS: vin + PLUS: vip + params: + {} + is_primitive: false +props: + connectivityLastUpdated: + - 0 + - 6590 + instance#: + - 0 + - 10 + lastSchematicExtraction: + - 4 + - time_val: 1634030416 + net#: + - 0 + - 0 + pin#: + - 0 + - 14 + schGeometryLastUpdated: + - 0 + - 6590 + schGeometryVersion: + - 3 + - sch.ds.gm.1.4 + schXtrVersion: + - 3 + - sch.10.0 +app_defs: + _dbLastSavedCounter: + - 0 + - 6590 + _dbvCvTimeStamp: + - 0 + - 6590 + cdbRevision: + - 0 + - 227612 diff --git a/src/bag3_analog/schematic/tia.py b/src/bag3_analog/schematic/tia.py new file mode 100644 index 0000000..7d2b764 --- /dev/null +++ b/src/bag3_analog/schematic/tia.py @@ -0,0 +1,88 @@ +# BSD 3-Clause License +# +# Copyright (c) 2018, Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# -*- coding: utf-8 -*- + +from typing import Mapping, Any + +import pkg_resources +from pathlib import Path + +from bag.design.module import Module +from bag.design.database import ModuleDB +from bag.util.immutable import Param + + +# noinspection PyPep8Naming +class bag3_analog__tia(Module): + """Module for library bag3_analog cell tia. + + Fill in high level description here. + """ + + yaml_file = pkg_resources.resource_filename(__name__, + str(Path('netlist_info', + 'tia.yaml'))) + + def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None: + Module.__init__(self, self.yaml_file, database, params, **kwargs) + + @classmethod + def get_params_info(cls) -> Mapping[str, str]: + """Returns a dictionary from parameter names to descriptions. + + Returns + ------- + param_info : Optional[Mapping[str, str]] + dictionary from parameter names to descriptions. + """ + return dict( + buf_cmos_cell_params='buffer cmos cell parameters ', + res_params='resistor parameters', + cap_params='capacitor parameters', + with_cap='True to have cap', + ) + + def design(self, buf_cmos_cell_params: Param, res_params: Param, cap_params: Param, with_cap: bool) -> None: + self.instances['XBUF'].design(**buf_cmos_cell_params) + self.instances['XRES0'].design(**res_params) + self.instances['XRES1'].design(**res_params) + if with_cap: + self.instances['XCAP0'].design(**cap_params) + self.instances['XCAP1'].design(**cap_params) + else: + self.delete_instance('XCAP0') + self.delete_instance('XCAP1') + self.reconnect_instance_terminal('XBUF', 'vip', 'vip') + self.reconnect_instance_terminal('XBUF', 'vin', 'vin') + self.reconnect_instance_terminal('XRES1', 'MINUS', 'vip') + self.reconnect_instance_terminal('XRES0', 'MINUS', 'vin') + self.remove_pin('vip_m') + self.remove_pin('vin_m') \ No newline at end of file diff --git a/src/bag3_analog/schematic/tia_res.py b/src/bag3_analog/schematic/tia_res.py new file mode 100644 index 0000000..02c2f1c --- /dev/null +++ b/src/bag3_analog/schematic/tia_res.py @@ -0,0 +1,89 @@ +# BSD 3-Clause License +# +# Copyright (c) 2018, Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# -*- coding: utf-8 -*- + +from typing import Mapping, Any + +import pkg_resources +from pathlib import Path + +from bag.design.module import Module +from bag.design.database import ModuleDB +from bag.util.immutable import Param + + +# noinspection PyPep8Naming +class bag3_analog__tia_res(Module): + """Module for library bag3_analog cell tia_res. + + Fill in high level description here. + """ + + yaml_file = pkg_resources.resource_filename(__name__, + str(Path('netlist_info', + 'tia_res.yaml'))) + + def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None: + Module.__init__(self, self.yaml_file, database, params, **kwargs) + + @classmethod + def get_params_info(cls) -> Mapping[str, str]: + """Returns a dictionary from parameter names to descriptions. + + Returns + ------- + param_info : Optional[Mapping[str, str]] + dictionary from parameter names to descriptions. + """ + return dict( + res_params='Parameters for feedback resistors', + dum_params='Optional Parameters for dummy resistors', + sub_type='"ntap" or "ptap"', + ) + + @classmethod + def get_default_param_values(cls) -> Mapping[str, Any]: + return dict(dum_params=None) + + def design(self, res_params: Mapping[str, Any], dum_params: Mapping[str, Any], sub_type: str) -> None: + if sub_type == 'ptap': + for inst_name in ('XRES', 'XDUM'): + self.reconnect_instance_terminal(inst_name, 'BULK', 'VSS') + self.rename_pin('VDD', 'VSS') + + if dum_params: + self.design_resistor('XDUM', **dum_params, mid='dum') + else: + self.remove_instance('XDUM') + + self.design_resistor('XRES', **res_params, mid='mid') + + diff --git a/src/bag3_analog/schematic/tia_term.py b/src/bag3_analog/schematic/tia_term.py new file mode 100644 index 0000000..53b3d53 --- /dev/null +++ b/src/bag3_analog/schematic/tia_term.py @@ -0,0 +1,82 @@ +# BSD 3-Clause License +# +# Copyright (c) 2018, Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# -*- coding: utf-8 -*- + +from typing import Mapping, Any + +import pkg_resources +from pathlib import Path + +from bag.design.module import Module +from bag.design.database import ModuleDB +from bag.util.immutable import Param + + +# noinspection PyPep8Naming +class bag3_analog__tia_term(Module): + """Module for library bag3_analog cell tia_term. + + Fill in high level description here. + """ + + yaml_file = pkg_resources.resource_filename(__name__, + str(Path('netlist_info', + 'tia_term.yaml'))) + + def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None: + Module.__init__(self, self.yaml_file, database, params, **kwargs) + + @classmethod + def get_params_info(cls) -> Mapping[str, str]: + """Returns a dictionary from parameter names to descriptions. + + Returns + ------- + param_info : Optional[Mapping[str, str]] + dictionary from parameter names to descriptions. + """ + return dict( + buf_cmos_cell_params='buffer cmos cell parameters ', + res_params='resistor parameters', + res_term_params='termination resistor parameters', + decap_params='decoupling capacitor parameters', + ) + + def design(self, buf_cmos_cell_params: Param, res_params: Param, res_term_params: Param, + decap_params: Param) -> None: + self.instances['XBUF'].design(**buf_cmos_cell_params) + self.instances['XRES0'].design(**res_params) + self.instances['XRES1'].design(**res_params) + self.instances['XTERM'].design(**res_term_params) + self.instances['XDECAP'].design(**decap_params) + + self.reconnect_instance_terminal('XTERM', 'MID', 'mid') + self.reconnect_instance_terminal('XTERM', 'VDD', 'VDD')