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SMEtestApp.swift
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SMEtestApp.swift
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extension Double {
func rounded(places:Int) -> Double {
let divisor = pow(10.0, Double(places))
return (self * divisor).rounded() / divisor
}
}
let SME_FEATURES = [
"FEAT_SME",
"FEAT_SME2",
"SME_F32F32",
"SME_BI32I32",
"SME_B16F32",
"SME_F16F32",
"SME_I8I32",
"SME_I16I32",
"FEAT_SME_F64F64",
"FEAT_SME_I16I64"
]
@main
struct SMEtestApp {
static func main() {
print("-- SME features --")
for feat in SME_FEATURES {
print("\(feat) = \(supports_hw_feature("hw.optional.arm." + feat))")
}
print("Vector length = \(sme_vector_length()*8) bits")
print("")
print("-- Peak outer product accumulating to ZA storage --")
print("")
print(" type | ZA tiles | GFLOPS ")
print(" ------ | ----------- | ---------")
print(" f32 | 4 (full) |", sme_fmopa_f32_4().rounded(places: 2))
print(" f32 | 3 |", sme_fmopa_f32_3().rounded(places: 2))
print(" f32 | 2 |", sme_fmopa_f32_2().rounded(places: 2))
print(" f32 | 1 |", sme_fmopa_f32_1().rounded(places: 2))
print(" ------ | ----------- | ---------")
print(" f64 | 8 (full) |", sme_fmopa_f64_8().rounded(places: 2))
print(" f64 | 7 |", sme_fmopa_f64_7().rounded(places: 2))
print(" f64 | 6 |", sme_fmopa_f64_6().rounded(places: 2))
print(" f64 | 5 |", sme_fmopa_f64_5().rounded(places: 2))
print(" f64 | 4 |", sme_fmopa_f64_4().rounded(places: 2))
print(" f64 | 3 |", sme_fmopa_f64_3().rounded(places: 2))
print(" f64 | 2 |", sme_fmopa_f64_2().rounded(places: 2))
print(" f64 | 1 |", sme_fmopa_f64_1().rounded(places: 2))
print(" ------ | ----------- | ---------")
print(" f16f32 | 4 (full) |", sme_fmopa_f16f32_4().rounded(places: 2))
print(" f16f32 | 3 |", sme_fmopa_f16f32_3().rounded(places: 2))
print(" f16f32 | 2 |", sme_fmopa_f16f32_2().rounded(places: 2))
print(" f16f32 | 1 |", sme_fmopa_f16f32_1().rounded(places: 2))
print(" ------ | ----------- | ---------")
print(" i16i32 | 4 (full) |", sme_smopa_i16i32_4().rounded(places: 2))
print(" i16i32 | 3 |", sme_smopa_i16i32_3().rounded(places: 2))
print(" i16i32 | 2 |", sme_smopa_i16i32_2().rounded(places: 2))
print(" i16i32 | 1 |", sme_smopa_i16i32_1().rounded(places: 2))
print(" ------ | ----------- | ---------")
print(" i8i32 | 4 (full) |", sme_smopa_i8i32_4().rounded(places: 2))
print(" i8i32 | 3 |", sme_smopa_i8i32_3().rounded(places: 2))
print(" i8i32 | 2 |", sme_smopa_i8i32_2().rounded(places: 2))
print(" i8i32 | 1 |", sme_smopa_i8i32_1().rounded(places: 2))
print("")
print("-- Peak fused multiply-add rate accumulating to ZA storage (SME2) --")
print("")
print(" type | VGx | Z registers | ZA slices | GFLOPS ")
print(" ------ | ----- | ------------|------------| ---------")
print(" f32 | 4 | 64, 64 | 64 (full) |", sme_fmla_f32_VGx4_64().rounded(places: 2))
print(" f32 | 4 | 60, 60 | 60 |", sme_fmla_f32_VGx4_60().rounded(places: 2))
print(" f32 | 4 | 56, 56 | 56 |", sme_fmla_f32_VGx4_56().rounded(places: 2))
print(" f32 | 4 | 52, 52 | 52 |", sme_fmla_f32_VGx4_52().rounded(places: 2))
print(" f32 | 4 | 48, 48 | 48 |", sme_fmla_f32_VGx4_48().rounded(places: 2))
print(" f32 | 4 | 44, 44 | 44 |", sme_fmla_f32_VGx4_44().rounded(places: 2))
print(" f32 | 4 | 40, 40 | 40 |", sme_fmla_f32_VGx4_40().rounded(places: 2))
print(" f32 | 4 | 36, 36 | 36 |", sme_fmla_f32_VGx4_36().rounded(places: 2))
print(" f32 | 4 | 32, 32 | 32 |", sme_fmla_f32_VGx4_32().rounded(places: 2))
print(" f32 | 4 | 28, 28 | 28 |", sme_fmla_f32_VGx4_28().rounded(places: 2))
print(" f32 | 4 | 24, 24 | 24 |", sme_fmla_f32_VGx4_24().rounded(places: 2))
print(" f32 | 4 | 20, 20 | 20 |", sme_fmla_f32_VGx4_20().rounded(places: 2))
print(" f32 | 4 | 16, 16 | 16 |", sme_fmla_f32_VGx4_16().rounded(places: 2))
print(" f32 | 4 | 12, 12 | 12 |", sme_fmla_f32_VGx4_12().rounded(places: 2))
print(" f32 | 4 | 8, 8 | 8 |", sme_fmla_f32_VGx4_8().rounded(places: 2))
print(" f32 | 4 | 4, 4 | 4 |", sme_fmla_f32_VGx4_4().rounded(places: 2))
print(" ------ | ----- | ------------|------------| ---------")
print(" f32 | 2 | 64, 64 | 64 (full) |", sme_fmla_f32_VGx2_64().rounded(places: 2))
print(" f32 | 2 | 62, 62 | 62 |", sme_fmla_f32_VGx2_62().rounded(places: 2))
print(" f32 | 2 | 60, 60 | 60 |", sme_fmla_f32_VGx2_60().rounded(places: 2))
print(" f32 | 2 | 58, 58 | 58 |", sme_fmla_f32_VGx2_58().rounded(places: 2))
print(" f32 | 2 | 56, 56 | 56 |", sme_fmla_f32_VGx2_56().rounded(places: 2))
print(" f32 | 2 | 54, 54 | 54 |", sme_fmla_f32_VGx2_54().rounded(places: 2))
print(" f32 | 2 | 52, 52 | 52 |", sme_fmla_f32_VGx2_52().rounded(places: 2))
print(" f32 | 2 | 50, 50 | 50 |", sme_fmla_f32_VGx2_50().rounded(places: 2))
print(" f32 | 2 | 48, 48 | 48 |", sme_fmla_f32_VGx2_48().rounded(places: 2))
print(" f32 | 2 | 46, 46 | 46 |", sme_fmla_f32_VGx2_46().rounded(places: 2))
print(" f32 | 2 | 44, 44 | 44 |", sme_fmla_f32_VGx2_44().rounded(places: 2))
print(" f32 | 2 | 42, 42 | 42 |", sme_fmla_f32_VGx2_42().rounded(places: 2))
print(" f32 | 2 | 40, 40 | 40 |", sme_fmla_f32_VGx2_40().rounded(places: 2))
print(" f32 | 2 | 38, 38 | 38 |", sme_fmla_f32_VGx2_38().rounded(places: 2))
print(" f32 | 2 | 36, 36 | 36 |", sme_fmla_f32_VGx2_36().rounded(places: 2))
print(" f32 | 2 | 34, 34 | 34 |", sme_fmla_f32_VGx2_34().rounded(places: 2))
print(" f32 | 2 | 32, 32 | 32 |", sme_fmla_f32_VGx2_32().rounded(places: 2))
print(" f32 | 2 | 30, 30 | 30 |", sme_fmla_f32_VGx2_30().rounded(places: 2))
print(" f32 | 2 | 28, 28 | 28 |", sme_fmla_f32_VGx2_28().rounded(places: 2))
print(" f32 | 2 | 26, 26 | 26 |", sme_fmla_f32_VGx2_26().rounded(places: 2))
print(" f32 | 2 | 24, 24 | 24 |", sme_fmla_f32_VGx2_24().rounded(places: 2))
print(" f32 | 2 | 22, 22 | 22 |", sme_fmla_f32_VGx2_22().rounded(places: 2))
print(" f32 | 2 | 20, 20 | 20 |", sme_fmla_f32_VGx2_20().rounded(places: 2))
print(" f32 | 2 | 18, 18 | 18 |", sme_fmla_f32_VGx2_18().rounded(places: 2))
print(" f32 | 2 | 16, 16 | 16 |", sme_fmla_f32_VGx2_16().rounded(places: 2))
print(" f32 | 2 | 14, 14 | 14 |", sme_fmla_f32_VGx2_14().rounded(places: 2))
print(" f32 | 2 | 12, 12 | 12 |", sme_fmla_f32_VGx2_12().rounded(places: 2))
print(" f32 | 2 | 10, 10 | 10 |", sme_fmla_f32_VGx2_10().rounded(places: 2))
print(" f32 | 2 | 8, 8 | 8 |", sme_fmla_f32_VGx2_8().rounded(places: 2))
print(" f32 | 2 | 6, 6 | 6 |", sme_fmla_f32_VGx2_6().rounded(places: 2))
print(" f32 | 2 | 4, 4 | 4 |", sme_fmla_f32_VGx2_4().rounded(places: 2))
print(" f32 | 2 | 2, 2 | 2 |", sme_fmla_f32_VGx2_2().rounded(places: 2))
print(" ------ | ----- | ------------|------------| ---------")
print(" f64 | 4 | 64, 64 | 64 (full) |", sme_fmla_f64_VGx4_64().rounded(places: 2))
print(" f64 | 4 | 60, 60 | 60 |", sme_fmla_f64_VGx4_60().rounded(places: 2))
print(" f64 | 4 | 56, 56 | 56 |", sme_fmla_f64_VGx4_56().rounded(places: 2))
print(" f64 | 4 | 52, 52 | 52 |", sme_fmla_f64_VGx4_52().rounded(places: 2))
print(" f64 | 4 | 48, 48 | 48 |", sme_fmla_f64_VGx4_48().rounded(places: 2))
print(" f64 | 4 | 44, 44 | 44 |", sme_fmla_f64_VGx4_44().rounded(places: 2))
print(" f64 | 4 | 40, 40 | 40 |", sme_fmla_f64_VGx4_40().rounded(places: 2))
print(" f64 | 4 | 36, 36 | 36 |", sme_fmla_f64_VGx4_36().rounded(places: 2))
print(" f64 | 4 | 32, 32 | 32 |", sme_fmla_f64_VGx4_32().rounded(places: 2))
print(" f64 | 4 | 28, 28 | 28 |", sme_fmla_f64_VGx4_28().rounded(places: 2))
print(" f64 | 4 | 24, 24 | 24 |", sme_fmla_f64_VGx4_24().rounded(places: 2))
print(" f64 | 4 | 20, 20 | 20 |", sme_fmla_f64_VGx4_20().rounded(places: 2))
print(" f64 | 4 | 16, 16 | 16 |", sme_fmla_f64_VGx4_16().rounded(places: 2))
print(" f64 | 4 | 12, 12 | 12 |", sme_fmla_f64_VGx4_12().rounded(places: 2))
print(" f64 | 4 | 8, 8 | 8 |", sme_fmla_f64_VGx4_8().rounded(places: 2))
print(" f64 | 4 | 4, 4 | 4 |", sme_fmla_f64_VGx4_4().rounded(places: 2))
print(" ------ | ----- | ------------|------------| ---------")
print(" f64 | 2 | 64, 64 | 64 (full) |", sme_fmla_f64_VGx2_64().rounded(places: 2))
print(" f64 | 2 | 62, 62 | 62 |", sme_fmla_f64_VGx2_62().rounded(places: 2))
print(" f64 | 2 | 60, 60 | 60 |", sme_fmla_f64_VGx2_60().rounded(places: 2))
print(" f64 | 2 | 58, 58 | 58 |", sme_fmla_f64_VGx2_58().rounded(places: 2))
print(" f64 | 2 | 56, 56 | 56 |", sme_fmla_f64_VGx2_56().rounded(places: 2))
print(" f64 | 2 | 54, 54 | 54 |", sme_fmla_f64_VGx2_54().rounded(places: 2))
print(" f64 | 2 | 52, 52 | 52 |", sme_fmla_f64_VGx2_52().rounded(places: 2))
print(" f64 | 2 | 50, 50 | 50 |", sme_fmla_f64_VGx2_50().rounded(places: 2))
print(" f64 | 2 | 48, 48 | 48 |", sme_fmla_f64_VGx2_48().rounded(places: 2))
print(" f64 | 2 | 46, 46 | 46 |", sme_fmla_f64_VGx2_46().rounded(places: 2))
print(" f64 | 2 | 44, 44 | 44 |", sme_fmla_f64_VGx2_44().rounded(places: 2))
print(" f64 | 2 | 42, 42 | 42 |", sme_fmla_f64_VGx2_42().rounded(places: 2))
print(" f64 | 2 | 40, 40 | 40 |", sme_fmla_f64_VGx2_40().rounded(places: 2))
print(" f64 | 2 | 38, 38 | 38 |", sme_fmla_f64_VGx2_38().rounded(places: 2))
print(" f64 | 2 | 36, 36 | 36 |", sme_fmla_f64_VGx2_36().rounded(places: 2))
print(" f64 | 2 | 34, 34 | 34 |", sme_fmla_f64_VGx2_34().rounded(places: 2))
print(" f64 | 2 | 32, 32 | 32 |", sme_fmla_f64_VGx2_32().rounded(places: 2))
print(" f64 | 2 | 30, 30 | 30 |", sme_fmla_f64_VGx2_30().rounded(places: 2))
print(" f64 | 2 | 28, 28 | 28 |", sme_fmla_f64_VGx2_28().rounded(places: 2))
print(" f64 | 2 | 26, 26 | 26 |", sme_fmla_f64_VGx2_26().rounded(places: 2))
print(" f64 | 2 | 24, 24 | 24 |", sme_fmla_f64_VGx2_24().rounded(places: 2))
print(" f64 | 2 | 22, 22 | 22 |", sme_fmla_f64_VGx2_22().rounded(places: 2))
print(" f64 | 2 | 20, 20 | 20 |", sme_fmla_f64_VGx2_20().rounded(places: 2))
print(" f64 | 2 | 18, 18 | 18 |", sme_fmla_f64_VGx2_18().rounded(places: 2))
print(" f64 | 2 | 16, 16 | 16 |", sme_fmla_f64_VGx2_16().rounded(places: 2))
print(" f64 | 2 | 14, 14 | 14 |", sme_fmla_f64_VGx2_14().rounded(places: 2))
print(" f64 | 2 | 12, 12 | 12 |", sme_fmla_f64_VGx2_12().rounded(places: 2))
print(" f64 | 2 | 10, 10 | 10 |", sme_fmla_f64_VGx2_10().rounded(places: 2))
print(" f64 | 2 | 8, 8 | 8 |", sme_fmla_f64_VGx2_8().rounded(places: 2))
print(" f64 | 2 | 6, 6 | 6 |", sme_fmla_f64_VGx2_6().rounded(places: 2))
print(" f64 | 2 | 4, 4 | 4 |", sme_fmla_f64_VGx2_4().rounded(places: 2))
print(" f64 | 2 | 2, 2 | 2 |", sme_fmla_f64_VGx2_2().rounded(places: 2))
print(" ------ | ----- | ------------|------------| ---------")
print(" f16f32 | 4 | 32, 32 | 64 (full) |", sme_fmlal_f16f32_VGx4_64().rounded(places: 2))
print(" f16f32 | 4 | 28, 28 | 56 |", sme_fmlal_f16f32_VGx4_56().rounded(places: 2))
print(" f16f32 | 4 | 24, 24 | 48 |", sme_fmlal_f16f32_VGx4_48().rounded(places: 2))
print(" f16f32 | 4 | 20, 20 | 40 |", sme_fmlal_f16f32_VGx4_40().rounded(places: 2))
print(" f16f32 | 4 | 16, 16 | 32 |", sme_fmlal_f16f32_VGx4_32().rounded(places: 2))
print(" f16f32 | 4 | 12, 12 | 24 |", sme_fmlal_f16f32_VGx4_24().rounded(places: 2))
print(" f16f32 | 4 | 8, 8 | 16 |", sme_fmlal_f16f32_VGx4_16().rounded(places: 2))
print(" f16f32 | 4 | 4, 4 | 8 |", sme_fmlal_f16f32_VGx4_8 ().rounded(places: 2))
print(" ------ | ----- | ------------|------------| ---------")
print(" f16f32 | 2 | 32, 32 | 64 (full) |", sme_fmlal_f16f32_VGx2_64().rounded(places: 2))
print(" f16f32 | 2 | 30, 30 | 60 |", sme_fmlal_f16f32_VGx2_60().rounded(places: 2))
print(" f16f32 | 2 | 28, 28 | 56 |", sme_fmlal_f16f32_VGx2_56().rounded(places: 2))
print(" f16f32 | 2 | 26, 26 | 52 |", sme_fmlal_f16f32_VGx2_52().rounded(places: 2))
print(" f16f32 | 2 | 24, 24 | 48 |", sme_fmlal_f16f32_VGx2_48().rounded(places: 2))
print(" f16f32 | 2 | 22, 22 | 44 |", sme_fmlal_f16f32_VGx2_44().rounded(places: 2))
print(" f16f32 | 2 | 20, 20 | 40 |", sme_fmlal_f16f32_VGx2_40().rounded(places: 2))
print(" f16f32 | 2 | 18, 18 | 36 |", sme_fmlal_f16f32_VGx2_36().rounded(places: 2))
print(" f16f32 | 2 | 16, 16 | 32 |", sme_fmlal_f16f32_VGx2_32().rounded(places: 2))
print(" f16f32 | 2 | 14, 14 | 28 |", sme_fmlal_f16f32_VGx2_28().rounded(places: 2))
print(" f16f32 | 2 | 12, 12 | 24 |", sme_fmlal_f16f32_VGx2_24().rounded(places: 2))
print(" f16f32 | 2 | 10, 10 | 20 |", sme_fmlal_f16f32_VGx2_20().rounded(places: 2))
print(" f16f32 | 2 | 8, 8 | 16 |", sme_fmlal_f16f32_VGx2_16().rounded(places: 2))
print(" f16f32 | 2 | 6, 6 | 12 |", sme_fmlal_f16f32_VGx2_12().rounded(places: 2))
print(" f16f32 | 2 | 4, 4 | 8 |", sme_fmlal_f16f32_VGx2_8 ().rounded(places: 2))
print(" f16f32 | 2 | 2, 2 | 4 |", sme_fmlal_f16f32_VGx2_4 ().rounded(places: 2))
}
}