From c5ad2d3d6b2dd2f68c60f151e635a024390551d5 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 24 Feb 2025 13:54:25 +0100 Subject: [PATCH 1/7] add insert_markers_llvm20.patch (untested) --- .../patches/llvm/insert_markers_llvm20.patch | 183 ++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 seal5/resources/patches/llvm/insert_markers_llvm20.patch diff --git a/seal5/resources/patches/llvm/insert_markers_llvm20.patch b/seal5/resources/patches/llvm/insert_markers_llvm20.patch new file mode 100644 index 00000000..74cf5a9d --- /dev/null +++ b/seal5/resources/patches/llvm/insert_markers_llvm20.patch @@ -0,0 +1,183 @@ +diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td +--- a/clang/include/clang/Basic/BuiltinsRISCV.td ++++ b/clang/include/clang/Basic/BuiltinsRISCV.td +@@ -151,3 +151,6 @@ def ntl_store : RISCVBuiltin<"void(...)">; + // XCV extensions. + //===----------------------------------------------------------------------===// + include "clang/Basic/BuiltinsRISCVXCV.td" ++ ++// BuiltinsRISCV.td - builtins_riscv - INSERTION_START ++// BuiltinsRISCV.td - builtins_riscv - INSERTION_END +diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp +--- a/clang/lib/CodeGen/CGBuiltin.cpp ++++ b/clang/lib/CodeGen/CGBuiltin.cpp +@@ -23337,6 +23337,9 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, + ID = Intrinsic::riscv_sha256sum1; + break; + ++// CGBuiltin.cpp - cg_builtin - INSERTION_START ++// CGBuiltin.cpp - cg_builtin - INSERTION_END ++ + // Zksed + case RISCV::BI__builtin_riscv_sm4ks: + ID = Intrinsic::riscv_sm4ks; +diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td +--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td ++++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td +@@ -1876,6 +1876,8 @@ let TargetPrefix = "riscv" in { + // Zvksh + def int_riscv_vsm3c : RISCVBinaryAAXUnMaskedZvk; + def int_riscv_vsm3me : RISCVBinaryAAXUnMasked; ++// IntrinsicsRISCV.td - intrinsics_riscv - INSERTION_START ++// IntrinsicsRISCV.td - intrinsics_riscv - INSERTION_END + } // TargetPrefix = "riscv" + + // Vendor extensions +diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h +--- a/llvm/include/llvm/InitializePasses.h ++++ b/llvm/include/llvm/InitializePasses.h +@@ -323,6 +323,8 @@ void initializeWasmEHPreparePass(PassRegistry &); + void initializeWinEHPreparePass(PassRegistry &); + void initializeWriteBitcodePassPass(PassRegistry &); + void initializeXRayInstrumentationPass(PassRegistry &); ++// InitializePasses.h - initialize_passes_decl - INSERTION_START ++// InitializePasses.h - initialize_passes_decl - INSERTION_END + + } // end namespace llvm + +diff --git a/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt b/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt +--- a/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt ++++ b/llvm/lib/CodeGen/GlobalISel/CMakeLists.txt +@@ -28,6 +28,8 @@ add_llvm_component_library(LLVMGlobalISel + MachineIRBuilder.cpp + RegBankSelect.cpp + Utils.cpp ++ # CMakeLists.txt - gisel_cmake_srcs - INSERTION_START ++ # CMakeLists.txt - gisel_cmake_srcs - INSERTION_END + + ADDITIONAL_HEADER_DIRS + ${LLVM_MAIN_INCLUDE_DIR}/llvm/CodeGen/GlobalISel +diff --git a/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp b/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp +--- a/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp ++++ b/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp +@@ -21,4 +21,6 @@ void llvm::initializeGlobalISel(PassRegistry &Registry) { + initializeLocalizerPass(Registry); + initializeRegBankSelectPass(Registry); + initializeInstructionSelectPass(Registry); ++ // GlobalISel.cpp - gisel_init - INSERTION_START ++ // GlobalISel.cpp - gisel_init - INSERTION_END + } +diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp ++++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +@@ -724,6 +724,8 @@ public: + bool isUImm32() const { return IsUImm<32>(); } + bool isUImm48() const { return IsUImm<48>(); } + bool isUImm64() const { return IsUImm<64>(); } ++ // RISCVAsmParser.cpp - riscv_operands - INSERTION_START ++ // RISCVAsmParser.cpp - riscv_operands - INSERTION_END + + bool isUImm5NonZero() const { + if (!isImm()) +diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp ++++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +@@ -122,6 +122,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) + const LLT nxv8p0 = LLT::scalable_vector(8, p0); + const LLT nxv16p0 = LLT::scalable_vector(16, p0); + ++// RISCVLegalizerInfo.cpp - riscv_legalizer_info - INSERTION_START ++// RISCVLegalizerInfo.cpp - riscv_legalizer_info - INSERTION_END ++ + using namespace TargetOpcode; + + auto BoolVecTys = {nxv1s1, nxv2s1, nxv4s1, nxv8s1, nxv16s1, nxv32s1, nxv64s1}; +diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h ++++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +@@ -337,6 +337,8 @@ enum OperandType : unsigned { + OPERAND_CLUI_IMM, + OPERAND_VTYPEI10, + OPERAND_VTYPEI11, ++ // RISCVBaseInfo.h - riscv_operands - INSERTION_START ++ // RISCVBaseInfo.h - riscv_operands - INSERTION_END + OPERAND_RVKRNUM, + OPERAND_RVKRNUM_0_7, + OPERAND_RVKRNUM_1_10, +diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td +--- a/llvm/lib/Target/RISCV/RISCV.td ++++ b/llvm/lib/Target/RISCV/RISCV.td +@@ -93,3 +93,6 @@ def RISCV : Target { + let AssemblyWriters = [RISCVAsmWriter]; + let AllowRegisterRenaming = 1; + } ++ ++// RISCV.td - riscv_td_includes - INSERTION_START ++// RISCV.td - riscv_td_includes - INSERTION_END +diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td +--- a/llvm/lib/Target/RISCV/RISCVFeatures.td ++++ b/llvm/lib/Target/RISCV/RISCVFeatures.td +@@ -949,6 +949,9 @@ def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, + AssemblerPredicate<(all_of FeatureStdExtSvinval), + "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; + ++// RISCVFeatures.td - riscv_features - INSERTION_START ++// RISCVFeatures.td - riscv_features - INSERTION_END ++ + def FeatureStdExtSvnapot + : RISCVExtension<1, 0, "NAPOT Translation Contiguity">; + +diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp ++++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +@@ -658,6 +658,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, + setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); + + setBooleanContents(ZeroOrOneBooleanContent); ++// RISCVISelLowering.cpp - legal_ops - INSERTION_START ++// RISCVISelLowering.cpp - legal_ops - INSERTION_END + + if (getTargetMachine().getTargetTriple().isOSLinux()) { + // Custom lowering of llvm.clear_cache. +diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td ++++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +@@ -319,6 +319,9 @@ def simm21_lsb0_jal : Operand { + let OperandType = "OPERAND_PCREL"; + } + ++// RISCVInstrInfo.td - field_types - INSERTION_START ++// RISCVInstrInfo.td - field_types - INSERTION_END ++ + def BareSymbol : AsmOperandClass { + let Name = "BareSymbol"; + let RenderMethod = "addImmOperands"; +@@ -410,6 +413,8 @@ def uimm6gt32 : ImmLeaf; ++// RISCVInstrInfo.td - complex_patterns - INSERTION_START ++// RISCVInstrInfo.td - complex_patterns - INSERTION_END + + // Return the negation of an immediate value. + def NegImm : SDNodeXForm { + let RegInfos = XLenRI; + let isAllocatable = 0; + } ++ ++// RISCVRegisterInfo.td - riscv_register_info - INSERTION_START ++// RISCVRegisterInfo.td - riscv_register_info - INSERTION_END From bd232cdd1cfb3d573f10b081f31a0576aa4f7da9 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 24 Feb 2025 14:15:29 +0100 Subject: [PATCH 2/7] initial changes for llvm20 eval --- examples/common/cfg/patches.yml | 4 +++- seal5/dependencies.py | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/examples/common/cfg/patches.yml b/examples/common/cfg/patches.yml index 1e229487..1362d2b9 100644 --- a/examples/common/cfg/patches.yml +++ b/examples/common/cfg/patches.yml @@ -21,7 +21,9 @@ patches: onlyif: "settings.llvm.state.version.major == 18" - name: insert_markers_llvm19 onlyif: "settings.llvm.state.version.major == 19" - - name: legalizer_split + # - name: legalizer_split + - name: insert_markers_llvm20 + onlyif: "settings.llvm.state.version.major == 20" # TODO: automatially select patch depending on llvm version # generated patch (TODO: implement) # - name: ??? diff --git a/seal5/dependencies.py b/seal5/dependencies.py index 17d6bfb2..cef372e1 100644 --- a/seal5/dependencies.py +++ b/seal5/dependencies.py @@ -114,7 +114,9 @@ def pick_coredsl2llvm_ref(ref: str, llvm_version: LLVMVersion): major, minor, patch = llvm_version.triple - if major == 19: + if major == 20: + ref = "llvm-20.1.0" + elif major == 19: ref = "llvm-19.1.0" elif major == 18: ref = "philippvk5" From 167c4861f1a757e31ffcd8d5d7535d508e9895eb Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 24 Feb 2025 14:15:46 +0100 Subject: [PATCH 3/7] add uimm12_op_llvm20.patch (untested) --- .../patches/llvm/uimm12_op_llvm20.patch | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 seal5/resources/patches/llvm/uimm12_op_llvm20.patch diff --git a/seal5/resources/patches/llvm/uimm12_op_llvm20.patch b/seal5/resources/patches/llvm/uimm12_op_llvm20.patch new file mode 100644 index 00000000..4ac71e3b --- /dev/null +++ b/seal5/resources/patches/llvm/uimm12_op_llvm20.patch @@ -0,0 +1,22 @@ +diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp ++++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +@@ -725,6 +725,7 @@ public: + bool isUImm48() const { return IsUImm<48>(); } + bool isUImm64() const { return IsUImm<64>(); } + // RISCVAsmParser.cpp - riscv_operands - INSERTION_START ++ bool isUImm12() const { return IsUImm<12>(); } + // RISCVAsmParser.cpp - riscv_operands - INSERTION_END + + bool isUImm5NonZero() const { +diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td ++++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +@@ -320,6 +320,7 @@ def simm21_lsb0_jal : Operand { + } + + // RISCVInstrInfo.td - field_types - INSERTION_START ++def uimm12 : RISCVUImmLeafOp<12>; + // RISCVInstrInfo.td - field_types - INSERTION_END + + def BareSymbol : AsmOperandClass { From 05c24e31e688a965f0752956944c42435c040540 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 6 Mar 2025 13:56:06 +0100 Subject: [PATCH 4/7] Revert "add uimm12_op_llvm20.patch (untested)" This reverts commit 18c8526d1725c7c7163680f6be12118ad138ed6a. --- .../patches/llvm/uimm12_op_llvm20.patch | 22 ------------------- 1 file changed, 22 deletions(-) delete mode 100644 seal5/resources/patches/llvm/uimm12_op_llvm20.patch diff --git a/seal5/resources/patches/llvm/uimm12_op_llvm20.patch b/seal5/resources/patches/llvm/uimm12_op_llvm20.patch deleted file mode 100644 index 4ac71e3b..00000000 --- a/seal5/resources/patches/llvm/uimm12_op_llvm20.patch +++ /dev/null @@ -1,22 +0,0 @@ -diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp ---- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp -+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp -@@ -725,6 +725,7 @@ public: - bool isUImm48() const { return IsUImm<48>(); } - bool isUImm64() const { return IsUImm<64>(); } - // RISCVAsmParser.cpp - riscv_operands - INSERTION_START -+ bool isUImm12() const { return IsUImm<12>(); } - // RISCVAsmParser.cpp - riscv_operands - INSERTION_END - - bool isUImm5NonZero() const { -diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td ---- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td -+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td -@@ -320,6 +320,7 @@ def simm21_lsb0_jal : Operand { - } - - // RISCVInstrInfo.td - field_types - INSERTION_START -+def uimm12 : RISCVUImmLeafOp<12>; - // RISCVInstrInfo.td - field_types - INSERTION_END - - def BareSymbol : AsmOperandClass { From 9a892b2a584b2698d25d7f6b5b78caf870742f50 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 6 Mar 2025 13:59:28 +0100 Subject: [PATCH 5/7] [ci] demo_weekly.yml: enable llvm20 in weekly demo --- .github/workflows/demo_weekly.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/demo_weekly.yml b/.github/workflows/demo_weekly.yml index cbd5e892..4ce48cfd 100644 --- a/.github/workflows/demo_weekly.yml +++ b/.github/workflows/demo_weekly.yml @@ -80,6 +80,7 @@ jobs: llvm-ref: - "llvmorg-18.1.0-rc3" - "llvmorg-19.1.7" + - "llvmorg-20.1.0" runs-on: ${{ matrix.os }} steps: - uses: actions/checkout@v4 From b33633048fb0beffd89d2763f56615daddbcb620 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 6 Mar 2025 16:58:02 +0100 Subject: [PATCH 6/7] ExtensionsSettings: drop std field --- seal5/settings.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/seal5/settings.py b/seal5/settings.py index 6371596b..762f6667 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -537,7 +537,6 @@ class ExtensionsSettings(YAMLSettings): version: Optional[str] = None experimental: Optional[bool] = None vendor: Optional[bool] = None - std: Optional[bool] = None description: Optional[str] = None requires: Optional[List[str]] = None instructions: Optional[List[str]] = None @@ -592,12 +591,9 @@ def get_predicate(self, name: Optional[str] = None, with_has: bool = False): feature = self.get_feature(name=name) assert feature is not None if self.vendor: - assert not self.std prefix = "Vendor" - elif self.std: - prefix = "StdExt" else: - prefix = "Ext" + prefix = "StdExt" if with_has: prefix = "Has" + prefix return prefix + feature From 6e9b4ad428a68d5c64353eea5d2525c64b9c8c64 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 6 Mar 2025 16:58:28 +0100 Subject: [PATCH 7/7] riscv_features: llvm 20 support --- .../riscv_features_experimental_new_slim.mako | 2 ++ .../templates/riscv_features_new_slim.mako | 2 ++ seal5/backends/riscv_features/writer.py | 12 ++++++++++-- 3 files changed, 14 insertions(+), 2 deletions(-) create mode 100644 seal5/backends/riscv_features/templates/riscv_features_experimental_new_slim.mako create mode 100644 seal5/backends/riscv_features/templates/riscv_features_new_slim.mako diff --git a/seal5/backends/riscv_features/templates/riscv_features_experimental_new_slim.mako b/seal5/backends/riscv_features/templates/riscv_features_experimental_new_slim.mako new file mode 100644 index 00000000..12be7d39 --- /dev/null +++ b/seal5/backends/riscv_features/templates/riscv_features_experimental_new_slim.mako @@ -0,0 +1,2 @@ +def Feature${predicate} : RISCVExperimentalExtension<"${arch}", ${major}, ${minor}, "${description}">; +def Has${predicate} : Predicate<"Subtarget->has${predicate}()">, AssemblerPredicate<(any_of Feature${predicate}), "'${feature}' (${description})">; diff --git a/seal5/backends/riscv_features/templates/riscv_features_new_slim.mako b/seal5/backends/riscv_features/templates/riscv_features_new_slim.mako new file mode 100644 index 00000000..9dcde111 --- /dev/null +++ b/seal5/backends/riscv_features/templates/riscv_features_new_slim.mako @@ -0,0 +1,2 @@ +def Feature${predicate} : RISCVExtension<${major}, ${minor}, "${description}">; +def Has${predicate} : Predicate<"Subtarget->has${predicate}()">, AssemblerPredicate<(any_of Feature${predicate}), "'${feature}' (${description})">; diff --git a/seal5/backends/riscv_features/writer.py b/seal5/backends/riscv_features/writer.py index 51074e07..35d5258a 100644 --- a/seal5/backends/riscv_features/writer.py +++ b/seal5/backends/riscv_features/writer.py @@ -35,24 +35,28 @@ def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings, llvm_set predicate = ext_settings.get_predicate(name=name) version = ext_settings.get_version() experimental = ext_settings.experimental + vendor = ext_settings.vendor if requires: raise NotImplementedError legacy = True + slim = False if llvm_settings: llvm_state = llvm_settings.state if llvm_state: llvm_version = llvm_state.version # unused today, but needed very soon if llvm_version.major >= 19: legacy = False + if llvm_version.major >= 20: + slim = True if legacy: template_name = "riscv_features" else: if experimental: - template_name = "riscv_features_experimental_new" + template_name = "riscv_features_experimental_new_slim" if slim else "riscv_features_experimental_new" else: - template_name = "riscv_features_new" + template_name = "riscv_features_new_slim" if slim else "riscv_features_new" # TODO: make util! if not isinstance(version, str): @@ -61,6 +65,10 @@ def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings, llvm_set major, minor = list(map(int, version.split(".", 1))) content_template = Template(filename=str(template_dir / f"{template_name}.mako")) + if slim: + # TODO: support experimental- prefix + assert feature.lower() == arch_, "LLVM 20 requires matching arch and feature names" + assert predicate == (f"Vendor{feature}" if vendor else f"StdExt{feature}") content_text = content_template.render( predicate=predicate, feature=feature, arch=arch_, description=description, major=major, minor=minor )