From 2a525f863a3074bbf297d9fc4ac36c53c1d0248a Mon Sep 17 00:00:00 2001 From: Fabian Peddinghaus Date: Wed, 15 Sep 2021 03:33:06 +0200 Subject: [PATCH 1/3] add vector instruction support to riscv arch --- ArchImpl/RISCV/RISCV.h | 2 +- ArchImpl/RISCV/RISCVArch.cpp | 9609 ++++++++++++++++++++----- ArchImpl/RISCV/RISCVArchSpecificImp.h | 6 +- 3 files changed, 7766 insertions(+), 1851 deletions(-) diff --git a/ArchImpl/RISCV/RISCV.h b/ArchImpl/RISCV/RISCV.h index 5959f2e02a..6aefc68277 100755 --- a/ArchImpl/RISCV/RISCV.h +++ b/ArchImpl/RISCV/RISCV.h @@ -79,6 +79,7 @@ struct RISCV { etiss_uint32 CSR[4096]; etiss_uint32 FENCE[4]; etiss_uint32 RES; + etiss_uint8 V[1025]; }; #pragma pack(pop) // undo changes @@ -87,4 +88,3 @@ typedef struct RISCV RISCV; // convenient use of X instead of struct X in genera } // extern "C" #endif #endif - diff --git a/ArchImpl/RISCV/RISCVArch.cpp b/ArchImpl/RISCV/RISCVArch.cpp index b4927270d7..9ea748f52b 100644 --- a/ArchImpl/RISCV/RISCVArch.cpp +++ b/ArchImpl/RISCV/RISCVArch.cpp @@ -6,30 +6,30 @@ * Modification guidelines: - 1. The initial value of SP register should be initialized by ctr0.S/board.S. If not, it could be initialized + 1. The initial value of SP register should be initialized by ctr0.S/board.S. If not, it could be initialized through utility class etiss::VirtualStruct::Field. - + 2. Debug mode print out all assignment results. GDB in 8 is prefered. - + 3. Manually copy the content in bracket ["return ETISS_RETURNCODE_CPUFINISHED; \n"] to terminating instruction, otherwise the emulation can not be ended. - + 4. If subset of encoding error occurs, it means the format of the encoding in the input model was not appropriate - - 5. If the PC register points to wrong address, please notice that some assembly may cause branch operation + + 5. If the PC register points to wrong address, please notice that some assembly may cause branch operation implicitly such as "MOV Rd Rn" in ARMv6-M - - 6. If a variable is the result of dynamic slicing such as, var_1 = var_2, the size would be - calculated during process (if possible), otherwise it is assumed to be the register size. Problems may occur when - var_1 encounters bit manipulation such as "~" due to bit expansion. To change the nml model with explicit slicing + + 6. If a variable is the result of dynamic slicing such as, var_1 = var_2, the size would be + calculated during process (if possible), otherwise it is assumed to be the register size. Problems may occur when + var_1 encounters bit manipulation such as "~" due to bit expansion. To change the nml model with explicit slicing e.g var_1 = val_2<3..0> or avoid bit manipulation for dynamic sliced variable. Otherwise, you have to manually correct it. - - 7. Implementation dependent functionalities such as exception handling should be manully added. Corresponding interfaces - are provided in RISCVArchSpecificImp.h - + + 7. Implementation dependent functionalities such as exception handling should be manully added. Corresponding interfaces + are provided in RISCVArchSpecificImp.h + 8. RISCVGDBCore.h provides the GDBCore class to support gdb flavor debugging feature, modify iy if in need. - + *********************************************************************************************************************************/ #include "RISCVArch.h" @@ -41,7 +41,7 @@ using namespace etiss ; using namespace etiss::instr ; -RISCVArch::RISCVArch():CPUArch("RISCV") +RISCVArch::RISCVArch():CPUArch("RISCV") { headers_.insert("Arch/RISCV/RISCV.h"); } @@ -84,14 +84,14 @@ void RISCVArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) cpu->cycles[i] = 0; } #endif - + // Instantiate the pointers in order to avoid segmentation fault for(int i = 0; i < 32; i ++) { riscvcpu->ins_X[i] = 0; riscvcpu->X[i] = & riscvcpu->ins_X[i]; } - + // Initialize the registers and state flags; riscvcpu->ZERO = 0; riscvcpu->X[0] = & (riscvcpu->ZERO); @@ -164,12 +164,12 @@ void RISCVArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer) for (int i = 0; i<4096 ;i++){ riscvcpu->CSR[i] = 0; } - riscvcpu->CSR[0] = 15; - riscvcpu->CSR[256] = 15; - riscvcpu->CSR[768] = 15; - riscvcpu->CSR[260] = 4294967295; - riscvcpu->CSR[769] = 1315077; - riscvcpu->CSR[3088] = 3; + riscvcpu->CSR[0] = 15; + riscvcpu->CSR[256] = 15; + riscvcpu->CSR[768] = 15; + riscvcpu->CSR[260] = 4294967295; + riscvcpu->CSR[769] = 1315077; + riscvcpu->CSR[3088] = 3; for (int i = 0; i<4 ;i++){ riscvcpu->FENCE[i] = 0; } @@ -212,7 +212,7 @@ const std::set & RISCVArch::getHeaders() const { return headers_ ; } - + void RISCVArch::initCodeBlock(etiss::CodeBlock & cb) const { cb.fileglobalCode().insert("#include \"Arch/RISCV/RISCV.h\"\n"); @@ -220,44 +220,44 @@ void RISCVArch::initCodeBlock(etiss::CodeBlock & cb) const etiss::plugin::gdb::GDBCore & RISCVArch::getGDBCore() { - + return gdbcore_; } static const char * const reg_name[] = { - "X0", - "X1", - "X2", - "X3", - "X4", - "X5", - "X6", - "X7", - "X8", - "X9", - "X10", - "X11", - "X12", - "X13", - "X14", - "X15", - "X16", - "X17", - "X18", - "X19", - "X20", - "X21", - "X22", - "X23", - "X24", - "X25", - "X26", - "X27", - "X28", - "X29", - "X30", - "X31", + "X0", + "X1", + "X2", + "X3", + "X4", + "X5", + "X6", + "X7", + "X8", + "X9", + "X10", + "X11", + "X12", + "X13", + "X14", + "X15", + "X16", + "X17", + "X18", + "X19", + "X20", + "X21", + "X22", + "X23", + "X24", + "X25", + "X26", + "X27", + "X28", + "X29", + "X30", + "X31", }; ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////--// @@ -297,19 +297,19 @@ static InstructionDefinition lui_rd_imm( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -352,7 +352,7 @@ static InstructionDefinition auipc_rd_imm( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" @@ -363,13 +363,13 @@ static InstructionDefinition auipc_rd_imm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0 + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -422,13 +422,13 @@ static InstructionDefinition jal_rd_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x100000)>>20 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -436,18 +436,18 @@ static InstructionDefinition jal_rd_imm( "imm_extended = 4292870144;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -463,12 +463,12 @@ static InstructionDefinition jal_rd_imm( "cpu->instructionPointer = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -518,13 +518,13 @@ static InstructionDefinition jalr_rd_rs1_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 new_pc = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -532,12 +532,12 @@ static InstructionDefinition jalr_rd_rs1_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -546,13 +546,13 @@ static InstructionDefinition jalr_rd_rs1_imm( "new_pc = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"new_pc = %#x\\n\",new_pc); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -563,12 +563,12 @@ static InstructionDefinition jalr_rd_rs1_imm( "cpu->instructionPointer = (new_pc & ~1)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -627,13 +627,13 @@ static InstructionDefinition beq_rs1_rs2_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -641,12 +641,12 @@ static InstructionDefinition beq_rs1_rs2_imm( "imm_extended = 4294959104;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(*((RISCV*)cpu)->X[" + toString(rs1) + "] == *((RISCV*)cpu)->X[" + toString(rs2) + "])\n" "{\n" "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" @@ -657,7 +657,7 @@ static InstructionDefinition beq_rs1_rs2_imm( "choose1 = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" "}\n" @@ -667,17 +667,17 @@ static InstructionDefinition beq_rs1_rs2_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -728,13 +728,13 @@ static InstructionDefinition lb_rd_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -742,12 +742,12 @@ static InstructionDefinition lb_rd_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -756,7 +756,7 @@ static InstructionDefinition lb_rd_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_uint8 MEM_offs;\n" @@ -770,14 +770,14 @@ static InstructionDefinition lb_rd_imm_rs1_( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -831,13 +831,13 @@ static InstructionDefinition sb_rs2_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -845,12 +845,12 @@ static InstructionDefinition sb_rs2_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -859,27 +859,27 @@ static InstructionDefinition sb_rs2_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint8 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,1);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 1 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -928,13 +928,13 @@ static InstructionDefinition addi_rd_rs1_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -942,12 +942,12 @@ static InstructionDefinition addi_rd_rs1_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" @@ -958,13 +958,13 @@ static InstructionDefinition addi_rd_rs1_imm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -1023,13 +1023,13 @@ static InstructionDefinition bne_rs1_rs2_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -1037,12 +1037,12 @@ static InstructionDefinition bne_rs1_rs2_imm( "imm_extended = 4294959104;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(*((RISCV*)cpu)->X[" + toString(rs1) + "] != *((RISCV*)cpu)->X[" + toString(rs2) + "])\n" "{\n" "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" @@ -1053,7 +1053,7 @@ static InstructionDefinition bne_rs1_rs2_imm( "choose1 = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" "}\n" @@ -1063,17 +1063,17 @@ static InstructionDefinition bne_rs1_rs2_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -1124,13 +1124,13 @@ static InstructionDefinition lh_rd_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -1138,12 +1138,12 @@ static InstructionDefinition lh_rd_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -1152,7 +1152,7 @@ static InstructionDefinition lh_rd_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_uint16 MEM_offs;\n" @@ -1166,14 +1166,14 @@ static InstructionDefinition lh_rd_imm_rs1_( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -1227,13 +1227,13 @@ static InstructionDefinition sh_rs2_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -1241,12 +1241,12 @@ static InstructionDefinition sh_rs2_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -1255,27 +1255,27 @@ static InstructionDefinition sh_rs2_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint16 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,2);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 2 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -1322,15 +1322,15 @@ static InstructionDefinition fence_i_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "((RISCV*)cpu)->FENCE[1] = " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FENCE[1] = %#x\\n\",((RISCV*)cpu)->FENCE[1]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -1387,101 +1387,101 @@ static InstructionDefinition csrrw_rd_csr_rs1( "etiss_uint32 rs_val = 0;\n" "etiss_uint32 csr_val = 0;\n" "etiss_int32 writeMaskM = 0;\n" - + "rs_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs_val = %#x\\n\",rs_val); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "csr_val = ((RISCV*)cpu)->CSR[" + toString(csr) + "];\n" #if RISCV_DEBUG_CALL "printf(\"csr_val = %#x\\n\",csr_val); \n" - #endif + #endif "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n" "{\n" "uAddr = 0;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 256;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 768;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = -2139096645;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = -2146574029;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = -2146574319;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n" "{\n" "uAddr = 68;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 324;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 836;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n" "{\n" "uAddr = 4;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 260;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 772;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(uAddr != sAddr)\n" "{\n" "if(((RISCV*)cpu)->CSR[3088] == 3)\n" @@ -1489,50 +1489,50 @@ static InstructionDefinition csrrw_rd_csr_rs1( "writeMask = writeMaskM;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->CSR[uAddr] = ((((RISCV*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[uAddr] = %#x\\n\",((RISCV*)cpu)->CSR[uAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[sAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[sAddr] = %#x\\n\",((RISCV*)cpu)->CSR[sAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[mAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[mAddr] = %#x\\n\",((RISCV*)cpu)->CSR[mAddr]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "((RISCV*)cpu)->CSR[" + toString(csr) + "] = rs_val;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[" + toString(csr) + "] = %#x\\n\",((RISCV*)cpu)->CSR[" + toString(csr) + "]); \n" - #endif + #endif "}\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = csr_val;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -1542,85 +1542,85 @@ static InstructionDefinition csrrw_rd_csr_rs1( "uAddr = 0;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 256;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 768;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = -2139096645;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = -2146574029;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = -2146574319;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n" "{\n" "uAddr = 68;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 324;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 836;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n" "{\n" "uAddr = 4;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 260;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 772;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(uAddr != sAddr)\n" "{\n" "if(((RISCV*)cpu)->CSR[3088] == 3)\n" @@ -1628,51 +1628,51 @@ static InstructionDefinition csrrw_rd_csr_rs1( "writeMask = writeMaskM;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->CSR[uAddr] = ((((RISCV*)cpu)->CSR[uAddr] & ~writeMask) | (rs_val & writeMask))&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[uAddr] = %#x\\n\",((RISCV*)cpu)->CSR[uAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[sAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[sAddr] = %#x\\n\",((RISCV*)cpu)->CSR[sAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[mAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[mAddr] = %#x\\n\",((RISCV*)cpu)->CSR[mAddr]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "((RISCV*)cpu)->CSR[" + toString(csr) + "] = rs_val;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[" + toString(csr) + "] = %#x\\n\",((RISCV*)cpu)->CSR[" + toString(csr) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -1731,13 +1731,13 @@ static InstructionDefinition blt_rs1_rs2_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -1745,12 +1745,12 @@ static InstructionDefinition blt_rs1_rs2_imm( "imm_extended = 4294959104;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -1771,7 +1771,7 @@ static InstructionDefinition blt_rs1_rs2_imm( "choose1 = (etiss_int32)cast_2 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" "}\n" @@ -1781,17 +1781,17 @@ static InstructionDefinition blt_rs1_rs2_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -1842,13 +1842,13 @@ static InstructionDefinition lbu_rd_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -1856,12 +1856,12 @@ static InstructionDefinition lbu_rd_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -1870,7 +1870,7 @@ static InstructionDefinition lbu_rd_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_uint8 MEM_offs;\n" @@ -1879,14 +1879,14 @@ static InstructionDefinition lbu_rd_imm_rs1_( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -1935,13 +1935,13 @@ static InstructionDefinition xori_rd_rs1_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -1949,12 +1949,12 @@ static InstructionDefinition xori_rd_rs1_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" @@ -1965,13 +1965,13 @@ static InstructionDefinition xori_rd_rs1_imm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((etiss_int32)cast_0 ^ imm_extended);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -2030,13 +2030,13 @@ static InstructionDefinition bge_rs1_rs2_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -2044,12 +2044,12 @@ static InstructionDefinition bge_rs1_rs2_imm( "imm_extended = 4294959104;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -2070,7 +2070,7 @@ static InstructionDefinition bge_rs1_rs2_imm( "choose1 = (etiss_int32)cast_2 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" "}\n" @@ -2080,17 +2080,17 @@ static InstructionDefinition bge_rs1_rs2_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -2141,13 +2141,13 @@ static InstructionDefinition lhu_rd_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -2155,12 +2155,12 @@ static InstructionDefinition lhu_rd_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -2169,7 +2169,7 @@ static InstructionDefinition lhu_rd_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_uint16 MEM_offs;\n" @@ -2178,14 +2178,14 @@ static InstructionDefinition lhu_rd_imm_rs1_( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -2239,13 +2239,13 @@ static InstructionDefinition csrrwi_rd_csr_zimm( "etiss_int32 writeMaskS = 0;\n" "etiss_int32 uAddr = 0;\n" "etiss_int32 writeMaskM = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((RISCV*)cpu)->CSR[" + toString(csr) + "];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n" @@ -2253,27 +2253,27 @@ static InstructionDefinition csrrwi_rd_csr_zimm( "uAddr = 0;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 256;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 768;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = -2139096645;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = -2146574029;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = -2146574319;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n" @@ -2281,27 +2281,27 @@ static InstructionDefinition csrrwi_rd_csr_zimm( "uAddr = 68;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 324;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 836;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n" @@ -2309,27 +2309,27 @@ static InstructionDefinition csrrwi_rd_csr_zimm( "uAddr = 4;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 260;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 772;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" "if(uAddr != sAddr)\n" @@ -2339,37 +2339,37 @@ static InstructionDefinition csrrwi_rd_csr_zimm( "writeMask = writeMaskM;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->CSR[uAddr] = ((((RISCV*)cpu)->CSR[uAddr] & ~writeMask) | ((etiss_uint32)" + toString(zimm) + " & writeMask))&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[uAddr] = %#x\\n\",((RISCV*)cpu)->CSR[uAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[sAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[sAddr] = %#x\\n\",((RISCV*)cpu)->CSR[sAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[mAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[mAddr] = %#x\\n\",((RISCV*)cpu)->CSR[mAddr]); \n" - #endif + #endif "}\n" "else\n" @@ -2377,12 +2377,12 @@ static InstructionDefinition csrrwi_rd_csr_zimm( "((RISCV*)cpu)->CSR[" + toString(csr) + "] = (etiss_uint32)" + toString(zimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[" + toString(csr) + "] = %#x\\n\",((RISCV*)cpu)->CSR[" + toString(csr) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -2441,13 +2441,13 @@ static InstructionDefinition bltu_rs1_rs2_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -2455,12 +2455,12 @@ static InstructionDefinition bltu_rs1_rs2_imm( "imm_extended = 4294959104;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(*((RISCV*)cpu)->X[" + toString(rs1) + "] < *((RISCV*)cpu)->X[" + toString(rs2) + "])\n" "{\n" "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" @@ -2471,7 +2471,7 @@ static InstructionDefinition bltu_rs1_rs2_imm( "choose1 = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" "}\n" @@ -2481,17 +2481,17 @@ static InstructionDefinition bltu_rs1_rs2_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -2540,13 +2540,13 @@ static InstructionDefinition ori_rd_rs1_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -2554,12 +2554,12 @@ static InstructionDefinition ori_rd_rs1_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" @@ -2570,13 +2570,13 @@ static InstructionDefinition ori_rd_rs1_imm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((etiss_int32)cast_0 | imm_extended);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -2631,11 +2631,11 @@ static InstructionDefinition csrrsi_rd_csr_zimm( "etiss_int32 writeMaskS = 0;\n" "etiss_int32 uAddr = 0;\n" "etiss_int32 writeMaskM = 0;\n" - + "res = ((RISCV*)cpu)->CSR[" + toString(csr) + "];\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" -#endif +#endif "if(" + toString(zimm) + " != 0)\n" "{\n" "if(((" + toString(csr) + " == 0) || (" + toString(csr) + " == 256)) || (" + toString(csr) + " == 768))\n" @@ -2643,85 +2643,85 @@ static InstructionDefinition csrrsi_rd_csr_zimm( "uAddr = 0;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 256;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 768;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = -2139096645;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = -2146574029;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = -2146574319;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n" "{\n" "uAddr = 68;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 324;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 836;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n" "{\n" "uAddr = 4;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 260;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 772;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(uAddr != sAddr)\n" "{\n" "if(((RISCV*)cpu)->CSR[3088] == 3)\n" @@ -2729,45 +2729,45 @@ static InstructionDefinition csrrsi_rd_csr_zimm( "writeMask = writeMaskM;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->CSR[uAddr] = ((((RISCV*)cpu)->CSR[uAddr] & ~writeMask) | ((res | (etiss_uint32)" + toString(zimm) + ") & writeMask))&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[uAddr] = %#x\\n\",((RISCV*)cpu)->CSR[uAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[sAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[sAddr] = %#x\\n\",((RISCV*)cpu)->CSR[sAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[mAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[mAddr] = %#x\\n\",((RISCV*)cpu)->CSR[mAddr]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "((RISCV*)cpu)->CSR[" + toString(csr) + "] = (res | (etiss_uint32)" + toString(zimm) + ");\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[" + toString(csr) + "] = %#x\\n\",((RISCV*)cpu)->CSR[" + toString(csr) + "]); \n" - #endif + #endif "}\n" "}\n" @@ -2776,13 +2776,13 @@ static InstructionDefinition csrrsi_rd_csr_zimm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -2841,13 +2841,13 @@ static InstructionDefinition bgeu_rs1_rs2_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x1000)>>12 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -2855,12 +2855,12 @@ static InstructionDefinition bgeu_rs1_rs2_imm( "imm_extended = 4294959104;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(*((RISCV*)cpu)->X[" + toString(rs1) + "] >= *((RISCV*)cpu)->X[" + toString(rs2) + "])\n" "{\n" "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" @@ -2871,7 +2871,7 @@ static InstructionDefinition bgeu_rs1_rs2_imm( "choose1 = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" "}\n" @@ -2881,17 +2881,17 @@ static InstructionDefinition bgeu_rs1_rs2_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 4;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -2940,13 +2940,13 @@ static InstructionDefinition andi_rd_rs1_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -2954,12 +2954,12 @@ static InstructionDefinition andi_rd_rs1_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" @@ -2970,13 +2970,13 @@ static InstructionDefinition andi_rd_rs1_imm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((etiss_int32)cast_0 & imm_extended);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -3031,17 +3031,17 @@ static InstructionDefinition csrrci_rd_csr_zimm( "etiss_int32 writeMaskS = 0;\n" "etiss_int32 uAddr = 0;\n" "etiss_int32 writeMaskM = 0;\n" - + "res = ((RISCV*)cpu)->CSR[" + toString(csr) + "];\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "if(" + toString(zimm) + " != 0)\n" @@ -3051,85 +3051,85 @@ static InstructionDefinition csrrci_rd_csr_zimm( "uAddr = 0;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 256;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 768;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = -2139096645;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = -2146574029;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = -2146574319;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n" "{\n" "uAddr = 68;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 324;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 836;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n" "{\n" "uAddr = 4;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 260;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 772;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(uAddr != sAddr)\n" "{\n" "if(((RISCV*)cpu)->CSR[3088] == 3)\n" @@ -3137,52 +3137,52 @@ static InstructionDefinition csrrci_rd_csr_zimm( "writeMask = writeMaskM;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->CSR[uAddr] = ((((RISCV*)cpu)->CSR[uAddr] & ~writeMask) | ((res & ~(etiss_uint32)" + toString(zimm) + ") & writeMask))&0xffffffff&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[uAddr] = %#x\\n\",((RISCV*)cpu)->CSR[uAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[sAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[sAddr] = %#x\\n\",((RISCV*)cpu)->CSR[sAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[mAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[mAddr] = %#x\\n\",((RISCV*)cpu)->CSR[mAddr]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "((RISCV*)cpu)->CSR[" + toString(csr) + "] = (res & ~(etiss_uint32)" + toString(zimm) + ")&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[" + toString(csr) + "] = %#x\\n\",((RISCV*)cpu)->CSR[" + toString(csr) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -3233,13 +3233,13 @@ static InstructionDefinition lw_rd_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -3247,12 +3247,12 @@ static InstructionDefinition lw_rd_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -3261,7 +3261,7 @@ static InstructionDefinition lw_rd_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" @@ -3275,14 +3275,14 @@ static InstructionDefinition lw_rd_imm_rs1_( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -3336,13 +3336,13 @@ static InstructionDefinition sw_rs2_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -3350,12 +3350,12 @@ static InstructionDefinition sw_rs2_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -3364,27 +3364,27 @@ static InstructionDefinition sw_rs2_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -3434,13 +3434,13 @@ static InstructionDefinition slti_rd_rs1_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int8 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -3448,12 +3448,12 @@ static InstructionDefinition slti_rd_rs1_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = imm_extended; \n" @@ -3471,26 +3471,26 @@ static InstructionDefinition slti_rd_rs1_imm( "choose1 = 1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -3547,21 +3547,21 @@ static InstructionDefinition csrrs_rd_csr_rs1( "etiss_int32 uAddr = 0;\n" "etiss_uint32 xrd = 0;\n" "etiss_int32 writeMaskM = 0;\n" - + "xrd = ((RISCV*)cpu)->CSR[" + toString(csr) + "];\n" #if RISCV_DEBUG_CALL "printf(\"xrd = %#x\\n\",xrd); \n" -#endif +#endif "xrs1 = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"xrs1 = %#x\\n\",xrs1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = xrd;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "if(" + toString(rs1) + " != 0)\n" @@ -3571,85 +3571,85 @@ static InstructionDefinition csrrs_rd_csr_rs1( "uAddr = 0;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 256;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 768;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = -2139096645;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = -2146574029;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = -2146574319;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n" "{\n" "uAddr = 68;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 324;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 836;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n" "{\n" "uAddr = 4;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 260;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 772;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(uAddr != sAddr)\n" "{\n" "if(((RISCV*)cpu)->CSR[3088] == 3)\n" @@ -3657,52 +3657,52 @@ static InstructionDefinition csrrs_rd_csr_rs1( "writeMask = writeMaskM;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->CSR[uAddr] = ((((RISCV*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd | xrs1) & writeMask))&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[uAddr] = %#x\\n\",((RISCV*)cpu)->CSR[uAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[sAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[sAddr] = %#x\\n\",((RISCV*)cpu)->CSR[sAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[mAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[mAddr] = %#x\\n\",((RISCV*)cpu)->CSR[mAddr]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "((RISCV*)cpu)->CSR[" + toString(csr) + "] = (xrd | xrs1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[" + toString(csr) + "] = %#x\\n\",((RISCV*)cpu)->CSR[" + toString(csr) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -3754,13 +3754,13 @@ static InstructionDefinition flw_rd_imm_xrs1_( "etiss_int32 imm_extended = 0;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -3768,12 +3768,12 @@ static InstructionDefinition flw_rd_imm_xrs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -3782,20 +3782,20 @@ static InstructionDefinition flw_rd_imm_xrs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "res = MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" -#endif +#endif "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -3803,17 +3803,17 @@ static InstructionDefinition flw_rd_imm_xrs1_( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -3866,13 +3866,13 @@ static InstructionDefinition fsw_rs2_imm_xrs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -3880,12 +3880,12 @@ static InstructionDefinition fsw_rs2_imm_xrs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -3894,27 +3894,27 @@ static InstructionDefinition fsw_rs2_imm_xrs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -3965,13 +3965,13 @@ static InstructionDefinition sltiu_rd_rs1_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 full_imm = 0;\n" "etiss_int8 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -3979,12 +3979,12 @@ static InstructionDefinition sltiu_rd_rs1_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = imm_extended; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -3993,7 +3993,7 @@ static InstructionDefinition sltiu_rd_rs1_imm( "full_imm = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"full_imm = %#x\\n\",full_imm); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "if((etiss_uint32)*((RISCV*)cpu)->X[" + toString(rs1) + "] < (etiss_uint32)full_imm)\n" @@ -4001,26 +4001,26 @@ static InstructionDefinition sltiu_rd_rs1_imm( "choose1 = 1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -4077,21 +4077,21 @@ static InstructionDefinition csrrc_rd_csr_rs1( "etiss_int32 uAddr = 0;\n" "etiss_uint32 xrd = 0;\n" "etiss_int32 writeMaskM = 0;\n" - + "xrd = ((RISCV*)cpu)->CSR[" + toString(csr) + "];\n" #if RISCV_DEBUG_CALL "printf(\"xrd = %#x\\n\",xrd); \n" -#endif +#endif "xrs1 = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"xrs1 = %#x\\n\",xrs1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = xrd;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "if(" + toString(rs1) + " != 0)\n" @@ -4101,85 +4101,85 @@ static InstructionDefinition csrrc_rd_csr_rs1( "uAddr = 0;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 256;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 768;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = -2139096645;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = -2146574029;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = -2146574319;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 68) || (" + toString(csr) + " == 324)) || (" + toString(csr) + " == 836))\n" "{\n" "uAddr = 68;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 324;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 836;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(((" + toString(csr) + " == 4) || (" + toString(csr) + " == 260)) || (" + toString(csr) + " == 772))\n" "{\n" "uAddr = 4;\n" #if RISCV_DEBUG_CALL "printf(\"uAddr = %#x\\n\",uAddr); \n" - #endif + #endif "sAddr = 260;\n" #if RISCV_DEBUG_CALL "printf(\"sAddr = %#x\\n\",sAddr); \n" - #endif + #endif "mAddr = 772;\n" #if RISCV_DEBUG_CALL "printf(\"mAddr = %#x\\n\",mAddr); \n" - #endif + #endif "writeMaskM = 3003;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskM = %#x\\n\",writeMaskM); \n" - #endif + #endif "writeMaskS = 819;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskS = %#x\\n\",writeMaskS); \n" - #endif + #endif "writeMaskU = 273;\n" #if RISCV_DEBUG_CALL "printf(\"writeMaskU = %#x\\n\",writeMaskU); \n" - #endif + #endif "}\n" - + "if(uAddr != sAddr)\n" "{\n" "if(((RISCV*)cpu)->CSR[3088] == 3)\n" @@ -4187,52 +4187,52 @@ static InstructionDefinition csrrc_rd_csr_rs1( "writeMask = writeMaskM;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 1)\n" "{\n" "writeMask = writeMaskS;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "if(((RISCV*)cpu)->CSR[3088] == 0)\n" "{\n" "writeMask = writeMaskU;\n" #if RISCV_DEBUG_CALL "printf(\"writeMask = %#x\\n\",writeMask); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->CSR[uAddr] = ((((RISCV*)cpu)->CSR[uAddr] & ~writeMask) | ((xrd & ~xrs1) & writeMask))&0xffffffff&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[uAddr] = %#x\\n\",((RISCV*)cpu)->CSR[uAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[sAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[sAddr] = %#x\\n\",((RISCV*)cpu)->CSR[sAddr]); \n" - #endif + #endif "((RISCV*)cpu)->CSR[mAddr] = ((RISCV*)cpu)->CSR[uAddr];\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[mAddr] = %#x\\n\",((RISCV*)cpu)->CSR[mAddr]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "((RISCV*)cpu)->CSR[" + toString(csr) + "] = (xrd & ~xrs1)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->CSR[" + toString(csr) + "] = %#x\\n\",((RISCV*)cpu)->CSR[" + toString(csr) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -4284,13 +4284,13 @@ static InstructionDefinition fld_rd_imm_rs1_( "etiss_int32 imm_extended = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -4298,12 +4298,12 @@ static InstructionDefinition fld_rd_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -4312,20 +4312,20 @@ static InstructionDefinition fld_rd_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -4333,17 +4333,17 @@ static InstructionDefinition fld_rd_imm_rs1_( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -4396,13 +4396,13 @@ static InstructionDefinition fsd_rs2_imm_rs1_( "etiss_int32 offs = 0;\n" "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -4410,12 +4410,12 @@ static InstructionDefinition fsd_rs2_imm_rs1_( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -4424,27 +4424,27 @@ static InstructionDefinition fsd_rs2_imm_rs1_( "offs = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 8 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -4505,7 +4505,7 @@ static InstructionDefinition fmadd_s_rd_frs1_frs2_frs3( "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -4513,20 +4513,20 @@ static InstructionDefinition fmadd_s_rd_frs1_frs2_frs3( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], ((RISCV*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)0, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -4534,55 +4534,55 @@ static InstructionDefinition fmadd_s_rd_frs1_frs2_frs3( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "frs3 = unbox_s(((RISCV*)cpu)->F[" + toString(rs3) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs3 = %#x\\n\",frs3); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)0, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -4643,7 +4643,7 @@ static InstructionDefinition fmsub_s_rd_frs1_frs2_frs3( "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -4651,20 +4651,20 @@ static InstructionDefinition fmsub_s_rd_frs1_frs2_frs3( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], ((RISCV*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)1, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -4672,55 +4672,55 @@ static InstructionDefinition fmsub_s_rd_frs1_frs2_frs3( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "frs3 = unbox_s(((RISCV*)cpu)->F[" + toString(rs3) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs3 = %#x\\n\",frs3); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)1, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -4781,7 +4781,7 @@ static InstructionDefinition fnmadd_s_rd_frs1_frs2_frs3( "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -4789,20 +4789,20 @@ static InstructionDefinition fnmadd_s_rd_frs1_frs2_frs3( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], ((RISCV*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)2, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -4810,55 +4810,55 @@ static InstructionDefinition fnmadd_s_rd_frs1_frs2_frs3( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "frs3 = unbox_s(((RISCV*)cpu)->F[" + toString(rs3) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs3 = %#x\\n\",frs3); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)2, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -4919,7 +4919,7 @@ static InstructionDefinition fnmsub_s_rd_frs1_frs2_frs3( "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" "etiss_uint32 frs3 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -4927,20 +4927,20 @@ static InstructionDefinition fnmsub_s_rd_frs1_frs2_frs3( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fmadd_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], ((RISCV*)cpu)->F[" + toString(rs3) + "], (etiss_uint32)3, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -4948,55 +4948,55 @@ static InstructionDefinition fnmsub_s_rd_frs1_frs2_frs3( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "frs3 = unbox_s(((RISCV*)cpu)->F[" + toString(rs3) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs3 = %#x\\n\",frs3); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_s(frs1, frs2, frs3, (etiss_uint32)3, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5054,13 +5054,13 @@ static InstructionDefinition fmadd_d_rd_frs1_frs2_frs3( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -5068,18 +5068,18 @@ static InstructionDefinition fmadd_d_rd_frs1_frs2_frs3( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint64)0, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -5087,24 +5087,24 @@ static InstructionDefinition fmadd_d_rd_frs1_frs2_frs3( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5162,13 +5162,13 @@ static InstructionDefinition fmsub_d_rd_frs1_frs2_frs3( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -5176,18 +5176,18 @@ static InstructionDefinition fmsub_d_rd_frs1_frs2_frs3( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)1, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -5195,24 +5195,24 @@ static InstructionDefinition fmsub_d_rd_frs1_frs2_frs3( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5270,13 +5270,13 @@ static InstructionDefinition fnmadd_d_rd_frs1_frs2_frs3( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -5284,18 +5284,18 @@ static InstructionDefinition fnmadd_d_rd_frs1_frs2_frs3( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)2, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -5303,24 +5303,24 @@ static InstructionDefinition fnmadd_d_rd_frs1_frs2_frs3( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5378,13 +5378,13 @@ static InstructionDefinition fnmsub_d_rd_frs1_frs2_frs3( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -5392,18 +5392,18 @@ static InstructionDefinition fnmsub_d_rd_frs1_frs2_frs3( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmadd_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs3) + "] & 0xffffffffffffffff), (etiss_uint32)3, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -5411,24 +5411,24 @@ static InstructionDefinition fnmsub_d_rd_frs1_frs2_frs3( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5482,7 +5482,7 @@ static InstructionDefinition slli_rd_rs1_shamt( "{\n" "X ^= ((-*((RISCV*)cpu)->X[i])^X) & (1 << i ); \n" "}\n" - + "if(" + toString(shamt) + " > 31)\n" "{\n" "exception = ETISS_RETURNCODE_IBUS_READ_ERROR; \n" @@ -5495,15 +5495,15 @@ static InstructionDefinition slli_rd_rs1_shamt( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] << " + toString(shamt) + ");\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -5557,19 +5557,19 @@ static InstructionDefinition sll_rd_rs1_rs2( "{\n" "X ^= ((-*((RISCV*)cpu)->X[i])^X) & (1 << i ); \n" "}\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] << (*((RISCV*)cpu)->X[" + toString(rs2) + "] & 32 - 1));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5623,7 +5623,7 @@ static InstructionDefinition srli_rd_rs1_shamt( "{\n" "X ^= ((-*((RISCV*)cpu)->X[i])^X) & (1 << i ); \n" "}\n" - + "if(" + toString(shamt) + " > 31)\n" "{\n" "exception = ETISS_RETURNCODE_IBUS_READ_ERROR; \n" @@ -5636,15 +5636,15 @@ static InstructionDefinition srli_rd_rs1_shamt( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] >> " + toString(shamt) + ");\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -5698,19 +5698,19 @@ static InstructionDefinition srl_rd_rs1_rs2( "{\n" "X ^= ((-*((RISCV*)cpu)->X[i])^X) & (1 << i ); \n" "}\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] >> (*((RISCV*)cpu)->X[" + toString(rs2) + "] & 32 - 1));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5759,19 +5759,19 @@ static InstructionDefinition add_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = *((RISCV*)cpu)->X[" + toString(rs1) + "] + *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5821,7 +5821,7 @@ static InstructionDefinition slt_rd_rs1_rs2( #endif "etiss_int8 choose1 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" @@ -5839,26 +5839,26 @@ static InstructionDefinition slt_rd_rs1_rs2( "choose1 = 1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5908,7 +5908,7 @@ static InstructionDefinition sltu_rd_rs1_rs2( #endif "etiss_int8 choose1 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "if((etiss_uint32)*((RISCV*)cpu)->X[" + toString(rs1) + "] < (etiss_uint32)*((RISCV*)cpu)->X[" + toString(rs2) + "])\n" @@ -5916,26 +5916,26 @@ static InstructionDefinition sltu_rd_rs1_rs2( "choose1 = 1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -5984,19 +5984,19 @@ static InstructionDefinition xor_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] ^ *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6045,19 +6045,19 @@ static InstructionDefinition or_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] | *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6106,19 +6106,19 @@ static InstructionDefinition and_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] & *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6152,17 +6152,17 @@ static InstructionDefinition uret_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "((RISCV*)cpu)->CSR[3088] = 0;\n"//PRIVLV=0 "((RISCV*)cpu)->CSR[0] ^= ((etiss_uint32)((((RISCV*)cpu)->CSR[0] & 0x10)>>4)) ^ (((RISCV*)cpu)->CSR[0] & 0x1);\n"//UIE=UPIE "cpu->instructionPointer = ((RISCV*)cpu)->CSR[65];\n"//PC=UEPC "((RISCV*)cpu)->CSR[768]= ((RISCV*)cpu)->CSR[0];\n"//keep MSTATUS synchronous to USTATUS "((RISCV*)cpu)->CSR[256]=((RISCV*)cpu)->CSR[0];\n"//keep SSTATUS synchronous to USTATUS - + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -6218,7 +6218,7 @@ static InstructionDefinition fadd_s_rd_frs1_frs2( "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -6226,20 +6226,20 @@ static InstructionDefinition fadd_s_rd_frs1_frs2( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fadd_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -6247,51 +6247,51 @@ static InstructionDefinition fadd_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fadd_s(frs1, frs2, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6340,7 +6340,7 @@ static InstructionDefinition srai_rd_rs1_shamt( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(shamt) + " > 31)\n" "{\n" "exception = ETISS_RETURNCODE_IBUS_READ_ERROR; \n" @@ -6358,15 +6358,15 @@ static InstructionDefinition srai_rd_rs1_shamt( "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((etiss_int32)cast_0 >> " + toString(shamt) + ");\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -6415,7 +6415,7 @@ static InstructionDefinition sra_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" @@ -6426,13 +6426,13 @@ static InstructionDefinition sra_rd_rs1_rs2( "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((etiss_int32)cast_0 >> (*((RISCV*)cpu)->X[" + toString(rs2) + "] & 32 - 1));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6481,19 +6481,19 @@ static InstructionDefinition sub_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = *((RISCV*)cpu)->X[" + toString(rs1) + "] - *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6541,23 +6541,23 @@ static InstructionDefinition fcvt_s_d_rd_frs1( "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" - + "res = fconv_d2f(((RISCV*)cpu)->F[" + toString(rs1) + "], (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" -#endif +#endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" -#endif +#endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6608,15 +6608,15 @@ static InstructionDefinition fence_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "((RISCV*)cpu)->FENCE[0] = ((" + toString(pred) + " << 4) | " + toString(succ) + ");\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FENCE[0] = %#x\\n\",((RISCV*)cpu)->FENCE[0]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6651,13 +6651,13 @@ static InstructionDefinition ecall_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "exception = ETISS_RETURNCODE_SYSCALL; \n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -6692,13 +6692,13 @@ static InstructionDefinition ebreak_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "return ETISS_RETURNCODE_CPUFINISHED; \n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -6732,18 +6732,18 @@ static InstructionDefinition sret_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "((RISCV*)cpu)->CSR[3088] = (((RISCV*)cpu)->CSR[256] & 0x100)>>8;\n"//PRIVLV=SPP "((RISCV*)cpu)->CSR[256] ^= (((RISCV*)cpu)->CSR[256] & 0x100);\n"//SPP=0 "((RISCV*)cpu)->CSR[256] ^= ((etiss_uint32)((((RISCV*)cpu)->CSR[256] & 0x20)>>4)) ^ (((RISCV*)cpu)->CSR[256] & 0x2);\n"//SIE=SPIE "cpu->instructionPointer = ((RISCV*)cpu)->CSR[321];\n"//PC=SEPC "((RISCV*)cpu)->CSR[768]= ((RISCV*)cpu)->CSR[256];\n"//keep MSTATUS synchronous to SSTATUS "((RISCV*)cpu)->CSR[0]=((RISCV*)cpu)->CSR[256];\n"//keep USTATUS synchronous to SSTATUS - + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -6778,13 +6778,13 @@ static InstructionDefinition wfi_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "return ETISS_RETURNCODE_CPUFINISHED; \n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -6840,7 +6840,7 @@ static InstructionDefinition fmul_s_rd_frs1_frs2( "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -6848,20 +6848,20 @@ static InstructionDefinition fmul_s_rd_frs1_frs2( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fmul_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -6869,51 +6869,51 @@ static InstructionDefinition fmul_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmul_s(frs1, frs2, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -6947,18 +6947,18 @@ static InstructionDefinition mret_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "((RISCV*)cpu)->CSR[3088] = (((RISCV*)cpu)->CSR[768] & 0x1800)>>11;\n"//PRIVLV=MPP "((RISCV*)cpu)->CSR[768] ^= (((RISCV*)cpu)->CSR[768] & 0x1800);\n"//MPP=0 "((RISCV*)cpu)->CSR[768] ^= ((etiss_uint32)((((RISCV*)cpu)->CSR[768] & 0x80)>>4)) ^ (((RISCV*)cpu)->CSR[768] & 0x8);\n"//MIE=MPIE "cpu->instructionPointer = ((RISCV*)cpu)->CSR[833];\n"//PC=MEPC "((RISCV*)cpu)->CSR[0]= ((RISCV*)cpu)->CSR[768];\n"//keep USTATUS synchronous to MSTATUS "((RISCV*)cpu)->CSR[256]=((RISCV*)cpu)->CSR[768];\n"//keep SSTATUS synchronous to MSTATUS - + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -7002,19 +7002,19 @@ static InstructionDefinition sfence_vma_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "((RISCV*)cpu)->FENCE[2] = " + toString(rs1) + ";\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FENCE[2] = %#x\\n\",((RISCV*)cpu)->FENCE[2]); \n" -#endif +#endif "((RISCV*)cpu)->FENCE[3] = " + toString(rs2) + ";\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FENCE[3] = %#x\\n\",((RISCV*)cpu)->FENCE[3]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7068,13 +7068,13 @@ static InstructionDefinition fmul_d_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -7082,18 +7082,18 @@ static InstructionDefinition fmul_d_rd_frs1_frs2( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fmul_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -7101,24 +7101,24 @@ static InstructionDefinition fmul_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7168,23 +7168,23 @@ static InstructionDefinition mul_rd_rs1_rs2( #endif "etiss_uint64 res = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "res = ((etiss_uint64)*((RISCV*)cpu)->X[" + toString(rs1) + "] * (etiss_uint64)*((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)res;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7234,7 +7234,7 @@ static InstructionDefinition mulh_rd_rs1_rs2( #endif "etiss_int64 res = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" @@ -7250,17 +7250,17 @@ static InstructionDefinition mulh_rd_rs1_rs2( "res = ((etiss_int64)cast_1 * (etiss_int64)cast_0);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)(res >> 32);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7310,7 +7310,7 @@ static InstructionDefinition mulhsu_rd_rs1_rs2( #endif "etiss_uint64 res = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" @@ -7321,17 +7321,17 @@ static InstructionDefinition mulhsu_rd_rs1_rs2( "res = ((etiss_int64)cast_0 * (etiss_uint64)*((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)(res >> 32);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7381,23 +7381,23 @@ static InstructionDefinition mulhu_rd_rs1_rs2( #endif "etiss_uint64 res = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "res = ((etiss_uint64)*((RISCV*)cpu)->X[" + toString(rs1) + "] * (etiss_uint64)*((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)(res >> 32);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7450,7 +7450,7 @@ static InstructionDefinition div_rd_rs1_rs2( "etiss_int32 MMIN = 0;\n" "etiss_int32 M1 = 0;\n" "etiss_int32 ONE = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "if(*((RISCV*)cpu)->X[" + toString(rs2) + "] != 0)\n" @@ -7458,27 +7458,27 @@ static InstructionDefinition div_rd_rs1_rs2( "M1 = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"M1 = %#x\\n\",M1); \n" - #endif + #endif "XLM1 = 32 - 1;\n" #if RISCV_DEBUG_CALL "printf(\"XLM1 = %#x\\n\",XLM1); \n" - #endif + #endif "ONE = 1;\n" #if RISCV_DEBUG_CALL "printf(\"ONE = %#x\\n\",ONE); \n" - #endif + #endif "MMIN = (ONE << XLM1);\n" #if RISCV_DEBUG_CALL "printf(\"MMIN = %#x\\n\",MMIN); \n" - #endif + #endif "if((*((RISCV*)cpu)->X[" + toString(rs1) + "] == MMIN) && (*((RISCV*)cpu)->X[" + toString(rs2) + "] == M1))\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = MMIN;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" @@ -7494,23 +7494,23 @@ static InstructionDefinition div_rd_rs1_rs2( "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((etiss_int32)cast_1 / (etiss_int32)cast_0);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "}\n" - + "else\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7559,7 +7559,7 @@ static InstructionDefinition divu_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "if(*((RISCV*)cpu)->X[" + toString(rs2) + "] != 0)\n" @@ -7567,22 +7567,22 @@ static InstructionDefinition divu_rd_rs1_rs2( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] / *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7635,7 +7635,7 @@ static InstructionDefinition rem_rd_rs1_rs2( "etiss_int32 MMIN = 0;\n" "etiss_int32 M1 = 0;\n" "etiss_int32 ONE = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "if(*((RISCV*)cpu)->X[" + toString(rs2) + "] != 0)\n" @@ -7643,27 +7643,27 @@ static InstructionDefinition rem_rd_rs1_rs2( "M1 = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"M1 = %#x\\n\",M1); \n" - #endif + #endif "XLM1 = 32 - 1;\n" #if RISCV_DEBUG_CALL "printf(\"XLM1 = %#x\\n\",XLM1); \n" - #endif + #endif "ONE = 1;\n" #if RISCV_DEBUG_CALL "printf(\"ONE = %#x\\n\",ONE); \n" - #endif + #endif "MMIN = (ONE << XLM1);\n" #if RISCV_DEBUG_CALL "printf(\"MMIN = %#x\\n\",MMIN); \n" - #endif + #endif "if((*((RISCV*)cpu)->X[" + toString(rs1) + "] == MMIN) && (*((RISCV*)cpu)->X[" + toString(rs2) + "] == M1))\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = 0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" @@ -7679,23 +7679,23 @@ static InstructionDefinition rem_rd_rs1_rs2( "*((RISCV*)cpu)->X[" + toString(rd) + "] = ((etiss_int32)cast_1 % (etiss_int32)cast_0);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "}\n" - + "else\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7744,7 +7744,7 @@ static InstructionDefinition remu_rd_rs1_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(rd) + " != 0)\n" "{\n" "if(*((RISCV*)cpu)->X[" + toString(rs2) + "] != 0)\n" @@ -7752,22 +7752,22 @@ static InstructionDefinition remu_rd_rs1_rs2( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] % *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7821,13 +7821,13 @@ static InstructionDefinition fadd_d_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -7835,18 +7835,18 @@ static InstructionDefinition fadd_d_rd_frs1_frs2( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fadd_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -7854,24 +7854,24 @@ static InstructionDefinition fadd_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -7925,13 +7925,13 @@ static InstructionDefinition lr_w_rd_rs1( #endif "etiss_uint32 offs = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" - #endif + #endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -7943,18 +7943,18 @@ static InstructionDefinition lr_w_rd_rs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "((RISCV*)cpu)->RES = offs;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8013,11 +8013,11 @@ static InstructionDefinition sc_w_rd_rs1_rs2( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "if(offs == ((RISCV*)cpu)->RES)\n" "{\n" "etiss_uint32 MEM_offs;\n" @@ -8026,19 +8026,19 @@ static InstructionDefinition sc_w_rd_rs1_rs2( "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" - #endif + #endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = 0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" "else\n" @@ -8048,19 +8048,19 @@ static InstructionDefinition sc_w_rd_rs1_rs2( "*((RISCV*)cpu)->X[" + toString(rd) + "] = 1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8119,11 +8119,11 @@ static InstructionDefinition amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "etiss_uint32 MEM_offs;\n" @@ -8137,7 +8137,7 @@ static InstructionDefinition amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "etiss_uint32 MEM_offs;\n" @@ -8146,20 +8146,20 @@ static InstructionDefinition amoswap_w_rd_rs1_rs2_aqu_aq_rel_rl_( "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8220,11 +8220,11 @@ static InstructionDefinition amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_uint32 offs = 0;\n" "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -8236,38 +8236,38 @@ static InstructionDefinition amoadd_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "res2 = res1 + *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8328,11 +8328,11 @@ static InstructionDefinition amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_uint32 offs = 0;\n" "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -8344,38 +8344,38 @@ static InstructionDefinition amoxor_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "res2 = (res1 ^ *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8436,11 +8436,11 @@ static InstructionDefinition amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_uint32 offs = 0;\n" "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -8452,38 +8452,38 @@ static InstructionDefinition amoand_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "res2 = (res1 & *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8544,11 +8544,11 @@ static InstructionDefinition amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_uint32 offs = 0;\n" "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -8560,38 +8560,38 @@ static InstructionDefinition amoor_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "res2 = (res1 | *((RISCV*)cpu)->X[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8653,11 +8653,11 @@ static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -8669,13 +8669,13 @@ static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "etiss_int32 cast_1 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" @@ -8693,7 +8693,7 @@ static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -8701,31 +8701,31 @@ static InstructionDefinition amomin_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = res1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8787,11 +8787,11 @@ static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -8803,13 +8803,13 @@ static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "etiss_int32 cast_1 = *((RISCV*)cpu)->X[" + toString(rs2) + "]; \n" @@ -8827,7 +8827,7 @@ static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -8835,31 +8835,31 @@ static InstructionDefinition amomax_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = res1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -8921,11 +8921,11 @@ static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -8937,13 +8937,13 @@ static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "if(res1 > *((RISCV*)cpu)->X[" + toString(rs2) + "])\n" @@ -8951,7 +8951,7 @@ static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -8959,31 +8959,31 @@ static InstructionDefinition amominu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = res1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -9045,11 +9045,11 @@ static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "etiss_int32 res1 = 0;\n" "etiss_uint32 res2 = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -9061,13 +9061,13 @@ static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "res1 = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"res1 = %#x\\n\",res1); \n" -#endif +#endif "if(" + toString(rd) + " != 0)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = res1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "if(res1 < *((RISCV*)cpu)->X[" + toString(rs2) + "])\n" @@ -9075,7 +9075,7 @@ static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -9083,31 +9083,31 @@ static InstructionDefinition amomaxu_w_rd_rs1_rs2_aqu_aq_rel_rl_( "choose1 = res1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"res2 = %#x\\n\",res2); \n" -#endif - "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" +#endif + "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = res2;\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -9163,7 +9163,7 @@ static InstructionDefinition fsub_s_rd_frs1_frs2( "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -9171,20 +9171,20 @@ static InstructionDefinition fsub_s_rd_frs1_frs2( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fsub_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9192,51 +9192,51 @@ static InstructionDefinition fsub_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fsub_s(frs1, frs2, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9292,7 +9292,7 @@ static InstructionDefinition fdiv_s_rd_frs1_frs2( "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -9300,20 +9300,20 @@ static InstructionDefinition fdiv_s_rd_frs1_frs2( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fdiv_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9321,51 +9321,51 @@ static InstructionDefinition fdiv_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fdiv_s(frs1, frs2, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9416,7 +9416,7 @@ static InstructionDefinition fsqrt_s_rd_frs1( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(64 == 32)\n" "{\n" "if(" + toString(rm) + " < 7)\n" @@ -9424,20 +9424,20 @@ static InstructionDefinition fsqrt_s_rd_frs1( "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fsqrt_s(((RISCV*)cpu)->F[" + toString(rs1) + "], choose1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9445,47 +9445,47 @@ static InstructionDefinition fsqrt_s_rd_frs1( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fsqrt_s(frs1, choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9535,13 +9535,13 @@ static InstructionDefinition fsgnj_s_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = ((((RISCV*)cpu)->F[" + toString(rs1) + "] & 2147483647) | (((RISCV*)cpu)->F[" + toString(rs2) + "] & -2147483648));\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9549,28 +9549,28 @@ static InstructionDefinition fsgnj_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "res = ((frs1 & 2147483647) | (frs2 & -2147483648));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9620,13 +9620,13 @@ static InstructionDefinition fsgnjn_s_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = ((((RISCV*)cpu)->F[" + toString(rs1) + "] & 2147483647) | (~((RISCV*)cpu)->F[" + toString(rs2) + "] & -2147483648))&0xffffffffffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9634,28 +9634,28 @@ static InstructionDefinition fsgnjn_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "res = ((frs1 & 2147483647) | (~frs2 & -2147483648))&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9705,13 +9705,13 @@ static InstructionDefinition fsgnjx_s_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = (((RISCV*)cpu)->F[" + toString(rs1) + "] ^ (((RISCV*)cpu)->F[" + toString(rs2) + "] & -2147483648));\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9719,28 +9719,28 @@ static InstructionDefinition fsgnjx_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "res = (frs1 ^ (frs2 & -2147483648));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9791,13 +9791,13 @@ static InstructionDefinition fmin_s_rd_frs1_frs2( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fsel_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)0);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9805,36 +9805,36 @@ static InstructionDefinition fmin_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "res = fsel_s(frs1, frs2, (etiss_uint32)0);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9885,13 +9885,13 @@ static InstructionDefinition fmax_s_rd_frs1_frs2( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fsel_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)1);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9899,36 +9899,36 @@ static InstructionDefinition fmax_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "res = fsel_s(frs1, frs2, (etiss_uint32)1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -9977,7 +9977,7 @@ static InstructionDefinition fcvt_w_s_rd_frs1( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" - + "if(64 == 32)\n" "{\n" "etiss_int32 cast_0 = fcvt_s(((RISCV*)cpu)->F[" + toString(rs1) + "], (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n" @@ -9988,7 +9988,7 @@ static InstructionDefinition fcvt_w_s_rd_frs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -9996,7 +9996,7 @@ static InstructionDefinition fcvt_w_s_rd_frs1( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" @@ -10005,20 +10005,20 @@ static InstructionDefinition fcvt_w_s_rd_frs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10067,7 +10067,7 @@ static InstructionDefinition fcvt_wu_s_rd_frs1( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" - + "if(64 == 32)\n" "{\n" "etiss_int32 cast_0 = fcvt_s(((RISCV*)cpu)->F[" + toString(rs1) + "], (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n" @@ -10078,7 +10078,7 @@ static InstructionDefinition fcvt_wu_s_rd_frs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10086,7 +10086,7 @@ static InstructionDefinition fcvt_wu_s_rd_frs1( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "etiss_int32 cast_1 = fcvt_s(frs1, (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x80000000) > 0x0)\n" "{\n" @@ -10095,20 +10095,20 @@ static InstructionDefinition fcvt_wu_s_rd_frs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10158,13 +10158,13 @@ static InstructionDefinition feq_s_rd_frs1_frs2( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)0);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10172,28 +10172,28 @@ static InstructionDefinition feq_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_s(frs1, frs2, (etiss_uint32)0);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10243,13 +10243,13 @@ static InstructionDefinition flt_s_rd_frs1_frs2( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)2);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10257,32 +10257,32 @@ static InstructionDefinition flt_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_s(frs1, frs2, (etiss_uint32)2);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = fcmp_s((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffff), (etiss_uint32)2);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif +#endif "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10332,13 +10332,13 @@ static InstructionDefinition fle_s_rd_frs1_frs2( "etiss_uint32 flags = 0;\n" "etiss_uint32 frs1 = 0;\n" "etiss_uint32 frs2 = 0;\n" - + "if(64 == 32)\n" "{\n" "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_s(((RISCV*)cpu)->F[" + toString(rs1) + "], ((RISCV*)cpu)->F[" + toString(rs2) + "], (etiss_uint32)1);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10346,28 +10346,28 @@ static InstructionDefinition fle_s_rd_frs1_frs2( "frs1 = unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs1 = %#x\\n\",frs1); \n" - #endif + #endif "frs2 = unbox_s(((RISCV*)cpu)->F[" + toString(rs2) + "]);\n" #if RISCV_DEBUG_CALL "printf(\"frs2 = %#x\\n\",frs2); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_s(frs1, frs2, (etiss_uint32)1);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10410,15 +10410,15 @@ static InstructionDefinition fclass_s_rd_frs1( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "*((RISCV*)cpu)->X[" + toString(rd) + "] = fclass_s(unbox_s(((RISCV*)cpu)->F[" + toString(rs1) + "]));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10461,7 +10461,7 @@ static InstructionDefinition fmv_x_w_rd_frs1( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "etiss_int64 cast_0 = (((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffff); \n" "if((etiss_int64)((etiss_uint64)cast_0 - 0x8000000000000000) > 0x0)\n" "{\n" @@ -10470,11 +10470,11 @@ static InstructionDefinition fmv_x_w_rd_frs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10522,13 +10522,13 @@ static InstructionDefinition fcvt_s_w_rd_rs1( "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fcvt_s((*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10536,20 +10536,20 @@ static InstructionDefinition fcvt_s_w_rd_rs1( "res = fcvt_s((*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10597,13 +10597,13 @@ static InstructionDefinition fcvt_s_wu_rd_rs1( "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = fcvt_s((*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10611,20 +10611,20 @@ static InstructionDefinition fcvt_s_wu_rd_rs1( "res = fcvt_s((*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" - #endif + #endif "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10668,13 +10668,13 @@ static InstructionDefinition fmv_w_x_rd_rs1( #endif "etiss_int64 upper = 0;\n" - + "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10682,16 +10682,16 @@ static InstructionDefinition fmv_w_x_rd_rs1( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)(*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff));\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10745,13 +10745,13 @@ static InstructionDefinition fsub_d_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -10759,18 +10759,18 @@ static InstructionDefinition fsub_d_rd_frs1_frs2( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fsub_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10778,24 +10778,24 @@ static InstructionDefinition fsub_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10849,13 +10849,13 @@ static InstructionDefinition fdiv_d_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -10863,18 +10863,18 @@ static InstructionDefinition fdiv_d_rd_frs1_frs2( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fdiv_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10882,24 +10882,24 @@ static InstructionDefinition fdiv_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -10949,13 +10949,13 @@ static InstructionDefinition fsqrt_d_rd_frs1( "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" "etiss_uint32 choose1 = 0;\n" - + "if(" + toString(rm) + " < 7)\n" "{\n" "choose1 = (" + toString(rm) + " & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "else\n" @@ -10963,18 +10963,18 @@ static InstructionDefinition fsqrt_d_rd_frs1( "choose1 = (((RISCV*)cpu)->FCSR & 0xff);\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "res = fsqrt_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), choose1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -10982,24 +10982,24 @@ static InstructionDefinition fsqrt_d_rd_frs1( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11050,29 +11050,29 @@ static InstructionDefinition fsgnj_d_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "etiss_int64 MSK2 = 0;\n" - + "ONE = 1;\n" #if RISCV_DEBUG_CALL "printf(\"ONE = %#lx\\n\",ONE); \n" -#endif +#endif "MSK1 = (ONE << 63);\n" #if RISCV_DEBUG_CALL "printf(\"MSK1 = %#lx\\n\",MSK1); \n" -#endif +#endif "MSK2 = MSK1 - 1;\n" #if RISCV_DEBUG_CALL "printf(\"MSK2 = %#lx\\n\",MSK2); \n" -#endif +#endif "res = (((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) & MSK2) | ((((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -11080,16 +11080,16 @@ static InstructionDefinition fsgnj_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11140,29 +11140,29 @@ static InstructionDefinition fsgnjn_d_rd_frs1_frs2( "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" "etiss_int64 MSK2 = 0;\n" - + "ONE = 1;\n" #if RISCV_DEBUG_CALL "printf(\"ONE = %#lx\\n\",ONE); \n" -#endif +#endif "MSK1 = (ONE << 63);\n" #if RISCV_DEBUG_CALL "printf(\"MSK1 = %#lx\\n\",MSK1); \n" -#endif +#endif "MSK2 = MSK1 - 1;\n" #if RISCV_DEBUG_CALL "printf(\"MSK2 = %#lx\\n\",MSK2); \n" -#endif +#endif "res = (((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) & MSK2) | (~(((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1))&0xffffffffffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -11170,16 +11170,16 @@ static InstructionDefinition fsgnjn_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11229,25 +11229,25 @@ static InstructionDefinition fsgnjx_d_rd_frs1_frs2( "etiss_int64 ONE = 0;\n" "etiss_int64 upper = 0;\n" "etiss_int64 MSK1 = 0;\n" - + "ONE = 1;\n" #if RISCV_DEBUG_CALL "printf(\"ONE = %#lx\\n\",ONE); \n" -#endif +#endif "MSK1 = (ONE << 63);\n" #if RISCV_DEBUG_CALL "printf(\"MSK1 = %#lx\\n\",MSK1); \n" -#endif +#endif "res = ((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff) ^ ((((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff) & MSK1));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -11255,16 +11255,16 @@ static InstructionDefinition fsgnjx_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11313,17 +11313,17 @@ static InstructionDefinition fmin_d_rd_frs1_frs2( "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" - + "res = fsel_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)0);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -11331,24 +11331,24 @@ static InstructionDefinition fmin_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11397,17 +11397,17 @@ static InstructionDefinition fmax_d_rd_frs1_frs2( "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" "etiss_uint32 flags = 0;\n" - + "res = fsel_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)1);\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -11415,24 +11415,24 @@ static InstructionDefinition fmax_d_rd_frs1_frs2( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11480,17 +11480,17 @@ static InstructionDefinition fcvt_d_s_rd_frs1( "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" - + "res = fconv_f2d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffff), (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -11498,16 +11498,16 @@ static InstructionDefinition fcvt_d_s_rd_frs1( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11555,23 +11555,23 @@ static InstructionDefinition feq_d_rd_frs1_frs2( #endif "etiss_uint32 flags = 0;\n" - + "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)0);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif +#endif "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11619,23 +11619,23 @@ static InstructionDefinition flt_d_rd_frs1_frs2( #endif "etiss_uint32 flags = 0;\n" - + "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)2);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif +#endif "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11683,23 +11683,23 @@ static InstructionDefinition fle_d_rd_frs1_frs2( #endif "etiss_uint32 flags = 0;\n" - + "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_uint32)fcmp_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff), (etiss_uint32)1);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif +#endif "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11742,15 +11742,15 @@ static InstructionDefinition fclass_d_rd_frs1( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "*((RISCV*)cpu)->X[" + toString(rd) + "] = fclass_d((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11798,7 +11798,7 @@ static InstructionDefinition fcvt_w_d_rd_frs1( #endif "etiss_uint32 flags = 0;\n" - + "etiss_int32 cast_0 = fcvt_64_32((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)0, (" + toString(rm) + " & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -11807,19 +11807,19 @@ static InstructionDefinition fcvt_w_d_rd_frs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif +#endif "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11867,7 +11867,7 @@ static InstructionDefinition fcvt_wu_d_rd_frs1( #endif "etiss_uint32 flags = 0;\n" - + "etiss_int32 cast_0 = fcvt_64_32((((RISCV*)cpu)->F[" + toString(rs1) + "] & 0xffffffffffffffff), (etiss_uint32)1, (" + toString(rm) + " & 0xff)); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -11876,19 +11876,19 @@ static InstructionDefinition fcvt_wu_d_rd_frs1( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif +#endif "flags = fget_flags();\n" #if RISCV_DEBUG_CALL "printf(\"flags = %#x\\n\",flags); \n" -#endif +#endif "((RISCV*)cpu)->FCSR = (((RISCV*)cpu)->FCSR & ~31) + (flags & 0x1f)&0xffffffff;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->FCSR = %#x\\n\",((RISCV*)cpu)->FCSR); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -11937,7 +11937,7 @@ static InstructionDefinition fcvt_d_w_rd_rs1( "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" - + "etiss_int32 cast_0 = (*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff); \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -11946,13 +11946,13 @@ static InstructionDefinition fcvt_d_w_rd_rs1( "res = fcvt_32_64((etiss_int64)cast_0, (etiss_uint32)2, (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -11960,16 +11960,16 @@ static InstructionDefinition fcvt_d_w_rd_rs1( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -12018,17 +12018,17 @@ static InstructionDefinition fcvt_d_wu_rd_rs1( "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" - + "res = fcvt_32_64((etiss_uint64)(*((RISCV*)cpu)->X[" + toString(rs1) + "] & 0xffffffff), (etiss_uint32)3, (" + toString(rm) + " & 0xff));\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -12036,16 +12036,16 @@ static InstructionDefinition fcvt_d_wu_rd_rs1( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -12099,7 +12099,7 @@ static InstructionDefinition c_addi4spn_rd_imm( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "if(" + toString(imm) + " == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" @@ -12108,12 +12108,12 @@ static InstructionDefinition c_addi4spn_rd_imm( "*((RISCV*)cpu)->X[" + toString(rd) + " + 8] = *((RISCV*)cpu)->X[2] + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + " + 8] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + " + 8]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12161,13 +12161,13 @@ static InstructionDefinition c_addi_rs1_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -12175,12 +12175,12 @@ static InstructionDefinition c_addi_rs1_imm( "imm_extended = 4294967232;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[" + toString(rs1) + "]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -12189,11 +12189,11 @@ static InstructionDefinition c_addi_rs1_imm( "*((RISCV*)cpu)->X[" + toString(rs1) + "] = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rs1) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rs1) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -12227,11 +12227,11 @@ static InstructionDefinition c_nop_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - - + + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -12266,13 +12266,13 @@ static InstructionDefinition dii_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12322,7 +12322,7 @@ static InstructionDefinition c_slli_rs1_shamt( "{\n" "X ^= ((-*((RISCV*)cpu)->X[i])^X) & (1 << i ); \n" "}\n" - + "if(" + toString(rs1) + " == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" @@ -12331,12 +12331,12 @@ static InstructionDefinition c_slli_rs1_shamt( "*((RISCV*)cpu)->X[" + toString(rs1) + "] = (*((RISCV*)cpu)->X[" + toString(rs1) + "] << " + toString(shamt) + ");\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rs1) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rs1) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12392,11 +12392,11 @@ static InstructionDefinition c_lw_8_rd_uimm_8_rs1_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -12408,12 +12408,12 @@ static InstructionDefinition c_lw_8_rd_uimm_8_rs1_( "*((RISCV*)cpu)->X[" + toString(rd) + " + 8] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + " + 8] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + " + 8]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12461,13 +12461,13 @@ static InstructionDefinition c_li_rd_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -12475,12 +12475,12 @@ static InstructionDefinition c_li_rd_imm( "imm_extended = 4294967232;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" @@ -12489,12 +12489,12 @@ static InstructionDefinition c_li_rd_imm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12546,11 +12546,11 @@ static InstructionDefinition c_lwsp_rd_sp_uimm( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[2] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" @@ -12562,12 +12562,12 @@ static InstructionDefinition c_lwsp_rd_sp_uimm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = (etiss_int32)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12623,31 +12623,31 @@ static InstructionDefinition c_sw_8_rs2_uimm_8_rs1_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV*)cpu)->X[" + toString(rs2) + " + 8];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12704,13 +12704,13 @@ static InstructionDefinition c_beqz_8_rs1_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x100)>>8 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -12718,12 +12718,12 @@ static InstructionDefinition c_beqz_8_rs1_imm( "imm_extended = 4294966784;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(*((RISCV*)cpu)->X[" + toString(rs1) + " + 8] == 0)\n" "{\n" "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" @@ -12734,7 +12734,7 @@ static InstructionDefinition c_beqz_8_rs1_imm( "choose1 = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" "}\n" @@ -12744,17 +12744,17 @@ static InstructionDefinition c_beqz_8_rs1_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 2;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -12803,31 +12803,31 @@ static InstructionDefinition c_swsp_rs2_uimm_sp_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[2] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -12888,13 +12888,13 @@ static InstructionDefinition c_jal_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -12902,16 +12902,16 @@ static InstructionDefinition c_jal_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "*((RISCV*)cpu)->X[1] = " +toString((uint32_t)ic.current_address_)+"ULL + 2;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[1] = %#x\\n\",*((RISCV*)cpu)->X[1]); \n" -#endif +#endif "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -12920,12 +12920,12 @@ static InstructionDefinition c_jal_imm( "cpu->instructionPointer = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -12979,24 +12979,24 @@ static InstructionDefinition c_fld_rd_uimm_8_rs1_( "etiss_uint32 offs = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + " + 8] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + " + 8]); \n" - #endif + #endif "}\n" "else\n" @@ -13004,17 +13004,17 @@ static InstructionDefinition c_fld_rd_uimm_8_rs1_( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + " + 8] = ((upper << 64) | res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + " + 8]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -13067,24 +13067,24 @@ static InstructionDefinition c_fldsp_rd_uimm_x2_( "etiss_uint32 offs = 0;\n" "etiss_uint64 res = 0;\n" "etiss_int64 upper = 0;\n" - + "offs = *((RISCV*)cpu)->X[2] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,8);\n" "res = MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#lx\\n\",res); \n" -#endif +#endif "if(64 == 64)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -13092,17 +13092,17 @@ static InstructionDefinition c_fldsp_rd_uimm_x2_( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 64) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -13150,13 +13150,13 @@ static InstructionDefinition c_lui_rd_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x20000)>>17 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -13164,12 +13164,12 @@ static InstructionDefinition c_lui_rd_imm( "imm_extended = 4294705152;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(" + toString(rd) + " == 0)\n" "{\n" "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION; \n" @@ -13183,12 +13183,12 @@ static InstructionDefinition c_lui_rd_imm( "*((RISCV*)cpu)->X[" + toString(rd) + "] = imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -13241,13 +13241,13 @@ static InstructionDefinition c_addi16sp_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x200)>>9 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -13255,12 +13255,12 @@ static InstructionDefinition c_addi16sp_imm( "imm_extended = 4294966272;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[2]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -13269,11 +13269,11 @@ static InstructionDefinition c_addi16sp_imm( "*((RISCV*)cpu)->X[2] = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[2] = %#x\\n\",*((RISCV*)cpu)->X[2]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13330,24 +13330,24 @@ static InstructionDefinition c_flw_rd_uimm_8_rs1_( "etiss_uint32 offs = 0;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "res = MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" -#endif +#endif "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + " + 8] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + " + 8]); \n" - #endif + #endif "}\n" "else\n" @@ -13355,17 +13355,17 @@ static InstructionDefinition c_flw_rd_uimm_8_rs1_( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + " + 8] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + " + 8] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + " + 8]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -13418,24 +13418,24 @@ static InstructionDefinition c_flwsp_rd_uimm_x2_( "etiss_uint32 offs = 0;\n" "etiss_uint32 res = 0;\n" "etiss_int64 upper = 0;\n" - + "offs = *((RISCV*)cpu)->X[2] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "exception = (*(system->dread))(system->handle,cpu,offs,tmpbuf,4);\n" "res = MEM_offs;\n" #if RISCV_DEBUG_CALL "printf(\"res = %#x\\n\",res); \n" -#endif +#endif "if(64 == 32)\n" "{\n" "((RISCV*)cpu)->F[" + toString(rd) + "] = res;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" "else\n" @@ -13443,17 +13443,17 @@ static InstructionDefinition c_flwsp_rd_uimm_x2_( "upper = - 1;\n" #if RISCV_DEBUG_CALL "printf(\"upper = %#lx\\n\",upper); \n" - #endif + #endif "((RISCV*)cpu)->F[" + toString(rd) + "] = ((upper << 32) | (etiss_uint64)res);\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->F[" + toString(rd) + "] = %#lx\\n\",((RISCV*)cpu)->F[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -13503,19 +13503,19 @@ static InstructionDefinition c_srli_8_rs1_shamt( "X ^= ((-*((RISCV*)cpu)->X[i])^X) & (1 << i ); \n" "}\n" "etiss_int8 rs1_idx = 0;\n" - + "rs1_idx = " + toString(rs1) + " + 8;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n" -#endif +#endif "*((RISCV*)cpu)->X[rs1_idx] = (*((RISCV*)cpu)->X[rs1_idx] >> " + toString(shamt) + ");\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[rs1_idx] = %#x\\n\",*((RISCV*)cpu)->X[rs1_idx]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13560,11 +13560,11 @@ static InstructionDefinition c_srai_8_rs1_shamt( #endif "etiss_int8 rs1_idx = 0;\n" - + "rs1_idx = " + toString(rs1) + " + 8;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[rs1_idx]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -13573,11 +13573,11 @@ static InstructionDefinition c_srai_8_rs1_shamt( "*((RISCV*)cpu)->X[rs1_idx] = ((etiss_int32)cast_0 >> " + toString(shamt) + ");\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[rs1_idx] = %#x\\n\",*((RISCV*)cpu)->X[rs1_idx]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13623,19 +13623,19 @@ static InstructionDefinition c_sub_8_rd_8_rs2( #endif "etiss_int8 rd_idx = 0;\n" - + "rd_idx = " + toString(rd) + " + 8;\n" #if RISCV_DEBUG_CALL "printf(\"rd_idx = %#x\\n\",rd_idx); \n" -#endif +#endif "*((RISCV*)cpu)->X[rd_idx] = *((RISCV*)cpu)->X[rd_idx] - *((RISCV*)cpu)->X[" + toString(rs2) + " + 8];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[rd_idx] = %#x\\n\",*((RISCV*)cpu)->X[rd_idx]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13681,19 +13681,19 @@ static InstructionDefinition c_xor_8_rd_8_rs2( #endif "etiss_int8 rd_idx = 0;\n" - + "rd_idx = " + toString(rd) + " + 8;\n" #if RISCV_DEBUG_CALL "printf(\"rd_idx = %#x\\n\",rd_idx); \n" -#endif +#endif "*((RISCV*)cpu)->X[rd_idx] = (*((RISCV*)cpu)->X[rd_idx] ^ *((RISCV*)cpu)->X[" + toString(rs2) + " + 8]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[rd_idx] = %#x\\n\",*((RISCV*)cpu)->X[rd_idx]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13739,19 +13739,19 @@ static InstructionDefinition c_or_8_rd_8_rs2( #endif "etiss_int8 rd_idx = 0;\n" - + "rd_idx = " + toString(rd) + " + 8;\n" #if RISCV_DEBUG_CALL "printf(\"rd_idx = %#x\\n\",rd_idx); \n" -#endif +#endif "*((RISCV*)cpu)->X[rd_idx] = (*((RISCV*)cpu)->X[rd_idx] | *((RISCV*)cpu)->X[" + toString(rs2) + " + 8]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[rd_idx] = %#x\\n\",*((RISCV*)cpu)->X[rd_idx]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13797,19 +13797,19 @@ static InstructionDefinition c_and_8_rd_8_rs2( #endif "etiss_int8 rd_idx = 0;\n" - + "rd_idx = " + toString(rd) + " + 8;\n" #if RISCV_DEBUG_CALL "printf(\"rd_idx = %#x\\n\",rd_idx); \n" -#endif +#endif "*((RISCV*)cpu)->X[rd_idx] = (*((RISCV*)cpu)->X[rd_idx] & *((RISCV*)cpu)->X[" + toString(rs2) + " + 8]);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[rd_idx] = %#x\\n\",*((RISCV*)cpu)->X[rd_idx]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13853,15 +13853,15 @@ static InstructionDefinition c_mv_rd_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "*((RISCV*)cpu)->X[" + toString(rd) + "] = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -13900,16 +13900,16 @@ static InstructionDefinition c_jr_rs1( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "cpu->instructionPointer = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -13958,13 +13958,13 @@ static InstructionDefinition c_andi_8_rs1_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int8 rs1_idx = 0;\n" - + "if((" + toString(imm) + " & 0x20)>>5 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -13972,16 +13972,16 @@ static InstructionDefinition c_andi_8_rs1_imm( "imm_extended = 4294967232;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "rs1_idx = " + toString(rs1) + " + 8;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_idx = %#x\\n\",rs1_idx); \n" -#endif +#endif "etiss_int32 cast_0 = *((RISCV*)cpu)->X[rs1_idx]; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -13990,11 +13990,11 @@ static InstructionDefinition c_andi_8_rs1_imm( "*((RISCV*)cpu)->X[rs1_idx] = ((etiss_int32)cast_0 & imm_extended);\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[rs1_idx] = %#x\\n\",*((RISCV*)cpu)->X[rs1_idx]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -14039,15 +14039,15 @@ static InstructionDefinition c_add_rd_rs2( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "*((RISCV*)cpu)->X[" + toString(rd) + "] = *((RISCV*)cpu)->X[" + toString(rd) + "] + *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" -#endif - +#endif + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -14087,20 +14087,20 @@ static InstructionDefinition c_jalr_rs1( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "*((RISCV*)cpu)->X[1] = " +toString((uint32_t)ic.current_address_)+"ULL + 2;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[1] = %#x\\n\",*((RISCV*)cpu)->X[1]); \n" -#endif +#endif "cpu->instructionPointer = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -14135,13 +14135,13 @@ static InstructionDefinition c_ebreak_( "handleResources(resource_time, resources, num_stages, num_resources, cpu);\n" #endif - + "return ETISS_RETURNCODE_CPUFINISHED; \n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -14201,13 +14201,13 @@ static InstructionDefinition c_j_imm( #endif "etiss_int32 imm_extended = 0;\n" - + "if((" + toString(imm) + " & 0x800)>>11 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -14215,12 +14215,12 @@ static InstructionDefinition c_j_imm( "imm_extended = 4294963200;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" "if((etiss_int32)((etiss_uint32)cast_0 - 0x80000000) > 0x0)\n" "{\n" @@ -14229,12 +14229,12 @@ static InstructionDefinition c_j_imm( "cpu->instructionPointer = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -14286,31 +14286,31 @@ static InstructionDefinition c_fsd_rs2_uimm_8_rs1_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV*)cpu)->F[" + toString(rs2) + " + 8] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 8 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -14358,31 +14358,31 @@ static InstructionDefinition c_fsdsp_rs2_uimm_x2_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[2] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint64 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffffffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,8);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 8 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -14439,13 +14439,13 @@ static InstructionDefinition c_bnez_8_rs1_imm( "etiss_int32 imm_extended = 0;\n" "etiss_int32 choose1 = 0;\n" - + "if((" + toString(imm) + " & 0x100)>>8 == 0)\n" "{\n" "imm_extended = 0;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "else\n" @@ -14453,12 +14453,12 @@ static InstructionDefinition c_bnez_8_rs1_imm( "imm_extended = 4294966784;\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" - #endif + #endif "}\n" "imm_extended = imm_extended + " + toString(imm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"imm_extended = %#x\\n\",imm_extended); \n" -#endif +#endif "if(*((RISCV*)cpu)->X[" + toString(rs1) + " + 8] != 0)\n" "{\n" "etiss_int32 cast_0 = " +toString((uint32_t)ic.current_address_)+"ULL ; \n" @@ -14469,7 +14469,7 @@ static InstructionDefinition c_bnez_8_rs1_imm( "choose1 = (etiss_int32)cast_0 + imm_extended;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif // Explicit assignment to PC "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" "}\n" @@ -14479,17 +14479,17 @@ static InstructionDefinition c_bnez_8_rs1_imm( "choose1 = " +toString((uint32_t)ic.current_address_)+"ULL + 2;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "cpu->instructionPointer = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"cpu->instructionPointer = %#lx\\n\",cpu->instructionPointer); \n" -#endif - +#endif + "cpu->instructionPointer = (uint32_t)cpu->instructionPointer; \n" - + "return 0;\n" -; +; return true; }, 0, @@ -14544,31 +14544,31 @@ static InstructionDefinition c_fsw_rs2_uimm_8_rs1_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[" + toString(rs1) + " + 8] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV*)cpu)->F[" + toString(rs2) + " + 8] & 0xffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -14616,31 +14616,31 @@ static InstructionDefinition c_fswsp_rs2_uimm_x2_( #endif "etiss_uint32 offs = 0;\n" - + "offs = *((RISCV*)cpu)->X[2] + " + toString(uimm) + ";\n" #if RISCV_DEBUG_CALL "printf(\"offs = %#x\\n\",offs); \n" -#endif +#endif "etiss_uint32 MEM_offs;\n" "tmpbuf = (etiss_uint8 *)&MEM_offs;\n" "MEM_offs = (((RISCV*)cpu)->F[" + toString(rs2) + "] & 0xffffffff);\n" "exception = (*(system->dwrite))(system->handle,cpu,offs,tmpbuf,4);\n" #if RISCV_DEBUG_CALL "printf(\"MEM_offs = %#x\\n\",MEM_offs); \n" -#endif +#endif "if((offs + 4 > ((RISCV*)cpu)->RES) && (offs < 4 + ((RISCV*)cpu)->RES))\n" "{\n" "((RISCV*)cpu)->RES = 0;\n" #if RISCV_DEBUG_CALL "printf(\"((RISCV*)cpu)->RES = %#x\\n\",((RISCV*)cpu)->RES); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 2 ))+"ULL; \n" - + "return exception;\n" -; +; return true; }, 0, @@ -14703,17 +14703,17 @@ static InstructionDefinition add8_rs2_rs1_rd( "etiss_int8 rs2_3 = 0;\n" "etiss_int8 rs1_3 = 0;\n" "etiss_int8 rs2_2 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "etiss_int8 cast_0 = (rs1_val & 0xff); \n" "if((etiss_int8)((etiss_uint8)cast_0 - 0x80) > 0x0)\n" "{\n" @@ -14722,7 +14722,7 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs1_0 = (etiss_int8)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#x\\n\",rs1_0); \n" - #endif + #endif "etiss_int32 cast_1 = ((rs1_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x800000) > 0x0)\n" "{\n" @@ -14731,7 +14731,7 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs1_1 = (etiss_int8)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#x\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = ((rs1_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -14740,7 +14740,7 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs1_2 = (etiss_int8)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_2 = %#x\\n\",rs1_2); \n" - #endif + #endif "etiss_int8 cast_3 = ((rs1_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_3 - 0x80) > 0x0)\n" "{\n" @@ -14749,7 +14749,7 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs1_3 = (etiss_int8)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_3 = %#x\\n\",rs1_3); \n" - #endif + #endif "etiss_int8 cast_4 = ((rs2_val & 0xff) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_4 - 0x80) > 0x0)\n" "{\n" @@ -14758,7 +14758,7 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs2_0 = (etiss_int8)cast_4;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#x\\n\",rs2_0); \n" - #endif + #endif "etiss_int32 cast_5 = ((rs2_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_5 - 0x800000) > 0x0)\n" "{\n" @@ -14767,7 +14767,7 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs2_1 = (etiss_int8)cast_5;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#x\\n\",rs2_1); \n" - #endif + #endif "etiss_int16 cast_6 = ((rs2_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_6 - 0x8000) > 0x0)\n" "{\n" @@ -14776,7 +14776,7 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs2_2 = (etiss_int8)cast_6;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_2 = %#x\\n\",rs2_2); \n" - #endif + #endif "etiss_int8 cast_7 = ((rs2_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_7 - 0x80) > 0x0)\n" "{\n" @@ -14785,33 +14785,33 @@ static InstructionDefinition add8_rs2_rs1_rd( "rs2_3 = (etiss_int8)cast_7;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_3 = %#x\\n\",rs2_3); \n" - #endif + #endif "byte_1 = rs1_0 + rs2_0;\n" #if RISCV_DEBUG_CALL "printf(\"byte_1 = %#x\\n\",byte_1); \n" - #endif + #endif "byte_2 = rs1_1 + rs2_1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_2 = %#x\\n\",byte_2); \n" - #endif + #endif "byte_3 = rs1_2 + rs2_2;\n" #if RISCV_DEBUG_CALL "printf(\"byte_3 = %#x\\n\",byte_3); \n" - #endif + #endif "byte_4 = rs1_3 + rs2_3;\n" #if RISCV_DEBUG_CALL "printf(\"byte_4 = %#x\\n\",byte_4); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (((((byte_4 & 255) << 24) | ((byte_3 & 255) << 16)) | ((byte_2 & 255) << 8)) | (byte_1 & 255));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -14874,17 +14874,17 @@ static InstructionDefinition sub8_rs2_rs1_rd( "etiss_int8 rs2_3 = 0;\n" "etiss_int8 rs1_3 = 0;\n" "etiss_int8 rs2_2 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "etiss_int8 cast_0 = (rs1_val & 0xff); \n" "if((etiss_int8)((etiss_uint8)cast_0 - 0x80) > 0x0)\n" "{\n" @@ -14893,7 +14893,7 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs1_0 = (etiss_int8)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#d\\n\",rs1_0); \n" - #endif + #endif "etiss_int32 cast_1 = ((rs1_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x800000) > 0x0)\n" "{\n" @@ -14902,7 +14902,7 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs1_1 = (etiss_int8)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#d\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = ((rs1_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -14911,7 +14911,7 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs1_2 = (etiss_int8)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_2 = %#d\\n\",rs1_2); \n" - #endif + #endif "etiss_int8 cast_3 = ((rs1_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_3 - 0x80) > 0x0)\n" "{\n" @@ -14920,7 +14920,7 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs1_3 = (etiss_int8)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_3 = %#d\\n\",rs1_3); \n" - #endif + #endif "etiss_int8 cast_4 = ((rs2_val & 0xff) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_4 - 0x80) > 0x0)\n" "{\n" @@ -14929,7 +14929,7 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs2_0 = (etiss_int8)cast_4;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#d\\n\",rs2_0); \n" - #endif + #endif "etiss_int32 cast_5 = ((rs2_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_5 - 0x800000) > 0x0)\n" "{\n" @@ -14938,7 +14938,7 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs2_1 = (etiss_int8)cast_5;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#d\\n\",rs2_1); \n" - #endif + #endif "etiss_int16 cast_6 = ((rs2_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_6 - 0x8000) > 0x0)\n" "{\n" @@ -14947,7 +14947,7 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs2_2 = (etiss_int8)cast_6;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_2 = %#d\\n\",rs2_2); \n" - #endif + #endif "etiss_int8 cast_7 = ((rs2_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_7 - 0x80) > 0x0)\n" "{\n" @@ -14956,33 +14956,33 @@ static InstructionDefinition sub8_rs2_rs1_rd( "rs2_3 = (etiss_int8)cast_7;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_3 = %#d\\n\",rs2_3); \n" - #endif + #endif "byte_1 = rs1_0 - rs2_0;\n" #if RISCV_DEBUG_CALL "printf(\"byte_1 = %#d\\n\",byte_1); \n" - #endif + #endif "byte_2 = rs1_1 - rs2_1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_2 = %#d\\n\",byte_2); \n" - #endif + #endif "byte_3 = rs1_2 - rs2_2;\n" #if RISCV_DEBUG_CALL "printf(\"byte_3 = %#d\\n\",byte_3); \n" - #endif + #endif "byte_4 = rs1_3 - rs2_3;\n" #if RISCV_DEBUG_CALL "printf(\"byte_4 = %#d\\n\",byte_4); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (((((byte_4 & 255) << 24) | ((byte_3 & 255) << 16)) | ((byte_2 & 255) << 8)) | (byte_1 & 255));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -15047,21 +15047,21 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "etiss_int8 rs2_3 = 0;\n" "etiss_int8 rs1_3 = 0;\n" "etiss_int8 rs2_2 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "rd_val = *((RISCV*)cpu)->X[" + toString(rd) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rd_val = %#x\\n\",rd_val); \n" - #endif + #endif "etiss_int8 cast_0 = (rs1_val & 0xff); \n" "if((etiss_int8)((etiss_uint8)cast_0 - 0x80) > 0x0)\n" "{\n" @@ -15070,7 +15070,7 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs1_0 = (etiss_int8)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#x\\n\",rs1_0); \n" - #endif + #endif "etiss_int32 cast_1 = ((rs1_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x800000) > 0x0)\n" "{\n" @@ -15079,7 +15079,7 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs1_1 = (etiss_int8)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#x\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = ((rs1_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -15088,7 +15088,7 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs1_2 = (etiss_int8)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_2 = %#x\\n\",rs1_2); \n" - #endif + #endif "etiss_int8 cast_3 = ((rs1_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_3 - 0x80) > 0x0)\n" "{\n" @@ -15097,7 +15097,7 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs1_3 = (etiss_int8)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_3 = %#x\\n\",rs1_3); \n" - #endif + #endif "etiss_int8 cast_4 = ((rs2_val & 0xff) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_4 - 0x80) > 0x0)\n" "{\n" @@ -15106,7 +15106,7 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs2_0 = (etiss_int8)cast_4;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#x\\n\",rs2_0); \n" - #endif + #endif "etiss_int32 cast_5 = ((rs2_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_5 - 0x800000) > 0x0)\n" "{\n" @@ -15115,7 +15115,7 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs2_1 = (etiss_int8)cast_5;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#x\\n\",rs2_1); \n" - #endif + #endif "etiss_int16 cast_6 = ((rs2_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_6 - 0x8000) > 0x0)\n" "{\n" @@ -15124,7 +15124,7 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs2_2 = (etiss_int8)cast_6;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_2 = %#x\\n\",rs2_2); \n" - #endif + #endif "etiss_int8 cast_7 = ((rs2_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_7 - 0x80) > 0x0)\n" "{\n" @@ -15133,33 +15133,33 @@ static InstructionDefinition smaqa_rs2_rs1_rd( "rs2_3 = (etiss_int8)cast_7;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_3 = %#x\\n\",rs2_3); \n" - #endif + #endif "byte_1 = (rs1_0 * rs2_0);\n" #if RISCV_DEBUG_CALL "printf(\"byte_1 = %#x\\n\",byte_1); \n" - #endif + #endif "byte_2 = (rs1_1 * rs2_1);\n" #if RISCV_DEBUG_CALL "printf(\"byte_2 = %#x\\n\",byte_2); \n" - #endif + #endif "byte_3 = (rs1_2 * rs2_2);\n" #if RISCV_DEBUG_CALL "printf(\"byte_3 = %#x\\n\",byte_3); \n" - #endif + #endif "byte_4 = (rs1_3 * rs2_3);\n" #if RISCV_DEBUG_CALL "printf(\"byte_4 = %#x\\n\",byte_4); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = rd_val + byte_1 + byte_2 + byte_3 + byte_4;\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -15222,17 +15222,17 @@ static InstructionDefinition sll8_rs2_rs1_rd( "etiss_int8 rs2_3 = 0;\n" "etiss_int8 rs1_3 = 0;\n" "etiss_int8 rs2_2 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "etiss_int8 cast_0 = (rs1_val & 0xff); \n" "if((etiss_int8)((etiss_uint8)cast_0 - 0x80) > 0x0)\n" "{\n" @@ -15241,7 +15241,7 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs1_0 = (etiss_int8)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#x\\n\",rs1_0); \n" - #endif + #endif "etiss_int32 cast_1 = ((rs1_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x800000) > 0x0)\n" "{\n" @@ -15250,7 +15250,7 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs1_1 = (etiss_int8)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#x\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = ((rs1_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -15259,7 +15259,7 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs1_2 = (etiss_int8)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_2 = %#x\\n\",rs1_2); \n" - #endif + #endif "etiss_int8 cast_3 = ((rs1_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_3 - 0x80) > 0x0)\n" "{\n" @@ -15268,7 +15268,7 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs1_3 = (etiss_int8)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_3 = %#x\\n\",rs1_3); \n" - #endif + #endif "etiss_int8 cast_4 = ((rs2_val & 0xff) & 7); \n" "if((etiss_int8)((etiss_uint8)cast_4 - 0x80) > 0x0)\n" "{\n" @@ -15277,7 +15277,7 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs2_0 = (etiss_int8)cast_4;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#x\\n\",rs2_0); \n" - #endif + #endif "etiss_int32 cast_5 = ((rs2_val >> 8) & 7); \n" "if((etiss_int32)((etiss_uint32)cast_5 - 0x800000) > 0x0)\n" "{\n" @@ -15286,7 +15286,7 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs2_1 = (etiss_int8)cast_5;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#x\\n\",rs2_1); \n" - #endif + #endif "etiss_int16 cast_6 = ((rs2_val >> 16) & 7); \n" "if((etiss_int16)((etiss_uint16)cast_6 - 0x8000) > 0x0)\n" "{\n" @@ -15295,7 +15295,7 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs2_2 = (etiss_int8)cast_6;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_2 = %#x\\n\",rs2_2); \n" - #endif + #endif "etiss_int8 cast_7 = ((rs2_val >> 24) & 7); \n" "if((etiss_int8)((etiss_uint8)cast_7 - 0x80) > 0x0)\n" "{\n" @@ -15304,33 +15304,33 @@ static InstructionDefinition sll8_rs2_rs1_rd( "rs2_3 = (etiss_int8)cast_7;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_3 = %#x\\n\",rs2_3); \n" - #endif + #endif "byte_1 = (rs1_0 << rs2_0);\n" #if RISCV_DEBUG_CALL "printf(\"byte_1 = %#x\\n\",byte_1); \n" - #endif + #endif "byte_2 = (rs1_1 << rs2_1);\n" #if RISCV_DEBUG_CALL "printf(\"byte_2 = %#x\\n\",byte_2); \n" - #endif + #endif "byte_3 = (rs1_2 << rs2_2);\n" #if RISCV_DEBUG_CALL "printf(\"byte_3 = %#x\\n\",byte_3); \n" - #endif + #endif "byte_4 = (rs1_3 << rs2_3);\n" #if RISCV_DEBUG_CALL "printf(\"byte_4 = %#x\\n\",byte_4); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (((((byte_4 & 255) << 24) | ((byte_3 & 255) << 16)) | ((byte_2 & 255) << 8)) | (byte_1 & 255));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -15394,17 +15394,17 @@ static InstructionDefinition smin8_rs2_rs1_rd( "etiss_int8 rs2_3 = 0;\n" "etiss_int8 rs1_3 = 0;\n" "etiss_int8 rs2_2 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "etiss_int8 cast_0 = (rs1_val & 0xff); \n" "if((etiss_int8)((etiss_uint8)cast_0 - 0x80) > 0x0)\n" "{\n" @@ -15413,7 +15413,7 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs1_0 = (etiss_int8)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#x\\n\",rs1_0); \n" - #endif + #endif "etiss_int32 cast_1 = ((rs1_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x800000) > 0x0)\n" "{\n" @@ -15422,7 +15422,7 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs1_1 = (etiss_int8)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#x\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = ((rs1_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -15431,7 +15431,7 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs1_2 = (etiss_int8)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_2 = %#x\\n\",rs1_2); \n" - #endif + #endif "etiss_int8 cast_3 = ((rs1_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_3 - 0x80) > 0x0)\n" "{\n" @@ -15440,7 +15440,7 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs1_3 = (etiss_int8)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_3 = %#x\\n\",rs1_3); \n" - #endif + #endif "etiss_int8 cast_4 = ((rs2_val & 0xff) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_4 - 0x80) > 0x0)\n" "{\n" @@ -15449,7 +15449,7 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs2_0 = (etiss_int8)cast_4;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#x\\n\",rs2_0); \n" - #endif + #endif "etiss_int32 cast_5 = ((rs2_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_5 - 0x800000) > 0x0)\n" "{\n" @@ -15458,7 +15458,7 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs2_1 = (etiss_int8)cast_5;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#x\\n\",rs2_1); \n" - #endif + #endif "etiss_int16 cast_6 = ((rs2_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_6 - 0x8000) > 0x0)\n" "{\n" @@ -15467,7 +15467,7 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs2_2 = (etiss_int8)cast_6;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_2 = %#x\\n\",rs2_2); \n" - #endif + #endif "etiss_int8 cast_7 = ((rs2_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_7 - 0x80) > 0x0)\n" "{\n" @@ -15476,93 +15476,93 @@ static InstructionDefinition smin8_rs2_rs1_rd( "rs2_3 = (etiss_int8)cast_7;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_3 = %#x\\n\",rs2_3); \n" - #endif + #endif "if(rs1_0 < rs2_0)\n" "{\n" "choose1 = rs1_0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_1 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_1 = %#x\\n\",byte_1); \n" - #endif + #endif "if(rs1_1 < rs2_1)\n" "{\n" "choose1 = rs1_1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_2 = %#x\\n\",byte_2); \n" - #endif + #endif "if(rs1_2 < rs2_2)\n" "{\n" "choose1 = rs1_2;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_2;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_3 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_3 = %#x\\n\",byte_3); \n" - #endif + #endif "if(rs1_3 < rs2_3)\n" "{\n" "choose1 = rs1_3;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_3;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_4 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_4 = %#x\\n\",byte_4); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (((((byte_4 & 255) << 24) | ((byte_3 & 255) << 16)) | ((byte_2 & 255) << 8)) | (byte_1 & 255));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -15626,17 +15626,17 @@ static InstructionDefinition smax8_rs2_rs1_rd( "etiss_int8 rs2_3 = 0;\n" "etiss_int8 rs1_3 = 0;\n" "etiss_int8 rs2_2 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "etiss_int8 cast_0 = (rs1_val & 0xff); \n" "if((etiss_int8)((etiss_uint8)cast_0 - 0x80) > 0x0)\n" "{\n" @@ -15645,7 +15645,7 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs1_0 = (etiss_int8)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#x\\n\",rs1_0); \n" - #endif + #endif "etiss_int32 cast_1 = ((rs1_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x800000) > 0x0)\n" "{\n" @@ -15654,7 +15654,7 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs1_1 = (etiss_int8)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#x\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = ((rs1_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -15663,7 +15663,7 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs1_2 = (etiss_int8)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_2 = %#x\\n\",rs1_2); \n" - #endif + #endif "etiss_int8 cast_3 = ((rs1_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_3 - 0x80) > 0x0)\n" "{\n" @@ -15672,7 +15672,7 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs1_3 = (etiss_int8)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_3 = %#x\\n\",rs1_3); \n" - #endif + #endif "etiss_int8 cast_4 = ((rs2_val & 0xff) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_4 - 0x80) > 0x0)\n" "{\n" @@ -15681,7 +15681,7 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs2_0 = (etiss_int8)cast_4;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#x\\n\",rs2_0); \n" - #endif + #endif "etiss_int32 cast_5 = ((rs2_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_5 - 0x800000) > 0x0)\n" "{\n" @@ -15690,7 +15690,7 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs2_1 = (etiss_int8)cast_5;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#x\\n\",rs2_1); \n" - #endif + #endif "etiss_int16 cast_6 = ((rs2_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_6 - 0x8000) > 0x0)\n" "{\n" @@ -15699,7 +15699,7 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs2_2 = (etiss_int8)cast_6;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_2 = %#x\\n\",rs2_2); \n" - #endif + #endif "etiss_int8 cast_7 = ((rs2_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_7 - 0x80) > 0x0)\n" "{\n" @@ -15708,93 +15708,93 @@ static InstructionDefinition smax8_rs2_rs1_rd( "rs2_3 = (etiss_int8)cast_7;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_3 = %#x\\n\",rs2_3); \n" - #endif + #endif "if(rs1_0 > rs2_0)\n" "{\n" "choose1 = rs1_0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_1 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_1 = %#x\\n\",byte_1); \n" - #endif + #endif "if(rs1_1 > rs2_1)\n" "{\n" "choose1 = rs1_1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_2 = %#x\\n\",byte_2); \n" - #endif + #endif "if(rs1_2 > rs2_2)\n" "{\n" "choose1 = rs1_2;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_2;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_3 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_3 = %#x\\n\",byte_3); \n" - #endif + #endif "if(rs1_3 > rs2_3)\n" "{\n" "choose1 = rs1_3;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_3;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_4 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_4 = %#x\\n\",byte_4); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (((((byte_4 & 255) << 24) | ((byte_3 & 255) << 16)) | ((byte_2 & 255) << 8)) | (byte_1 & 255));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -15852,17 +15852,17 @@ static InstructionDefinition smax16_rs2_rs1_rd( "etiss_int16 choose1 = 0;\n" "etiss_int16 half_word_2 = 0;\n" "etiss_int16 half_word_1 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "etiss_int16 cast_0 = (rs1_val & 0xffff); \n" "if((etiss_int16)((etiss_uint16)cast_0 - 0x8000) > 0x0)\n" "{\n" @@ -15871,7 +15871,7 @@ static InstructionDefinition smax16_rs2_rs1_rd( "rs1_0 = (etiss_int16)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#x\\n\",rs1_0); \n" - #endif + #endif "etiss_int16 cast_1 = ((rs1_val >> 16) & 65535); \n" "if((etiss_int16)((etiss_uint16)cast_1 - 0x8000) > 0x0)\n" "{\n" @@ -15880,7 +15880,7 @@ static InstructionDefinition smax16_rs2_rs1_rd( "rs1_1 = (etiss_int16)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#x\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = (rs2_val & 0xffff); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -15889,7 +15889,7 @@ static InstructionDefinition smax16_rs2_rs1_rd( "rs2_0 = (etiss_int16)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#x\\n\",rs2_0); \n" - #endif + #endif "etiss_int16 cast_3 = ((rs2_val >> 16) & 65535); \n" "if((etiss_int16)((etiss_uint16)cast_3 - 0x8000) > 0x0)\n" "{\n" @@ -15898,55 +15898,55 @@ static InstructionDefinition smax16_rs2_rs1_rd( "rs2_1 = (etiss_int16)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#x\\n\",rs2_1); \n" - #endif + #endif "if(rs1_0 > rs2_0)\n" "{\n" "choose1 = rs1_0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "half_word_1 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"half_word_1 = %#x\\n\",half_word_1); \n" - #endif + #endif "if(rs1_1 > rs2_1)\n" "{\n" "choose1 = rs1_1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = rs2_1;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "half_word_2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"half_word_2 = %#x\\n\",half_word_2); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (((half_word_2 & 65535) << 16) | (half_word_1 & 65535));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -16010,17 +16010,17 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "etiss_int8 rs2_3 = 0;\n" "etiss_int8 rs1_3 = 0;\n" "etiss_int8 rs2_2 = 0;\n" - + "if(" + toString(rd) + " != 0)\n" "{\n" "rs1_val = *((RISCV*)cpu)->X[" + toString(rs1) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs1_val = %#x\\n\",rs1_val); \n" - #endif + #endif "rs2_val = *((RISCV*)cpu)->X[" + toString(rs2) + "];\n" #if RISCV_DEBUG_CALL "printf(\"rs2_val = %#x\\n\",rs2_val); \n" - #endif + #endif "etiss_int8 cast_0 = (rs1_val & 0xff); \n" "if((etiss_int8)((etiss_uint8)cast_0 - 0x80) > 0x0)\n" "{\n" @@ -16029,7 +16029,7 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs1_0 = (etiss_int8)cast_0;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_0 = %#x\\n\",rs1_0); \n" - #endif + #endif "etiss_int32 cast_1 = ((rs1_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_1 - 0x800000) > 0x0)\n" "{\n" @@ -16038,7 +16038,7 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs1_1 = (etiss_int8)cast_1;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_1 = %#x\\n\",rs1_1); \n" - #endif + #endif "etiss_int16 cast_2 = ((rs1_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_2 - 0x8000) > 0x0)\n" "{\n" @@ -16047,7 +16047,7 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs1_2 = (etiss_int8)cast_2;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_2 = %#x\\n\",rs1_2); \n" - #endif + #endif "etiss_int8 cast_3 = ((rs1_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_3 - 0x80) > 0x0)\n" "{\n" @@ -16056,7 +16056,7 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs1_3 = (etiss_int8)cast_3;\n" #if RISCV_DEBUG_CALL "printf(\"rs1_3 = %#x\\n\",rs1_3); \n" - #endif + #endif "etiss_int8 cast_4 = ((rs2_val & 0xff) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_4 - 0x80) > 0x0)\n" "{\n" @@ -16065,7 +16065,7 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs2_0 = (etiss_int8)cast_4;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_0 = %#x\\n\",rs2_0); \n" - #endif + #endif "etiss_int32 cast_5 = ((rs2_val >> 8) & 255); \n" "if((etiss_int32)((etiss_uint32)cast_5 - 0x800000) > 0x0)\n" "{\n" @@ -16074,7 +16074,7 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs2_1 = (etiss_int8)cast_5;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_1 = %#x\\n\",rs2_1); \n" - #endif + #endif "etiss_int16 cast_6 = ((rs2_val >> 16) & 255); \n" "if((etiss_int16)((etiss_uint16)cast_6 - 0x8000) > 0x0)\n" "{\n" @@ -16083,7 +16083,7 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs2_2 = (etiss_int8)cast_6;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_2 = %#x\\n\",rs2_2); \n" - #endif + #endif "etiss_int8 cast_7 = ((rs2_val >> 24) & 255); \n" "if((etiss_int8)((etiss_uint8)cast_7 - 0x80) > 0x0)\n" "{\n" @@ -16092,93 +16092,93 @@ static InstructionDefinition scmple8_rs2_rs1_rd( "rs2_3 = (etiss_int8)cast_7;\n" #if RISCV_DEBUG_CALL "printf(\"rs2_3 = %#x\\n\",rs2_3); \n" - #endif + #endif "if(rs1_0 <= rs2_0)\n" "{\n" "choose1 = 255;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_1 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_1 = %#x\\n\",byte_1); \n" - #endif + #endif "if(rs1_1 <= rs2_1)\n" "{\n" "choose1 = 255;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_2 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_2 = %#x\\n\",byte_2); \n" - #endif + #endif "if(rs1_2 <= rs2_2)\n" "{\n" "choose1 = 255;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_3 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_3 = %#x\\n\",byte_3); \n" - #endif + #endif "if(rs1_3 <= rs2_3)\n" "{\n" "choose1 = 255;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" - + "else\n" "{\n" "choose1 = 0;\n" #if RISCV_DEBUG_CALL "printf(\"choose1 = %#x\\n\",choose1); \n" - #endif + #endif "}\n" "byte_4 = choose1;\n" #if RISCV_DEBUG_CALL "printf(\"byte_4 = %#x\\n\",byte_4); \n" - #endif + #endif "*((RISCV*)cpu)->X[" + toString(rd) + "] = (((((byte_4 & 255) << 24) | ((byte_3 & 255) << 16)) | ((byte_2 & 255) << 8)) | (byte_1 & 255));\n" #if RISCV_DEBUG_CALL "printf(\"*((RISCV*)cpu)->X[" + toString(rd) + "] = %#x\\n\",*((RISCV*)cpu)->X[" + toString(rd) + "]); \n" - #endif + #endif "}\n" - + "cpu->instructionPointer = " +toString((uint32_t)(ic.current_address_+ 4 ))+"ULL; \n" - -; + +; return true; }, 0, @@ -16186,3 +16186,5916 @@ nullptr ); //------------------------------------------------------------------------------------------------------------------- +// VSETVLI --------------------------------------------------------------------- +static InstructionDefinition vsetvli_rd_rs1_zimm ( + ISA32_RISCV, + "vsetvli", + (uint32_t) 0x007057, + (uint32_t) 0x8000707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 zimm = 0; +static BitArrayRange R_zimm_0(30, 20); +zimm += R_zimm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSETVLI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint8 sew = (vtype_extractSEW(" + std::to_string(zimm) + ")) & 0x7;\n"; +partInit.code() += "etiss_uint8 lmul = (vtype_extractLMUL(" + std::to_string(zimm) + ")) & 0x7;\n"; +partInit.code() += "etiss_uint8 vta = (vtype_extractTA(" + std::to_string(zimm) + ")) & 0x1;\n"; +partInit.code() += "etiss_uint8 vma = (vtype_extractMA(" + std::to_string(zimm) + ")) & 0x1;\n"; +partInit.code() += "etiss_uint32 _vlmax = " + std::to_string(0) + ";\n"; +partInit.code() += "etiss_uint32 _illmask = " + std::to_string(0) + ";\n"; +partInit.code() += "etiss_uint32 vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "if (lmul & " + std::to_string(4) + ") {\n"; +partInit.code() += "_illmask = " + std::to_string((1) << (32 - 1)) + ";\n"; +partInit.code() += "if (lmul == " + std::to_string(6) + ") {\n"; +partInit.code() += "_vlmax = vlen / (" + std::to_string(8) + ") << (sew) / " + std::to_string(4) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(7) + ") {\n"; +partInit.code() += "_vlmax = vlen / (" + std::to_string(8) + ") << (sew) / " + std::to_string(2) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "_vlmax = vlen / (" + std::to_string(8) + ") << (sew) / " + std::to_string(8) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "_illmask = " + std::to_string((0) << (32 - 1)) + ";\n"; +partInit.code() += "if (lmul == " + std::to_string(0) + ") {\n"; +partInit.code() += "_vlmax = vlen / (" + std::to_string(8) + ") << (sew);\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(1) + ") {\n"; +partInit.code() += "_vlmax = vlen / (" + std::to_string(8) + ") << (sew) * " + std::to_string(2) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(2) + ") {\n"; +partInit.code() += "_vlmax = vlen / (" + std::to_string(8) + ") << (sew) * " + std::to_string(4) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(3) + ") {\n"; +partInit.code() += "_vlmax = vlen / (" + std::to_string(8) + ") << (sew) * " + std::to_string(8) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "etiss_uint32 _avl = " + std::to_string(0) + ";\n"; +if (rs1 != 0) { +partInit.code() += "_avl = *((RISCV*)cpu)->X[" + std::to_string(rs1) + "];\n"; +} else { +if (rd != 0) { +partInit.code() += "_avl = " + std::to_string(~(0)) + ";\n"; +} else { +partInit.code() += "_avl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +} +} +partInit.code() += "etiss_uint32 _vl = " + std::to_string(0) + ";\n"; +partInit.code() += "if (_avl <= _vlmax) {\n"; +partInit.code() += "_vl = _avl;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (_avl >= (" + std::to_string(2) + " * _vlmax)) {\n"; +partInit.code() += "_vl = _vlmax;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "_vl = (_avl & " + std::to_string(2) + ") ? (_avl / " + std::to_string(2) + " + " + std::to_string(1) + ") : (_avl / " + std::to_string(2) + ");\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(3104) + "] = _vl;\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(3105) + "] = _illmask | " + std::to_string(zimm) + ";\n"; +if (rd != 0) { +partInit.code() += "*((RISCV*)cpu)->X[" + std::to_string(rd) + "] = _vl;\n"; +} +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getRegisterDependencies().add(reg_name[rs1], 32); + partInit.getAffectedRegisters().add(reg_name[rd], 32); + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 zimm = 0; +static BitArrayRange R_zimm_0(30, 20); +zimm += R_zimm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsetvli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | zimm=" + std::to_string(zimm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSETVL ---------------------------------------------------------------------- +static InstructionDefinition vsetvl_rd_rs1_rs2 ( + ISA32_RISCV, + "vsetvl", + (uint32_t) 0x80007057, + (uint32_t) 0xfe00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSETVL\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint16 zimm = (*((RISCV*)cpu)->X[" + std::to_string(rs2) + "]) & 0x7ff;\n"; +partInit.code() += "etiss_uint8 sew = (vtype_extractSEW(zimm)) & 0x7;\n"; +partInit.code() += "etiss_uint8 lmul = (vtype_extractLMUL(zimm)) & 0x7;\n"; +partInit.code() += "etiss_uint8 vta = (vtype_extractTA(zimm)) & 0x1;\n"; +partInit.code() += "etiss_uint8 vma = (vtype_extractMA(zimm)) & 0x1;\n"; +partInit.code() += "etiss_uint32 _vlmax = " + std::to_string(0) + ";\n"; +partInit.code() += "etiss_uint32 _illmask = " + std::to_string(0) + ";\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "if (lmul & " + std::to_string(4) + ") {\n"; +partInit.code() += "_illmask = " + std::to_string((1) << (32 - 1)) + ";\n"; +partInit.code() += "if (lmul == " + std::to_string(6) + ") {\n"; +partInit.code() += "_vlmax = _vlen / (" + std::to_string(8) + ") << (sew) / " + std::to_string(4) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(7) + ") {\n"; +partInit.code() += "_vlmax = _vlen / (" + std::to_string(8) + ") << (sew) / " + std::to_string(2) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "_vlmax = _vlen / (" + std::to_string(8) + ") << (sew) / " + std::to_string(8) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "_illmask = " + std::to_string((0) << (32 - 1)) + ";\n"; +partInit.code() += "if (lmul == " + std::to_string(0) + ") {\n"; +partInit.code() += "_vlmax = _vlen / (" + std::to_string(8) + ") << (sew);\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(1) + ") {\n"; +partInit.code() += "_vlmax = _vlen / (" + std::to_string(8) + ") << (sew) * " + std::to_string(2) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(2) + ") {\n"; +partInit.code() += "_vlmax = _vlen / (" + std::to_string(8) + ") << (sew) * " + std::to_string(4) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (lmul == " + std::to_string(3) + ") {\n"; +partInit.code() += "_vlmax = _vlen / (" + std::to_string(8) + ") << (sew) * " + std::to_string(8) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "etiss_uint32 _avl = " + std::to_string(0) + ";\n"; +if (rs1 != 0) { +partInit.code() += "_avl = *((RISCV*)cpu)->X[" + std::to_string(rs1) + "];\n"; +} else { +if (rd != 0) { +partInit.code() += "_avl = " + std::to_string(~(0)) + ";\n"; +} else { +partInit.code() += "_avl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +} +} +partInit.code() += "etiss_uint32 _vl = " + std::to_string(0) + ";\n"; +partInit.code() += "if (_avl <= _vlmax) {\n"; +partInit.code() += "_vl = _avl;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "if (_avl >= (" + std::to_string(2) + " * _vlmax)) {\n"; +partInit.code() += "_vl = _vlmax;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "_vl = (_avl & " + std::to_string(2) + ") ? (_avl / " + std::to_string(2) + " + " + std::to_string(1) + ") : (_avl / " + std::to_string(2) + ");\n"; +partInit.code() += "}\n"; +partInit.code() += "}\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(3104) + "] = _vl;\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(3105) + "] = _illmask | zimm;\n"; +if (rd != 0) { +partInit.code() += "*((RISCV*)cpu)->X[" + std::to_string(rd) + "] = _vl;\n"; +} +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getRegisterDependencies().add(reg_name[rs2], 32); + partInit.getRegisterDependencies().add(reg_name[rs1], 32); + partInit.getAffectedRegisters().add(reg_name[rd], 32); + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 rs2 = 0; +static BitArrayRange R_rs2_0(24, 20); +rs2 += R_rs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsetvl" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + + +/* TODO(fabianpedd): The vector load and store instructions VLE.U and VSU.U + * are commented out as they currently cause errors when + * building the ETISS instruction decoder, which in turn lead + * to Segfaults when running ETISS. + */ + +// // VLE.U ----------------------------------------------------------------------- +// static InstructionDefinition vle_u_vd_width_rs1_vm_mew ( +// ISA32_RISCV, +// "vle.u", +// (uint32_t) 0x000007, +// (uint32_t) 0xedf0007f, +// [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) +// { +// +// // ----------------------------------------------------------------------------- +// +// // ----------------------------------------------------------------------------- +// +// // ----------------------------------------------------------------------------- +// etiss_uint32 vd = 0; +// static BitArrayRange R_vd_0(11, 7); +// vd += R_vd_0.read(ba) << 0; +// etiss_uint32 width = 0; +// static BitArrayRange R_width_0(14, 12); +// width += R_width_0.read(ba) << 0; +// etiss_uint32 rs1 = 0; +// static BitArrayRange R_rs1_0(19, 15); +// rs1 += R_rs1_0.read(ba) << 0; +// etiss_uint32 vm = 0; +// static BitArrayRange R_vm_0(25, 25); +// vm += R_vm_0.read(ba) << 0; +// etiss_uint32 mew = 0; +// static BitArrayRange R_mew_0(28, 28); +// mew += R_mew_0.read(ba) << 0; +// +// // ----------------------------------------------------------------------------- +// +// CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); +// +// partInit.code() = std::string("//VLE.U\n"); +// +// // ----------------------------------------------------------------------------- +// partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +// partInit.code() += "etiss_uint32 _eew = vcfg_concatEEW(" + std::to_string(mew) + ", " + std::to_string(width) + ");\n"; +// partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +// partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +// partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +// partInit.code() += "etiss_uint32 ret = etiss_vload_encoded_unitstride(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", _eew, " + std::to_string(vd) + ", _vstart, _vlen, _vl, *((RISCV*)cpu)->X[" + std::to_string(rs1) + "]);\n"; +// partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +// partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +// partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +// partInit.code() += "}\n"; +// partInit.code() += " else {\n"; +// partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +// partInit.code() += "}\n"; +// partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// // ----------------------------------------------------------------------------- +// +// partInit.getRegisterDependencies().add(reg_name[rs1], 32); +// partInit.getAffectedRegisters().add("instructionPointer", 32); +// +// return true; +// }, +// 0, +// [] (BitArray & ba, Instruction & instr) +// { +// // ----------------------------------------------------------------------------- +// etiss_uint32 vd = 0; +// static BitArrayRange R_vd_0(11, 7); +// vd += R_vd_0.read(ba) << 0; +// etiss_uint32 width = 0; +// static BitArrayRange R_width_0(14, 12); +// width += R_width_0.read(ba) << 0; +// etiss_uint32 rs1 = 0; +// static BitArrayRange R_rs1_0(19, 15); +// rs1 += R_rs1_0.read(ba) << 0; +// etiss_uint32 vm = 0; +// static BitArrayRange R_vm_0(25, 25); +// vm += R_vm_0.read(ba) << 0; +// etiss_uint32 mew = 0; +// static BitArrayRange R_mew_0(28, 28); +// mew += R_mew_0.read(ba) << 0; +// +// // ----------------------------------------------------------------------------- +// +// std::stringstream ss; +// // ----------------------------------------------------------------------------- +// ss << "vle.u" << " # " << ba << (" [vd=" + std::to_string(vd) + " | width=" + std::to_string(width) + " | rs1=" + std::to_string(rs1) + " | vm=" + std::to_string(vm) + " | mew=" + std::to_string(mew) + "]"); +// // ----------------------------------------------------------------------------- +// return ss.str(); +// } +// ); +// +// // VSE.U ----------------------------------------------------------------------- +// static InstructionDefinition vse_u_vs3_width_rs1_vm_mew ( +// ISA32_RISCV, +// "vse.u", +// (uint32_t) 0x000027, +// (uint32_t) 0xedf0007f, +// [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) +// { +// +// // ----------------------------------------------------------------------------- +// +// // ----------------------------------------------------------------------------- +// +// // ----------------------------------------------------------------------------- +// etiss_uint32 vs3 = 0; +// static BitArrayRange R_vs3_0(11, 7); +// vs3 += R_vs3_0.read(ba) << 0; +// etiss_uint32 width = 0; +// static BitArrayRange R_width_0(14, 12); +// width += R_width_0.read(ba) << 0; +// etiss_uint32 rs1 = 0; +// static BitArrayRange R_rs1_0(19, 15); +// rs1 += R_rs1_0.read(ba) << 0; +// etiss_uint32 vm = 0; +// static BitArrayRange R_vm_0(25, 25); +// vm += R_vm_0.read(ba) << 0; +// etiss_uint32 mew = 0; +// static BitArrayRange R_mew_0(28, 28); +// mew += R_mew_0.read(ba) << 0; +// +// // ----------------------------------------------------------------------------- +// +// CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); +// +// partInit.code() = std::string("//VSE.U\n"); +// +// // ----------------------------------------------------------------------------- +// partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +// partInit.code() += "etiss_uint32 _eew = vcfg_concatEEW(" + std::to_string(mew) + ", " + std::to_string(width) + ");\n"; +// partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +// partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +// partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +// partInit.code() += "etiss_uint32 ret = etiss_vstore_encoded_unitstride(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", _eew, " + std::to_string(vs3) + ", _vstart, _vlen, _vl, *((RISCV*)cpu)->X[" + std::to_string(rs1) + "]);\n"; +// partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +// partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +// partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +// partInit.code() += "}\n"; +// partInit.code() += " else {\n"; +// partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +// partInit.code() += "}\n"; +// partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// // ----------------------------------------------------------------------------- +// +// partInit.getRegisterDependencies().add(reg_name[rs1], 32); +// partInit.getAffectedRegisters().add("instructionPointer", 32); +// +// return true; +// }, +// 0, +// [] (BitArray & ba, Instruction & instr) +// { +// // ----------------------------------------------------------------------------- +// etiss_uint32 vs3 = 0; +// static BitArrayRange R_vs3_0(11, 7); +// vs3 += R_vs3_0.read(ba) << 0; +// etiss_uint32 width = 0; +// static BitArrayRange R_width_0(14, 12); +// width += R_width_0.read(ba) << 0; +// etiss_uint32 rs1 = 0; +// static BitArrayRange R_rs1_0(19, 15); +// rs1 += R_rs1_0.read(ba) << 0; +// etiss_uint32 vm = 0; +// static BitArrayRange R_vm_0(25, 25); +// vm += R_vm_0.read(ba) << 0; +// etiss_uint32 mew = 0; +// static BitArrayRange R_mew_0(28, 28); +// mew += R_mew_0.read(ba) << 0; +// +// // ----------------------------------------------------------------------------- +// +// std::stringstream ss; +// // ----------------------------------------------------------------------------- +// ss << "vse.u" << " # " << ba << (" [vs3=" + std::to_string(vs3) + " | width=" + std::to_string(width) + " | rs1=" + std::to_string(rs1) + " | vm=" + std::to_string(vm) + " | mew=" + std::to_string(mew) + "]"); +// // ----------------------------------------------------------------------------- +// return ss.str(); +// } +// ); + +// VADD.VV --------------------------------------------------------------------- +static InstructionDefinition vadd_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vadd.vv", + (uint32_t) 0x000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VADD.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vadd_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vadd.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VADD.VI --------------------------------------------------------------------- +static InstructionDefinition vadd_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vadd.vi", + (uint32_t) 0x003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VADD.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vadd_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vadd.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VADD.VX --------------------------------------------------------------------- +static InstructionDefinition vadd_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vadd.vx", + (uint32_t) 0x004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VADD.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vadd_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vadd.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSUB.VV --------------------------------------------------------------------- +static InstructionDefinition vsub_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vsub.vv", + (uint32_t) 0x8000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSUB.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsub_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsub.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSUB.VX --------------------------------------------------------------------- +static InstructionDefinition vsub_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vsub.vx", + (uint32_t) 0x8004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSUB.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsub_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsub.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADDU.VV ------------------------------------------------------------------- +static InstructionDefinition vwaddu_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwaddu.vv", + (uint32_t) 0xc0000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADDU.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwaddu_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwaddu.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADDU.VX ------------------------------------------------------------------- +static InstructionDefinition vwaddu_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwaddu.vx", + (uint32_t) 0xc0004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADDU.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwaddu_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwaddu.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADD.VV -------------------------------------------------------------------- +static InstructionDefinition vwadd_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwadd.vv", + (uint32_t) 0xc4000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADD.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwadd_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwadd.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADD.VX -------------------------------------------------------------------- +static InstructionDefinition vwadd_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwadd.vx", + (uint32_t) 0xc4004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADD.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwadd_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwadd.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUBU.VV ------------------------------------------------------------------- +static InstructionDefinition vwsubu_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwsubu.vv", + (uint32_t) 0xc8000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUBU.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsubu_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsubu.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUBU.VX ------------------------------------------------------------------- +static InstructionDefinition vwsubu_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwsubu.vx", + (uint32_t) 0xc8004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUBU.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsubu_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsubu.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUB.VV -------------------------------------------------------------------- +static InstructionDefinition vwsub_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwsub.vv", + (uint32_t) 0xcc000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUB.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsub_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsub.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUB.VX -------------------------------------------------------------------- +static InstructionDefinition vwsub_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwsub.vx", + (uint32_t) 0xcc004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUB.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsub_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsub.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADDU.W.VV ----------------------------------------------------------------- +static InstructionDefinition vwaddu_w_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwaddu.w.vv", + (uint32_t) 0xd0000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADDU.W.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwaddu_w_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwaddu.w.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADDU.W.VX ----------------------------------------------------------------- +static InstructionDefinition vwaddu_w_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwaddu.w.vx", + (uint32_t) 0xd0004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADDU.W.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwaddu_w_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwaddu.w.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADD.W.VV ------------------------------------------------------------------ +static InstructionDefinition vwadd_w_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwadd.w.vv", + (uint32_t) 0xd4000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADD.W.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwadd_w_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwadd.w.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWADD.W.VX ------------------------------------------------------------------ +static InstructionDefinition vwadd_w_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwadd.w.vx", + (uint32_t) 0xd4004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWADD.W.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwadd_w_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwadd.w.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUBU.W.VV ----------------------------------------------------------------- +static InstructionDefinition vwsubu_w_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwsubu.w.vv", + (uint32_t) 0xd8000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUBU.W.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsubu_w_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsubu.w.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUBU.W.VX ----------------------------------------------------------------- +static InstructionDefinition vwsubu_w_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwsubu.w.vx", + (uint32_t) 0xd8004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUBU.W.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsubu_w_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsubu.w.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUB.W.VV ------------------------------------------------------------------ +static InstructionDefinition vwsub_w_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vwsub.w.vv", + (uint32_t) 0xdc000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUB.W.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsub_w_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsub.w.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VWSUB.W.VX ------------------------------------------------------------------ +static InstructionDefinition vwsub_w_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vwsub.w.vx", + (uint32_t) 0xdc004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VWSUB.W.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vwsub_w_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vwsub.w.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VAND.VV --------------------------------------------------------------------- +static InstructionDefinition vand_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vand.vv", + (uint32_t) 0x24000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VAND.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vand_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vand.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VAND.VI --------------------------------------------------------------------- +static InstructionDefinition vand_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vand.vi", + (uint32_t) 0x24003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VAND.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vand_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vand.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VAND.VX --------------------------------------------------------------------- +static InstructionDefinition vand_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vand.vx", + (uint32_t) 0x24004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VAND.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vand_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vand.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VOR.VV ---------------------------------------------------------------------- +static InstructionDefinition vor_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vor.vv", + (uint32_t) 0x28000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VOR.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vor_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vor.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VOR.VI ---------------------------------------------------------------------- +static InstructionDefinition vor_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vor.vi", + (uint32_t) 0x28003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VOR.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vor_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vor.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VOR.VX ---------------------------------------------------------------------- +static InstructionDefinition vor_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vor.vx", + (uint32_t) 0x28004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VOR.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vor_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vor.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VXOR.VV --------------------------------------------------------------------- +static InstructionDefinition vxor_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vxor.vv", + (uint32_t) 0x2c000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VXOR.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vxor_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vxor.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VXOR.VI --------------------------------------------------------------------- +static InstructionDefinition vxor_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vxor.vi", + (uint32_t) 0x2c003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VXOR.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vxor_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vxor.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VXOR.VX --------------------------------------------------------------------- +static InstructionDefinition vxor_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vxor.vx", + (uint32_t) 0x2c004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VXOR.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vxor_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vxor.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLL.VV --------------------------------------------------------------------- +static InstructionDefinition vsll_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vsll.vv", + (uint32_t) 0x94000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLL.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsll_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsll.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLL.VI --------------------------------------------------------------------- +static InstructionDefinition vsll_vi_vd_uimm5_vs2_vm ( + ISA32_RISCV, + "vsll.vi", + (uint32_t) 0x94003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLL.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsll_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(uimm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsll.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | uimm5=" + std::to_string(uimm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLL.VX --------------------------------------------------------------------- +static InstructionDefinition vsll_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vsll.vx", + (uint32_t) 0x94004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLL.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsll_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsll.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSRL.VV --------------------------------------------------------------------- +static InstructionDefinition vsrl_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vsrl.vv", + (uint32_t) 0xa0000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSRL.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsrl_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsrl.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSRL.VI --------------------------------------------------------------------- +static InstructionDefinition vsrl_vi_vd_uimm5_vs2_vm ( + ISA32_RISCV, + "vsrl.vi", + (uint32_t) 0xa0003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSRL.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsrl_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(uimm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsrl.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | uimm5=" + std::to_string(uimm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSRL.VX --------------------------------------------------------------------- +static InstructionDefinition vsrl_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vsrl.vx", + (uint32_t) 0xa0004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSRL.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsrl_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsrl.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSRA.VV --------------------------------------------------------------------- +static InstructionDefinition vsra_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vsra.vv", + (uint32_t) 0xa4000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSRA.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsra_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsra.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSRA.VI --------------------------------------------------------------------- +static InstructionDefinition vsra_vi_vd_uimm5_vs2_vm ( + ISA32_RISCV, + "vsra.vi", + (uint32_t) 0xa4003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSRA.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsra_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(uimm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsra.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | uimm5=" + std::to_string(uimm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSRA.VX --------------------------------------------------------------------- +static InstructionDefinition vsra_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vsra.vx", + (uint32_t) 0xa4004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSRA.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vsra_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vsra.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSEQ.VV -------------------------------------------------------------------- +static InstructionDefinition vmseq_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmseq.vv", + (uint32_t) 0x60000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSEQ.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmseq_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmseq.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSNE.VI -------------------------------------------------------------------- +static InstructionDefinition vmsne_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vmsne.vi", + (uint32_t) 0x64003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSNE.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsne_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsne.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSEQ.VX -------------------------------------------------------------------- +static InstructionDefinition vmseq_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmseq.vx", + (uint32_t) 0x60004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSEQ.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmseq_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmseq.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSNE.VV -------------------------------------------------------------------- +static InstructionDefinition vmsne_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmsne.vv", + (uint32_t) 0x64000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSNE.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsne_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsne.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSNE.VX -------------------------------------------------------------------- +static InstructionDefinition vmsne_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmsne.vx", + (uint32_t) 0x64004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSNE.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsne_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsne.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLTU.VV ------------------------------------------------------------------- +static InstructionDefinition vmsltu_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmsltu.vv", + (uint32_t) 0x68000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLTU.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsltu_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsltu.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLTU.VX ------------------------------------------------------------------- +static InstructionDefinition vmsltu_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmsltu.vx", + (uint32_t) 0x68004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLTU.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsltu_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsltu.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLT.VV -------------------------------------------------------------------- +static InstructionDefinition vmslt_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmslt.vv", + (uint32_t) 0x6c000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLT.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmslt_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmslt.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLT.VX -------------------------------------------------------------------- +static InstructionDefinition vmslt_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmslt.vx", + (uint32_t) 0x6c004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLT.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmslt_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmslt.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLEU.VV ------------------------------------------------------------------- +static InstructionDefinition vmsleu_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmsleu.vv", + (uint32_t) 0x70000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLEU.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsleu_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsleu.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLEU.VI ------------------------------------------------------------------- +static InstructionDefinition vmsleu_vi_vd_uimm5_vs2_vm ( + ISA32_RISCV, + "vmsleu.vi", + (uint32_t) 0x70003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLEU.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsleu_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(uimm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 uimm5 = 0; +static BitArrayRange R_uimm5_0(19, 15); +uimm5 += R_uimm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsleu.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | uimm5=" + std::to_string(uimm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLEU.VX ------------------------------------------------------------------- +static InstructionDefinition vmsleu_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmsleu.vx", + (uint32_t) 0x70004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLEU.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsleu_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsleu.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLE.VV -------------------------------------------------------------------- +static InstructionDefinition vmsle_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmsle.vv", + (uint32_t) 0x74000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLE.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsle_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsle.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLE.VI -------------------------------------------------------------------- +static InstructionDefinition vmsle_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vmsle.vi", + (uint32_t) 0x74003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLE.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsle_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsle.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSLE.VX -------------------------------------------------------------------- +static InstructionDefinition vmsle_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmsle.vx", + (uint32_t) 0x74004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSLE.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsle_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsle.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSGTU.VV ------------------------------------------------------------------- +static InstructionDefinition vmsgtu_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmsgtu.vv", + (uint32_t) 0x78000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSGTU.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsgtu_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsgtu.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSGTU.VX ------------------------------------------------------------------- +static InstructionDefinition vmsgtu_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmsgtu.vx", + (uint32_t) 0x78004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSGTU.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsgtu_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsgtu.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSGT.VV -------------------------------------------------------------------- +static InstructionDefinition vmsgt_vv_vd_vs1_vs2_vm ( + ISA32_RISCV, + "vmsgt.vv", + (uint32_t) 0x7c000057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSGT.VV\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsgt_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs1) + ", " + std::to_string(vs2) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsgt.vv" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMSGT.VX -------------------------------------------------------------------- +static InstructionDefinition vmsgt_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vmsgt.vx", + (uint32_t) 0x7c004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMSGT.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmsgt_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmsgt.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMV.V.V --------------------------------------------------------------------- +static InstructionDefinition vmv_v_v_vd_vs1 ( + ISA32_RISCV, + "vmv.v.v", + (uint32_t) 0x5e000057, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMV.V.V\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmv_vv(((RISCV*)cpu)->V, _vtype, " + std::to_string(vd) + ", " + std::to_string(vs1) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 vs1 = 0; +static BitArrayRange R_vs1_0(19, 15); +vs1 += R_vs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmv.v.v" << " # " << ba << (" [vd=" + std::to_string(vd) + " | vs1=" + std::to_string(vs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMV.V.I --------------------------------------------------------------------- +static InstructionDefinition vmv_v_i_vd_simm5 ( + ISA32_RISCV, + "vmv.v.i", + (uint32_t) 0x5e003057, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMV.V.I\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmv_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vd) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmv.v.i" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMV.V.X --------------------------------------------------------------------- +static InstructionDefinition vmv_v_x_vd_rs1 ( + ISA32_RISCV, + "vmv.v.x", + (uint32_t) 0x5e004057, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMV.V.X\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmv_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vd) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmv.v.x" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMV.X.S --------------------------------------------------------------------- +static InstructionDefinition vmv_x_s_rd_vs2 ( + ISA32_RISCV, + "vmv.x.s", + (uint32_t) 0x42004057, + (uint32_t) 0xfe0ff07f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMV.X.S\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +if (rd != 0) { +partInit.code() += "etiss_uint32 ret = vmv_xs(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(rd) + ", " + std::to_string(vs2) + ", _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +} +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 rd = 0; +static BitArrayRange R_rd_0(11, 7); +rd += R_rd_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmv.x.s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | vs2=" + std::to_string(vs2) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VMV.S.X --------------------------------------------------------------------- +static InstructionDefinition vmv_s_x_vd_rs1 ( + ISA32_RISCV, + "vmv.s.x", + (uint32_t) 0x42004057, + (uint32_t) 0xfff0707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VMV.S.X\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vmv_sx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vd) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vmv.s.x" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLIDEUP.VI ----------------------------------------------------------------- +static InstructionDefinition vslideup_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vslideup.vi", + (uint32_t) 0x38003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLIDEUP.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vslideup_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vslideup.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLIDEUP.VX ----------------------------------------------------------------- +static InstructionDefinition vslideup_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vslideup.vx", + (uint32_t) 0x38004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLIDEUP.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vslideup_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vslideup.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLIDEDOWN.VI --------------------------------------------------------------- +static InstructionDefinition vslidedown_vi_vd_simm5_vs2_vm ( + ISA32_RISCV, + "vslidedown.vi", + (uint32_t) 0x3c003057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLIDEDOWN.VI\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vslidedown_vi(((RISCV*)cpu)->V, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(simm5) + ", _vstart, _vlen, _vl);\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 simm5 = 0; +static BitArrayRange R_simm5_0(19, 15); +simm5 += R_simm5_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vslidedown.vi" << " # " << ba << (" [vd=" + std::to_string(vd) + " | simm5=" + std::to_string(simm5) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLIDEDOWN.VX --------------------------------------------------------------- +static InstructionDefinition vslidedown_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vslidedown.vx", + (uint32_t) 0x3c004057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLIDEDOWN.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vslidedown_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vslidedown.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLIDE1UP.VX ---------------------------------------------------------------- +static InstructionDefinition vslide1up_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vslide1up.vx", + (uint32_t) 0x38006057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLIDE1UP.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vslide1up_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vslide1up.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); + +// VSLIDE1DOWN.VX -------------------------------------------------------------- +static InstructionDefinition vslide1down_vx_vd_rs1_vs2_vm ( + ISA32_RISCV, + "vslide1down.vx", + (uint32_t) 0x3c006057, + (uint32_t) 0xfc00707f, + [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic) + { + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- + +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + CodePart & partInit = cs.append(CodePart::INITIALREQUIRED); + + partInit.code() = std::string("//VSLIDE1DOWN.VX\n"); + +// ----------------------------------------------------------------------------- +partInit.code() += "etiss_uint32 _vtype = ((RISCV*)cpu)->CSR[" + std::to_string(3105) + "];\n"; +partInit.code() += "etiss_uint32 _vstart = ((RISCV*)cpu)->CSR[" + std::to_string(8) + "];\n"; +partInit.code() += "etiss_uint32 _vl = ((RISCV*)cpu)->CSR[" + std::to_string(3104) + "];\n"; +partInit.code() += "etiss_uint32 _vlen = ((RISCV*)cpu)->CSR[" + std::to_string(3106) + "] * " + std::to_string(8) + ";\n"; +partInit.code() += "etiss_uint32 ret = vslide1down_vx(((RISCV*)cpu)->V, *((RISCV*)cpu)->X, _vtype, " + std::to_string(vm) + ", " + std::to_string(vd) + ", " + std::to_string(vs2) + ", " + std::to_string(rs1) + ", _vstart, _vlen, _vl, " + std::to_string(32) + ");\n"; +partInit.code() += "if (ret != " + std::to_string(0) + ") {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = (ret) >> (" + std::to_string(8) + ");\n"; +partInit.code() += "return ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n"; +partInit.code() += "}\n"; +partInit.code() += " else {\n"; +partInit.code() += "((RISCV*)cpu)->CSR[" + std::to_string(8) + "] = " + std::to_string(0) + ";\n"; +partInit.code() += "}\n"; +partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 4) + ";\n"; +// ----------------------------------------------------------------------------- + + partInit.getAffectedRegisters().add("instructionPointer", 32); + + return true; + }, + 0, + [] (BitArray & ba, Instruction & instr) + { +// ----------------------------------------------------------------------------- +etiss_uint32 vd = 0; +static BitArrayRange R_vd_0(11, 7); +vd += R_vd_0.read(ba) << 0; +etiss_uint32 rs1 = 0; +static BitArrayRange R_rs1_0(19, 15); +rs1 += R_rs1_0.read(ba) << 0; +etiss_uint32 vs2 = 0; +static BitArrayRange R_vs2_0(24, 20); +vs2 += R_vs2_0.read(ba) << 0; +etiss_uint32 vm = 0; +static BitArrayRange R_vm_0(25, 25); +vm += R_vm_0.read(ba) << 0; + +// ----------------------------------------------------------------------------- + + std::stringstream ss; +// ----------------------------------------------------------------------------- +ss << "vslide1down.vx" << " # " << ba << (" [vd=" + std::to_string(vd) + " | rs1=" + std::to_string(rs1) + " | vs2=" + std::to_string(vs2) + " | vm=" + std::to_string(vm) + "]"); +// ----------------------------------------------------------------------------- + return ss.str(); + } +); diff --git a/ArchImpl/RISCV/RISCVArchSpecificImp.h b/ArchImpl/RISCV/RISCVArchSpecificImp.h index 00b0c4a23f..34aa75fbf0 100755 --- a/ArchImpl/RISCV/RISCVArchSpecificImp.h +++ b/ArchImpl/RISCV/RISCVArchSpecificImp.h @@ -362,10 +362,12 @@ void RISCVArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const /* Set default JIT Extensions. Read Parameters set from ETISS configuration and append with architecturally needed */ std::string cfgPar = ""; cfgPar = etiss::cfg().get("jit.external_headers", ";"); - etiss::cfg().set("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h"); + etiss::cfg().set("jit.external_headers", cfgPar + "etiss/jit/libsoftfloat.h;" + + "etiss/jit/libsoftvector.h"); cfgPar = etiss::cfg().get("jit.external_libs", ";"); - etiss::cfg().set("jit.external_libs", cfgPar + "softfloat"); + etiss::cfg().set("jit.external_libs", cfgPar + "softfloat;" + + "softvector"); cfgPar = etiss::cfg().get("jit.external_header_paths", ";"); etiss::cfg().set("jit.external_header_paths", cfgPar + "/etiss/jit"); From ba7f973c6afd866b67d90c2f588ce84306060e52 Mon Sep 17 00:00:00 2001 From: Fabian Peddinghaus Date: Wed, 15 Sep 2021 03:33:51 +0200 Subject: [PATCH 2/3] add softvector jitlib support --- src/jitlibs/CMakeLists.txt | 1 + src/jitlibs/softvector/CMakeLists.txt | 43 ++++ src/jitlibs/softvector/etiss_softvector.cpp | 260 ++++++++++++++++++++ src/jitlibs/softvector/libsoftvector.h | 121 +++++++++ 4 files changed, 425 insertions(+) create mode 100644 src/jitlibs/softvector/CMakeLists.txt create mode 100644 src/jitlibs/softvector/etiss_softvector.cpp create mode 100644 src/jitlibs/softvector/libsoftvector.h diff --git a/src/jitlibs/CMakeLists.txt b/src/jitlibs/CMakeLists.txt index b43b88d46d..dbe5667001 100644 --- a/src/jitlibs/CMakeLists.txt +++ b/src/jitlibs/CMakeLists.txt @@ -4,3 +4,4 @@ ENDMACRO() ADD_SUBDIRECTORY(softfloat) ADD_SUBDIRECTORY(resources) +ADD_SUBDIRECTORY(softvector) diff --git a/src/jitlibs/softvector/CMakeLists.txt b/src/jitlibs/softvector/CMakeLists.txt new file mode 100644 index 0000000000..06fe39f3e6 --- /dev/null +++ b/src/jitlibs/softvector/CMakeLists.txt @@ -0,0 +1,43 @@ +SET(ETISS_PREFIX ${PROJECT_SOURCE_DIR}) + +PROJECT(etiss_softvector) + +SET(TARGET_PLATFORM_NAME "riscv") + +include(FetchContent) +FetchContent_Declare(softvector_srcs + GIT_REPOSITORY https://github.com/tum-ei-eda/softvector.git + GIT_TAG master +) + +if(NOT softvector_srcs_POPULATED) + FetchContent_Populate(softvector_srcs) + FetchContent_GetProperties(softvector_srcs) + set(EXTERNAL_INSTALL_LOCATION ${softvector_srcs_SOURCE_DIR}) + INSTALL( + FILES ${softvector_srcs_SOURCE_DIR}/include/target/${TARGET_PLATFORM_NAME}/softvector.h + DESTINATION include/jit/etiss/jit) + SET(SOFTVECTOR_BUILD_DOC OFF) +endif() + +ADD_SUBDIRECTORY(${softvector_srcs_SOURCE_DIR} ${softvector_srcs_BINARY_DIR}) + +##################### SOFTVECTOR JIT LIBRARY ##################### + +ADD_LIBRARY(${PROJECT_NAME} SHARED + etiss_softvector.cpp +) + +TARGET_INCLUDE_DIRECTORIES(${PROJECT_NAME} PRIVATE + ${ETISS_PREFIX}/include_c + ${softvector_srcs_SOURCE_DIR}/include/target/${TARGET_PLATFORM_NAME} +) + +TARGET_LINK_LIBRARIES(${PROJECT_NAME} INTERFACE softvector) + +INSTALL(FILES + libsoftvector.h + DESTINATION include/jit/etiss/jit +) +InstallJitLib(${PROJECT_NAME}) +InstallJitLib(softvector) diff --git a/src/jitlibs/softvector/etiss_softvector.cpp b/src/jitlibs/softvector/etiss_softvector.cpp new file mode 100644 index 0000000000..d9e31fb8ea --- /dev/null +++ b/src/jitlibs/softvector/etiss_softvector.cpp @@ -0,0 +1,260 @@ +/* + * Copyright [2020] [Technical University of Munich] + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +////////////////////////////////////////////////////////////////////////////////////// +/// \file etiss_softvector.cpp +/// \brief C++ Source for ETISS JIT libary or independent C application. Implements a C interface when compiled to +/// library beforehand \date 11/23/2020 +////////////////////////////////////////////////////////////////////////////////////// + +//#include "softvector.h" +#include "base/base.hpp" +#include "lsu/lsu.hpp" + +#include "etiss/jit/CPU.h" +#include "etiss/jit/System.h" + +#include "libsoftvector.h" +extern "C" +{ + + uint8_t etiss_vload_encoded_unitstride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, + uint16_t pVLEN, uint16_t pVL, uint64_t pMSTART) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * 8) || (_z_emul > _n_emul * 8)) + return 1; + + uint8_t *VectorRegField = pV; + std::function f_readMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dread))(pSystem->handle, pCpu, addr, buff, len); + }; + + VLSU::load_eew(f_readMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, pVd, pMSTART, pVSTART, + pVm, 0); + return (0); + } + + uint8_t etiss_vload_encoded_stride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, uint16_t pVTYPE, + uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, + uint16_t pVL, uint64_t pMSTART, int16_t pSTRIDE) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * 8) || (_z_emul > _n_emul * 8)) + { + return 1; + } + + uint8_t *VectorRegField = pV; + std::function f_readMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dread))(pSystem->handle, pCpu, addr, buff, len); + }; + + VLSU::load_eew(f_readMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, pVd, pMSTART, pVSTART, + pVm, pSTRIDE); + + return (0); + } + + uint8_t etiss_vload_segment_unitstride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, + uint16_t pVSTART, uint16_t pVLEN, uint16_t pVL, uint64_t pMSTART) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * pNF * 8) || (_z_emul * pNF > _n_emul * 8)) + return 1; + if ((pVd + pNF * _z_emul / _n_emul) > 32) + return 1; + if (pVSTART >= pVL) + return (0); + + uint8_t *VectorRegField = pV; + std::function f_readMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dread))(pSystem->handle, pCpu, addr, buff, len); + }; + + uint16_t _vstart = pVSTART; + uint64_t _moffset = pMSTART; + for (int i = 0; i < pNF; ++i) + { + VLSU::load_eew(f_readMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, + pVd + (i * _z_emul / _n_emul), _moffset, _vstart, pVm, 0); + _moffset += (pVL - _vstart) * pEEW / 8; + _vstart = 0; + } + return (0); + } + + uint8_t etiss_vload_segment_stride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, uint16_t pVTYPE, + uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, uint16_t pVSTART, + uint16_t pVLEN, uint16_t pVL, uint64_t pMSTART, int16_t pSTRIDE) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * pNF * 8) || (_z_emul * pNF > _n_emul * 8)) + return 1; + if ((pVd + pNF * _z_emul / _n_emul) > 32) + return 1; + if (pVSTART >= pVL) + return (0); + + uint8_t *VectorRegField = pV; + std::function f_readMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dread))(pSystem->handle, pCpu, addr, buff, len); + }; + + uint16_t _vstart = pVSTART; + uint64_t _moffset = pMSTART; + for (int i = 0; i < pNF; ++i) + { + _moffset = pMSTART + i * pEEW / 8; + VLSU::load_eew(f_readMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, + pVd + (i * _z_emul / _n_emul), _moffset, _vstart, pVm, pSTRIDE); + _vstart = 0; + } + return (0); + } + + uint8_t etiss_vstore_encoded_unitstride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, + uint16_t pVLEN, uint16_t pVL, uint64_t pMSTART) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * 8) || (_z_emul > _n_emul * 8)) + return 1; + + uint8_t *VectorRegField = pV; + std::function f_writeMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dwrite))(pSystem->handle, pCpu, addr, buff, len); + }; + + VLSU::store_eew(f_writeMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, pVd, pMSTART, pVSTART, + pVm, 0); + + return (0); + } + + uint8_t etiss_vstore_encoded_stride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, + uint16_t pVLEN, uint16_t pVL, uint64_t pMSTART, int16_t pStride) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * 8) || (_z_emul > _n_emul * 8)) + return 1; + + uint8_t *VectorRegField = pV; + std::function f_writeMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dwrite))(pSystem->handle, pCpu, addr, buff, len); + }; + + VLSU::store_eew(f_writeMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, pVd, pMSTART, pVSTART, + pVm, pStride); + + return (0); + } + + uint8_t etiss_vstore_segment_unitstride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, + uint16_t pVSTART, uint16_t pVLEN, uint16_t pVL, uint64_t pMSTART) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * pNF * 8) || (_z_emul * pNF > _n_emul * 8)) + return 1; + if ((pVd + pNF * _z_emul / _n_emul) > 32) + return 1; + if (pVSTART >= pVL) + return (0); + + uint8_t *VectorRegField = pV; + std::function f_writeMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dwrite))(pSystem->handle, pCpu, addr, buff, len); + }; + + uint16_t _vstart = pVSTART; + uint64_t _moffset = pMSTART; + for (int i = 0; i < pNF; ++i) + { + VLSU::store_eew(f_writeMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, + pVd + (i * _z_emul / _n_emul), _moffset, _vstart, pVm, 0); + _moffset += (pVL - _vstart) * pEEW / 8; + _vstart = 0; + } + return (0); + } + + uint8_t etiss_vstore_segment_stride(ETISS_CPU *const pCpu, ETISS_System *const pSystem, uint8_t *pV, + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, + uint16_t pVSTART, uint16_t pVLEN, uint16_t pVL, uint64_t pMSTART, + int16_t pStride) + { + VTYPE::VTYPE _vt(pVTYPE); + uint64_t _z_emul = pEEW * _vt._z_lmul; + uint64_t _n_emul = _vt._sew * _vt._n_lmul; + + if ((_n_emul > _z_emul * pNF * 8) || (_z_emul * pNF > _n_emul * 8)) + return 1; + if ((pVd + pNF * _z_emul / _n_emul) > 32) + return 1; + if (pVSTART >= pVL) + return (0); + + uint8_t *VectorRegField = pV; + std::function f_writeMem = [pSystem, pCpu](size_t addr, uint8_t *buff, + size_t len) { + (*(pSystem->dwrite))(pSystem->handle, pCpu, addr, buff, len); + }; + + uint16_t _vstart = pVSTART; + uint64_t _moffset = pMSTART; + for (int i = 0; i < pNF; ++i) + { + _moffset = pMSTART + i * pEEW / 8; + VLSU::store_eew(f_writeMem, VectorRegField, _z_emul, _n_emul, pEEW / 8, pVL, pVLEN / 8, + pVd + (i * _z_emul / _n_emul), _moffset, _vstart, pVm, 0); + _moffset += (pVL - _vstart) * pEEW / 8; + _vstart = 0; + } + return (0); + } + +} // extern "C" diff --git a/src/jitlibs/softvector/libsoftvector.h b/src/jitlibs/softvector/libsoftvector.h new file mode 100644 index 0000000000..b0fdf12803 --- /dev/null +++ b/src/jitlibs/softvector/libsoftvector.h @@ -0,0 +1,121 @@ +/* + * Copyright [2020] [Technical University of Munich] + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +////////////////////////////////////////////////////////////////////////////////////// +/// \file libsoftvector.h +/// \brief C/C++ Header for ETISS JIT libary or independent C application +/// \date 11/23/2020 +////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __ETISS_SOFTVECTOR_H__ +#define __ETISS_SOFTVECTOR_H__ + +#include "stdint.h" +#include "softvector.h" + +struct ETISS_System; +struct ETISS_CPU; + +#ifdef __cplusplus +extern "C" +{ +#endif + + /* Vector Loads/Stores Helpers*/ + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Load encoded (unitstride) from memory to target vector (-group) + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vload_encoded_unitstride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, uint16_t pVL, + uint64_t pMSTART); + + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Load encoded (strided) from memory to target vector (-group) + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vload_encoded_stride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, uint16_t pVL, + uint64_t pMSTART, int16_t pSTRIDE); + + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Load seqgmented (unitstride) from memory to target vector (-group) + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vload_segment_unitstride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, + uint16_t pVL, uint64_t pMSTART); + + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Load encoded (strided) from memory to target vector (-group) + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vload_segment_stride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, + uint16_t pVL, uint64_t pMSTART, int16_t pSTRIDE); + + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Store encoded (unitstride) source vector (-group) to memory + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vstore_encoded_unitstride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, uint16_t pVL, + uint64_t pMSTART); + + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Store encoded (strided) source vector (-group) to memory + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vstore_encoded_stride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, uint16_t pVL, + uint64_t pMSTART, int16_t pStride); + + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Store segmented (unitstride) source vector (-group) to memory + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vstore_segment_unitstride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, + uint16_t pVL, uint64_t pMSTART); + + ////////////////////////////////////////////////////////////////////////////////////// + /// \brief Store segmented (strided) source vector (-group) to memory + /// \return 0 if no exception triggered, else 1 + uint8_t etiss_vstore_segment_stride( + ETISS_CPU *const pCpu, //!<[inout] Pointer to ETISS_CPU structure. Supports Vector register field + ETISS_System *const pSystem, //!<[inout] Pointer to ETISS_System structure. Supports databus/memory acesses + uint8_t *pV, //!<[inout] Vector register field as local memory + uint16_t pVTYPE, uint8_t pVm, uint16_t pEEW, uint8_t pNF, uint8_t pVd, uint16_t pVSTART, uint16_t pVLEN, + uint16_t pVL, uint64_t pMSTART, int16_t pStride); + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif /* __ETISS_SOFTVECTOR_H__ */ From ca9613be39453abd32ddec679eaf1d04fab317a7 Mon Sep 17 00:00:00 2001 From: Fabian Peddinghaus Date: Fri, 17 Sep 2021 00:35:12 +0200 Subject: [PATCH 3/3] Link softvector as public Make softvector part of etiss_softvector's link interface --- src/jitlibs/softvector/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/jitlibs/softvector/CMakeLists.txt b/src/jitlibs/softvector/CMakeLists.txt index 06fe39f3e6..7bc18b15f9 100644 --- a/src/jitlibs/softvector/CMakeLists.txt +++ b/src/jitlibs/softvector/CMakeLists.txt @@ -33,7 +33,7 @@ TARGET_INCLUDE_DIRECTORIES(${PROJECT_NAME} PRIVATE ${softvector_srcs_SOURCE_DIR}/include/target/${TARGET_PLATFORM_NAME} ) -TARGET_LINK_LIBRARIES(${PROJECT_NAME} INTERFACE softvector) +TARGET_LINK_LIBRARIES(${PROJECT_NAME} PUBLIC softvector) INSTALL(FILES libsoftvector.h