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Implement rdcycle, rdtime, and rdinstret #105

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fpedd opened this issue Jan 31, 2022 · 2 comments
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Implement rdcycle, rdtime, and rdinstret #105

fpedd opened this issue Jan 31, 2022 · 2 comments
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@wysiwyng

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@fpedd
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fpedd commented Jan 31, 2022

Would be nice if ETISS supported these (OVPsim and Spike offer them). Currently reading them returns 0.

See RISC-V User-Level ISA V2.2, 2.8 Control and Status Register Instructions, Timers and Counters for more info. They can then in turn be used to, for example, run performance tests on TensorFlow Lite Micro.
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@Samanti-Das and me will have a go at implementing this, stay tuned.

@wysiwyng wysiwyng self-assigned this Feb 17, 2022
@fpedd fpedd mentioned this issue Jun 21, 2022
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Implemeted in #115. rdtime currently returns microseconds since Unix epoch, rdcycle and rdinstret return instruction count since simulator start.

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