ETISS.ini

;############################### Configurations ################################
; All configurations can be overwritten with program arguments (Section names
; are not necessary):
;
; ./main [-o<option> <value>] [-f[no]<flag>]
;
; Bool configurations can be set with -f. The optional no sets the flag to
; false. The default value is true. All other configurations can be set with -o.


; In this section all available configurations in ETISS of type string can be
; set.
[StringConfigurations]

  ; Working directory. Used by TCCJIT, CPUArch, addLibrary
  ; It will be set to const in the etiss::Initialiser, cause it must not
  ; change while runtime.
  ; default=

  ;etiss_wd=

  ; The binary file for the target software of the simulation. Example software
  ; exists under the folder SW, but it must be compiled first.
  ; ATTENTION: If you change the CPU Architectur you have to change the
  ;            software, too!
  ;
  ; ARMv6M: ../SW/arm/build/code.bin
  ; RISCV : ../SW/riscv/build/code.bin
  ; default (or1k)=../SW/or1k/build/code.bin
  vp.sw_binary_rom=../SW/riscv/build/riscv_example.rom
  vp.sw_binary_ram=../SW/riscv/build/riscv_example.ram

  ; Select architectur type of the CPU.
  ; Currently available:
  ; - or1k
  ; - ARMv6M
  ; - RISCV
  ; - RISCV64
  ; ATTENTION: If you change the CPU Architectur you have to change the
  ;            software, too!

  arch.cpu=RISCV

  ; Select a jit manually.
  ; Available are:
  ; - GCCJIT
  ; - LLVMJIT
  ; - TCCJIT
  ; default=GCCJIT

  jit.type=TCCJIT


; In this section all available configurations in ETISS of type bool can be set.
[BoolConfigurations]

  ; When instantiating an OR1K CPUArchitecure, it can be configured to  ignore
  ; the IEE flag of the SR register.
  ; default = false

  arch.or1k.ignore_sr_iee=false

  ; When destructing the GCC JIT it can clean up the created files.
  ; dafault = true

  jit.gcc.cleanup=true

  ; Enable test for JIT compability to ETISS
  ; default = true

  jit.verify=false

  ; Load integrated Libraries
  ; Available for
  ; default = true

  etiss.load_integrated_libraries=true

  ;Causes the JIT Engines to compile in debug mode
  ; default = false

  jit.debug=true

  ; Print Debug outputs to std::cout for Bus accesses on the Debug System
  ; default=false

	simple_mem_system.print_ibus_access=false
	simple_mem_system.print_dbus_access=false
	simple_mem_system.print_dbgbus_access=false


; In this section all available configurations in ETISS of type int can be set.
[IntConfigurations]

  ; The log levels determine the produeced output. The following are
  ; implemented:
  ;   0 = etiss::SILENT
  ;   1 = etiss::FATALERROR
  ;   2 = etiss::ERROR
  ;   3 = etiss::WARNING
  ;   4 = etiss::INFO
  ;   5 = etiss::VERBOSE

  etiss.loglevel=2

  ; For simulating cache or bus delay additional cycles before an instruction
  ; can be added. arch.or1k.if_stall_cycles defines the number of cycles.
  ; default = 0

  arch.or1k.if_stall_cycles=0

  ; Set max size for a basic block.
  ; This parameter defines how much instructions can maximally put together in
  ; one file for the just in time compiler.
  ; ATTENTION: Coroutines will only called after a basic block has finished.
  ;            Thus any synchronisation of the coroutines will only be done
  ;            thereafter. So in some cases e.g. Interupts will evaluated not
  ;            before a block ends.

  etiss.max_block_size=100

  ; Set CPU freuquency in pico seconds
  ; (or1k)   default=10000
  ; (RISCV)  default=31250

  arch.cpu_cycle_time_ps=31250

  ; Set the memory configuration of bare_etiss_processor
  ; Up to 99 segments are supported
  ; ELF sections are automatically mapped to these memory slices. If no matching
  ; slice can be found for an ELF section, a new one is allocated using origin and
  ; size information from the ELF headers. This can lead to problems when e.g. the
  ; SRAM section of the ELF file does not take the stack into account.

  simple_mem_system.memseg_origin_00=0x00000000
  simple_mem_system.memseg_length_00=0x00080000

  simple_mem_system.memseg_origin_01=0x00080000
  simple_mem_system.memseg_length_01=0x00080000


;############################# INTEGRATED PLUGINS ##############################

; a plugin that print the instruction and its address when
; it is executed
;[Plugin PrintInstruction]




; adds a gdb debug server (connect with "target remote localhost:2222")
; minPcAlign: PC LSBs aligment. E.g. 1 for 16 bits instuction, 2 for 32 bits, 3 for 64 bits
;[Plugin gdbserver]
;  plugin.gdbserver.port=2222
;  minPcAlign=1



; adds a Logger Plugin
; NOTE: the logger plugin is of the type etiss::SystemWrapperPlugin and will
; wrap the passed system before it is used by the cpu to be able to redirect
; reads/writes for the logging address range.
[Plugin Logger]
  plugin.logger.logaddr=0x80000000
  plugin.logger.logmask=0xF0000000




; injects errors after an block into registers
;[Plugin BlockAccurateHandler]
;  -rR5=./fail_set_00000
;  -rR6=./fail_set_00000
;  -rR7=./fail_set_00000
;  -rR8=./fail_set_00000
;  -rR10=./fail_set_00000
;  -rR14=./fail_set_00000
;  -rR15=./fail_set_00000
;  -rR16=./fail_set_00000
;  -rR17=./fail_set_00000
;  -rR18=./fail_set_00000
;  -rR19=./fail_set_00000
;  -rR20=./fail_set_00000