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litexOnColorlightLab004

Demonstration on using a Soft Core (VexRiscv) built with LiTex in a Colorlight 5A-75B or Colorlight I5 (ECP5). This demo is based on lab004 of fpga_101 repository.

  • push button is used as reset
  • led is used for led demo in firmware

Colorlight 5A-75B

UART use (arbitrary) J1 pins 1 & 2

name Pin note
clk25 P6 25MHz clock
cpu_reset P11 button J28
user_led P11 button J28
Uart TX F3 J1.1
Uart RX F1 J1.2

Colorlight I5

UART is directly available through CMSIS-DAP ACM interface

name Pin note
clk25 P3 25MHz clock
cpu_reset_n K18 button J28
user_led U16 button J28
Uart TX J17 CMSIS-DAP
Uart RX H18 CMSIS-DAP

Prerequisite

software

hardware (Colorlight 5A-75B only)

  • ColorLight 5A-75B has no on-board JTAG adapter, so user must solder a pinheader (J27 for JTAG signals, J33 for VCC and J34 for GND) and connect an external probe (see. chubby75);
  • level shifter 74HC245T are used between FPGA and Jx connectors. To be able to use corresponding pins in bidirectional mode and in 3.3V instead 5V, buffer must be desoldered, and replace or just bypass. To have, a partial, access to J1, buffer U28 must be dropped (see next figure);
  • an USB <-> serial converter must be used to have access to serial interface

JX direct connection

U28 without buffer and with direct connection between input and output.

Build

gateware

Just:

./base.py --version 5A-75B --build

or

./base.py --version i5 --build

firmware

cd firmware && make [VERSION=5a_75b]

where VERSION may be 5a_75b or i5

see lab004 for more details.

load bitstream

./base.py --version 5A-75B --load [--cable yourCable] # change 5A-75B by I5

where yourCable depends on your JTAG probe. If --cable is not provided openFPGALoader will uses ft2232 generic interface. Not required for I5.

load firmware

litex_term /dev/ttyYYYX --kernel firmware/firmware.bin

where ttyYYYX is your USB <-> UART converter device (usually ttyUSB0 (5A-75B) or ttyACM0 (I5)).

boot

serialboot

test

To start the blink led use command

led