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FPGA_KASPA_GUIDE.txt
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TeamRedMiner FPGA Kaspa Guide
=============================
History:
v1.1 2022-12-23 Updated for new voltage support on TH53/55 and FK33.
v1.0 2022-10-18 Initial Version.
General Overview
================
Starting in version v0.10.5 TeamRedMiner(TRM) has support for mining Kaspa on
currently supported FPGA platforms: C1100, U50C, FK33, TH53, TH55, E300. The
Kaspa algorithm is a compute heavy algorithm and does not use the HBM on these
FPGAs. Due to it being compute heavy it will draw large amounts of core
(vccint) current, and miners should becareful not to exceed their card's power
delivery and cooling capabilities. Please read the section corresponding to
your hardware below and be aware of the limits of your hardware before testing.
For details on how to start the miner, set voltages and clocks, update firmware
on C1100/U50C, etc see FPGA_GUIDE.txt.
Mining Instructions
===================
Kaspa mining can be started with the 'kas' algorithm. Example:
sudo ./teamredminer -a kas -o stratum+tcp://pool.woolypooly.com:3112 -u kaspa:qq0vgkm89v3k2plkw2cv9t8wrhcqhpxeunq5ayu9mwjghdavalfggat2hu8nn -p x --fpga_clk_core=200
It is strongly advised to start with a low core clock of around 200MHz and
slowly ramp up from there to ensure you do not exceed your hardware's power
delivery and cooling capabilities.
Clock/Voltage Tuning
==============
With the release of Kaspa, we have also released a new version of the SC
firmware for the C1100 and U50C to allow setting lower voltages on the cards.
Users will likely want to update the TRM firmware on these cards to achieve
optimal results. For detailed description on how to perform tuning, see the
ethash example in FPGA_GUIDE.txt
Tuning Kaspa is much simpler than ethash since memory is not used. The only two
variables that play an effect are core clock and core voltage (vccint). Miners
will want to start with a low clock and voltage and ramp up clock as necessary
until they see error rates increase. At this point they should either lower the
core clock, or increase the core voltage, until they achieve their desired
performance and efficiency results. For C1100, U50C, and FK33 we recommend
running with the --debug option to get additional information about the
regulator current outputs and to ensure they do not exceed the cards' limits.
Here is a general tuning process that has worked for us:
1) Start with a low core voltage of 600mV and core clock of 300MHz.
2) Run cards for 5mins to ensure there are no errors and that temperatures are
stable. If there are no errors, go to step 3. Otherwise, go to step 4.
3) If you are below 500MHz, increase core clock by 100MHz. If you are at or
above 500MHz, increase core clock by 25MHz. Repeat step 2.
4) If you are seeing errors appearing on some cards you can try to adjust
settings to reduce the errors by either:
a) reduce core clock for those FPGAs by 5MHz
b) increase vccint for those FGPAs by 5mV
If your temperatures are exceeding your targets, reduced core clock and/or
voltage by 5MHz/5mV.
5) Run cards for 5-10 mins and note temperatures and error rates. If error
rates or temperatures exceed your targets, repeat step 4.
NOTE: If you see cards crash with jtag errors, you may want to try setting
--fpga_max_jtag_mhz=10 as lower voltages can cause the jtag logic to
not function correctly at higher jtag clock rates.
Tuning Xilinx Varium C1100
==========================
We strongly recommend using an aftermarket cooling setup on the C1100s before
running Kaspa. The original passive heatsink will not be sufficient for cooling
the card on this algo. The VCCINT regulators on the C1100 are rated to 180A.
With good cooling, we typically see most C1100s capable of running 550-600MHz at
600mV vccint. Typically most cards will work at 575MHz@600mV with a few getting
some errors and need a little extra tuning.
For more efficiency oriented setups, we find that 550Mhz@575mV is a good
compromise where most cards are happy to run at.
Tuning Xilinx U50C or ECU50
===========================
The frequency and voltage characteristics of this card are essentially the same
as the C1100. However, U50C and ECU50 users should keep a close eye on total
board power in order to not pull excessive current over the PCIe edge connector.
See your card's retail info for what the maximum safe power to run is for these
boards. The VCCINT regulators should be rated to 180A.
Tuning SQRL Forest Kitten 33
============================
Unfortunately unmodified FK33s are very limited in their voltage control
capabilities. With the new voltage control support in TRM v0.10.7, vccint
voltage can now be dropped to to 0.733mV for unmodified cards, and down to 600mV
for cards with the resistor modification. See FPGA_FK33_MOD.txt for details on
how to modify FK33s to allow lower voltage settings. Due to the FK33's limited
voltage range and 120A rated vccint regulators, the maximum hashrate and
efficiency will be limited compared to other boards. For stock FK33s, we
recommend setting the lowest possible voltage of 0.733mV and not exceeding
525MHz for core clock, at which point the regulators will roughly be running
just below the full 120A limit.
For FK33s modified to run voltages down to ~600mV, we find that you can run up
to about 700MHz before exceeding the 120A, however you will likely start
seeing errors above roughly 625MHz.
Tuning TUL TH53/TH55
===========================
The TH53/TH55 should be able to supply at least 180A from the vccint regulators.
Starting in version v0.10.7 TRM can now set VCCINT and VCCBRAM voltages on TH53
and TH55 cards, as well as read current board metrics such as regulator output
current and temperatures (printed when using --debug). Since both boards have
the same power delivery and cooling design, but the TH53 has a smaller VU33P
FPGA, the TH53 can push significantly higher clocks than the TH55 while stay
with-in the limits of the power and cooling capabilities. Achieving these
higher clock rates will come at the cost of efficiency.
Tuning Osprey E300
===========================
The Osprey E300 is rather overbuilt with VCCINT regulators rated to 420A. Users
with E300s can safely push higher clocks and should just keep an eye on
temperatures. For high efficiency, we find that most E300s run well at
575MHz@600mV. For vu13p boards we suggest starting tuning at 500MHz@600mV, and
moving clock up as necessary while monitoring temperatures and regulator
currents.
Bittware CVP13
===========================
The Bittware CVP13 is a well built and well cooled card, however the VU13P part
on the card is large and consumes large amounts of current. Users should use
the Bittware supplied tools to configure their CVP13's regulator voltages and
monitor currents, as TRM does not support setting voltages or reading
current/power values from the CVP13. We find that CVP13s typically will run
stabily at around 570MHz at 600mV.
SQRL BCU1525/TUL BTU9P/Osprey ECU200/VCU1525/Alveo U200
===========================
Thes boards are all clones of the original VCU1525 Xilinx dev board that become
one of the first widely used FPGA mining platforms. Owners of these boards will
need to make sure they have a way of setting voltages to be able to run
efficiently with TRM's Kaspa. While these boards are very similar, they vary
significantly in regulator efficiency as well as silicon quality of the FPGAs.
From our early testing, we see that boards can typically run somewhere between
550-625MHz at 650mV. Users will want to keep an eye on total power and voltage
regulator temperatures as TRM does not monitor or report these.
SQRL JC33/JC35 on JCC2L Carrier
===========================
The SQRL JungleCat modules (JCMs) have good power delivery and good cooling when
run in a liquid cooled loop. As of version v0.10.9 TRM can now run JC33 and
JC35 modules on JCC2L carriers using the --fpga_jc_addr option to specify
carrier IP addresses. TRM does not currently have the ability to set voltages
or monitor the regulators on JCMs, thus users will need other tools like the
SQRL bridge to set voltages, and will need to run moderate clocks/voltages to
ensure that there is plenty of margin on the regulators, unless they have an
external method of monitoring them. The JCMs have a design maximum current
handle capability of 240A, though we have not verified how well they run at max
current. Our testing shows that JC33s can safely run up to 850MHz@~750mV,
though this will not be practical due to the large drop in efficiency at higher
voltages. While we have not done thorough testing on the JC35s, we generally
suggest users to not exceed 750MHz core clock as this should result in
approximately 200A of VCCINT current. In general we suggest that users should
monitor temperatures closely, especially when testing new settings. We suggest
not exceeding a core temperature of 60-65C on liquid cooled modules.
SQRL JC13
===========================
We have little experience with the JC13s, so we suggest starting tuning at
400MHz@625mV and slowly increasing clock frequency while monitoring power
usage and temperature.