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Which ice40.pcf is correct pico-ice-sdk/examples/ice_makefile_iverilog/ice40.pcf or pico-ice-sdk/examples/ice_makefile_verilator/ice40.pcf? #56

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develone opened this issue Aug 2, 2024 · 1 comment

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@develone
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develone commented Aug 2, 2024

devel@pi5-70:~/pico-ice/my-new-pico-ice-firmware/ice_makefile_verilator_counter $ make
/usr/local//bin/yosys -q -p "read_verilog -sv ice40.sv top.sv; synth_ice40 -top ice40 -json gateware.json"
Warning: Resizing cell port ice40.top0.rst_ni from 32 bits to 1 bits.
/usr/local//bin/nextpnr-ice40 -q --randomize-seed --up5k --package sg48 --pcf ice40.pcf --json gateware.json --asc gateware.asc
ERROR: package does not have a pin named '30' (on line 2)
ERROR: Loading PCF failed.
0 warnings, 2 errors
make: *** [Makefile:24: gateware.bin] Error 255

devel@pi5-70:~/pico-ice/my-new-pico-ice-firmware/ice_makefile_verilator_counter $ diff ice40.pcf ~/pico-ice-sdk/examples/ice_makefile_verilator_counter/ice40.pcf
2c2
< set_io --warn-no-port led_green 39

set_io --warn-no-port led_green 30
This is after the change.
devel@pi5-70:~/pico-ice/my-new-pico-ice-firmware/ice_makefile_verilator_counter $ make
/usr/local//bin/yosys -q -p "read_verilog -sv ice40.sv top.sv; synth_ice40 -top ice40 -json gateware.json"
Warning: Resizing cell port ice40.top0.rst_ni from 32 bits to 1 bits.
/usr/local//bin/nextpnr-ice40 -q --randomize-seed --up5k --package sg48 --pcf ice40.pcf --json gateware.json --asc gateware.asc
/usr/local//bin/icepack gateware.asc gateware.bin

@josuah
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josuah commented Aug 2, 2024

Good catch, thank you!

You are right, there is a bug in the example.

The iverilog one is right (pin 39).
The verilator one is wrong (pin 30).

There is also this this one which acts as a reference from which to copy-paste.
https://github.com/tinyvision-ai-inc/pico-ice-sdk/blob/main/rtl/pico_ice.pcf

This will be corrected on the next release, and was adjusted on the develop branch.

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