sha_padder_tb.vcd

$date
	Fri Feb  2 01:14:49 2018
$end
$version
	Icarus Verilog
$end
$timescale
	10ps
$end
$scope module sha_padder_tb $end
$var wire 512 ! padded [511:0] $end
$var reg 24 " message [23:0] $end
$scope module uut $end
$var wire 24 # message [23:0] $end
$var wire 512 $ padded [511:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b1100001011000100110001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000 $
b11000010110001001100011 #
b11000010110001001100011 "
b1100001011000100110001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000 !
$end
#500