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swervolf.core
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CAPI=2:
name : ::swervolf:0
filesets:
core:
files:
- rtl/dpram64.v
- rtl/axi_mem_wrapper.v
- rtl/axi_uart_wrapper.v
- rtl/axi_multicon.v
- rtl/swervolf_core.v
file_type : systemVerilogSource
depend :
- "pulp-platform.org::apb_uart_sv"
- "pulp-platform.org::axi2apb"
- "pulp-platform.org::axi_mem_if"
- ">=pulp-platform.org::axi_node:1.1.1-r2"
- ">=chipsalliance.org:cores:SweRV_EH1:1.2"
bfm:
files:
- tb/uart_decoder.v
file_type : verilogSource
tb : {files: [tb/swervolf_core_tb.v : {file_type : systemVerilogSource}]}
verilator_tb: {files: [tb/tb.cpp : {file_type : cppSource}]}
verilator_waiver: {files: [data/verilator_waiver.vlt : {file_type : vlt}]}
nexys_a7_files:
files :
- data/swervolf_nexys.xdc : {file_type : xdc}
- rtl/clk_gen_nexys.v : {file_type : verilogSource}
nexys_a7_nodram:
files :
- rtl/swervolf_nexys.v : {file_type : systemVerilogSource}
nexys_a7_dram:
files :
- data/ips.tcl : {file_type : tclSource}
- rtl/swervolf_nexys_ddr.v : {file_type : systemVerilogSource}
depend : [":swervolf:litedram"]
bootrom:
files :
- sw/zephyr_blinky.vh : {file_type : user, copyto : zephyr_blinky.vh}
- sw/jumptoram.vh : {file_type : user, copyto : jumptoram.vh}
targets:
sim:
default_tool : verilator
filesets :
- core
- "!tool_verilator? (bfm)"
- tb
- bootrom
- "tool_verilator? (verilator_tb)"
- "tool_verilator? (verilator_waiver)"
generate : [intercon, swerv_default_config]
parameters : [SIMPRINT=true, ram_init_file, rom_init_file, signature, timeout, vcd]
tools:
modelsim:
vlog_options :
- -mfcu
- -cuautoname=du
- config/common_defines.vh
- -timescale 1ns/1ns
verilator:
verilator_options : [--trace, -Wno-fatal]
toplevel : swervolf_core_tb
nexys_a7:
default_tool : vivado
filesets :
- bootrom
- core
- nexys_a7_files
- nexys_a7_nodram
generate : [intercon, swerv_default_config]
parameters : [bootrom_file, ram_init_file]
tools:
vivado: {part : xc7a100tcsg324-1}
toplevel : swervolf_nexys_a7
nexys_a7_ddr:
default_tool : vivado
filesets :
- bootrom
- core
- nexys_a7_files
- nexys_a7_dram
generate : [intercon, swerv_default_config]
parameters : [bootrom_file]
tools:
vivado: {part : xc7a100tcsg324-1}
toplevel : swervolf_nexys_a7
generate:
intercon:
generator: axi_intercon_gen
parameters:
masters:
ifu:
id_width : 3
read_only : true
lsu:
id_width : 4
slaves:
rom:
offset : 0x80000000
size : 0x00001000
multicon:
offset : 0x80001000
size : 0x00001000
uart:
offset : 0x80002000
size : 0x00001000
ram:
offset : 0x00000000
size : 0x08000000 #128MiB
swerv_default_config:
generator: swerv_config
position : first
parameters:
args : [-unset=assert_on, -set=reset_vec=0x80000000, -set=fpga_optimize=1]
parameters:
SIMPRINT:
datatype : bool
description : Enable simulation character output
paramtype : vlogdefine
bootrom_file:
datatype: file
description : Verilog hex file to use as boot ROM
paramtype : vlogparam
ram_init_file:
datatype: file
description : Verilog hex file to use as initial on-chip RAM contents
paramtype : "tool_vivado? (vlogparam) !tool_vivado? (plusarg)"
rom_init_file:
datatype: file
description : Verilog hex file to use as initial bootrom RAM contents
paramtype : plusarg
signature:
datatype : file
paramtype : plusarg
timeout:
datatype : int
paramtype : plusarg
vcd:
datatype : bool
description : Dump VCD
paramtype : plusarg