Tracer improvements

[kpgriesser]

This PR is to capture miscellaneous improves to the REV tracer and to communicate odd behaviors to trace users.

Two current observation in testing sign extension for memory loads are

1. The full 64 bit data is not be shown for the load ( implying sign-extensions did not occur)
2. The write for the destination register (t3) is not being shown ( we only see the effect when it is subsequently read )

*I 0x10418:01c7b223 sd t3, 4(a5) 0x3ffffac0<-a5 0xbadbeef1badbeef0<-t3 [0x3ffffac4,8]<-0xbadbeef1badbeef0
*I 0x1041c:0007ae03 lw t3, 0(a5) 0x3ffffac0<-a5 0xbadbeef0<-[0x3ffffac0,4]
*I 0x10420:01de0463 beq t3, t4, pc + 8 0xffffffffbadbeef0<-t3 0xffffffffbadbeef0<-t4 pc<-0x10428 <_okneg>

Note that the REV core functionality is correct but interpreting the trace may be confusing, especially if the LW and the read of the destination register is separate by many cycles.