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Odd segfault at the end of .text section #197

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ukasz opened this issue Nov 6, 2023 · 6 comments
Open

Odd segfault at the end of .text section #197

ukasz opened this issue Nov 6, 2023 · 6 comments

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@ukasz
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ukasz commented Nov 6, 2023

Describe the bug

We observe this behavior on multiple occassions, but it is not quite clear what is the root cause.
The problem doesn't happen on a particular instruction, but rather at the particular offset group.
When .text size is slightly below 0x1000 (0xffc, 0xff8, 0xff4) REV reports a segmentation fault at the address which is technically at the end of .text section.
Similar behavior is observed when .text size is around muliples of a 0x1000.
The odd thing is that I am not able to reproduce this issue with GCC compiler, it only happens on LLVM.
There are two main differences I can see between code generated by those compilers a) .text offset address and b) slightly different prologue/epilogue.
Given the fact the the problem doesn't occur on any particular instruction I assume that b) has probably no effect.
The easiest way to reproduce the problem is to create a binary with main function filled with NOP instructions to the point
where .text section size is 0xff4-0xffc.

To Reproduce

  • The source code branch being used rev-devel
  • The last commit hash: c4f21a7
  • The compiler utilized to build Rev: gcc version 11.4.0 (Ubuntu 11.4.0-1ubuntu1~22.04)
  • The compiler utilized to build the test: Intel LLVM at beed157291c05

Build the following source code:

//clang -march=rv64gxinteltigrea -O0 -o sum.exe sum.c -nostdlib
#define NOP asm("nop;");
#define NOP2 NOP NOP
#define NOP4 NOP2 NOP2
#define NOP8 NOP4 NOP4
#define NOP16 NOP8 NOP8
#define NOP32 NOP16 NOP16
#define NOP64 NOP32 NOP32
#define NOP128 NOP64 NOP64
#define NOP256 NOP128 NOP128
#define NOP512 NOP256 NOP256

int main() {
        NOP512
        NOP256
        NOP128
        NOP64
        NOP32
        NOP16
        NOP4
        NOP
		return 0;
}

Lets confirm .text size of 0xffc

llvm-readelf --sections sum.exe | grep text
  [ 3] .text             PROGBITS        00000000000111e4 0001e4 000ffc 00  AX  0   0  4

Entry point is main:

llvm-readelf -s sum.exe | grep main
     3: 00000000000111e4  4092 FUNC    GLOBAL DEFAULT     3 main

Now run it with python config file >

** Python Config File**

import os
import sst
import sys

program = os.getenv("REV_EXE", "sum.exe")
ep = "[0:0x111e4]" # main address

# Define SST core options
sst.setProgramOption("timebase", "1ps")
sst.setStatisticLoadLevel(4)

max_addr_gb = 1

# Define the simulation components
comp_cpu = sst.Component("cpu", "revcpu.RevCPU")
comp_cpu.addParams({
            "verbose" : 8,                                # Verbosity
        "numCores" : 1,                               # Number of cores
        "clock" : "1.0GHz",                           # Clock
        "memSize" : 1024*1024*10,                     # Memory size in bytes
        "machine" : "[0:RV64GC]",                      # Core:Config; RV64I for core 0
        "startAddr" : ep,                             # Starting address for core 0
        "memCost" : "[0:1:1]",                       # Memory loads required 1-10 cycles
        "program" : program,                          # Target executable
        "splash" : 1,                                  # Display the splash message
        "trcStartCycle" : 1
})

sst.setStatisticOutput("sst.statOutputCSV")
sst.enableAllStatisticsForAllComponents()

# EOF

Expected behavior
There should be no segfault at end of .text section when executing aforementioned program.

Trace
REV_EXE=sum.exe sst sum.py
WARNING: Building component "cpu" with no links assigned.
RevCPU[cpu:RevCPU:0]: Building Rev with 1 cores and 1 hart(s) on each core
RevCPU[cpu:LoadElf:0]: Symbol Table Entry [:0x111e4]
RevCPU[cpu:LoadElf:0]: Symbol Table Entry [main:0x111e4]
RevCPU[cpu:LoadElf:0]: Symbol Table Entry [sum.c:0x0]
RevCPU[cpu:LoadProgramArgs:0]: Loading program argv[0] = sum.exe
RevCPU[cpu:RevFeature:0]: Core 0 ; Initializing feature set from machine string=RV64GC
RevCPU[cpu:ParseMachineModel:0]: Core 0 ; Setting XLEN to 64
RevCPU[cpu:ParseMachineModel:0]: Core 0 ; Architecture string=GC
RevCPU[cpu:SeedInstTable:0]: Core 0 ; Seeding instruction table for machine model=RV64GC
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV32I
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV32I
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV64I
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV64I
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV32M
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV32M
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV64M
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV64M
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV32A
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV32A
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV64A
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV64A
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV32F
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV32F
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV64F
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV64F
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV32D
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV32D
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling extension=RV64D
RevCPU[cpu:EnableExt:0]: Core 0 ; Enabling compressed extension=RV64D
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Initializing table mapping for machine model=RV64GC
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 55 = lui
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 23 = auipc
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 111 = jal
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 103 = jalr
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 99 = beq
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 355 = bne
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1123 = blt
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1379 = bge
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1635 = bltu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1891 = bgeu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3 = lb
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 259 = lh
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 515 = lw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1027 = lbu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1283 = lhu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 35 = sb
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 291 = sh
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 547 = sw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 19 = addi
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 531 = slti
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 787 = sltiu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1043 = xori
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1555 = ori
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1811 = andi
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 275 = slli
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1299 = srli
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 34067 = srai
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 51 = add
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 65587 = sub
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 307 = sll
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 563 = slt
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 819 = sltu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1075 = xor
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1331 = srl
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 66867 = sra
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1587 = or
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1843 = and
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 15 = fence
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 271 = fence.i
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 115 = ecall
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 262259 = ebreak
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 371 = csrrw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 627 = csrrs
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 883 = csrrc
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1395 = csrrwi
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1651 = csrrsi
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1907 = csrrci
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 0 = c.addi4spn
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 34 = c.lwsp
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 98 = c.swsp
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 32 = c.lw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 96 = c.sw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 81 = c.j
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 2050 = c.jr
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 2306 = c.jalr
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 97 = c.beqz
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 113 = c.bnez
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 33 = c.li
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 49 = c.lui
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 1 = c.addi
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 2 = c.slli
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 65 = c.srli
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 69 = c.srai
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 73 = c.andi
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 143373 = c.and
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 143369 = c.or
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 143365 = c.xor
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 143361 = c.sub
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1539 = lwu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 771 = ld
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 803 = sd
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 27 = addiw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 283 = slliw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1307 = srliw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 66843 = sraiw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 59 = addw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 65595 = subw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 315 = sllw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1339 = srlw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 66875 = sraw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 50 = c.ldsp
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 114 = c.sdsp
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 48 = c.ld
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 112 = c.sd
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 17 = c.addiw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 159749 = c.addw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 159745 = c.subw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2099 = mul
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2355 = mulh
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2611 = mulhsu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2867 = mulhu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3123 = div
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3379 = divu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3635 = rem
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3891 = remu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2107 = mulw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3131 = divw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3387 = divuw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3643 = remw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3899 = remuw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 4655 = lr.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 6703 = sc.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2607 = amoswap.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 559 = amoadd.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 8751 = amoxor.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 25135 = amoand.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 16943 = amoor.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 33327 = amomin.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 41519 = amomax.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 49711 = amominu.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 57903 = amomaxu.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 4911 = lr.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 6959 = sc.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2863 = amoswap.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 815 = amoadd.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 9007 = amoxor.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 25391 = amoand.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 17199 = amoor.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 33583 = amomin.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 41775 = amomax.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 49967 = amominu.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 58159 = amomaxu.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 519 = flw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 551 = fsw
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 67 = fmadd.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 71 = fmsub.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 75 = fnmsub.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 79 = fnmadd.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 83 = fadd.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 8275 = fsub.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 16467 = fmul.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 24659 = fdiv.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 90195 = fsqrt.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 41043 = fmin.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 41299 = fmax.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 32851 = fsgnj.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 33107 = fsgnjn.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 33363 = fsgnjx.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 196691 = fcvt.w.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1073938515 = fcvt.wu.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 229459 = fmv.x.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 164435 = feq.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 164179 = flt.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 163923 = fle.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 229715 = fclass.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 213075 = fcvt.s.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1073954899 = fcvt.s.wu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 245843 = fmv.w.x
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2147680339 = fcvt.l.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3221422163 = fcvt.lu.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2147696723 = fcvt.s.l
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3221438547 = fcvt.s.lu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 775 = fld
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 807 = fsd
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 67 = fmadd.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 71 = fmsub.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 75 = fnmsub.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 79 = fnmadd.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2131 = fadd.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 10323 = fsub.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 18515 = fmul.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 26707 = fdiv.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 92243 = fsqrt.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 43091 = fmin.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 43347 = fmax.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 34899 = fsgnj.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 35155 = fsgnjn.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 35411 = fsgnjx.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1073807443 = fcvt.s.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 67667 = fcvt.d.s
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 166483 = feq.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 166227 = flt.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 165971 = fle.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 231763 = fclass.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 198739 = fcvt.w.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1073940563 = fcvt.wu.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 215123 = fcvt.d.w
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 1073956947 = fcvt.d.wu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 18 = c.fldsp
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 82 = c.fsdsp
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 16 = c.fld
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Compressed Table Entry 80 = c.fsd
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2147682387 = fcvt.l.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3221424211 = fcvt.lu.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 2147698771 = fcvt.d.l
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 3221440595 = fcvt.d.lu
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 231507 = fmv.x.d
RevCPU[cpu:InitTableMapping:0]: Core 0 ; Table Entry 247891 = fmv.d.x
RevCPU[cpu:ReadOverrideTables:0]: Core 0 ; Reading override tables for machine model=RV64GC
RevCPU[cpu:RevCPU:0]: Warning: tracer could not find disassembler. Using REV default
RevCPU[cpu:RevCPU:0]:

/////
/** /** ***** ** **
/******* ////** /**
//// ///** /**
/** //** /**//// //
/** ////* //**
// // ////// //

RevCPU[cpu:RevCPU:0]: Initialization of RevCPUs complete.
RevCPU[cpu:clockTick:1000]: Cycle: 1
RevCPU[cpu:clockTick:2000]: Cycle: 2
RevCPU[cpu:DecodeInst:2000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x111e4:0xfe010113
RevCPU[cpu:InstTrace:2000]: Core 0; Hart 0; Thread 1]; *I 0x111e4:fe010113 + addi %rd, %rs1, $imm 0x9ffbfc<-x2 x2<-0x9ffbdc
RevCPU[cpu:clockTick:3000]: Cycle: 3
RevCPU[cpu:DecodeInst:3000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x111e8:0x113c23
RevCPU[cpu:InstTrace:3000]: Core 0; Hart 0; Thread 1]; *I 0x111e8:00113c23 sd %rs2, $imm(%rs1) 0x0<-x1 0x9ffbdc<-x2 [0x9ffbf4,8]<-0x0000000000000000
RevCPU[cpu:clockTick:4000]: Cycle: 4
RevCPU[cpu:DecodeInst:4000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x111ec:0x813823
RevCPU[cpu:InstTrace:4000]: Core 0; Hart 0; Thread 1]; *I 0x111ec:00813823 sd %rs2, $imm(%rs1) 0x0<-x8 0x9ffbdc<-x2 [0x9ffbec,8]<-0x0000000000000000
RevCPU[cpu:clockTick:5000]: Cycle: 5
RevCPU[cpu:DecodeInst:5000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x111f0:0x2010413
RevCPU[cpu:InstTrace:5000]: Core 0; Hart 0; Thread 1]; *I 0x111f0:02010413 addi %rd, %rs1, $imm 0x9ffbdc<-x2 x8<-0x9ffbfc
RevCPU[cpu:clockTick:6000]: Cycle: 6
RevCPU[cpu:DecodeInst:6000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x111f4:0x513
RevCPU[cpu:InstTrace:6000]: Core 0; Hart 0; Thread 1]; *I 0x111f4:00000513 addi %rd, %rs1, $imm 0x0<-x0 x10<-0x0
RevCPU[cpu:clockTick:7000]: Cycle: 7
RevCPU[cpu:DecodeInst:7000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x111f8:0xfea42623
RevCPU[cpu:InstTrace:7000]: Core 0; Hart 0; Thread 1]; *I 0x111f8:fea42623 sw %rs2, $imm(%rs1) 0x0<-x10 0x9ffbfc<-x8 [0x9ffbe8,4]<-0x00000000
RevCPU[cpu:clockTick:8000]: Cycle: 8
RevCPU[cpu:DecodeInst:8000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x111fc:0x13
RevCPU[cpu:InstTrace:8000]: Core 0; Hart 0; Thread 1]; *I 0x111fc:00000013 addi %rd, %rs1, $imm 0x0<-x0 x0<-0x0
RevCPU[cpu:clockTick:9000]: Cycle: 9
RevCPU[cpu:DecodeInst:9000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x11200:0x13
RevCPU[cpu:InstTrace:9000]: Core 0; Hart 0; Thread 1]; *I 0x11200:00000013 addi %rd, %rs1, $imm 0x0<-x0 x0<-0x0
RevCPU[cpu:clockTick:10000]: Cycle: 10
(........SNIP..........)
RevCPU[cpu:DecodeInst:1017000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x121c0:0x13
RevCPU[cpu:InstTrace:1017000]: Core 0; Hart 0; Thread 1]; *I 0x121c0:00000013 addi %rd, %rs1, $imm 0x0<-x0 x0<-0x0
RevCPU[cpu:clockTick:1018000]: Cycle: 1018
RevCPU[cpu:DecodeInst:1018000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x121c4:0x13
RevCPU[cpu:InstTrace:1018000]: Core 0; Hart 0; Thread 1]; *I 0x121c4:00000013 addi %rd, %rs1, $imm 0x0<-x0 x0<-0x0
RevCPU[cpu:clockTick:1019000]: Cycle: 1019
RevCPU[cpu:DecodeInst:1019000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x121c8:0x13
RevCPU[cpu:InstTrace:1019000]: Core 0; Hart 0; Thread 1]; *I 0x121c8:00000013 addi %rd, %rs1, $imm 0x0<-x0 x0<-0x0
RevCPU[cpu:clockTick:1020000]: Cycle: 1020
RevCPU[cpu:DecodeInst:1020000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x121cc:0x13
RevCPU[cpu:InstTrace:1020000]: Core 0; Hart 0; Thread 1]; *I 0x121cc:00000013 addi %rd, %rs1, $imm 0x0<-x0 x0<-0x0
RevCPU[cpu:clockTick:1021000]: Cycle: 1021
RevCPU[cpu:DecodeInst:1021000]: Core 0; Hart 0; Thread 1; PC:InstPayload = 0x121d0:0x1813083
RevCPU[cpu:InstTrace:1021000]: Core 0; Hart 0; Thread 1]; *I 0x121d0:01813083 ld %rd, $imm(%rs1) 0x9ffbdc<-x2 0x0000000000000000<-[0x9ffbf4,8] x1<-0x0
RevCPU[cpu:clockTick:1022000]: Cycle: 1022
| BaseAddr: 0x9ffc00 | TopAddr: 0xa00000 | Size: 1024 Bytes
| BaseAddr: 0x10000 | TopAddr: 0x11190 | Size: 4496 Bytes
| BaseAddr: 0x111e4 | TopAddr: 0x121e4 | Size: 4096 Bytes
| BaseAddr: 0x0 | TopAddr: 0x1000 | Size: 4096 Bytes
| BaseAddr: 0x8ffc00 | TopAddr: 0x9ffc00 | Size: 1048576 Bytes
FATAL: RevCPU[cpu:CalcPhysAddr:1022000]: Segmentation Fault: Virtual address 0x121e4 (PhysAddr = 0xffffffffffffffff) was not found in any mem segments
SST Fatal Backtrace Information:
0 : sst(_ZNK3SST6Output5fatalEjPKcS2_iS2_z+0x4ae) [0x55e9cad2ec6e]
1 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU6RevMem12CalcPhysAddrEmm+0x465) [0x7f470484b9c5]
2 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU6RevMem7ReadMemEjmmPvRKNS0_6MemReqEj+0x3e) [0x7f470484c78e]
3 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU13RevPrefetcher4FillEm+0x4db) [0x7f47048b33fb]
4 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU13RevPrefetcher4FillEm+0x674) [0x7f47048b3594]
5 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU13RevPrefetcher9InstFetchEmRbRj+0x13a) [0x7f47048b397a]
6 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU7RevProc10DecodeInstEv+0x5c) [0x7f470488349c]
7 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU7RevProc9ClockTickEm+0x8d0) [0x7f4704884b90]
8 : /usr/local/lib/sst-elements-library/librevcpu.so(_ZN3SST6RevCPU6RevCPU9clockTickEm+0x1c3) [0x7f4704815a73]
9 : sst(_ZN3SST5Clock7executeEv+0x10c) [0x55e9cacbf9cc]
10 : sst(_ZN3SST15Simulation_impl3runEv+0x3d3) [0x55e9cad584d3]
11 : sst(+0xf808e) [0x55e9caca208e]
12 : sst(main+0x186b) [0x55e9cac87e0b]
13 : /lib/x86_64-linux-gnu/libc.so.6(+0x29d90) [0x7f4708683d90]
14 : /lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0x80) [0x7f4708683e40]
15 : sst(_start+0x25) [0x55e9cac9f4b5]

MPI_ABORT was invoked on rank 0 in communicator MPI_COMM_WORLD
with errorcode 11.

NOTE: invoking MPI_ABORT causes Open MPI to kill all MPI processes.
You may or may not see output from other processes, depending on
@jleidel
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jleidel commented Nov 6, 2023

This may be due to the prefetcher attempting to fetch beyond the end of the .text space.

@rkabrick
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This may be due to the prefetcher attempting to fetch beyond the end of the .text space.

If this is indeed the prefetcher how would we prevent it from happening?

@jleidel
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jleidel commented Nov 10, 2023

This may be due to the prefetcher attempting to fetch beyond the end of the .text space.

If this is indeed the prefetcher how would we prevent it from happening?

We would need to pass the address of the end of the text space down to the prefetcher such that we don't overreach.

@ukasz
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ukasz commented Dec 4, 2023 •
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We would need to pass the address of the end of the text space down to the prefetcher such that we don't overreach.

This was in fact a prefetcher bug and @vcave fixed it this way.

@leekillough
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This is not reproducible anymore; can we close this?

@ukasz
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ukasz commented Jul 22, 2024

I'll try to reproduce it and report back.

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@ukasz @jleidel @leekillough @rkabrick