diff --git a/.gitmodules b/.gitmodules index 5241f58b2dd..6440c3395af 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,70 +1,70 @@ [submodule "3rdparty/blobs"] path = 3rdparty/blobs - url = ../blobs.git + url = https://review.coreboot.org/blobs.git update = none ignore = dirty [submodule "util/nvidia-cbootimage"] path = util/nvidia/cbootimage - url = ../nvidia-cbootimage.git + url = https://review.coreboot.org/nvidia-cbootimage.git [submodule "vboot"] path = 3rdparty/vboot - url = ../vboot.git + url = https://review.coreboot.org/vboot.git branch = main [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware - url = ../arm-trusted-firmware.git + url = https://review.coreboot.org/arm-trusted-firmware.git [submodule "3rdparty/chromeec"] path = 3rdparty/chromeec - url = ../chrome-ec.git + url = https://review.coreboot.org/chrome-ec.git [submodule "libhwbase"] path = 3rdparty/libhwbase - url = ../libhwbase.git + url = https://review.coreboot.org/libhwbase.git [submodule "libgfxinit"] path = 3rdparty/libgfxinit - url = ../libgfxinit.git + url = https://review.coreboot.org/libgfxinit.git [submodule "3rdparty/fsp"] path = 3rdparty/fsp - url = ../fsp.git + url = https://review.coreboot.org/fsp.git update = none ignore = dirty [submodule "opensbi"] path = 3rdparty/opensbi - url = ../opensbi.git + url = https://review.coreboot.org/opensbi.git [submodule "intel-microcode"] path = 3rdparty/intel-microcode - url = ../intel-microcode.git + url = https://review.coreboot.org/intel-microcode.git update = none ignore = dirty branch = main [submodule "3rdparty/ffs"] path = 3rdparty/ffs - url = ../ffs.git + url = https://review.coreboot.org/ffs.git [submodule "3rdparty/amd_blobs"] path = 3rdparty/amd_blobs - url = ../amd_blobs + url = https://review.coreboot.org/amd_blobs update = none ignore = dirty [submodule "3rdparty/cmocka"] path = 3rdparty/cmocka - url = ../cmocka.git + url = https://review.coreboot.org/cmocka.git update = none branch = stable-1.1 [submodule "3rdparty/qc_blobs"] path = 3rdparty/qc_blobs - url = ../qc_blobs.git + url = https://review.coreboot.org/qc_blobs.git update = none ignore = dirty [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools - url = ../9esec-security-tooling.git + url = https://review.coreboot.org/9esec-security-tooling.git [submodule "3rdparty/stm"] path = 3rdparty/stm - url = ../STM + url = https://review.coreboot.org/STM branch = stmpe [submodule "util/goswid"] path = util/goswid - url = ../goswid + url = https://review.coreboot.org/goswid.git branch = trunk [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"] path = src/vendorcode/amd/opensil/genoa_poc/opensil - url = ../opensil_genoa_poc.git + url = https://review.coreboot.org/opensil_genoa_poc.git diff --git a/src/drivers/gfx/nvidia/Kconfig b/src/drivers/gfx/nvidia/Kconfig new file mode 100644 index 00000000000..4c9c7ff08c6 --- /dev/null +++ b/src/drivers/gfx/nvidia/Kconfig @@ -0,0 +1,38 @@ +config DRIVERS_GFX_NVIDIA + bool + default n + help + Support for NVIDIA Optimus graphics + +config DRIVERS_GFX_NVIDIA_BRIDGE + hex "PCI bridge for the GPU device" + default 0x01 + depends on DRIVERS_GFX_NVIDIA + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + depends on DRIVERS_GFX_NVIDIA + bool + default n + help + Support for NVIDIA Dynamic Boost + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP + int "Total processor power offset from default TGP in watts" + default 45 + depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + help + This identifies the available power for the CPU or GPU boost + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN + int "Minimum TGP offset from default TGP in watts" + default 0 + depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + help + This is used to transfer power from the GPU to the CPU + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX + int "Maximum TGP offset from default TGP in watts" + default 0 + depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + help + This is used to transfer power from the CPU to the GPU diff --git a/src/drivers/gfx/nvidia/Makefile.inc b/src/drivers/gfx/nvidia/Makefile.inc new file mode 100644 index 00000000000..32ddf7e64e5 --- /dev/null +++ b/src/drivers/gfx/nvidia/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c + +ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c diff --git a/src/drivers/gfx/nvidia/acpi/coffeelake.asl b/src/drivers/gfx/nvidia/acpi/coffeelake.asl new file mode 100644 index 00000000000..c515ec1cb29 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/coffeelake.asl @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* NVIDIA GC6 on CFL and CML CPU PCIe ports */ + +// Memory mapped PCI express config space +OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000) + +Field (PCIC, ByteAcc, NoLock, Preserve) { + PVID, 16, + PDID, 16, + + Offset (0x248), + , 7, + L23E, 1, /* L23_Rdy Entry Request */ + L23R, 1, /* L23_Rdy to Detect Transition */ + + Offset (0xC20), + , 4, + P0AP, 2, /* Additional power savings */ + + Offset (0xC38), + , 3, + P0RM, 1, /* Robust squelch mechanism */ +} + +// Enter L23 +Method (DL23, 0, Serialized) { + Printf(" GPU PORT DL23 START") + + L23E = 1 + Sleep (16) + Local0 = 0 + While (L23E) { + If ((Local0 > 4)) { + Break + } + + Sleep (16) + Local0++ + } + + P0RM = 1 + P0AP = 3 + + Printf(" GPU PORT DL23 FINISH") +} + +// Exit L23 +Method (L23D, 0, Serialized) { + Printf(" GPU PORT L23D START") + + L23R = 1 + Sleep (16) + Local0 = 0 + While (L23R) { + If ((Local0 > 4)) { + Break + } + + Sleep (16) + Local0++ + } + + P0RM = 0 + P0AP = 0 + + Printf(" GPU PORT L23D FINISH") +} + +// Main power resource +PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON, 0, Serialized) { + Printf("GPU PORT PWRR._ON") + + ^^DEV0._ON() + + _STA = 1 + } + + Method (_OFF, 0, Serialized) { + Printf("GPU PORT PWRR._OFF") + + ^^DEV0._OFF() + + _STA = 0 + } +} + +// Power resources for entering D0 +Name (_PR0, Package () { PWRR }) + +// Power resources for entering D3 +Name (_PR3, Package () { PWRR }) + +#include "common/gpu.asl" diff --git a/src/drivers/gfx/nvidia/acpi/common/dsm.asl b/src/drivers/gfx/nvidia/acpi/common/dsm.asl new file mode 100644 index 00000000000..ad440b58b74 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/dsm.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define NV_ERROR_SUCCESS 0x0 +#define NV_ERROR_UNSPECIFIED 0x80000001 +#define NV_ERROR_UNSUPPORTED 0x80000002 + +#include "gps.asl" +#include "nvjt.asl" + +Method (_DSM, 4, Serialized) { + Printf("GPU _DSM") + If (Arg0 == ToUUID (JT_DSM_GUID)) { + If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) { + Return (NVJT(Arg2, Arg3)) + } Else { + Printf(" Unsupported JT revision: %o", SFST(Arg1)) + Return (NV_ERROR_UNSUPPORTED) + } + } ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) { + If (ToInteger(Arg1) == GPS_REVISION_ID) { + Return (GPS(Arg2, Arg3)) + } Else { + Printf(" Unsupported GPS revision: %o", SFST(Arg1)) + Return (NV_ERROR_UNSUPPORTED) + } + } Else { + Printf(" Unsupported GUID: %o", IDST(Arg0)) + Return (NV_ERROR_UNSPECIFIED) + } +} diff --git a/src/drivers/gfx/nvidia/acpi/common/gps.asl b/src/drivers/gfx/nvidia/acpi/common/gps.asl new file mode 100644 index 00000000000..7d69b194066 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/gps.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81" +#define GPS_REVISION_ID 0x00000200 +#define GPS_FUNC_SUPPORT 0x00000000 +#define GPS_FUNC_PSHARESTATUS 0x00000020 +#define GPS_FUNC_PSHAREPARAMS 0x0000002A + +Method(GPS, 2, Serialized) { + Printf(" GPU GPS") + Switch(ToInteger(Arg0)) { + Case(GPS_FUNC_SUPPORT) { + Printf(" Supported Functions") + Return(ITOB( + (1 << GPS_FUNC_SUPPORT) | + (1 << GPS_FUNC_PSHARESTATUS) | + (1 << GPS_FUNC_PSHAREPARAMS) + )) + } + Case(GPS_FUNC_PSHARESTATUS) { + Printf(" Power Share Status") + Return(ITOB(0)) + } + Case(GPS_FUNC_PSHAREPARAMS) { + Printf(" Power Share Parameters") + + CreateField(Arg1, 0, 4, QTYP) // Query type + + Name(GPSP, Buffer(36) { 0x00 }) + CreateDWordField(GPSP, 0, RSTS) // Response status + CreateDWordField(GPSP, 4, VERS) // Version + + // Set query type of response + RSTS = QTYP + // Set version of response + VERS = 0x00010000 + + Switch(ToInteger(QTYP)) { + Case(0) { + Printf(" Request Current Information") + // No required information + Return(GPSP) + } + Case(1) { + Printf(" Request Supported Fields") + // Support GPU temperature field + RSTS |= (1 << 8) + Return(GPSP) + } + Case(2) { + Printf(" Request Current Limits") + // No required limits + Return(GPSP) + } + Default { + Printf(" Unknown Query: %o", SFST(QTYP)) + Return(NV_ERROR_UNSUPPORTED) + } + } + } + Default { + Printf(" Unsupported function: %o", SFST(Arg0)) + Return(NV_ERROR_UNSUPPORTED) + } + } +} diff --git a/src/drivers/gfx/nvidia/acpi/common/gpu.asl b/src/drivers/gfx/nvidia/acpi/common/gpu.asl new file mode 100644 index 00000000000..49e5c47285b --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/gpu.asl @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (DEV0) { + Name(_ADR, 0x00000000) + + #include "utility.asl" + #include "dsm.asl" + #include "power.asl" +} + +#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST) +Scope (\_SB) { + Device(NPCF) { + #include "utility.asl" + #include "nvpcf.asl" + } +} +#endif diff --git a/src/drivers/gfx/nvidia/acpi/common/nvjt.asl b/src/drivers/gfx/nvidia/acpi/common/nvjt.asl new file mode 100644 index 00000000000..31eaed275e8 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/nvjt.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define JT_DSM_GUID "CBECA351-067B-4924-9CBD-B46B00B86F34" +#define JT_REVISION_ID_MIN 0x00000100 +#define JT_REVISION_ID_MAX 0x00000200 +#define JT_FUNC_SUPPORT 0x00000000 +#define JT_FUNC_CAPS 0x00000001 +#define JT_FUNC_POWERCONTROL 0x00000003 + +//TODO: SMI traps and EGIN/XCLM +#define JT_GPC_GSS 0 // Get current GPU GCx sleep status +#define JT_GPC_EGNS 1 // Enter GC6 without self-refresh +#define JT_GPC_EGIS 2 // Enter GC6 with self-refresh +#define JT_GPC_XGXS 3 // Exit GC6 and stop self-refresh +#define JT_GPC_XGIS 4 // Exit GC6 for self-refresh update + +#define JT_DFGC_NONE 0 // Handle request immediately +#define JT_DFGC_DEFER 1 // Defer GPC and GPCX +//TODO #define JT_DFGC_CLEAR 2 // Clear pending requests + +// Deferred GC6 enter/exit until D3-cold (saved DFGC) +Name(DFEN, 0) + +// Deferred GC6 enter control (saved GPC) +Name(DFCI, 0) + +// Deferred GC6 exit control (saved GPCX) +Name(DFCO, 0) + +Method (NVJT, 2, Serialized) { + Printf(" GPU NVJT") + Switch (ToInteger(Arg0)) { + Case (JT_FUNC_SUPPORT) { + Printf(" Supported Functions") + Return(ITOB( + (1 << JT_FUNC_SUPPORT) | + (1 << JT_FUNC_CAPS) | + (1 << JT_FUNC_POWERCONTROL) + )) + } + Case (JT_FUNC_CAPS) { + Printf(" Capabilities") + Return(ITOB( + (1 << 0) | // G-SYNC NSVR power-saving features are enabled + (1 << 1) | // NVSR disabled + (2 << 3) | // Panel power and backlight are on the suspend rail + (0 << 5) | // self-refresh controller remains powered while panel is powered + (0 << 6) | // FB is not on the suspend rail but is powered on in GC6 + (0 << 8) | // Combined power rail for all GPUs + (0 << 10) | // External SPI ROM + (1 << 11) | // No SMI handler for kernel panic exit while in GC6 + (0 << 12) | // Supports notify on GC6 state done + (1 << 13) | // Support deferred GC6 + (1 << 14) | // Support fine-grained root port control + (2 << 15) | // GC6 version is GC6-R + (0 << 17) | // GC6 exit ISR is not supported + (0 << 18) | // GC6 self wakeup not supported + (JT_REVISION_ID_MAX << 20) // Highest revision supported + )) + } + Case (JT_FUNC_POWERCONTROL) { + Printf(" Power Control: %o", SFST(Arg1)) + + CreateField (Arg1, 0, 3, GPC) // GPU power control + CreateField (Arg1, 4, 1, PPC) // Panel power control + CreateField (Arg1, 14, 2, DFGC) // Defer GC6 enter/exit until D3 cold + CreateField (Arg1, 16, 3, GPCX) // Deferred GC6 exit control + + // Save deferred GC6 request + If ((ToInteger(GPC) != 0) || (ToInteger(DFGC) != 0)) { + DFEN = DFGC + DFCI = GPC + DFCO = GPCX + } + + // Buffer to cache current state + Name (JTBF, Buffer (4) { 0, 0, 0, 0 }) + CreateField (JTBF, 0, 3, CGCS) // Current GC state + CreateField (JTBF, 3, 1, CGPS) // Current GPU power status + CreateField (JTBF, 7, 1, CPSS) // Current panel and SRC state (0 when on) + + // If doing deferred GC6 request, return now + If (ToInteger(DFGC) != 0) { + CGCS = 1 + CGPS = 1 + Return (JTBF) + } + + // Apply requested state + Switch (ToInteger(GPC)) { + Case (JT_GPC_GSS) { + Printf(" Get current GPU GCx sleep status") + //TODO: include transitions! + If (GTXS(DGPU_RST_N)) { + // GPU powered on + CGCS = 1 + CGPS = 1 + } ElseIf (GTXS(DGPU_PWR_EN)) { + // GPU powered off, GC6 + CGCS = 3 + CGPS = 0 + } Else { + // GPU powered off, D3 cold + CGCS = 2 + CGPS = 0 + } + } + Case (JT_GPC_EGNS) { + Printf(" Enter GC6 without self-refresh") + GC6I() + CPSS = 1 + } + Case (JT_GPC_EGIS) { + Printf(" Enter GC6 with self-refresh") + GC6I() + If (ToInteger(PPC) == 0) { + CPSS = 0 + } + } + Case (JT_GPC_XGXS) { + Printf(" Exit GC6 and stop self-refresh") + GC6O() + + CGCS = 1 + CGPS = 1 + If (ToInteger(PPC) != 0) { + CPSS = 0 + } + } + Case (JT_GPC_XGIS) { + Printf(" Exit GC6 for self-refresh update") + GC6O() + + CGCS = 1 + CGPS = 1 + If (ToInteger(PPC) != 0) { + CPSS = 0 + } + } + Default { + Printf(" Unsupported GPU power control: %o", SFST(GPC)) + } + } + + Return (JTBF) + } + Default { + Printf(" Unsupported function: %o", SFST(Arg0)) + Return (NV_ERROR_UNSUPPORTED) + } + } +} diff --git a/src/drivers/gfx/nvidia/acpi/common/nvpcf.asl b/src/drivers/gfx/nvidia/acpi/common/nvpcf.asl new file mode 100644 index 00000000000..16b9fbd56dd --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/nvpcf.asl @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66" +#define NVPCF_REVISION_ID 0x00000200 +#define NVPCF_ERROR_SUCCESS 0x0 +#define NVPCF_ERROR_GENERIC 0x80000001 +#define NVPCF_ERROR_UNSUPPORTED 0x80000002 +#define NVPCF_FUNC_GET_SUPPORTED 0x00000000 +#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001 +#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002 + +Name(_HID, "NVDA0820") + +Name(_UID, "NPCF") + +Method(_DSM, 4, Serialized) { + Printf("NVPCF _DSM") + If (Arg0 == ToUUID(NVPCF_DSM_GUID)) { + If (ToInteger(Arg1) == NVPCF_REVISION_ID) { + Return(NPCF(Arg2, Arg3)) + } Else { + Printf(" Unsupported NVPCF revision: %o", SFST(Arg1)) + Return(NVPCF_ERROR_GENERIC) + } + } Else { + Printf(" Unsupported GUID: %o", IDST(Arg0)) + Return(NVPCF_ERROR_GENERIC) + } +} + +Method(NPCF, 2, Serialized) { + Printf(" NVPCF NPCF") + Switch(ToInteger(Arg0)) { + Case(NVPCF_FUNC_GET_SUPPORTED) { + Printf(" Supported Functions") + Return(ITOB( + (1 << NVPCF_FUNC_GET_SUPPORTED) | + (1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) | + (1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) + )) + } + Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) { + Printf(" Get Static Config") + Return(Buffer(14) { + // Device table header + 0x20, 0x03, 0x01, + // Intel + NVIDIA + 0x00, + // Controller table header + 0x23, 0x04, 0x05, 0x01, + // Dynamic boost controller + 0x01, + // Supports DC + 0x01, + // Reserved + 0x00, 0x00, 0x00, + // Checksum + 0xAD + }) + } + Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) { + Printf(" Update Dynamic Boost") + + CreateField(Arg1, 0x28, 2, ICMD) // Input command + + Name(PCFP, Buffer(49) { + // Table version + 0x23, + // Table header size + 0x05, + // Size of common status in bytes + 0x10, + // Size of controller entry in bytes + 0x1C, + // Other fields filled in later + }) + CreateByteField(PCFP, 0x04, CCNT) // Controller count + CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset + CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset + CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset + + Switch(ToInteger(ICMD)) { + Case(0) { + Printf(" Get Controller Params") + // Number of controllers + CCNT = 1 + // AC total processor power offset from default TGP in 1/8 watt units + ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3) + // AC maximum TGP offset from default TGP in 1/8 watt units + AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3) + // AC minimum TGP offset from default TGP in 1/8 watt units + AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3) + Printf("PCFP: %o", SFST(PCFP)) + Return(PCFP) + } + Case(1) { + Printf(" Set Controller Status") + //TODO + Printf("PCFP: %o", SFST(PCFP)) + Return(PCFP) + } + Default { + Printf(" Unknown Input Command: %o", SFST(ICMD)) + Return(NV_ERROR_UNSUPPORTED) + } + } + } + Default { + Printf(" Unsupported function: %o", SFST(Arg0)) + Return(NVPCF_ERROR_UNSUPPORTED) + } + } +} diff --git a/src/drivers/gfx/nvidia/acpi/common/power.asl b/src/drivers/gfx/nvidia/acpi/common/power.asl new file mode 100644 index 00000000000..b285ba6af0e --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/power.asl @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//TODO: evaluate sleeps + +OperationRegion (PCIC, PCI_Config, 0x00, 0xFF) +Field (PCIC, DwordAcc, NoLock, Preserve) { + Offset (0x40), + SSID, 32, // Subsystem vendor and product ID +} + +// Enter GC6 +Method(GC6I, 0, Serialized) { + Printf(" GPU GC6I START") + + // Enter L23 + ^^DL23() + Sleep(5) + + // Put GPU into reset + Printf(" Put GPU into reset") + CTXS(DGPU_RST_N) + Sleep(5) + + Printf(" GPU GC6I FINISH") +} + +// Exit GC6 +Method(GC6O, 0, Serialized) { + Printf(" GPU GC6O START") + + // Bring GPU out of reset + Printf(" Bring GPU out of reset") + STXS(DGPU_RST_N) + Sleep(5) + + // Exit L23 + ^^L23D() + Sleep(5) + + Printf(" GPU GC6O FINISH") +} + +Method (_ON, 0, Serialized) { + Printf(" GPU _ON START") + + If (DFEN == JT_DFGC_DEFER) { + Switch (ToInteger(DFCO)) { + Case (JT_GPC_XGXS) { + Printf(" Exit GC6 and stop self-refresh") + GC6O() + } + Default { + Printf(" Unsupported DFCO: %o", SFST(DFCO)) + } + } + DFEN = JT_DFGC_NONE + } Else { + Printf(" Standard RTD3 power on") + STXS(DGPU_PWR_EN) + Sleep(5) + GC6O() + } + + Printf(" GPU _ON FINISH") +} + +Method (_OFF, 0, Serialized) { + Printf(" GPU _OFF START") + + If (DFEN == JT_DFGC_DEFER) { + Switch (ToInteger(DFCI)) { + Case (JT_GPC_EGNS) { + Printf(" Enter GC6 without self-refresh") + GC6I() + } + Case (JT_GPC_EGIS) { + Printf(" Enter GC6 with self-refresh") + GC6I() + } + Default { + Printf(" Unsupported DFCI: %o", SFST(DFCI)) + } + } + DFEN = JT_DFGC_NONE + } Else { + Printf(" Standard RTD3 power off") + GC6I() + CTXS(DGPU_PWR_EN) + Sleep(5) + } + + Printf(" GPU _OFF FINISH") +} + +// Main power resource +PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON, 0, Serialized) { + Printf("GPU PWRR._ON") + + // Restore SSID + ^^SSID = DGPU_SSID + Printf(" Restore SSID: %o", SFST(^^SSID)) + + _STA = 1 + } + + Method (_OFF, 0, Serialized) { + Printf("GPU PWRR._OFF") + + _STA = 0 + } +} + +// Power resources for entering D0 +Name (_PR0, Package () { PWRR }) + +// Power resources for entering D3 +Name (_PR3, Package () { PWRR }) diff --git a/src/drivers/gfx/nvidia/acpi/common/utility.asl b/src/drivers/gfx/nvidia/acpi/common/utility.asl new file mode 100644 index 00000000000..edf42bd024b --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/common/utility.asl @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Convert a byte to a hex string, trimming extra parts +Method (BHEX, 1) { + Local0 = ToHexString(Arg0) + Return (Mid(Local0, SizeOf(Local0) - 2, 2)) +} + +// UUID to string +Method (IDST, 1) { + Local0 = "" + Fprintf( + Local0, + "%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o", + BHEX(DerefOf(Arg0[3])), + BHEX(DerefOf(Arg0[2])), + BHEX(DerefOf(Arg0[1])), + BHEX(DerefOf(Arg0[0])), + BHEX(DerefOf(Arg0[5])), + BHEX(DerefOf(Arg0[4])), + BHEX(DerefOf(Arg0[7])), + BHEX(DerefOf(Arg0[6])), + BHEX(DerefOf(Arg0[8])), + BHEX(DerefOf(Arg0[9])), + BHEX(DerefOf(Arg0[10])), + BHEX(DerefOf(Arg0[11])), + BHEX(DerefOf(Arg0[12])), + BHEX(DerefOf(Arg0[13])), + BHEX(DerefOf(Arg0[14])), + BHEX(DerefOf(Arg0[15])) + ) + Return (Local0) +} + +// Safe hex conversion, checks type first +Method (SFST, 1) { + Local0 = ObjectType(Arg0) + If (Local0 == 1 || Local0 == 2 || Local0 == 3) { + Return (ToHexString(Arg0)) + } Else { + Return (Concatenate("Type: ", Arg0)) + } +} + +// Convert from 4-byte buffer to 32-bit integer +Method (BTOI, 1) { + Return( + DerefOf(Arg0[0]) | + (DerefOf(Arg0[1]) << 8) | + (DerefOf(Arg0[2]) << 16) | + (DerefOf(Arg0[3]) << 24) + ) +} + +// Convert from 32-bit integer to 4-byte buffer +Method (ITOB, 1) { + Local0 = Buffer(4) { 0, 0, 0, 0 } + Local0[0] = Arg0 & 0xFF + Local0[1] = (Arg0 >> 8) & 0xFF + Local0[2] = (Arg0 >> 16) & 0xFF + Local0[3] = (Arg0 >> 24) & 0xFF + Return (Local0) +} diff --git a/src/drivers/gfx/nvidia/acpi/tigerlake.asl b/src/drivers/gfx/nvidia/acpi/tigerlake.asl new file mode 100644 index 00000000000..a13e46a04f8 --- /dev/null +++ b/src/drivers/gfx/nvidia/acpi/tigerlake.asl @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* NVIDIA GC6 on (TGL and ADL) (CPU and PCH) PCIe ports */ + +// Port mapped PCI express config space +OperationRegion (PCIC, PCI_Config, 0x00, 0xFF) + +Field (PCIC, AnyAcc, NoLock, Preserve) { + Offset(0x52), /* LSTS - Link Status Register */ + , 13, + LASX, 1, /* 0, Link Active Status */ + + Offset(0x60), /* RSTS - Root Status Register */ + , 16, + PSPX, 1, /* 16, PME Status */ + + Offset(0xD8), /* 0xD8, MPC - Miscellaneous Port Configuration Register */ + , 30, + HPEX, 1, /* 30, Hot Plug SCI Enable */ + PMEX, 1, /* 31, Power Management SCI Enable */ + + Offset (0xE0), /* 0xE0, SPR - Scratch Pad Register */ + SCB0, 1, /* Scratch bit 0 */ + + Offset(0xE2), /* 0xE2, RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ +} + +Field (PCIC, AnyAcc, NoLock, WriteAsZeros) { + Offset(0xDC), /* 0xDC, SMSCS - SMI/SCI Status Register */ + , 30, + HPSX, 1, /* 30, Hot Plug SCI Status */ + PMSX, 1 /* 31, Power Management SCI Status */ +} + +// Enter L23 +Method (DL23, 0, Serialized) { + Printf(" GPU PORT DL23 START") + + L23E = 1 + Sleep (16) + Local0 = 0 + While (L23E) { + If ((Local0 > 4)) { + Break + } + + Sleep (16) + Local0++ + } + SCB0 = 1 + + Printf(" GPU PORT DL23 FINISH") +} + +// Exit L23 +Method (L23D, 0, Serialized) { + Printf(" GPU PORT L23D START") + + If ((SCB0 == 1)) { + L23R = 1 + Local0 = 0 + While (L23R) { + If ((Local0 > 4)) { + Break + } + Sleep (16) + Local0++ + } + + SCB0 = 0 + Local0 = 0 + While ((LASX == 0)) { + If ((Local0 > 8)) { + Break + } + Sleep (16) + Local0++ + } + } + + Printf(" GPU PORT L23D FINISH") +} + +Method (HPME, 0, Serialized) { + Printf(" GPU PORT HPME START") + + If (PMSX == 1) { + Printf(" Notify GPU driver of PME SCI") + Notify(DEV0, 0x2) + Printf(" Clear PME SCI") + PMSX = 1 + Printf(" Consume PME notification") + PSPX = 1 + } + + Printf(" GPU PORT HPME FINISH") +} + +// Main power resource +PowerResource (PWRR, 0, 0) { + Name (_STA, 1) + + Method (_ON, 0, Serialized) { + Printf("GPU PORT PWRR._ON") + + HPME(); + If (PMEX == 1) { + Printf(" Disable power management SCI") + PMEX = 0 + } + + ^^DEV0._ON() + + _STA = 1 + } + + Method (_OFF, 0, Serialized) { + Printf("GPU PORT PWRR._OFF") + + ^^DEV0._OFF() + + If (PMEX == 0) { + Printf(" Enable power management SCI") + PMEX = 1 + HPME() + } + + _STA = 0 + } +} + +// Power resources for entering D0 +Name (_PR0, Package () { PWRR }) + +// Power resources for entering D3 +Name (_PR3, Package () { PWRR }) + +#include "common/gpu.asl" diff --git a/src/drivers/gfx/nvidia/chip.h b/src/drivers/gfx/nvidia/chip.h new file mode 100644 index 00000000000..b6d9c908ebc --- /dev/null +++ b/src/drivers/gfx/nvidia/chip.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_ +#define _DRIVERS_GFX_NVIDIA_CHIP_H_ + +struct drivers_gfx_nvidia_config { + /* TODO: Set GPIOs in devicetree? */ +}; + +#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */ diff --git a/src/drivers/gfx/nvidia/gpu.h b/src/drivers/gfx/nvidia/gpu.h new file mode 100644 index 00000000000..68b6cd2d590 --- /dev/null +++ b/src/drivers/gfx/nvidia/gpu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_ +#define _DRIVERS_GFX_NVIDIA_GPU_H_ + +#include + +struct nvidia_gpu_config { + /* GPIO for GPU_PWR_EN */ + unsigned int power_gpio; + /* GPIO for GPU_RST# */ + unsigned int reset_gpio; + /* Enable or disable GPU power */ + bool enable; +}; + +void nvidia_set_power(const struct nvidia_gpu_config *config); + +#endif /* _DRIVERS_NVIDIA_GPU_H_ */ diff --git a/src/drivers/gfx/nvidia/nvidia.c b/src/drivers/gfx/nvidia/nvidia.c new file mode 100644 index 00000000000..9df51094173 --- /dev/null +++ b/src/drivers/gfx/nvidia/nvidia.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "chip.h" +#include +#include +#include +#include + +#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40 + +static void nvidia_read_resources(struct device *dev) +{ + printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev)); + + pci_dev_read_resources(dev); + + // Find all BARs on GPU, mark them above 4g if prefetchable + for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { + struct resource *res = probe_resource(dev, bar); + + if (res) { + if (res->flags & IORESOURCE_PREFETCH) { + printk(BIOS_INFO, " BAR at 0x%02x marked above 4g\n", bar); + res->flags |= IORESOURCE_ABOVE_4G; + } else { + printk(BIOS_DEBUG, " BAR at 0x%02x not prefetch\n", bar); + } + } else { + printk(BIOS_DEBUG, " BAR at 0x%02x not found\n", bar); + } + } +} + +static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) +{ + pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations nvidia_device_ops_pci = { + .set_subsystem = nvidia_set_subsystem, +}; + +static struct device_operations nvidia_device_ops = { + .read_resources = nvidia_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = pci_rom_write_acpi_tables, + .acpi_fill_ssdt = pci_rom_ssdt, +#endif + .init = pci_dev_init, + .ops_pci = &nvidia_device_ops_pci, + +}; + +static void nvidia_enable(struct device *dev) +{ + if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI) + return; + + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_NVIDIA) + return; + + dev->ops = &nvidia_device_ops; +} + +struct chip_operations drivers_gfx_nvidia_ops = { + CHIP_NAME("NVIDIA Optimus Graphics Device") + .enable_dev = nvidia_enable +}; diff --git a/src/drivers/gfx/nvidia/romstage.c b/src/drivers/gfx/nvidia/romstage.c new file mode 100644 index 00000000000..78fe5ddf503 --- /dev/null +++ b/src/drivers/gfx/nvidia/romstage.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include "chip.h" +#include "gpu.h" + +void nvidia_set_power(const struct nvidia_gpu_config *config) +{ + if (!config->power_gpio || !config->reset_gpio) { + printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__); + return; + } + + printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio); + printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio); + + gpio_set(config->reset_gpio, 0); + mdelay(10); + + if (config->enable) { + gpio_set(config->power_gpio, 1); + mdelay(25); + gpio_set(config->reset_gpio, 1); + } else { + gpio_set(config->power_gpio, 0); + } + + mdelay(10); +} diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig new file mode 100644 index 00000000000..3db3718cdaf --- /dev/null +++ b/src/drivers/intel/dtbt/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_INTEL_DTBT + bool + default n + help + Support for discrete Thunderbolt controllers diff --git a/src/drivers/intel/dtbt/Makefile.inc b/src/drivers/intel/dtbt/Makefile.inc new file mode 100644 index 00000000000..1b5252dda09 --- /dev/null +++ b/src/drivers/intel/dtbt/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h new file mode 100644 index 00000000000..2b1dfa70a52 --- /dev/null +++ b/src/drivers/intel/dtbt/chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_ +#define _DRIVERS_INTEL_DTBT_CHIP_H_ + +struct drivers_intel_dtbt_config {}; + +#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */ diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c new file mode 100644 index 00000000000..603c66eed48 --- /dev/null +++ b/src/drivers/intel/dtbt/dtbt.c @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "chip.h" +#include +#include +#include +#include +#include +#include +#include + +#define PCIE2TBT 0x54C +#define PCIE2TBT_GO2SX ((0x02 << 1) | 1) +#define PCIE2TBT_GO2SX_NO_WAKE ((0x03 << 1) | 1) +#define PCIE2TBT_SX_EXIT_TBT_CONNECTED ((0x04 << 1) | 1) +#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED ((0x05 << 1) | 1) +#define PCIE2TBT_SET_SECURITY_LEVEL ((0x08 << 1) | 1) +#define PCIE2TBT_GET_SECURITY_LEVEL ((0x09 << 1) | 1) +#define PCIE2TBT_BOOT_ON ((0x18 << 1) | 1) +#define TBT2PCIE 0x548 + +static void dtbt_cmd(struct device *dev, u32 command) +{ + printk(BIOS_DEBUG, "DTBT send command %08x\n", command); + + pci_write_config32(dev, PCIE2TBT, command); + + u32 timeout; + u32 status; + for (timeout = 1000000; timeout > 0; timeout--) { + status = pci_read_config32(dev, TBT2PCIE); + if (status & 1) { + break; + } + udelay(1); + } + if (timeout == 0) { + printk(BIOS_ERR, "DTBT command %08x timeout on status %08x\n", command, status); + } + + printk(BIOS_DEBUG, "DTBT command %08x status %08x\n", command, status); + + pci_write_config32(dev, PCIE2TBT, 0); + + u32 status_clear; + for (timeout = 1000000; timeout > 0; timeout--) { + status_clear = pci_read_config32(dev, TBT2PCIE); + if (!(status_clear & 1)) { + break; + } + udelay(1); + } + if (timeout == 0) { + printk(BIOS_ERR, "DTBT command %08x timeout on status clear %08x\n", command, status_clear); + } +} + +static void dtbt_fill_ssdt(const struct device *dev) +{ + printk(BIOS_DEBUG, "DTBT fill SSDT\n"); + + if (!dev) { + printk(BIOS_ERR, "DTBT device invalid\n"); + } + printk(BIOS_DEBUG, " Dev %s\n", dev_path(dev)); + + struct bus *bus = dev->bus; + if (!bus) { + printk(BIOS_ERR, "DTBT bus invalid\n"); + } + printk(BIOS_DEBUG, " Bus %s\n", bus_path(bus)); + + struct device *parent = bus->dev; + if (!parent || parent->path.type != DEVICE_PATH_PCI) { + printk(BIOS_ERR, "DTBT parent invalid\n"); + return; + } + printk(BIOS_DEBUG, " Parent %s\n", dev_path(parent)); + + const char *parent_scope = acpi_device_path(parent); + if (!parent_scope) { + printk(BIOS_ERR, "DTBT parent scope not valid\n"); + return; + } + + { /* Scope */ + printk(BIOS_DEBUG, " Scope %s\n", parent_scope); + acpigen_write_scope(parent_scope); + + struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + + /* Indicate that device supports hotplug in D3. */ + acpi_device_add_hotplug_support_in_d3(dsd); + + /* Indicate that port is external. */ + acpi_device_add_external_facing_port(dsd); + + acpi_dp_write(dsd); + + { /* Device */ + const char *dev_name = acpi_device_name(dev); + printk(BIOS_DEBUG, " Device %s\n", dev_name); + acpigen_write_device(dev_name); + + acpigen_write_name_integer("_ADR", 0); + + uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS + + (((uintptr_t)(bus->secondary)) << 20); + printk(BIOS_DEBUG, " MMCONF base %08lx\n", mmconf_base); + const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000); + const struct fieldlist fieldlist[] = { + FIELDLIST_OFFSET(TBT2PCIE), + FIELDLIST_NAMESTR("TB2P", 32), + FIELDLIST_OFFSET(PCIE2TBT), + FIELDLIST_NAMESTR("P2TB", 32), + }; + acpigen_write_opregion(&opregion); + acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + { /* Method */ + acpigen_write_method_serialized("PTS", 0); + + acpigen_write_debug_string("DTBT prepare to sleep"); + + acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE, "P2TB"); + acpigen_write_delay_until_namestr_int(600, "TB2P", PCIE2TBT_GO2SX_NO_WAKE); + + acpigen_write_debug_namestr("TB2P"); + + acpigen_write_store_int_to_namestr(0, "P2TB"); + acpigen_write_delay_until_namestr_int(600, "TB2P", 0); + + acpigen_write_debug_namestr("TB2P"); + + acpigen_write_method_end(); + } + + acpigen_write_device_end(); + } + + acpigen_write_scope_end(); + } + + { /* Scope */ + acpigen_write_scope("\\"); + + { /* Method */ + acpigen_write_method("TBTS", 0); + + acpigen_emit_namestring(acpi_device_path_join(dev, "PTS")); + + acpigen_write_method_end(); + } + + acpigen_write_scope_end(); + } +} + +static const char *dtbt_acpi_name(const struct device *dev) +{ + return "DTBT"; +} + +static struct pci_operations dtbt_device_ops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations dtbt_device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .acpi_fill_ssdt = dtbt_fill_ssdt, + .acpi_name = dtbt_acpi_name, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &dtbt_device_ops_pci, +}; + +static void dtbt_enable(struct device *dev) +{ + if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI) + return; + + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL) + return; + + // TODO: check device ID + + dev->ops = &dtbt_device_ops; + + printk(BIOS_INFO, "DTBT controller found at %s\n", dev_path(dev)); + + printk(BIOS_DEBUG, "DTBT get security level\n"); + dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL); + + printk(BIOS_DEBUG, "DTBT set security level SL0\n"); + dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL); + + printk(BIOS_DEBUG, "DTBT get security level\n"); + dtbt_cmd(dev, PCIE2TBT_GET_SECURITY_LEVEL); + + if (acpi_is_wakeup_s3()) { + printk(BIOS_INFO, "DTBT SX exit\n"); + dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED); + } else { + printk(BIOS_INFO, "DTBT boot on\n"); + dtbt_cmd(dev, PCIE2TBT_BOOT_ON); + } +} + +struct chip_operations drivers_intel_dtbt_ops = { + CHIP_NAME("Intel Discrete Thunderbolt Device") + .enable_dev = dtbt_enable +}; diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c index ef80e221bc0..d0eeeb69003 100644 --- a/src/drivers/smmstore/ramstage.c +++ b/src/drivers/smmstore/ramstage.c @@ -8,6 +8,7 @@ #include #include #include +#include static struct smmstore_params_info info; @@ -39,6 +40,7 @@ static void init_store(void *unused) struct smmstore_params_init args; uint32_t eax = ~0; uint32_t ebx; + uint8_t retry = 5; if (smmstore_get_info(&info) < 0) { printk(BIOS_INFO, "SMMSTORE: Failed to get meta data\n"); @@ -57,14 +59,24 @@ static void init_store(void *unused) printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n"); - /* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */ - __asm__ __volatile__ ( - "outb %%al, %%dx" - : "=a" (eax) - : "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE), - "b" (ebx), - "d" (APM_CNT) - : "memory"); + /* + * Issue SMI using APM to update the com buffer and to lock the SMMSTORE. + * Retry 5 times in case the SMI isn't triggered immediately. + */ + do { + __asm__ __volatile__ ( + "outb %%al, %%dx" + : "=a" (eax) + : "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE), + "b" (ebx), + "d" (APM_CNT) + : "memory"); + + if (eax == SMMSTORE_RET_SUCCESS) + break; + + mdelay(1); + } while (retry--); if (eax != SMMSTORE_RET_SUCCESS) { printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n"); diff --git a/src/ec/system76/ec/Kconfig b/src/ec/system76/ec/Kconfig index d1cd079f1da..efcb1dfb33a 100644 --- a/src/ec/system76/ec/Kconfig +++ b/src/ec/system76/ec/Kconfig @@ -13,6 +13,11 @@ config EC_SYSTEM76_EC_DGPU bool default n +config EC_SYSTEM76_EC_LOCKDOWN + depends on EC_SYSTEM76_EC + bool + default n + config EC_SYSTEM76_EC_OLED depends on EC_SYSTEM76_EC bool diff --git a/src/ec/system76/ec/Makefile.inc b/src/ec/system76/ec/Makefile.inc index 9808e297d66..02fcda537ce 100644 --- a/src/ec/system76/ec/Makefile.inc +++ b/src/ec/system76/ec/Makefile.inc @@ -4,6 +4,7 @@ ifeq ($(CONFIG_EC_SYSTEM76_EC),y) all-y += system76_ec.c ramstage-y += smbios.c +ramstage-$(CONFIG_EC_SYSTEM76_EC_LOCKDOWN) += lockdown.c smm-$(CONFIG_DEBUG_SMI) += system76_ec.c diff --git a/src/ec/system76/ec/acpi/s76.asl b/src/ec/system76/ec/acpi/s76.asl index 329c5d32464..15c6e6a184a 100644 --- a/src/ec/system76/ec/acpi/s76.asl +++ b/src/ec/system76/ec/acpi/s76.asl @@ -153,6 +153,24 @@ Device (S76D) { Return ((Local1 << 8) | Local0) } + // Set Fan speed + Method (SFD0, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = Zero + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCE + } + } +#if CONFIG(EC_SYSTEM76_EC_DGPU) + Method (SFD1, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = Zero + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCF + } + } +#endif // CONFIG(EC_SYSTEM76_EC_DGPU) + // Temperature names Method (NTMP, 0, Serialized) { Return (Package() { diff --git a/src/ec/system76/ec/lockdown.c b/src/ec/system76/ec/lockdown.c new file mode 100644 index 00000000000..d6f52f41021 --- /dev/null +++ b/src/ec/system76/ec/lockdown.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "system76_ec.h" +#include +#include +#include +#include + +static int protect_region_by_name(const char *name) +{ + int res; + struct region region; + + res = fmap_locate_area(name, ®ion); + if (res < 0) { + printk(BIOS_ERR, "fmap_locate_area '%s' failed: %d\n", name, res); + return res; + } + + res = spi_flash_ctrlr_protect_region( + boot_device_spi_flash(), + ®ion, + WRITE_PROTECT + ); + if (res < 0) { + printk(BIOS_ERR, "spi_flash_ctrlr_protect_region '%s' failed: %d\n", name, res); + return res; + } + + printk(BIOS_INFO, "protected '%s'\n", name); + return 0; +} + +static void lock(void *unused) +{ + uint8_t state = SYSTEM76_EC_SECURITY_STATE_UNLOCK; + if (!system76_ec_security_get(&state)) { + printk(BIOS_INFO, "failed to get security state, assuming unlocked\n"); + state = SYSTEM76_EC_SECURITY_STATE_UNLOCK; + } + + printk(BIOS_INFO, "security state: %d\n", state); + if (state != SYSTEM76_EC_SECURITY_STATE_UNLOCK) { + // Protect WP_RO region, which should contain FMAP and COREBOOT + protect_region_by_name("WP_RO"); + // Protect RW_MRC_CACHE region, this must be done after it is written + protect_region_by_name("RW_MRC_CACHE"); + //TODO: protect entire flash except when in SMM? + } +} + +/* + * Keep in sync with mrc_cache.c + */ +#if CONFIG(MRC_WRITE_NV_LATE) +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, lock, NULL); +#else +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL); +#endif diff --git a/src/ec/system76/ec/system76_ec.c b/src/ec/system76/ec/system76_ec.c index 828376d0e5c..ee41b1e8d72 100644 --- a/src/ec/system76/ec/system76_ec.c +++ b/src/ec/system76/ec/system76_ec.c @@ -26,6 +26,9 @@ #define CMD_PRINT_REG_LEN 3 #define CMD_PRINT_REG_DATA 4 +// Get security state command +#define CMD_SECURITY_GET 20 + static inline uint8_t system76_ec_read(uint8_t addr) { return inb(SYSTEM76_EC_BASE + (uint16_t)addr); @@ -110,3 +113,9 @@ bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data, return ret; } + +bool system76_ec_security_get(uint8_t *state) +{ + *state = SYSTEM76_EC_SECURITY_STATE_LOCK; + return system76_ec_cmd(CMD_SECURITY_GET, NULL, 0, state, sizeof(*state)); +} diff --git a/src/ec/system76/ec/system76_ec.h b/src/ec/system76/ec/system76_ec.h index 9675bd0cafc..6c91bb6aec6 100644 --- a/src/ec/system76/ec/system76_ec.h +++ b/src/ec/system76/ec/system76_ec.h @@ -6,6 +6,15 @@ #include #include +// Default value, flashing is prevented, cannot be set with CMD_SECURITY_SET +#define SYSTEM76_EC_SECURITY_STATE_LOCK 0 +// Flashing is allowed, cannot be set with CMD_SECURITY_SET +#define SYSTEM76_EC_SECURITY_STATE_UNLOCK 1 +// Flashing will be prevented on the next reboot +#define SYSTEM76_EC_SECURITY_STATE_PREPARE_LOCK 2 +// Flashing will be allowed on the next reboot +#define SYSTEM76_EC_SECURITY_STATE_PREPARE_UNLOCK 3 + /* * Send a command to the EC. request_data/request_size are the request payload, * request_data can be NULL if request_size is 0. reply_data/reply_size are @@ -14,4 +23,6 @@ bool system76_ec_cmd(uint8_t cmd, const uint8_t *request_data, uint8_t request_size, uint8_t *reply_data, uint8_t reply_size); +bool system76_ec_security_get(uint8_t *state); + #endif diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index d0cdefcac14..3ad9a287ab4 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -35,6 +35,18 @@ #define DDR4_SPD_PART_OFF 329 #define DDR4_SPD_PART_LEN 20 #define DDR4_SPD_SN_OFF 325 +#define MAX_SPD_PAGE_SIZE_SPD5 128 +#define MAX_SPD_SIZE (SPD_PAGE_LEN * SPD_SN_LEN) +#define SPD_HUB_MEMREG(addr) ((u8)(0x80 | (addr))) +#define SPD5_MR11 0x0B +#define SPD5_MR0 0x00 +#define SPD5_MEMREG_REG(addr) ((u8)((~0x80) & (addr))) +#define SPD5_MR0_SPD5_HUB_DEV 0x51 + +struct spd_offset_table { + u16 start; /* Offset 0 */ + u16 end; /* Offset 2 */ +}; struct spd_block { u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index dff6ede8609..123c1819ce3 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -209,7 +209,7 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk) dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE); - if (dram_type == SPD_DRAM_DDR4) + if (dram_type == SPD_DRAM_DDR4 || dram_type == SPD_DRAM_DDR5) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; diff --git a/src/mainboard/system76/addw1/Kconfig b/src/mainboard/system76/addw1/Kconfig index f4c86233b2d..5fa51fcfef5 100644 --- a/src/mainboard/system76/addw1/Kconfig +++ b/src/mainboard/system76/addw1/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC diff --git a/src/mainboard/system76/addw1/Makefile.inc b/src/mainboard/system76/addw1/Makefile.inc index 09424595d72..1447b6a87f5 100644 --- a/src/mainboard/system76/addw1/Makefile.inc +++ b/src/mainboard/system76/addw1/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/addw1/acpi/mainboard.asl b/src/mainboard/system76/addw1/acpi/mainboard.asl index 4e67439c569..2f01acc0bc4 100644 --- a/src/mainboard/system76/addw1/acpi/mainboard.asl +++ b/src/mainboard/system76/addw1/acpi/mainboard.asl @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x03 /* GPP_K3 */ #define EC_GPE_SWI 0x06 /* GPP_K6 */ #include Scope (\_SB) { #include "sleep.asl" + Scope (PCI0) { + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } + } } Scope (\_GPE) { diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 529767c5683..f962bb3ca85 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -56,6 +56,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on # SA Thermal device diff --git a/src/mainboard/system76/addw1/romstage.c b/src/mainboard/system76/addw1/romstage.c index 02634ba2ad2..fdb208b88db 100644 --- a/src/mainboard/system76/addw1/romstage.c +++ b/src/mainboard/system76/addw1/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include static const struct cnl_mb_cfg memcfg = { .spd[0] = { @@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/system76/tgl-h/include/variant/gpio.h b/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h similarity index 53% rename from src/mainboard/system76/tgl-h/include/variant/gpio.h rename to src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h index 95d576294f6..c78f11b4cd0 100644 --- a/src/mainboard/system76/tgl-h/include/variant/gpio.h +++ b/src/mainboard/system76/addw1/variants/addw1/include/variant/gpio.h @@ -3,7 +3,16 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_C12 +#define DGPU_SSID 0x65d11558 + +#ifndef __ACPI__ void variant_configure_early_gpios(void); void variant_configure_gpios(void); +#endif #endif diff --git a/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h b/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h new file mode 100644 index 00000000000..321cd435271 --- /dev/null +++ b/src/mainboard/system76/addw1/variants/addw2/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_C12 +#define DGPU_SSID 0x65e11558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 17e9849e12a..af9e94be9f4 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -8,6 +8,7 @@ config BOARD_SYSTEM76_ADL_COMMON select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -33,10 +34,12 @@ config BOARD_SYSTEM76_GALP6 config BOARD_SYSTEM76_GAZE17_3050 select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA select EC_SYSTEM76_EC_DGPU config BOARD_SYSTEM76_GAZE17_3060_B select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA select EC_SYSTEM76_EC_DGPU select MAINBOARD_USES_IFD_GBE_REGION @@ -46,11 +49,15 @@ config BOARD_SYSTEM76_LEMP11 config BOARD_SYSTEM76_ORYP9 select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC_DGPU config BOARD_SYSTEM76_ORYP10 select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ADL_COMMON @@ -95,6 +102,10 @@ config MAINBOARD_VERSION default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8 + default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" + config CONSOLE_POST default y @@ -104,6 +115,12 @@ config D3COLD_SUPPORT config DIMM_SPD_SIZE default 512 +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP + default 45 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX + default 25 if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/system76/adl/Makefile.inc b/src/mainboard/system76/adl/Makefile.inc index c5334f1f0cf..727ce27218c 100644 --- a/src/mainboard/system76/adl/Makefile.inc +++ b/src/mainboard/system76/adl/Makefile.inc @@ -2,6 +2,10 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +endif + bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/adl/acpi/mainboard.asl b/src/mainboard/system76/adl/acpi/mainboard.asl index c982a9ee4cb..f7453fc339e 100644 --- a/src/mainboard/system76/adl/acpi/mainboard.asl +++ b/src/mainboard/system76/adl/acpi/mainboard.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(DRIVERS_GFX_NVIDIA) +#include +#endif + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +12,11 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + +#if CONFIG(DRIVERS_GFX_NVIDIA) + Scope (PEG2) { + #include + } +#endif } } diff --git a/src/mainboard/system76/adl/cmos-csme.default b/src/mainboard/system76/adl/cmos-csme.default new file mode 100644 index 00000000000..62715bc6bab --- /dev/null +++ b/src/mainboard/system76/adl/cmos-csme.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 05d6a4504c6..b50c5f85383 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/alderlake + register "s0ix_enable" = "1" + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56, diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h b/src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h new file mode 100644 index 00000000000..5c2c0635fad --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3050/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x866d1558 + +#endif diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb index 880bb275148..785a020da7c 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb @@ -38,6 +38,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref pcie4_0 on # PCIe PEG0 x4, Clock 0 (SSD2) diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c index 5e6cf7dd52a..cea4ff51551 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c +++ b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h b/src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h new file mode 100644 index 00000000000..6bf3550d25f --- /dev/null +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x867c1558 + +#endif diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb index 90bd5c18a0b..dcf60b50cfa 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb @@ -38,6 +38,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref igpu on # DDIA is eDP diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c index 5e6cf7dd52a..cea4ff51551 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h b/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h new file mode 100644 index 00000000000..489487ba7b1 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_GC6 GPP_A7 +#define DGPU_SSID 0x65f51558 + +#endif diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb index efebe7af91d..fd05663f571 100644 --- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -23,6 +23,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref igpu on register "ddi_portA_config" = "1" diff --git a/src/mainboard/system76/adl/variants/oryp10/romstage.c b/src/mainboard/system76/adl/variants/oryp10/romstage.c index 48714e0c854..082d0cbd10d 100644 --- a/src/mainboard/system76/adl/variants/oryp10/romstage.c +++ b/src/mainboard/system76/adl/variants/oryp10/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -20,6 +22,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h b/src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h new file mode 100644 index 00000000000..489487ba7b1 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp9/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_GC6 GPP_A7 +#define DGPU_SSID 0x65f51558 + +#endif diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb index 2f79c9edeb6..2738abfbf6d 100644 --- a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb @@ -23,6 +23,10 @@ chip soc/intel/alderlake .clk_req = 3, .flags = PCIE_RP_LTR, }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + end end device ref igpu on register "ddi_portA_config" = "1" diff --git a/src/mainboard/system76/adl/variants/oryp9/romstage.c b/src/mainboard/system76/adl/variants/oryp9/romstage.c index d16b4f8b038..201fc75f37b 100644 --- a/src/mainboard/system76/adl/variants/oryp9/romstage.c +++ b/src/mainboard/system76/adl/variants/oryp9/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -17,6 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/bonw14/Kconfig b/src/mainboard/system76/bonw14/Kconfig index 4478a236563..2fdbb84663f 100644 --- a/src/mainboard/system76/bonw14/Kconfig +++ b/src/mainboard/system76/bonw14/Kconfig @@ -5,7 +5,9 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID + select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC select EC_SYSTEM76_EC_DGPU select HAVE_ACPI_RESUME diff --git a/src/mainboard/system76/bonw14/Makefile.inc b/src/mainboard/system76/bonw14/Makefile.inc index 2efcac5f428..89b8816938e 100644 --- a/src/mainboard/system76/bonw14/Makefile.inc +++ b/src/mainboard/system76/bonw14/Makefile.inc @@ -10,3 +10,4 @@ romstage-y += romstage.c ramstage-y += ramstage.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += tas5825m.c diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index d79aa766592..44f9d5fbd44 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -59,11 +59,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU) register "PcieClkSrcUsage[7]" = "0x40" register "PcieClkSrcClkReq[7]" = "7" - - device pci 00.0 on end # VGA controller - device pci 00.1 on end # Audio device - device pci 00.2 on end # USB xHCI Host controller - device pci 00.3 on end # USB Type-C UCSI controller + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end # TODO: is this enough to disable iGPU? device pci 02.0 off end # Integrated Graphics Device @@ -219,7 +220,16 @@ chip soc/intel/cannonlake device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" end - device pci 1f.4 on end # SMBus + device pci 1f.4 on # SMBus + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end # (8bit address: 0x9c) + end + chip drivers/i2c/tas5825m + register "id" = "1" + device i2c 4f on end # (8bit address: 0x9e) + end + end device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE end diff --git a/src/mainboard/system76/bonw14/tas5825m-normal.c b/src/mainboard/system76/bonw14/tas5825m-normal.c new file mode 100644 index 00000000000..81695effd80 --- /dev/null +++ b/src/mainboard/system76/bonw14/tas5825m-normal.c @@ -0,0 +1,1240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +static int tas5825m_setup_normal(struct device *dev) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x7C); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x0C, 0xCC, 0xCD, + 0x00, 0x0C, 0xCC, 0xCD, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xA9, 0x15, 0xB8, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x01, 0x33, 0x51, 0x50, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85, + 0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E, + 0xF8, 0x5C, 0x9F, 0x28, 0x07, 0xD1, 0x27, 0x3E, + 0xF0, 0x5D, 0xB1, 0x85, 0x07, 0xD1, 0x27, 0x3E, + 0x0F, 0xA1, 0x3C, 0x1E, 0xF8, 0x5C, 0x9F, 0x28, + 0x08, 0x00, 0x00, 0x00, 0xF0, 0x71, 0x4C, 0x87, + 0x07, 0x91, 0xC6, 0x22, 0x0F, 0x8E, 0xB3, 0x79, + 0xF8, 0x6E, 0x39, 0xDE, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7, 0x0B, + 0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08, 0xF5, + 0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58, 0xFE, 0x57, + 0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4, 0x51, 0x2E, + 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2, 0xB0, 0x7B, + 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE, 0x92, 0xE5, + 0xFE, 0xEA, 0x2A, 0xF4, 0x05, 0x41, 0x6D, 0x1B, + 0xFE, 0x8A, 0x4B, 0xFE, 0x09, 0x6F, 0x71, 0xB3, + 0xF4, 0xC9, 0x2E, 0xBA, 0x02, 0xE0, 0x4E, 0xFB, + 0x0B, 0x36, 0xD1, 0x46, 0xFB, 0xB0, 0x3F, 0x52, + 0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50, 0x29, 0xD7, + 0x05, 0x3A, 0xF8, 0x0F, 0x0C, 0xAF, 0xD6, 0x29, + 0xFB, 0x3E, 0x46, 0x00, 0x08, 0x17, 0x5D, 0x4C, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x34, 0x29, 0xCB, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFC, 0xDB, 0x0F, 0xF0, 0x3A, 0xC4, 0xBE, + 0x07, 0xC9, 0x51, 0x50, 0x0F, 0xC5, 0x3B, 0x42, + 0xF8, 0x39, 0xD3, 0xA1, 0x07, 0xFC, 0x38, 0xBF, + 0xF0, 0x47, 0x14, 0xF2, 0x07, 0xBE, 0x4A, 0x80, + 0x0F, 0xB8, 0xEB, 0x0E, 0xF8, 0x45, 0x7C, 0xC1, + 0x07, 0xEB, 0xF6, 0xEF, 0xF1, 0x08, 0x7E, 0x56, + 0x07, 0x17, 0x63, 0xC3, 0x0E, 0xF7, 0x81, 0xAA, + 0xF8, 0xFC, 0xA5, 0x4E, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xD1, 0x27, 0x3E, + 0xF0, 0x5D, 0xB1, 0x85, 0x07, 0xD1, 0x27, 0x3E, + 0x0F, 0xA1, 0x3C, 0x1E, 0xF8, 0x5C, 0x9F, 0x28, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85, + 0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E, + 0xF8, 0x5C, 0x9F, 0x28, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0x71, 0x4C, 0x87, 0x07, 0x91, 0xC6, 0x22, + 0x0F, 0x8E, 0xB3, 0x79, 0xF8, 0x6E, 0x39, 0xDE, + 0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7, 0x0B, + 0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08, 0xF5, + 0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58, 0xFE, 0x57, + 0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4, 0x51, 0x2E, + 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2, 0xB0, 0x7B, + 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE, 0x92, 0xE5, + 0xFE, 0xEA, 0x2A, 0xF4, 0x05, 0x41, 0x6D, 0x1B, + 0xFE, 0x8A, 0x4B, 0xFE, 0x09, 0x6F, 0x71, 0xB3, + 0xF4, 0xC9, 0x2E, 0xBA, 0x02, 0xE0, 0x4E, 0xFB, + 0x0B, 0x36, 0xD1, 0x46, 0xFB, 0xB0, 0x3F, 0x52, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50, 0x29, 0xD7, + 0x05, 0x3A, 0xF8, 0x0F, 0x0C, 0xAF, 0xD6, 0x29, + 0xFB, 0x3E, 0x46, 0x00, 0x08, 0x17, 0x5D, 0x4C, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x34, 0x29, 0xCB, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x07, 0xFB, 0x25, 0x84, 0xF0, 0x49, 0xA3, 0xCE, + 0x07, 0xC7, 0xA6, 0xCB, 0x0F, 0xB6, 0x5C, 0x32, + 0xF8, 0x3D, 0x33, 0xB1, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x86, 0x43, 0x99, 0xFF, 0x02, 0xE6, 0x50, + 0x00, 0x77, 0xAC, 0xFD, 0x0F, 0xD7, 0xE6, 0xBF, + 0xF8, 0x27, 0x42, 0x5B + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x64, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4E, 0xBB); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4F, 0xB0); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/system76/bonw14/tas5825m-sub.c b/src/mainboard/system76/bonw14/tas5825m-sub.c new file mode 100644 index 00000000000..28987d9be20 --- /dev/null +++ b/src/mainboard/system76/bonw14/tas5825m-sub.c @@ -0,0 +1,1240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +static int tas5825m_setup_sub(struct device *dev) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x04); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x7C); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x29, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0xFD, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x5A, 0x84, + 0x00, 0x1E, 0x5A, 0x84, 0x00, 0x40, 0x26, 0xE7, + 0x00, 0x40, 0x26, 0xE7, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xEB, 0x8F, 0xA8, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x01, 0xEB, 0x55, 0xAC, + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x01, 0x0A, 0x7A, 0x00, 0x02, 0x14, 0xF5, + 0x00, 0x01, 0x0A, 0x7A, 0x0F, 0x7B, 0xDB, 0x58, + 0xF8, 0x7F, 0xFA, 0xBE, 0x00, 0x01, 0x0A, 0x7A, + 0x00, 0x02, 0x14, 0xF5, 0x00, 0x01, 0x0A, 0x7A, + 0x0F, 0x7B, 0xDB, 0x58, 0xF8, 0x7F, 0xFA, 0xBE, + 0x07, 0xFD, 0xF9, 0x62, 0xF0, 0x25, 0x7A, 0x1B, + 0x07, 0xDC, 0xC4, 0xC6, 0x0F, 0xDA, 0x85, 0xE5, + 0xF8, 0x25, 0x41, 0xD8, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF7, 0xFF, 0xB5, 0xF0, 0x4F, 0x8C, 0x33, + 0x07, 0xBA, 0x32, 0x37, 0x0F, 0xB0, 0x73, 0xCD, + 0xF8, 0x4D, 0xCE, 0x15, 0x07, 0xFA, 0x6B, 0x45, + 0xF0, 0x68, 0xC7, 0x1B, 0x07, 0x9E, 0xF0, 0xFB, + 0x0F, 0x97, 0x38, 0xE5, 0xF8, 0x66, 0xA3, 0xC0, + 0x07, 0xFE, 0x8C, 0x9C, 0xF0, 0x34, 0xCF, 0xDE, + 0x07, 0xCD, 0x94, 0xFF, 0x0F, 0xCB, 0x30, 0x22, + 0xF8, 0x33, 0xDE, 0x65, 0x07, 0xFE, 0x73, 0xDB, + 0xF0, 0x38, 0x93, 0x60, 0x07, 0xCA, 0x38, 0xAE, + 0x0F, 0xC7, 0x6C, 0xA0, 0xF8, 0x37, 0x53, 0x77, + 0x07, 0xF8, 0xC1, 0xBE, 0xF0, 0x88, 0xCB, 0x7D, + 0x07, 0x82, 0x08, 0xA9, 0x0F, 0x77, 0x34, 0x83, + 0xF8, 0x85, 0x35, 0x99, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4, + 0xF0, 0x22, 0x72, 0x97, 0x07, 0xEE, 0xC6, 0xB4, + 0x0F, 0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C, 0xCB, + 0x07, 0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67, 0xAD, + 0x07, 0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98, 0x53, + 0xF8, 0x33, 0xBE, 0x30, 0x08, 0x13, 0x15, 0xCB, + 0xF0, 0x0E, 0xB9, 0x1C, 0x07, 0xDE, 0xDC, 0x2A, + 0x0F, 0xF1, 0x86, 0x85, 0xF8, 0x0E, 0x4D, 0xAB, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xEE, 0xC6, 0xB4, 0xF0, 0x22, 0x72, 0x97, + 0x07, 0xEE, 0xC6, 0xB4, 0x0F, 0xDD, 0x77, 0x9C, + 0xF8, 0x22, 0x5C, 0xCB, 0x07, 0xF4, 0x93, 0x76, + 0xF0, 0x34, 0x67, 0xAD, 0x07, 0xD7, 0xAE, 0x5A, + 0x0F, 0xCB, 0x98, 0x53, 0xF8, 0x33, 0xBE, 0x30, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x13, 0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C, + 0x07, 0xDE, 0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85, + 0xF8, 0x0E, 0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x85, 0xC0, 0x8D, 0xFF, 0x02, 0x2B, 0x75, + 0x00, 0x78, 0xBE, 0x6E, 0x0F, 0xE2, 0x46, 0xF6, + 0xF8, 0x1D, 0x0E, 0x9A + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xAA, 0xC3, + 0xFF, 0xFD, 0x55, 0x85, 0xFF, 0xFE, 0xAA, 0xC3, + 0x0F, 0x2F, 0x01, 0x62, 0xF8, 0xCB, 0xA9, 0xA8, + 0x07, 0x98, 0xD5, 0xEF, 0xF0, 0xCE, 0x54, 0x23, + 0x07, 0x98, 0xD5, 0xEF, 0x0F, 0x2F, 0x01, 0x62, + 0xF8, 0xCB, 0xA9, 0xA8, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x64, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4E, 0xBB); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4F, 0xB0); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/system76/bonw14/tas5825m.c b/src/mainboard/system76/bonw14/tas5825m.c new file mode 100644 index 00000000000..95680fae92d --- /dev/null +++ b/src/mainboard/system76/bonw14/tas5825m.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "tas5825m-normal.c" +#include "tas5825m-sub.c" + +int tas5825m_setup(struct device *dev, int id) +{ + if (id == 0) + return tas5825m_setup_normal(dev); + if (id == 1) + return tas5825m_setup_sub(dev); + return -1; +} diff --git a/src/mainboard/system76/gaze15/Kconfig b/src/mainboard/system76/gaze15/Kconfig index da34ed63a99..ccd606192cf 100644 --- a/src/mainboard/system76/gaze15/Kconfig +++ b/src/mainboard/system76/gaze15/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select EC_SYSTEM76_EC select EC_SYSTEM76_EC_DGPU diff --git a/src/mainboard/system76/gaze15/Makefile.inc b/src/mainboard/system76/gaze15/Makefile.inc index 72f13667d31..ab7df6c275e 100644 --- a/src/mainboard/system76/gaze15/Makefile.inc +++ b/src/mainboard/system76/gaze15/Makefile.inc @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/gaze15/acpi/mainboard.asl b/src/mainboard/system76/gaze15/acpi/mainboard.asl index b235437c25d..610cdd12bad 100644 --- a/src/mainboard/system76/gaze15/acpi/mainboard.asl +++ b/src/mainboard/system76/gaze15/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x03 /* GPP_K3 */ #define EC_GPE_SWI 0x06 /* GPP_K6 */ #include @@ -8,6 +10,10 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } } } diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 4ae412d1556..8d4d0fdf40f 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -55,6 +55,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" diff --git a/src/mainboard/system76/gaze15/romstage.c b/src/mainboard/system76/gaze15/romstage.c index 02634ba2ad2..fdb208b88db 100644 --- a/src/mainboard/system76/gaze15/romstage.c +++ b/src/mainboard/system76/gaze15/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include static const struct cnl_mb_cfg memcfg = { .spd[0] = { @@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h b/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h new file mode 100644 index 00000000000..d1647fc437d --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze14/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x85501558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h b/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h new file mode 100644 index 00000000000..0bfd82ed799 --- /dev/null +++ b/src/mainboard/system76/gaze15/variants/gaze15/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x85201558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/oryp5/Kconfig b/src/mainboard/system76/oryp5/Kconfig index e01bac6634d..17fdc91e5ed 100644 --- a/src/mainboard/system76/oryp5/Kconfig +++ b/src/mainboard/system76/oryp5/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC diff --git a/src/mainboard/system76/oryp5/acpi/mainboard.asl b/src/mainboard/system76/oryp5/acpi/mainboard.asl index 17d2221ab4c..f816e3f2dad 100644 --- a/src/mainboard/system76/oryp5/acpi/mainboard.asl +++ b/src/mainboard/system76/oryp5/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x17 /* GPP_B23 */ #define EC_GPE_SWI 0x26 /* GPP_G6 */ #include @@ -9,6 +11,10 @@ Scope (\_SB) #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } } } diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index f17862f4af9..30d8242eaa2 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -63,6 +63,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" diff --git a/src/mainboard/system76/oryp5/include/mainboard/gpio.h b/src/mainboard/system76/oryp5/include/mainboard/gpio.h index c6393beebb6..2bfbd100afb 100644 --- a/src/mainboard/system76/oryp5/include/mainboard/gpio.h +++ b/src/mainboard/system76/oryp5/include/mainboard/gpio.h @@ -3,7 +3,16 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_C12 +#define DGPU_SSID 0x95e61558 + +#ifndef __ACPI__ void mainboard_configure_early_gpios(void); void mainboard_configure_gpios(void); +#endif #endif diff --git a/src/mainboard/system76/oryp5/romstage.c b/src/mainboard/system76/oryp5/romstage.c index 455a2bb9196..ec24f532b23 100644 --- a/src/mainboard/system76/oryp5/romstage.c +++ b/src/mainboard/system76/oryp5/romstage.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include @@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + // Allow memory speeds higher than 2666 MT/s memupd->FspmConfig.SaOcSupport = 1; diff --git a/src/mainboard/system76/oryp6/Kconfig b/src/mainboard/system76/oryp6/Kconfig index f4543eff34d..dd8d62d3f5b 100644 --- a/src/mainboard/system76/oryp6/Kconfig +++ b/src/mainboard/system76/oryp6/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select DRIVERS_I2C_TAS5825M select EC_SYSTEM76_EC diff --git a/src/mainboard/system76/oryp6/Makefile.inc b/src/mainboard/system76/oryp6/Makefile.inc index ab8e965d872..af0b83b615a 100644 --- a/src/mainboard/system76/oryp6/Makefile.inc +++ b/src/mainboard/system76/oryp6/Makefile.inc @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/oryp6/acpi/mainboard.asl b/src/mainboard/system76/oryp6/acpi/mainboard.asl index b235437c25d..610cdd12bad 100644 --- a/src/mainboard/system76/oryp6/acpi/mainboard.asl +++ b/src/mainboard/system76/oryp6/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x03 /* GPP_K3 */ #define EC_GPE_SWI 0x06 /* GPP_K6 */ #include @@ -8,6 +10,10 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Device (PEGP) { + Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16) + #include + } } } diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c0c1b4a12a1..23c9e1cfcd3 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -60,6 +60,12 @@ chip soc/intel/cannonlake # PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU) register "PcieClkSrcUsage[8]" = "0x40" register "PcieClkSrcClkReq[8]" = "8" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end end device pci 02.0 on # Integrated Graphics Device register "gfx" = "GMA_DEFAULT_PANEL(0)" diff --git a/src/mainboard/system76/oryp6/romstage.c b/src/mainboard/system76/oryp6/romstage.c index 8ea791a2d10..44da3d8c463 100644 --- a/src/mainboard/system76/oryp6/romstage.c +++ b/src/mainboard/system76/oryp6/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include #include static const struct cnl_mb_cfg memcfg = { @@ -21,6 +23,18 @@ static const struct cnl_mb_cfg memcfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + variant_configure_fspm(memupd); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); diff --git a/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h b/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h new file mode 100644 index 00000000000..697e1ecf510 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp6/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x50d31558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h new file mode 100644 index 00000000000..6e1d7dfa127 --- /dev/null +++ b/src/mainboard/system76/oryp6/variants/oryp7/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_F22 +#define DGPU_PWR_EN GPP_F23 +#define DGPU_GC6 GPP_K21 +#define DGPU_SSID 0x65e51558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index d654696c00e..ff6d8a19a28 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -6,6 +6,7 @@ config BOARD_SYSTEM76_RPL_COMMON select DRIVERS_GENERIC_CBFS_UUID select DRIVERS_I2C_HID select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -25,6 +26,9 @@ config BOARD_SYSTEM76_RPL_COMMON config BOARD_SYSTEM76_ADDW3 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + select DRIVERS_INTEL_DTBT select EC_SYSTEM76_EC_DGPU select MAINBOARD_USES_IFD_GBE_REGION select PCIEXP_HOTPLUG @@ -32,6 +36,9 @@ config BOARD_SYSTEM76_ADDW3 config BOARD_SYSTEM76_BONW15 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + select DRIVERS_INTEL_DTBT select EC_SYSTEM76_EC_DGPU select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE_PCH_S @@ -48,6 +55,8 @@ config BOARD_SYSTEM76_GALP7 config BOARD_SYSTEM76_GAZE18 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select EC_SYSTEM76_EC_DGPU select SOC_INTEL_ALDERLAKE_PCH_P @@ -59,12 +68,17 @@ config BOARD_SYSTEM76_LEMP12 config BOARD_SYSTEM76_ORYP11 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST select EC_SYSTEM76_EC_DGPU select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES config BOARD_SYSTEM76_SERW13 select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_GFX_NVIDIA + select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST + select DRIVERS_INTEL_DTBT select EC_SYSTEM76_EC_DGPU select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE_PCH_S @@ -117,6 +131,10 @@ config MAINBOARD_VERSION default "oryp11" if BOARD_SYSTEM76_ORYP11 default "serw13" if BOARD_SYSTEM76_SERW13 +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP9 + default "src/mainboard/\$(MAINBOARDDIR)/cmos.default" + config CONSOLE_POST default y @@ -126,6 +144,17 @@ config D3COLD_SUPPORT config DIMM_SPD_SIZE default 512 +config DRIVERS_GFX_NVIDIA_BRIDGE + default 0x02 if BOARD_SYSTEM76_BONW15 + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP + default 45 if BOARD_SYSTEM76_ORYP11 + default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13 + default 80 if BOARD_SYSTEM76_BONW15 + +config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX + default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_SERW13 + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" diff --git a/src/mainboard/system76/rpl/Makefile.inc b/src/mainboard/system76/rpl/Makefile.inc index cf92eb2b437..62c651cdd83 100644 --- a/src/mainboard/system76/rpl/Makefile.inc +++ b/src/mainboard/system76/rpl/Makefile.inc @@ -2,6 +2,10 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +ifeq ($(CONFIG_DRIVERS_GFX_NVIDIA),y) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +endif + bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/rpl/acpi/mainboard.asl b/src/mainboard/system76/rpl/acpi/mainboard.asl index c982a9ee4cb..288522ae9dc 100644 --- a/src/mainboard/system76/rpl/acpi/mainboard.asl +++ b/src/mainboard/system76/rpl/acpi/mainboard.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(DRIVERS_GFX_NVIDIA) +#include +#endif + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +12,17 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + +#if CONFIG(DRIVERS_GFX_NVIDIA) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(BOARD_SYSTEM76_BONW15) + Scope (PEG2) { + #include + } +#else + Scope (PEG1) { + #include + } +#endif +#endif // CONFIG(DRIVERS_GFX_NVIDIA) } } diff --git a/src/mainboard/system76/rpl/cmos-csme.default b/src/mainboard/system76/rpl/cmos-csme.default new file mode 100644 index 00000000000..62715bc6bab --- /dev/null +++ b/src/mainboard/system76/rpl/cmos-csme.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h new file mode 100644 index 00000000000..9ce0d6701c1 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw3/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_GC6 GPP_F8 +#define DGPU_SSID 0xa6711558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb index 9b8d4533f19..05b4bfb571b 100644 --- a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb @@ -101,6 +101,9 @@ chip soc/intel/alderlake .clk_req = 15, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR, }" + chip drivers/intel/dtbt + device pci 00.0 on end + end end device ref pcie_rp25 on diff --git a/src/mainboard/system76/rpl/variants/addw3/romstage.c b/src/mainboard/system76/rpl/variants/addw3/romstage.c index 30a904544cd..3992095a650 100644 --- a/src/mainboard/system76/rpl/variants/addw3/romstage.c +++ b/src/mainboard/system76/rpl/variants/addw3/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h new file mode 100644 index 00000000000..be865bb20dc --- /dev/null +++ b/src/mainboard/system76/rpl/variants/bonw15/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F22 +#define DGPU_GC6 GPP_F8 +#define DGPU_SSID 0x37021558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb index fde40f62454..05b5aac65fb 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb @@ -97,6 +97,9 @@ chip soc/intel/alderlake .clk_req = 15, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR, }" + chip drivers/intel/dtbt + device pci 00.0 on end + end end device ref pcie_rp21 on diff --git a/src/mainboard/system76/rpl/variants/bonw15/romstage.c b/src/mainboard/system76/rpl/variants/bonw15/romstage.c index 30a904544cd..3992095a650 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/romstage.c +++ b/src/mainboard/system76/rpl/variants/bonw15/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb index c3bc2bddaba..8900d339c66 100644 --- a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/alderlake + register "s0ix_enable" = "1" + register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ .tdp_pl1_override = 20, .tdp_pl2_override = 56, @@ -14,6 +16,11 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD2_RST# + register "srcclk_pin" = "0" # SSD2_CLKREQ# + device generic 0 on end + end end device ref pcie4_1 on # CPU RP#3 x4, Clock 4 (SSD1) @@ -22,6 +29,11 @@ chip soc/intel/alderlake .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST# + register "srcclk_pin" = "4" # SSD1_CLKREQ# + device generic 0 on end + end end device ref tbt_pcie_rp0 on end device ref tcss_xhci on diff --git a/src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h new file mode 100644 index 00000000000..612710995c0 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/gaze18/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x56301558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/gaze18/romstage.c b/src/mainboard/system76/rpl/variants/gaze18/romstage.c index 1e597c72a69..2c8a6737bba 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/romstage.c +++ b/src/mainboard/system76/rpl/variants/gaze18/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -19,6 +21,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h new file mode 100644 index 00000000000..070f5518194 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp11/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x66a21558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/oryp11/romstage.c b/src/mainboard/system76/rpl/variants/oryp11/romstage.c index 1e597c72a69..2c8a6737bba 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/romstage.c +++ b/src/mainboard/system76/rpl/variants/oryp11/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -19,6 +21,15 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h b/src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h new file mode 100644 index 00000000000..014f22df511 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/serw13/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_GC6 GPP_A11 +#define DGPU_SSID 0xd5021558 + +#endif diff --git a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb index b261d5923c8..32deed7854f 100644 --- a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb @@ -106,6 +106,9 @@ chip soc/intel/alderlake .clk_req = 15, .flags = PCIE_RP_LTR | PCIE_RP_HOTPLUG, // XXX: AER causes UnsupReq warnings }" + chip drivers/intel/dtbt + device pci 00.0 on end + end end end end diff --git a/src/mainboard/system76/rpl/variants/serw13/romstage.c b/src/mainboard/system76/rpl/variants/serw13/romstage.c index 30a904544cd..f58abadc3d3 100644 --- a/src/mainboard/system76/rpl/variants/serw13/romstage.c +++ b/src/mainboard/system76/rpl/variants/serw13/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -22,6 +24,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + // Set primary display to internal graphics mupd->FspmConfig.PrimaryDisplay = 0; diff --git a/src/mainboard/system76/tgl-h/Kconfig b/src/mainboard/system76/tgl-h/Kconfig index c0a070194f6..bdf45175b09 100644 --- a/src/mainboard/system76/tgl-h/Kconfig +++ b/src/mainboard/system76/tgl-h/Kconfig @@ -6,10 +6,12 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA select DRIVERS_I2C_HID select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP8 select EC_SYSTEM76_EC select EC_SYSTEM76_EC_DGPU + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/system76/tgl-h/Makefile.inc b/src/mainboard/system76/tgl-h/Makefile.inc index 7debd0d8c9c..f2fda437b57 100644 --- a/src/mainboard/system76/tgl-h/Makefile.inc +++ b/src/mainboard/system76/tgl-h/Makefile.inc @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c diff --git a/src/mainboard/system76/tgl-h/acpi/mainboard.asl b/src/mainboard/system76/tgl-h/acpi/mainboard.asl index c982a9ee4cb..1cf2a28bcad 100644 --- a/src/mainboard/system76/tgl-h/acpi/mainboard.asl +++ b/src/mainboard/system76/tgl-h/acpi/mainboard.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +10,8 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" + Scope (PEG1) { + #include + } } } diff --git a/src/mainboard/system76/tgl-h/romstage.c b/src/mainboard/system76/tgl-h/romstage.c index f69bae98eb1..8e304359235 100644 --- a/src/mainboard/system76/tgl-h/romstage.c +++ b/src/mainboard/system76/tgl-h/romstage.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include +#include #include static const struct mb_cfg board_cfg = { @@ -21,9 +23,21 @@ static const struct mem_spd spd_info = { void mainboard_memory_init_params(FSPM_UPD *mupd) { - variant_memory_init_params(mupd); - const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + variant_memory_init_params(mupd); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/addw1/include/variant/gpio.h b/src/mainboard/system76/tgl-h/variants/gaze16-3050/include/variant/gpio.h similarity index 53% rename from src/mainboard/system76/addw1/include/variant/gpio.h rename to src/mainboard/system76/tgl-h/variants/gaze16-3050/include/variant/gpio.h index 95d576294f6..27e1dc3ef30 100644 --- a/src/mainboard/system76/addw1/include/variant/gpio.h +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/include/variant/gpio.h @@ -3,7 +3,16 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H +#include + +#define DGPU_RST_N GPP_F8 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_GC6 GPP_K11 +#define DGPU_SSID 0x50151558 + +#ifndef __ACPI__ void variant_configure_early_gpios(void); void variant_configure_gpios(void); +#endif #endif diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index d03bd2e432b..a9da0b78da6 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -6,15 +6,11 @@ chip soc/intel/tigerlake # PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU) register "PcieClkSrcUsage[0]" = "0x42" register "PcieClkSrcClkReq[0]" = "0" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "0" # GFX_CLKREQ0# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref igpu on diff --git a/src/mainboard/system76/gaze15/include/variant/gpio.h b/src/mainboard/system76/tgl-h/variants/gaze16-3060/include/variant/gpio.h similarity index 53% rename from src/mainboard/system76/gaze15/include/variant/gpio.h rename to src/mainboard/system76/tgl-h/variants/gaze16-3060/include/variant/gpio.h index 95d576294f6..f3f8b01f59e 100644 --- a/src/mainboard/system76/gaze15/include/variant/gpio.h +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/include/variant/gpio.h @@ -3,7 +3,16 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H +#include + +#define DGPU_RST_N GPP_F8 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_GC6 GPP_K11 +#define DGPU_SSID 0x50e11558 + +#ifndef __ACPI__ void variant_configure_early_gpios(void); void variant_configure_gpios(void); +#endif #endif diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index b463fe7b7b4..f13c9d689d3 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -6,15 +6,11 @@ chip soc/intel/tigerlake # PCIe PEG1 x16, Clock 9 (DGPU) register "PcieClkSrcUsage[9]" = "0x41" register "PcieClkSrcClkReq[9]" = "9" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "9" # PEG_CLKREQ# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref igpu on diff --git a/src/mainboard/system76/oryp6/include/variant/gpio.h b/src/mainboard/system76/tgl-h/variants/oryp8/include/variant/gpio.h similarity index 53% rename from src/mainboard/system76/oryp6/include/variant/gpio.h rename to src/mainboard/system76/tgl-h/variants/oryp8/include/variant/gpio.h index 95d576294f6..33333f0b35c 100644 --- a/src/mainboard/system76/oryp6/include/variant/gpio.h +++ b/src/mainboard/system76/tgl-h/variants/oryp8/include/variant/gpio.h @@ -3,7 +3,16 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H +#include + +#define DGPU_RST_N GPP_F8 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_GC6 GPP_K11 +#define DGPU_SSID 0x65f11558 + +#ifndef __ACPI__ void variant_configure_early_gpios(void); void variant_configure_gpios(void); +#endif #endif diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index 6f25d7bb7c0..fa04d717f88 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -19,15 +19,11 @@ chip soc/intel/tigerlake # PCIe PEG1 x16, Clock 9 (DGPU) register "PcieClkSrcUsage[9]" = "0x41" register "PcieClkSrcClkReq[9]" = "9" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "9" # PEG_CLKREQ# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref peg0 on diff --git a/src/mainboard/system76/tgl-u/Kconfig b/src/mainboard/system76/tgl-u/Kconfig index 6cc5d068cbb..97c6c910db3 100644 --- a/src/mainboard/system76/tgl-u/Kconfig +++ b/src/mainboard/system76/tgl-u/Kconfig @@ -6,11 +6,13 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_CBFS_SERIAL select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5 select DRIVERS_I2C_HID select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_GALP5 + select EC_SYSTEM76_EC_LOCKDOWN select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE @@ -71,4 +73,15 @@ config UART_FOR_CONSOLE config USE_PM_ACPI_TIMER default n +# For galp5 with dGPU +if DRIVERS_GFX_NVIDIA + +config ONBOARD_VGA_IS_PRIMARY + default y + +config DRIVERS_GFX_NVIDIA_BRIDGE + default 0x1c + +endif # DRIVERS_GFX_NVIDIA + endif diff --git a/src/mainboard/system76/tgl-u/acpi/mainboard.asl b/src/mainboard/system76/tgl-u/acpi/mainboard.asl index c982a9ee4cb..6adceba1fdd 100644 --- a/src/mainboard/system76/tgl-u/acpi/mainboard.asl +++ b/src/mainboard/system76/tgl-u/acpi/mainboard.asl @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#if CONFIG(BOARD_SYSTEM76_GALP5) +#include +#endif + #define EC_GPE_SCI 0x6E #define EC_GPE_SWI 0x6B #include @@ -8,5 +12,10 @@ Scope (\_SB) { #include "sleep.asl" Scope (PCI0) { #include "backlight.asl" +#if CONFIG(BOARD_SYSTEM76_GALP5) + Scope (RP01) { // Remapped from RP05 + #include + } +#endif } } diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 7c3475e4662..ebc08bbdba1 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -145,15 +145,11 @@ chip soc/intel/tigerlake register "PcieRpLtrEnable[4]" = "1" register "PcieClkSrcUsage[2]" = "4" register "PcieClkSrcClkReq[2]" = "2" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH - register "enable_delay_ms" = "16" - register "enable_off_delay_ms" = "4" - register "reset_delay_ms" = "10" - register "reset_off_delay_ms" = "4" - register "srcclk_pin" = "2" # PEG_CLKREQ# - device generic 0 on end + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller end end device ref pcie_rp9 on diff --git a/src/mainboard/system76/tgl-u/variants/galp5/romstage.c b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c index eb4fd3974bb..e747521789f 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/romstage.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/romstage.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include #include +#include void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -18,5 +19,17 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const bool half_populated = false; + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 80f33d59c69..46a995ddfc7 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -70,6 +70,10 @@ static tpm_result_t tpm_setup_s3_helper(void) default: printk(BIOS_ERR, "TPM: Resume failed (%#x).\n", rc); + if (CONFIG(TPM2)) { + printk(BIOS_WARNING, "TPM: Clearing state\n"); + rc = tlcl_startup(); + } break; } diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index d86d62cc9b5..730701d7857 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -70,6 +70,7 @@ static const struct slot_irq_constraints irq_constraints[] = { .slot = SA_DEV_SLOT_CPU_1, .fns = { FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_0, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE1_1, PCI_INT_B, PIRQ_B), }, }, { diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index b451a727d1b..85b3c0493c7 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -20,8 +20,14 @@ #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 #endif +/* Hack to include SBREG in PCH_RESERVED region on ADL-S/RPL-S */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_PRESERVED_BASE_ADDRESS 0xe0000000 +#define PCH_PRESERVED_BASE_SIZE 0x1e800000 +#else #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 +#endif /* North (Intel) TraceHub Software. */ #define NTH_SW_BASE_ADDRESS 0xfc000000 diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 35c32527b2a..46f28f09d3a 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -118,7 +118,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { }, }; -static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + bool expand_channels) { uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, @@ -151,7 +152,16 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { uint32_t *spd_ptr = spd_upds[ch][dimm]; - *spd_ptr = data->spd[ch][dimm]; + // In DDR5 systems, we need to copy the SPD data such that: + // Channel 0 data is used by channel 0 and 1 + // Channel 2 data is used by channel 2 and 3 + // Channel 4 data is used by channel 4 and 5 + // Channel 6 data is used by channel 6 and 7 + if (expand_channels) + *spd_ptr = data->spd[ch & 6][dimm]; + else + *spd_ptr = data->spd[ch][dimm]; + if (*spd_ptr) enable_channel = 1; } @@ -217,27 +227,12 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); } -#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm)) - -static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info) -{ - for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) { - for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { - size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch]; - mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = - spd_info->smbus[ch].addr_dimm[dimm] << 1; - } - } - mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true); - mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); -} - void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; + bool expand_channels = false; FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; #if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) @@ -261,14 +256,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, case MEM_TYPE_DDR5: meminit_ddr(mem_cfg, &mb_cfg->ddr_config); dq_dqs_auto_detect = true; - /* - * TODO: Drop this workaround once SMBus driver in coreboot is updated to - * support DDR5 EEPROM reading. - */ - if (spd_info->topo == MEM_TOPO_DIMM_MODULE) { - ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info); - return; - } + expand_channels = true; break; case MEM_TYPE_LP4X: meminit_lp4x(mem_cfg); @@ -282,7 +270,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data); - mem_init_spd_upds(mem_cfg, &data); + mem_init_spd_upds(mem_cfg, &data, expand_channels); mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); } diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index abd7e466714..cda65f9d12e 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -144,6 +144,8 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp, acpigen_write_method_serialized("_ON", 0); + acpigen_write_debug_string("PCIe RTD3 _ON"); + /* When this feature is enabled, ONSK indicates if the previous _OFF was * skipped. If so, since the device was not in Off state, and the current * _ON can be skipped as well. @@ -167,9 +169,12 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp, acpigen_write_return_op(ONE_OP); acpigen_write_if_end(); - if (config->use_rp_mutex) - acpigen_write_acquire(acpi_device_path_join(parent, RP_MUTEX_NAME), - ACPI_MUTEX_NO_TIMEOUT); + /* When this feature is enabled, ONSK indicates if the previous _OFF was + * skipped. If so, since the device was not in Off state, and the current + * _ON can be skipped as well. + */ + if (config->skip_on_off_support) + acpigen_write_if_lequal_namestr_int("ONSK", 0); /* Disable modPHY power gating for PCH RPs. */ if (rp_type == PCIE_RP_PCH) @@ -228,6 +233,8 @@ pcie_rtd3_acpi_method_off(int pcie_rp, acpigen_write_method_serialized("_OFF", 0); + acpigen_write_debug_string("PCIe RTD3 _OFF"); + /* When this feature is enabled, ONSK is checked to see if the device * wants _OFF to be skipped for once. ONSK is normally incremented in the * device method, such as reset _RST, which is invoked during driver reload. @@ -384,7 +391,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) static bool mutex_created = false; const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); - static const char *const power_res_states[] = {"_PR0"}; + static const char *const power_res_states[] = {"_PR0", "_PR3"}; const struct device *parent = dev->bus->dev; const char *scope = acpi_device_path(parent); const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff); @@ -448,8 +455,8 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) } } - printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), - config->desc ?: dev->chip_ops->name); + printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s) on RP #%d\n", scope, dev_path(parent), + config->desc ?: dev->chip_ops->name, pcie_rp + 1); /* Create a mutex for exclusive access to the PMC registers. */ if (rp_type == PCIE_RP_PCH && !mutex_created) { diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index aff6fb0a1b2..dc254a98f0e 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -6,6 +6,17 @@ #include #include "smbuslib.h" +static const struct spd_offset_table spd_ddr5_table[] = { +{ 0, 1 }, /* General Configuration section */ +{ 2, 2 }, /* General Configuration section */ +{ 3, 47 }, /* General Configuration section */ +{ 126, 127 }, /* General Configuration section */ +{ 192, 213 }, /* Module-Specific section */ +{ 230, 235 }, /* Module-Specific section */ +{ 512, 520 }, /* Module Supplier's data */ +{ 521, 550 }, /* Module Supplier's data */ +}; + static void update_spd_len(struct spd_block *blk) { u8 i, j = 0; @@ -13,8 +24,8 @@ static void update_spd_len(struct spd_block *blk) if (blk->spd_array[i] != NULL) j |= blk->spd_array[i][SPD_DRAM_TYPE]; - /* If spd used is DDR4, then its length is 512 byte. */ - if (j == SPD_DRAM_DDR4) + /* If spd used is DDR4/5, then its length is 512 byte. */ + if (j == SPD_DRAM_DDR4 || j == SPD_DRAM_DDR5) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; @@ -37,6 +48,62 @@ static void smbus_read_spd(u8 *spd, u8 addr) } } +static void switch_page(u8 spd_addr, u8 new_page) +{ + u32 offset; + /* + * By default,an SPD5 hub accepts 1 byte addressing pointing + * to the first 128 bytes of memory. MR11[2:0] selects the page + * pointer to address the entire 1024 bytes of non-volatile memory. + */ + offset = SPD5_MEMREG_REG(SPD5_MR11); + smbus_write_byte(spd_addr, offset, new_page); +} + +/* + * Read the SPD data over the SMBus, at the specified SPD address, + * starting at the specified starting offset and read the given amount of data. + */ +static void smbus_read_spd5(u8 *spd, u8 spd_addr, const u16 start, u8 size, u8 *const page) +{ + u16 index; + u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5; + + if ((start + size) >= MAX_SPD_SIZE) { + printk(BIOS_ERR, "Maximum SPD size reached\n"); + return; + } + for (int i = 0; i < size; i++) { + index = start + i; + u8 next_page = index / max_page_size; + if (next_page != *page) { + switch_page(spd_addr, next_page); + *page = next_page; + } + unsigned int byte_addr = SPD_HUB_MEMREG(index % max_page_size); + spd[index] = smbus_read_byte(spd_addr, byte_addr); + } +} + +/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/ +static int is_spd5_hub(u8 spd_addr) +{ + u8 spd_hub_byte; + + spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0)); + return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV; +} + +/* + * Reset the SPD page back to page 0 on an SPD5 Hub device at the + * input SPD SMbus address. + */ +static void reset_page_spd5(u8 spd_addr) +{ + /* Set SPD5 MR11[2:0] = 0 (Page 0) */ + smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), 0); +} + /* return -1 if SMBus errors otherwise return 0 */ static int get_spd(u8 *spd, u8 addr) { @@ -52,22 +119,42 @@ static int get_spd(u8 *spd, u8 addr) return -1; } - if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { - printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd, addr); - } + if (is_spd5_hub(addr)) { + const struct spd_offset_table *tbl; + u32 byte; + u32 stop; + u8 page; + page = (u8) (~0); + stop = ARRAY_SIZE(spd_ddr5_table); + + for (byte = 0; byte < stop; byte++) { + tbl = &spd_ddr5_table[byte]; + smbus_read_spd5(spd, addr, tbl->start, + tbl->end - tbl->start + 1, &page); + } - /* Check if module is DDR4, DDR4 spd is 512 byte. */ - if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { - /* Switch to page 1 */ - smbus_write_byte(SPD_PAGE_1, 0, 0); + /* Reset the page for the next loop iteration */ + reset_page_spd5(addr); + } else { - if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - smbus_read_spd(spd + SPD_PAGE_LEN, addr); + smbus_read_spd(spd, addr); + } + + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { + /* Switch to page 1 */ + smbus_write_byte(SPD_PAGE_1, 0, 0); + + if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); + smbus_read_spd(spd + SPD_PAGE_LEN, addr); + } + /* Restore to page 0 */ + smbus_write_byte(SPD_PAGE_0, 0, 0); } - /* Restore to page 0 */ - smbus_write_byte(SPD_PAGE_0, 0, 0); } return 0; }