Estimated Speedup in ASIC

[jon-chuang]

What is the estimated speedup of the design as an ASIC, given smaller feature sizes and hence higher clock speeds? Could this possibly be 10x?

Further, I notice that the number of clk/sq for pearson_2 is 4. Is there any design where this is faster? Just curious.

Edit: I see the geriatric's is 1 clk. Amazing. I am guessing this is partly due to using fewer LUTs, but this comes at using BRAM, which slows down the clock?

[jon-chuang]

Furthermore, can I ask if the modulus is reconfigurable, or hard coded?