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fix: Changes required for Blink
- Updates to oscillators - Pin-mapping modification to remove clash with SWDIO
1 parent 7d2a2c6 commit c6fb119

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2 files changed

+22
-11
lines changed

2 files changed

+22
-11
lines changed

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/PeripheralPins_CYGNET.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -295,7 +295,7 @@ WEAK const PinMap PinMap_QUADSPI_SSEL[] = {
295295
WEAK const PinMap PinMap_USB[] = {
296296
{PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB_FS)}, // USB_DM
297297
{PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB_FS)}, // USB_DP
298-
{PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_FS)}, // USB_NOE
298+
// {PA_13, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_USB_FS)}, // USB_NOE - SWDIO
299299
{NC, NP, 0}
300300
};
301301
#endif

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.cpp

+21-10
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,11 @@
1515

1616
// Digital PinName array
1717
const PinName digitalPin[] = {
18-
PA_0, // 0 - A0/D0
19-
PA_1, // 1 - A1/D1
20-
PA_2, // 2 - A2/D2
21-
PA_3, // 3 - A3/D3
22-
PB_1, // 4 - A4/D4
18+
PA_0, // 0 - D0/A0
19+
PA_1, // 1 - D1/A1
20+
PA_2, // 2 - D2/A2
21+
PA_3, // 3 - D3/A3
22+
PB_1, // 4 - D4/A4
2323
PB_8, // 5 - D5
2424
PB_9, // 6 - D6
2525
PA_4, // 7 - BAT_VOLTAGE
@@ -114,43 +114,54 @@ WEAK void SystemClock_Config(void)
114114
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
115115
Error_Handler();
116116
}
117+
117118
/** Configure LSE Drive Capability
118119
*/
119120
HAL_PWR_EnableBkUpAccess();
120121
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
122+
121123
/** Initializes the RCC Oscillators according to the specified parameters
122124
* in the RCC_OscInitTypeDef structure.
123125
*/
124-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
126+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE
127+
| RCC_OSCILLATORTYPE_MSI
128+
| RCC_OSCILLATORTYPE_HSI;
125129
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
126130
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
127131
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
128132
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
133+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
134+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
129135
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
130136
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
131137
Error_Handler();
132138
}
139+
133140
/** Initializes the CPU, AHB and APB buses clocks
134141
*/
135142
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
136143
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
137-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
144+
// RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
145+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
138146
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
139147
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
140148
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
141-
142149
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
143150
Error_Handler();
144151
}
152+
153+
/** Initializes the Peripheral clocks
154+
*/
145155
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SDMMC1
146-
| RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_OSPI;
156+
| RCC_PERIPHCLK_ADC /* | RCC_PERIPHCLK_OSPI */;
147157
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
148-
PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK;
158+
// PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK;
149159
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
150160
PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_MSI;
151161
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
152162
Error_Handler();
153163
}
164+
154165
/** Enable MSI Auto calibration
155166
*/
156167
HAL_RCCEx_EnableMSIPLLMode();

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