From 0cfbb9a94ec1491966ad5ac30bda7e8543ae3bb4 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Mon, 17 Apr 2023 18:55:07 +0300 Subject: [PATCH] qei pins --- src/i2c.rs | 2 +- src/pwm.rs | 108 +++++++++++++++++--------------- src/qei.rs | 177 ++++++++--------------------------------------------- 3 files changed, 84 insertions(+), 203 deletions(-) diff --git a/src/i2c.rs b/src/i2c.rs index 93b99b03..a8c95c4e 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -288,7 +288,7 @@ impl I2c { prec: I2C::Rec, clocks: &CoreClocks, ) -> Self { - let _pins = (pins.0.into(), pins.1.into()); + let _pins: (I2C::Scl, I2C::Sda) = (pins.0.into(), pins.1.into()); Self::new_unchecked(i2c, frequency, prec, clocks) } /// Create and initialise a new I2C peripheral. diff --git a/src/pwm.rs b/src/pwm.rs index c13d282f..999f06c1 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -17,10 +17,10 @@ //! ```rust //! let gpioa = ..; // Set up and split GPIOA //! let pins = ( -//! gpioa.pa8.into_alternate_af1(), -//! gpioa.pa9.into_alternate_af1(), -//! gpioa.pa10.into_alternate_af1(), -//! gpioa.pa11.into_alternate_af1(), +//! gpioa.pa8.into_alternate(), +//! gpioa.pa9.into_alternate(), +//! gpioa.pa10.into_alternate(), +//! gpioa.pa11.into_alternate(), //! ); //! ``` //! @@ -56,10 +56,10 @@ //! ```rust //! let gpioa = ..; // Set up and split GPIOA //! let pins = ( -//! gpioa.pa8.into_alternate_af1(), -//! gpioa.pa9.into_alternate_af1(), -//! gpioa.pa10.into_alternate_af1(), -//! gpioa.pa11.into_alternate_af1(), +//! gpioa.pa8.into_alternate(), +//! gpioa.pa9.into_alternate(), +//! gpioa.pa10.into_alternate(), +//! gpioa.pa11.into_alternate(), //! ); //! ``` //! @@ -203,6 +203,10 @@ pub trait FaultPins { const INPUT: BreakInput; } +pub trait PinCh { + type Pin; +} + /// Channel wrapper pub struct Ch; impl Ch { @@ -1388,10 +1392,14 @@ pub trait PwmPinEnable { // Implement PwmPin for timer channels macro_rules! tim_pin_hal { // Standard pins (no complementary functionality) - ($TIMX:ty, $typ:ty: $( - ($CH:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident),)+ + ($TIMX:ty, $tim:ident, $typ:ty: $( + ($CH:ident, $Ch:ident, $ccmrx_output:ident, $ocxpe:ident, $ocxm:ident),)+ ) => { $( + impl PinCh<$CH> for $TIMX { + type Pin = gpio::alt::$tim::$Ch; + } + impl hal::PwmPin for Pwm<$TIMX, $CH, COMP> where Pwm<$TIMX, $CH, COMP>: PwmPinEnable { type Duty = $typ; @@ -1561,73 +1569,73 @@ macro_rules! tim_pin_hal { // Dual channel timers tim_pin_hal! { - pac::TIM12, u16: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), + pac::TIM12, tim12, u16: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), } tim_pin_hal! { - pac::TIM15, u16: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), + pac::TIM15, tim15, u16: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), } // Single channel timers tim_pin_hal! { - pac::TIM13, u16: (C1, ccmr1_output, oc1pe, oc1m), + pac::TIM13, tim13, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m), } tim_pin_hal! { - pac::TIM14, u16: (C1, ccmr1_output, oc1pe, oc1m), + pac::TIM14, tim14, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m), } tim_pin_hal! { - pac::TIM16, u16: (C1, ccmr1_output, oc1pe, oc1m), + pac::TIM16, tim16, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m), } tim_pin_hal! { - pac::TIM17, u16: (C1, ccmr1_output, oc1pe, oc1m), + pac::TIM17, tim17, u16: (C1, Ch1, ccmr1_output, oc1pe, oc1m), } // Quad channel timers tim_pin_hal! { - pac::TIM1, u16: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), - (C3, ccmr2_output, oc3pe, oc3m), - (C4, ccmr2_output, oc4pe, oc4m), + pac::TIM1, tim1, u16: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), + (C3, Ch3, ccmr2_output, oc3pe, oc3m), + (C4, Ch4, ccmr2_output, oc4pe, oc4m), } tim_pin_hal! { - pac::TIM2, u32: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), - (C3, ccmr2_output, oc3pe, oc3m), - (C4, ccmr2_output, oc4pe, oc4m), + pac::TIM2, tim2, u32: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), + (C3, Ch3, ccmr2_output, oc3pe, oc3m), + (C4, Ch4, ccmr2_output, oc4pe, oc4m), } tim_pin_hal! { - pac::TIM3, u16: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), - (C3, ccmr2_output, oc3pe, oc3m), - (C4, ccmr2_output, oc4pe, oc4m), + pac::TIM3, tim3, u16: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), + (C3, Ch3, ccmr2_output, oc3pe, oc3m), + (C4, Ch4, ccmr2_output, oc4pe, oc4m), } tim_pin_hal! { - pac::TIM4, u16: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), - (C3, ccmr2_output, oc3pe, oc3m), - (C4, ccmr2_output, oc4pe, oc4m), + pac::TIM4, tim4, u16: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), + (C3, Ch3, ccmr2_output, oc3pe, oc3m), + (C4, Ch4, ccmr2_output, oc4pe, oc4m), } tim_pin_hal! { - pac::TIM5, u32: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), - (C3, ccmr2_output, oc3pe, oc3m), - (C4, ccmr2_output, oc4pe, oc4m), + pac::TIM5, tim5, u32: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), + (C3, Ch3, ccmr2_output, oc3pe, oc3m), + (C4, Ch4, ccmr2_output, oc4pe, oc4m), } // Quad channel timers tim_pin_hal! { - pac::TIM8, u16: - (C1, ccmr1_output, oc1pe, oc1m), - (C2, ccmr1_output, oc2pe, oc2m), - (C3, ccmr2_output, oc3pe, oc3m), - (C4, ccmr2_output, oc4pe, oc4m), + pac::TIM8, tim8, u16: + (C1, Ch1, ccmr1_output, oc1pe, oc1m), + (C2, Ch2, ccmr1_output, oc2pe, oc2m), + (C3, Ch3, ccmr2_output, oc3pe, oc3m), + (C4, Ch4, ccmr2_output, oc4pe, oc4m), } // Low-power timers diff --git a/src/qei.rs b/src/qei.rs index 305619dc..f1aff580 100644 --- a/src/qei.rs +++ b/src/qei.rs @@ -1,158 +1,35 @@ //! # Quadrature Encoder Interface use crate::hal::{self, Direction}; +use crate::pac; +use crate::pwm::{PinCh, C1, C2}; use crate::rcc::{rec, ResetEnable}; -use crate::gpio::{self, Alternate}; - -use crate::stm32::{TIM1, TIM8}; - -use crate::stm32::{TIM2, TIM3, TIM4, TIM5}; - -pub trait Pins {} -pub trait PinCh1 {} -pub trait PinCh2 {} - -impl Pins for (PCH1, PCH2) -where - PCH1: PinCh1, - PCH2: PinCh2, -{ -} - -macro_rules! pins { - ($($TIMX:ty: - CH1: [$($( #[ $pmeta1:meta ] )* $CH1:ty),*] - CH2: [$($( #[ $pmeta2:meta ] )* $CH2:ty),*])+) => { - $( - $( - $( #[ $pmeta1 ] )* - impl PinCh1<$TIMX> for $CH1 {} - )* - $( - $( #[ $pmeta2 ] )* - impl PinCh2<$TIMX> for $CH2 {} - )* - )+ - } -} - -pins! { - TIM1: - CH1: [ - gpio::PA7>, - gpio::PA8>, - gpio::PB13>, - gpio::PE8>, - gpio::PE9>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PK0>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PK1> - ] - CH2: [ - gpio::PA9>, - gpio::PB0>, - gpio::PB14>, - gpio::PE10>, - gpio::PE11>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PJ10>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PJ11> - ] - - TIM2: - CH1: [ - gpio::PA0>, - gpio::PA5>, - gpio::PA15> - ] - CH2: [ - gpio::PA1>, - gpio::PB3> - ] - - TIM3: - CH1: [ - gpio::PA6>, - gpio::PB4>, - gpio::PC6> - ] - CH2: [ - gpio::PA7>, - gpio::PB5>, - gpio::PC7> - ] - - TIM4: - CH1: [ - gpio::PB6>, - gpio::PD12> - ] - CH2: [ - gpio::PB7>, - gpio::PD13> - ] - - TIM5: - CH1: [ - gpio::PA0>, - gpio::PH10> - ] - CH2: [ - gpio::PA1>, - gpio::PH11> - ] - - TIM8: - CH1: [ - gpio::PA5>, - gpio::PA7>, - gpio::PC6>, - gpio::PH13>, - #[cfg(not(feature = "rm0468"))] - gpio::PI5>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PJ8>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PJ9> - ] - CH2: [ - gpio::PB0>, - gpio::PB14>, - gpio::PC7>, - gpio::PH14>, - #[cfg(not(feature = "rm0468"))] - gpio::PI6>, - #[cfg(not(any(feature = "stm32h7b0", feature = "rm0468")))] - gpio::PJ6>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PJ7>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PJ10>, - #[cfg(not(feature = "stm32h7b0"))] - gpio::PJ11> - ] - -} - /// Hardware quadrature encoder interface peripheral pub struct Qei { tim: TIM, } -pub trait QeiExt { +pub trait QeiExt: Sized + PinCh + PinCh { type Rec: ResetEnable; - fn qei(self, _pins: PINS, prec: Self::Rec) -> Qei - where - PINS: Pins; + fn qei( + self, + pins: ( + impl Into<>::Pin>, + impl Into<>::Pin>, + ), + prec: Self::Rec, + ) -> Qei { + let _pins: (>::Pin, >::Pin) = + (pins.0.into(), pins.1.into()); + Self::qei_unchecked(self, prec) + } - fn qei_unchecked(self, prec: Self::Rec) -> Qei; + fn qei_unchecked(self, prec: Self::Rec) -> Qei; } macro_rules! tim_hal { - ($($TIM:ident: ($tim:ident, $Rec:ident, $bits:ident),)+) => { + ($($TIM:ty: ($tim:ident, $Rec:ident, $bits:ident),)+) => { $( impl Qei<$TIM> { /// Configures a TIM peripheral as a quadrature @@ -198,14 +75,10 @@ macro_rules! tim_hal { } } - impl QeiExt<$TIM> for $TIM { + impl QeiExt for $TIM { type Rec = rec::$Rec; - fn qei(self, _pins: PINS, prec: Self::Rec) -> Qei<$TIM> { - Qei::$tim(self, prec) - } - - fn qei_unchecked(self, prec: Self::Rec) -> Qei<$TIM> { + fn qei_unchecked(self, prec: Self::Rec) -> Qei { Qei::$tim(self, prec) } } @@ -231,10 +104,10 @@ macro_rules! tim_hal { } tim_hal! { - TIM1: (tim1, Tim1, u16), - TIM8: (tim8, Tim8, u16), - TIM2: (tim2, Tim2, u32), - TIM3: (tim3, Tim3, u16), - TIM4: (tim4, Tim4, u16), - TIM5: (tim5, Tim5, u32), + pac::TIM1: (tim1, Tim1, u16), + pac::TIM8: (tim8, Tim8, u16), + pac::TIM2: (tim2, Tim2, u32), + pac::TIM3: (tim3, Tim3, u16), + pac::TIM4: (tim4, Tim4, u16), + pac::TIM5: (tim5, Tim5, u32), }