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Cargo.toml

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@@ -64,6 +64,9 @@ version = "1.0"
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[dependencies.embedded-hal-nb]
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version = "1.0"
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[dependencies.embedded-io]
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version = "0.6.1"
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[dependencies.stm32_i2s_v12x]
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version = "0.5.0"
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optional = true

src/serial.rs

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@@ -17,6 +17,7 @@
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use core::marker::PhantomData;
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mod hal_02;
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mod hal_1;
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pub(crate) mod uart_impls;
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pub use uart_impls::Instance;

src/serial/hal_1.rs

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mod nb {
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use core::ops::Deref;
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use super::super::{Error, Instance, RegisterBlockImpl, Rx, Serial, Tx};
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use embedded_hal_nb::serial::{ErrorKind, Read, Write};
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impl embedded_hal_nb::serial::Error for Error {
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fn kind(&self) -> ErrorKind {
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match self {
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Error::Overrun => ErrorKind::Overrun,
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Error::FrameFormat => ErrorKind::FrameFormat,
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Error::Parity => ErrorKind::Parity,
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Error::Noise => ErrorKind::Noise,
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Error::Other => ErrorKind::Other,
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}
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}
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}
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impl<USART: Instance, WORD> embedded_hal_nb::serial::ErrorType for Serial<USART, WORD> {
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type Error = Error;
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}
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impl<USART: Instance, WORD> embedded_hal_nb::serial::ErrorType for Rx<USART, WORD> {
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type Error = Error;
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}
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impl<USART: Instance, WORD> embedded_hal_nb::serial::ErrorType for Tx<USART, WORD> {
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type Error = Error;
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}
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impl<USART: Instance, WORD: Copy> Read<WORD> for Serial<USART, WORD>
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where
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Rx<USART, WORD>: Read<WORD, Error = Error>,
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{
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fn read(&mut self) -> nb::Result<WORD, Self::Error> {
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self.rx.read()
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}
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}
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impl<USART: Instance> Read<u8> for Rx<USART, u8>
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where
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<USART as Instance>::RegisterBlock: RegisterBlockImpl,
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{
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fn read(&mut self) -> nb::Result<u8, Self::Error> {
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unsafe { (*USART::ptr()).read_u8() }
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}
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}
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/// Reads 9-bit words from the UART/USART
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///
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/// If the UART/USART was configured with `WordLength::DataBits9`, the returned value will contain
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/// 9 received data bits and all other bits set to zero. Otherwise, the returned value will contain
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/// 8 received data bits and all other bits set to zero.
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impl<USART: Instance> Read<u16> for Rx<USART, u16>
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where
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<USART as Instance>::RegisterBlock: RegisterBlockImpl,
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{
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fn read(&mut self) -> nb::Result<u16, Self::Error> {
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unsafe { (*USART::ptr()).read_u16() }
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}
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}
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impl<USART: Instance, WORD: Copy> Write<WORD> for Serial<USART, WORD>
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where
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Tx<USART, WORD>: Write<WORD, Error = Error>,
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{
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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self.tx.flush()
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}
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fn write(&mut self, byte: WORD) -> nb::Result<(), Self::Error> {
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self.tx.write(byte)
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}
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}
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impl<USART: Instance> Write<u8> for Tx<USART, u8>
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where
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<USART as Instance>::RegisterBlock: RegisterBlockImpl,
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USART: Deref<Target = <USART as Instance>::RegisterBlock>,
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{
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fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
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self.usart.write_u8(word)
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}
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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self.usart.flush()
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}
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}
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/// Writes 9-bit words to the UART/USART
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///
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/// If the UART/USART was configured with `WordLength::DataBits9`, the 9 least significant bits will
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/// be transmitted and the other 7 bits will be ignored. Otherwise, the 8 least significant bits
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/// will be transmitted and the other 8 bits will be ignored.
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impl<USART: Instance> Write<u16> for Tx<USART, u16>
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where
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<USART as Instance>::RegisterBlock: RegisterBlockImpl,
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USART: Deref<Target = <USART as Instance>::RegisterBlock>,
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{
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fn write(&mut self, word: u16) -> nb::Result<(), Self::Error> {
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self.usart.write_u16(word)
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}
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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self.usart.flush()
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}
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}
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}
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mod io {
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use core::ops::Deref;
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use super::super::{Error, Instance, RegisterBlockImpl, Rx, Serial, Tx};
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use embedded_io::Write;
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impl embedded_io::Error for Error {
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// TODO: fix error conversion
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fn kind(&self) -> embedded_io::ErrorKind {
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embedded_io::ErrorKind::Other
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}
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}
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impl<USART: Instance, WORD> embedded_io::ErrorType for Serial<USART, WORD> {
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type Error = Error;
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}
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impl<USART: Instance, WORD> embedded_io::ErrorType for Tx<USART, WORD> {
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type Error = Error;
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}
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impl<USART: Instance, WORD> embedded_io::ErrorType for Rx<USART, WORD> {
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type Error = Error;
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}
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impl<USART: Instance> Write for Tx<USART, u8>
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where
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<USART as Instance>::RegisterBlock: RegisterBlockImpl,
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USART: Deref<Target = <USART as Instance>::RegisterBlock>,
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{
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/*
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fn write(&mut self, bytes: &[u8]) -> Result<usize, Self::Error> {
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let mut iter = bytes.iter();
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let Some(first) = iter.next() else {
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return Ok(0);
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};
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// block for first byte
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self.usart.write_u8(*first)?;
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let mut i = 1;
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// write more bytes if it's possible
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for byte in iter {
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match self.usart.write_u8(*byte) {
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Ok(_) => {
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i += 1;
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}
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Err(nb::Error::WouldBlock) => {
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return Ok(i);
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}
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Err(nb::Error::Other(e)) => {
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return Err(e);
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}
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}
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}
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Ok(i)
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}*/
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fn write(&mut self, bytes: &[u8]) -> Result<usize, Self::Error> {
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let mut i = 0;
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for byte in bytes.iter() {
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match self.usart.write_u8(*byte) {
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Ok(_) => {
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i += 1;
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}
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Err(nb::Error::WouldBlock) => {
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return Ok(i);
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}
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Err(nb::Error::Other(e)) => {
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return Err(e);
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}
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}
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}
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Ok(i)
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}
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fn flush(&mut self) -> Result<(), Self::Error> {
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self.usart.bflush()?;
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Ok(())
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}
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}
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impl<USART: Instance> Write for Serial<USART, u8>
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where
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Tx<USART, u8>: Write<Error = Error>,
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{
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fn write(&mut self, bytes: &[u8]) -> Result<usize, Self::Error> {
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self.tx.write(bytes)
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}
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fn flush(&mut self) -> Result<(), Self::Error> {
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self.tx.flush()
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}
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}
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}

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