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DRS.cc
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/********************************************************************
Name: DRS.cpp
Created by: Stefan Ritt, Matthias Schneebeli
Contents: Library functions for DRS mezzanine and USB boards
$Id: DRS.cpp 21433 2014-07-30 12:53:51Z ritt $
\********************************************************************/
#define NEW_TIMING_CALIBRATION
#ifdef USE_DRS_MUTEX
#include "wx/wx.h" // must be before <windows.h>
#endif
#include <stdio.h>
#include <math.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#include <assert.h>
#include <algorithm>
#include <sys/stat.h>
#include <fcntl.h>
#include "strlcpy.h"
#include "DRS.h"
#ifdef _MSC_VER
#pragma warning(disable:4996)
# include <windows.h>
# include <direct.h>
#else
# include <unistd.h>
# include <sys/time.h>
inline void Sleep(useconds_t x)
{
usleep(x * 1000);
}
#endif
#ifdef _MSC_VER
#include <conio.h>
#define drs_kbhit() kbhit()
#else
#include <sys/ioctl.h>
int drs_kbhit()
{
int n;
ioctl(0, FIONREAD, &n);
return (n > 0);
}
static inline int getch()
{
return getchar();
}
#endif
#include <DRS.h>
#ifdef _MSC_VER
extern "C" {
#endif
#include <mxml.h>
#ifdef _MSC_VER
}
#endif
/*---- minimal FPGA firmvare version required for this library -----*/
const int REQUIRED_FIRMWARE_VERSION_DRS2 = 5268;
const int REQUIRED_FIRMWARE_VERSION_DRS3 = 6981;
const int REQUIRED_FIRMWARE_VERSION_DRS4 = 15147;
/*---- calibration methods to be stored in EEPROMs -----------------*/
#define VCALIB_METHOD_V4 1
#define TCALIB_METHOD_V4 1
#define VCALIB_METHOD 2
#define TCALIB_METHOD 2 // correct for sampling frequency, calibrate every channel
/*---- VME addresses -----------------------------------------------*/
#ifdef HAVE_VME
/* assuming following DIP Switch settings:
SW1-1: 1 (off) use geographical addressing (1=left, 21=right)
SW1-2: 1 (off) \
SW1-3: 1 (off) > VME_WINSIZE = 8MB, subwindow = 1MB
SW1-4: 0 (on) /
SW1-5: 0 (on) reserverd
SW1-6: 0 (on) reserverd
SW1-7: 0 (on) reserverd
SW1-8: 0 (on) \
|
SW2-1: 0 (on) |
SW2-2: 0 (on) |
SW2-3: 0 (on) |
SW2-4: 0 (on) > VME_ADDR_OFFSET = 0
SW2-5: 0 (on) |
SW2-6: 0 (on) |
SW2-7: 0 (on) |
SW2-8: 0 (on) /
which gives
VME base address = SlotNo * VME_WINSIZE + VME_ADDR_OFFSET
= SlotNo * 0x80'0000
*/
#define GEVPC_BASE_ADDR 0x00000000
#define GEVPC_WINSIZE 0x800000
#define GEVPC_USER_FPGA (GEVPC_WINSIZE*2/8)
#define PMC1_OFFSET 0x00000
#define PMC2_OFFSET 0x80000
#define PMC_CTRL_OFFSET 0x00000 /* all registers 32 bit */
#define PMC_STATUS_OFFSET 0x10000
#define PMC_FIFO_OFFSET 0x20000
#define PMC_RAM_OFFSET 0x40000
#endif // HAVE_VME
/*---- USB addresses -----------------------------------------------*/
#define USB_TIMEOUT 1000 // one second
#ifdef HAVE_USB
#define USB_CTRL_OFFSET 0x00 /* all registers 32 bit */
#define USB_STATUS_OFFSET 0x40
#define USB_RAM_OFFSET 0x80
#define USB_CMD_IDENT 0 // Query identification
#define USB_CMD_ADDR 1 // Address cycle
#define USB_CMD_READ 2 // "VME" read <addr><size>
#define USB_CMD_WRITE 3 // "VME" write <addr><size>
#define USB_CMD_READ12 4 // 12-bit read <LSB><MSB>
#define USB_CMD_WRITE12 5 // 12-bit write <LSB><MSB>
#define USB2_CMD_READ 1
#define USB2_CMD_WRITE 2
#define USB2_CTRL_OFFSET 0x00000 /* all registers 32 bit */
#define USB2_STATUS_OFFSET 0x10000
#define USB2_FIFO_OFFSET 0x20000
#define USB2_RAM_OFFSET 0x40000
#endif // HAVE_USB
/*------------------------------------------------------------------*/
using namespace std;
#ifdef HAVE_USB
#define USB2_BUFFER_SIZE (1024*1024+10)
unsigned char static *usb2_buffer = NULL;
#endif
/*------------------------------------------------------------------*/
#ifdef USE_DRS_MUTEX
static wxMutex *s_drsMutex = NULL; // used for wxWidgets multi-threaded programs
#endif
/*------------------------------------------------------------------*/
DRS::DRS()
: fNumberOfBoards(0)
#ifdef HAVE_VME
, fVmeInterface(0)
#endif
{
#ifdef HAVE_USB
MUSB_INTERFACE *usb_interface;
#endif
#if defined(HAVE_VME) || defined(HAVE_USB)
int index = 0, i=0;
#endif
memset(fError, 0, sizeof(fError));
#ifdef HAVE_VME
unsigned short type, fw, magic, serial, temperature;
mvme_addr_t addr;
if (mvme_open(&fVmeInterface, 0) == MVME_SUCCESS) {
mvme_set_am(fVmeInterface, MVME_AM_A32);
mvme_set_dmode(fVmeInterface, MVME_DMODE_D16);
/* check all VME slave slots */
for (index = 2; index <= 21; index++) {
/* check PMC1 */
addr = GEVPC_BASE_ADDR + index * GEVPC_WINSIZE; // VME board base address
addr += GEVPC_USER_FPGA; // UsrFPGA base address
addr += PMC1_OFFSET; // PMC1 offset
mvme_set_dmode(fVmeInterface, MVME_DMODE_D16);
i = mvme_read(fVmeInterface, &magic, addr + PMC_STATUS_OFFSET + REG_MAGIC, 2);
if (i == 2) {
if (magic != 0xC0DE) {
printf("Found old firmware, please upgrade immediately!\n");
fBoard[fNumberOfBoards] = new DRSBoard(fVmeInterface, addr, (index - 2) << 1);
fNumberOfBoards++;
} else {
/* read board type */
mvme_read(fVmeInterface, &type, addr + PMC_STATUS_OFFSET + REG_BOARD_TYPE, 2);
type &= 0xFF;
if (type == 2 || type == 3 || type == 4) { // DRS2 or DRS3 or DRS4
/* read firmware number */
mvme_read(fVmeInterface, &fw, addr + PMC_STATUS_OFFSET + REG_VERSION_FW, 2);
/* read serial number */
mvme_read(fVmeInterface, &serial, addr + PMC_STATUS_OFFSET + REG_SERIAL_BOARD, 2);
/* read temperature register to see if CMC card is present */
mvme_read(fVmeInterface, &temperature, addr + PMC_STATUS_OFFSET + REG_TEMPERATURE, 2);
/* LED blinking */
#if 0
do {
data = 0x00040000;
mvme_write(fVmeInterface, addr + PMC_CTRL_OFFSET + REG_CTRL, &data, sizeof(data));
mvme_write(fVmeInterface, addr + PMC2_OFFSET + PMC_CTRL_OFFSET + REG_CTRL, &data,
sizeof(data));
Sleep(500);
data = 0x00000000;
mvme_write(fVmeInterface, addr + PMC_CTRL_OFFSET + REG_CTRL, &data, sizeof(data));
mvme_write(fVmeInterface, addr + PMC2_OFFSET + PMC_CTRL_OFFSET + REG_CTRL, data,
sizeof(data));
Sleep(500);
} while (1);
#endif
if (temperature == 0xFFFF) {
printf("Found VME board in slot %d, fw %d, but no CMC board in upper slot\n", index, fw);
} else {
printf("Found DRS%d board %2d in upper VME slot %2d, serial #%d, firmware revision %d\n", type, fNumberOfBoards, index, serial, fw);
fBoard[fNumberOfBoards] = new DRSBoard(fVmeInterface, addr, (index - 2) << 1);
if (!fBoard[fNumberOfBoards]->HasCorrectFirmware())
sprintf(fError, "Wrong firmware version: board has %d, required is %d. Board may not work correctly.\n",
fBoard[fNumberOfBoards]->GetFirmwareVersion(),
fBoard[fNumberOfBoards]->GetRequiredFirmwareVersion());
fNumberOfBoards++;
}
}
}
}
/* check PMC2 */
addr = GEVPC_BASE_ADDR + index * GEVPC_WINSIZE; // VME board base address
addr += GEVPC_USER_FPGA; // UsrFPGA base address
addr += PMC2_OFFSET; // PMC2 offset
mvme_set_dmode(fVmeInterface, MVME_DMODE_D16);
i = mvme_read(fVmeInterface, &fw, addr + PMC_STATUS_OFFSET + REG_MAGIC, 2);
if (i == 2) {
if (magic != 0xC0DE) {
printf("Found old firmware, please upgrade immediately!\n");
fBoard[fNumberOfBoards] = new DRSBoard(fVmeInterface, addr, (index - 2) << 1 | 1);
fNumberOfBoards++;
} else {
/* read board type */
mvme_read(fVmeInterface, &type, addr + PMC_STATUS_OFFSET + REG_BOARD_TYPE, 2);
type &= 0xFF;
if (type == 2 || type == 3 || type == 4) { // DRS2 or DRS3 or DRS4
/* read firmware number */
mvme_read(fVmeInterface, &fw, addr + PMC_STATUS_OFFSET + REG_VERSION_FW, 2);
/* read serial number */
mvme_read(fVmeInterface, &serial, addr + PMC_STATUS_OFFSET + REG_SERIAL_BOARD, 2);
/* read temperature register to see if CMC card is present */
mvme_read(fVmeInterface, &temperature, addr + PMC_STATUS_OFFSET + REG_TEMPERATURE, 2);
if (temperature == 0xFFFF) {
printf("Found VME board in slot %d, fw %d, but no CMC board in lower slot\n", index, fw);
} else {
printf("Found DRS%d board %2d in lower VME slot %2d, serial #%d, firmware revision %d\n", type, fNumberOfBoards, index, serial, fw);
fBoard[fNumberOfBoards] = new DRSBoard(fVmeInterface, addr, ((index - 2) << 1) | 1);
if (!fBoard[fNumberOfBoards]->HasCorrectFirmware())
sprintf(fError, "Wrong firmware version: board has %d, required is %d. Board may not work correctly.\n",
fBoard[fNumberOfBoards]->GetFirmwareVersion(),
fBoard[fNumberOfBoards]->GetRequiredFirmwareVersion());
fNumberOfBoards++;
}
}
}
}
}
} else
printf("Cannot access VME crate, check driver, power and connection\n");
#endif // HAVE_VME
#ifdef HAVE_USB
unsigned char buffer[512];
int found, one_found, usb_slot;
one_found = 0;
usb_slot = 0;
for (index = 0; index < 127; index++) {
found = 0;
/* check for USB-Mezzanine test board */
if (musb_open(&usb_interface, 0x10C4, 0x1175, index, 1, 0) == MUSB_SUCCESS) {
/* check ID */
buffer[0] = USB_CMD_IDENT;
musb_write(usb_interface, 2, buffer, 1, USB_TIMEOUT);
i = musb_read(usb_interface, 1, (char *) buffer, sizeof(buffer), USB_TIMEOUT);
if (strcmp((char *) buffer, "USB_MEZZ2 V1.0") != 0) {
/* no USB-Mezzanine board found */
musb_close(usb_interface);
} else {
usb_interface->usb_type = 1; // USB 1.1
fBoard[fNumberOfBoards] = new DRSBoard(usb_interface, usb_slot++);
if (!fBoard[fNumberOfBoards]->HasCorrectFirmware())
sprintf(fError, "Wrong firmware version: board has %d, required is %d. Board may not work correctly.\n",
fBoard[fNumberOfBoards]->GetFirmwareVersion(),
fBoard[fNumberOfBoards]->GetRequiredFirmwareVersion());
fNumberOfBoards++;
found = 1;
one_found = 1;
}
}
/* check for DRS4 evaluation board */
if (musb_open(&usb_interface, 0x04B4, 0x1175, index, 1, 0) == MUSB_SUCCESS) {
/* check ID */
if (musb_get_device(usb_interface) != 1) {
/* no DRS evaluation board found */
musb_close(usb_interface);
} else {
/* drain any data from Cy7C68013 FIFO if FPGA startup caused erratic write */
do {
i = musb_read(usb_interface, 8, buffer, sizeof(buffer), 100);
if (i > 0)
printf("%d bytes stuck in buffer\n", i);
} while (i > 0);
usb_interface->usb_type = 2; // USB 2.0
fBoard[fNumberOfBoards] = new DRSBoard(usb_interface, usb_slot++);
if (!fBoard[fNumberOfBoards]->HasCorrectFirmware())
sprintf(fError, "Wrong firmware version: board has %d, required is %d. Board may not work correctly.\n",
fBoard[fNumberOfBoards]->GetFirmwareVersion(),
fBoard[fNumberOfBoards]->GetRequiredFirmwareVersion());
fNumberOfBoards++;
found = 1;
one_found = 1;
}
}
if (!found) {
if (!one_found)
printf("USB successfully scanned, but no boards found\n");
break;
}
}
#endif // HAVE_USB
return;
}
/*------------------------------------------------------------------*/
DRS::~DRS()
{
int i;
for (i = 0; i < fNumberOfBoards; i++) {
delete fBoard[i];
}
#ifdef HAVE_USB
if (usb2_buffer) {
free(usb2_buffer);
usb2_buffer = NULL;
}
#endif
#ifdef HAVE_VME
mvme_close(fVmeInterface);
#endif
}
/*------------------------------------------------------------------*/
void DRS::SortBoards()
{
/* sort boards according to serial number (simple bubble sort) */
for (int i=0 ; i<fNumberOfBoards-1 ; i++) {
for (int j=i+1 ; j<fNumberOfBoards ; j++) {
if (fBoard[i]->GetBoardSerialNumber() < fBoard[j]->GetBoardSerialNumber()) {
DRSBoard* b = fBoard[i];
fBoard[i] = fBoard[j];
fBoard[j] = b;
}
}
}
}
/*------------------------------------------------------------------*/
void DRS::SetBoard(int i, DRSBoard *b)
{
fBoard[i] = b;
}
/*------------------------------------------------------------------*/
bool DRS::GetError(char *str, int size)
{
if (fError[0])
strlcpy(str, fError, size);
return fError[0] > 0;
}
/*------------------------------------------------------------------*/
#ifdef HAVE_USB
DRSBoard::DRSBoard(MUSB_INTERFACE * musb_interface, int usb_slot)
: fDAC_COFSA(0)
, fDAC_COFSB(0)
, fDAC_DRA(0)
, fDAC_DSA(0)
, fDAC_TLEVEL(0)
, fDAC_ACALIB(0)
, fDAC_DSB(0)
, fDAC_DRB(0)
, fDAC_COFS(0)
, fDAC_ADCOFS(0)
, fDAC_CLKOFS(0)
, fDAC_ROFS_1(0)
, fDAC_ROFS_2(0)
, fDAC_INOFS(0)
, fDAC_BIAS(0)
, fDRSType(0)
, fBoardType(0)
, fRequiredFirmwareVersion(0)
, fFirmwareVersion(0)
, fBoardSerialNumber(0)
, fHasMultiBuffer(0)
, fCtrlBits(0)
, fNumberOfReadoutChannels(0)
, fReadoutChannelConfig(0)
, fADCClkPhase(0)
, fADCClkInvert(0)
, fExternalClockFrequency(0)
, fUsbInterface(musb_interface)
#ifdef HAVE_VME
, fVmeInterface(0)
, fBaseAddress(0)
#endif
, fSlotNumber(usb_slot)
, fNominalFrequency(0)
, fMultiBuffer(0)
, fDominoMode(0)
, fDominoActive(0)
, fChannelConfig(0)
, fChannelCascading(1)
, fChannelDepth(1024)
, fWSRLoop(0)
, fReadoutMode(0)
, fReadPointer(0)
, fNMultiBuffer(0)
, fTriggerEnable1(0)
, fTriggerEnable2(0)
, fTriggerSource(0)
, fTriggerDelay(0)
, fTriggerDelayNs(0)
, fSyncDelay(0)
, fDelayedStart(0)
, fTranspMode(0)
, fDecimation(0)
, fRange(0)
, fCommonMode(0.8)
, fAcalMode(0)
, fAcalVolt(0)
, fTcalFreq(0)
, fTcalLevel(0)
, fTcalPhase(0)
, fTcalSource(0)
, fRefclk(0)
, fMaxChips(0)
, fResponseCalibration(0)
, fVoltageCalibrationValid(false)
, fCellCalibratedRange(0)
, fCellCalibratedTemperature(0)
, fTimeData(0)
, fNumberOfTimeData(0)
, fDebug(0)
, fTriggerStartBin(0)
{
if (musb_interface->usb_type == 1)
fTransport = TR_USB;
else
fTransport = TR_USB2;
memset(fStopCell, 0, sizeof(fStopCell));
memset(fStopWSR, 0, sizeof(fStopWSR));
fTriggerBus = 0;
ConstructBoard();
}
#endif
#ifdef HAVE_VME
/*------------------------------------------------------------------*/
DRSBoard::DRSBoard(MVME_INTERFACE * mvme_interface, mvme_addr_t base_address, int slot_number)
:fDAC_COFSA(0)
, fDAC_COFSB(0)
, fDAC_DRA(0)
, fDAC_DSA(0)
, fDAC_TLEVEL(0)
, fDAC_ACALIB(0)
, fDAC_DSB(0)
, fDAC_DRB(0)
, fDAC_COFS(0)
, fDAC_ADCOFS(0)
, fDAC_CLKOFS(0)
, fDAC_ROFS_1(0)
, fDAC_ROFS_2(0)
, fDAC_INOFS(0)
, fDAC_BIAS(0)
, fDRSType(0)
, fBoardType(0)
, fRequiredFirmwareVersion(0)
, fFirmwareVersion(0)
, fBoardSerialNumber(0)
, fHasMultiBuffer(0)
, fTransport(TR_VME)
, fCtrlBits(0)
, fNumberOfReadoutChannels(0)
, fReadoutChannelConfig(0)
, fADCClkPhase(0)
, fADCClkInvert(0)
, fExternalClockFrequency(0)
#ifdef HAVE_USB
, fUsbInterface(0)
#endif
#ifdef HAVE_VME
, fVmeInterface(mvme_interface)
, fBaseAddress(base_address)
, fSlotNumber(slot_number)
#endif
, fNominalFrequency(0)
, fRefClock(0)
, fMultiBuffer(0)
, fDominoMode(1)
, fDominoActive(1)
, fChannelConfig(0)
, fChannelCascading(1)
, fChannelDepth(1024)
, fWSRLoop(1)
, fReadoutMode(0)
, fReadPointer(0)
, fNMultiBuffer(0)
, fTriggerEnable1(0)
, fTriggerEnable2(0)
, fTriggerSource(0)
, fTriggerDelay(0)
, fTriggerDelayNs(0)
, fSyncDelay(0)
, fDelayedStart(0)
, fTranspMode(0)
, fDecimation(0)
, fRange(0)
, fCommonMode(0.8)
, fAcalMode(0)
, fAcalVolt(0)
, fTcalFreq(0)
, fTcalLevel(0)
, fTcalPhase(0)
, fTcalSource(0)
, fRefclk(0)
, fMaxChips(0)
, fResponseCalibration(0)
, fTimeData(0)
, fNumberOfTimeData(0)
, fDebug(0)
, fTriggerStartBin(0)
{
ConstructBoard();
}
#endif
/*------------------------------------------------------------------*/
DRSBoard::~DRSBoard()
{
int i;
#ifdef HAVE_USB
if (fTransport == TR_USB || fTransport == TR_USB2)
musb_close(fUsbInterface);
#endif
#ifdef USE_DRS_MUTEX
if (s_drsMutex)
delete s_drsMutex;
s_drsMutex = NULL;
#endif
// Response Calibration
delete fResponseCalibration;
// Time Calibration
for (i = 0; i < fNumberOfTimeData; i++) {
delete fTimeData[i];
}
delete[]fTimeData;
}
/*------------------------------------------------------------------*/
void DRSBoard::ConstructBoard()
{
unsigned char buffer[2];
unsigned int bits;
fDebug = 0;
fWSRLoop = 1;
fCtrlBits = 0;
fExternalClockFrequency = 1000. / 30.;
strcpy(fCalibDirectory, ".");
/* check board communication */
if (Read(T_STATUS, buffer, REG_MAGIC, 2) < 0) {
InitFPGA();
if (Read(T_STATUS, buffer, REG_MAGIC, 2) < 0)
return;
}
ReadSerialNumber();
/* set correct reference clock */
if (fBoardType == 5 || fBoardType == 7 || fBoardType == 8 || fBoardType == 9)
fRefClock = 60;
else
fRefClock = 33;
/* get mode from hardware */
bits = GetCtrlReg();
fMultiBuffer = (bits & BIT_MULTI_BUFFER) > 0;
fNMultiBuffer = 0;
if (fHasMultiBuffer && fMultiBuffer)
fNMultiBuffer = 3;
if (fDRSType == 4) {
fDominoMode = (bits & BIT_CONFIG_DMODE) > 0;
} else {
fDominoMode = (bits & BIT_DMODE) > 0;
}
fTriggerEnable1 = (bits & BIT_ENABLE_TRIGGER1) > 0;
fTriggerEnable2 = (bits & BIT_ENABLE_TRIGGER2) > 0;
fTriggerSource = ((bits & BIT_TR_SOURCE1) > 0) | (((bits & BIT_TR_SOURCE2) > 0) << 1);
fReadoutMode = (bits & BIT_READOUT_MODE) > 0;
Read(T_CTRL, &fReadPointer, REG_READ_POINTER, 2);
fADCClkInvert = (bits & BIT_ADCCLK_INVERT) > 0;
fDominoActive = (bits & BIT_DACTIVE) > 0;
ReadFrequency(0, &fNominalFrequency);
if (fNominalFrequency < 0.1 || fNominalFrequency > 6)
fNominalFrequency = 1;
/* initialize number of channels */
if (fDRSType == 4) {
if (fBoardType == 6) {
unsigned short d;
Read(T_CTRL, &d, REG_CHANNEL_MODE, 2);
fReadoutChannelConfig = d & 0xFF;
if (d == 7)
fNumberOfReadoutChannels = 9;
else
fNumberOfReadoutChannels = 5;
} else
fNumberOfReadoutChannels = 9;
} else
fNumberOfReadoutChannels = 10;
if (fBoardType == 1) {
fDAC_COFSA = 0;
fDAC_COFSB = 1;
fDAC_DRA = 2;
fDAC_DSA = 3;
fDAC_TLEVEL = 4;
fDAC_ACALIB = 5;
fDAC_DSB = 6;
fDAC_DRB = 7;
} else if (fBoardType == 2 || fBoardType == 3) {
fDAC_COFS = 0;
fDAC_DSA = 1;
fDAC_DSB = 2;
fDAC_TLEVEL = 3;
fDAC_CLKOFS = 5;
fDAC_ACALIB = 6;
fDAC_ADCOFS = 7;
} else if (fBoardType == 4) {
fDAC_ROFS_1 = 0;
fDAC_DSA = 1;
fDAC_DSB = 2;
fDAC_ROFS_2 = 3;
fDAC_BIAS = 4;
fDAC_INOFS = 5;
fDAC_ACALIB = 6;
fDAC_ADCOFS = 7;
} else if (fBoardType == 5) {
fDAC_ROFS_1 = 0;
fDAC_CMOFS = 1;
fDAC_CALN = 2;
fDAC_CALP = 3;
fDAC_BIAS = 4;
fDAC_TLEVEL = 5;
fDAC_ONOFS = 6;
} else if (fBoardType == 6) {
fDAC_ONOFS = 0;
fDAC_CMOFSP = 1;
fDAC_CALN = 2;
fDAC_CALP = 3;
fDAC_CMOFSN = 5;
fDAC_ROFS_1 = 6;
fDAC_BIAS = 7;
} else if (fBoardType == 7) {
fDAC_ROFS_1 = 0;
fDAC_CMOFS = 1;
fDAC_CALN = 2;
fDAC_CALP = 3;
fDAC_BIAS = 4;
fDAC_TLEVEL = 5;
fDAC_ONOFS = 6;
} else if (fBoardType == 8 || fBoardType == 9) {
fDAC_ROFS_1 = 0;
fDAC_TLEVEL4 = 1;
fDAC_CALN = 2;
fDAC_CALP = 3;
fDAC_BIAS = 4;
fDAC_TLEVEL1 = 5;
fDAC_TLEVEL2 = 6;
fDAC_TLEVEL3 = 7;
}
if (fDRSType < 4) {
// Response Calibration
fResponseCalibration = new ResponseCalibration(this);
// Time Calibration
fTimeData = new DRSBoard::TimeData *[kNumberOfChipsMax];
fNumberOfTimeData = 0;
}
}
/*------------------------------------------------------------------*/
void DRSBoard::ReadSerialNumber()
{
unsigned char buffer[2];
int number;
// check magic number
if (Read(T_STATUS, buffer, REG_MAGIC, 2) < 0) {
printf("Cannot read from board\n");
return;
}
number = (static_cast < int >(buffer[1]) << 8) +buffer[0];
if (number != 0xC0DE) {
printf("Invalid magic number: %04X\n", number);
return;
}
// read board type
Read(T_STATUS, buffer, REG_BOARD_TYPE, 2);
fDRSType = buffer[0];
fBoardType = buffer[1];
// read firmware version
Read(T_STATUS, buffer, REG_VERSION_FW, 2);
fFirmwareVersion = (static_cast < int >(buffer[1]) << 8) +buffer[0];
// retrieve board serial number
Read(T_STATUS, buffer, REG_SERIAL_BOARD, 2);
number = (static_cast < int >(buffer[1]) << 8) +buffer[0];
fBoardSerialNumber = number;
// determine DRS type and board type for old boards from setial number
if (fBoardType == 0) {
// determine board version from serial number
if (number >= 2000 && number < 5000) {
fBoardType = 6;
fDRSType = 4;
} else if (number >= 1000) {
fBoardType = 4;
fDRSType = 3;
} else if (number >= 100)
fBoardType = 3;
else if (number > 0)
fBoardType = 2;
else {
fBoardType = 3;
fDRSType = 2;
fRequiredFirmwareVersion = REQUIRED_FIRMWARE_VERSION_DRS2;
}
}
// set constants according to board type
if (fBoardType == 6)
fNumberOfChips = 4;
else
fNumberOfChips = 1;
if (fDRSType == 4)
fNumberOfChannels = 9;
else
fNumberOfChannels = 10;
// retrieve firmware version
if (fDRSType == 2)
fRequiredFirmwareVersion = REQUIRED_FIRMWARE_VERSION_DRS2;
if (fDRSType == 3)
fRequiredFirmwareVersion = REQUIRED_FIRMWARE_VERSION_DRS3;
if (fDRSType == 4)
fRequiredFirmwareVersion = REQUIRED_FIRMWARE_VERSION_DRS4;
fHasMultiBuffer = ((fBoardType == 6) && fTransport == TR_VME);
}
/*------------------------------------------------------------------*/
void DRSBoard::ReadCalibration(void)
{
unsigned short buf[1024*16]; // 32 kB
int i, j, chip;
fVoltageCalibrationValid = false;
fTimingCalibratedFrequency = 0;
memset(fCellOffset, 0, sizeof(fCellOffset));
memset(fCellGain, 0, sizeof(fCellGain));
memset(fCellOffset2, 0, sizeof(fCellOffset2));
memset(fCellDT, 0, sizeof(fCellDT));
/* read offsets and gain from eeprom */
if (fBoardType == 9) {
memset(buf, 0, sizeof(buf));
ReadEEPROM(0, buf, 4096);
/* check voltage calibration method */
if ((buf[2] & 0xFF) == VCALIB_METHOD)
fVoltageCalibrationValid = true;
else {
fCellCalibratedRange = 0;
fCellCalibratedTemperature = -100;
return;
}
/* check timing calibration method */
if ((buf[2] >> 8) == TCALIB_METHOD) {
float fl; // float from two 16-bit integers
memcpy(&fl, &buf[8], sizeof(float));
fTimingCalibratedFrequency = fl;
} else
fTimingCalibratedFrequency = -1;
fCellCalibratedRange = ((int) (buf[10] & 0xFF)) / 100.0; // -50 ... +50 => -0.5 V ... +0.5 V
fCellCalibratedTemperature = (buf[10] >> 8) / 2.0;
ReadEEPROM(1, buf, 1024*32);
for (i=0 ; i<8 ; i++)
for (j=0 ; j<1024; j++) {
fCellOffset[i][j] = buf[(i*1024+j)*2];
fCellGain[i][j] = buf[(i*1024+j)*2 + 1]/65535.0*0.4+0.7;
}
ReadEEPROM(2, buf, 1024*32);
for (i=0 ; i<8 ; i++)
for (j=0 ; j<1024; j++)
fCellOffset2[i][j] = buf[(i*1024+j)*2];
} else if (fBoardType == 5 || fBoardType == 7 || fBoardType == 8) {
memset(buf, 0, sizeof(buf));
ReadEEPROM(0, buf, 32);
/* check voltage calibration method */
if ((buf[2] & 0xFF) == VCALIB_METHOD_V4) // board < 9 has "1", board 9 has "2"
fVoltageCalibrationValid = true;
else {
fCellCalibratedRange = 0;
return;
}
fCellCalibratedTemperature = -100;
/* check timing calibration method */
if ((buf[4] & 0xFF) == TCALIB_METHOD_V4) { // board < 9 has "1", board 9 has "2"
fTimingCalibratedFrequency = buf[6] / 1000.0;
} else
fTimingCalibratedFrequency = -1;
fCellCalibratedRange = ((int) (buf[2] >> 8)) / 100.0; // -50 ... +50 => -0.5 V ... +0.5 V
ReadEEPROM(1, buf, 1024*32);
for (i=0 ; i<8 ; i++)
for (j=0 ; j<1024; j++) {
fCellOffset[i][j] = buf[(i*1024+j)*2];
fCellGain[i][j] = buf[(i*1024+j)*2 + 1]/65535.0*0.4+0.7;
}
ReadEEPROM(2, buf, 1024*5*4);
for (i=0 ; i<1 ; i++)
for (j=0 ; j<1024; j++) {
fCellOffset[i+8][j] = buf[(i*1024+j)*2];
fCellGain[i+8][j] = buf[(i*1024+j)*2 + 1]/65535.0*0.4+0.7;
}
for (i=0 ; i<4 ; i++)
for (j=0 ; j<1024; j++) {
fCellOffset2[i*2][j] = buf[2*1024+(i*1024+j)*2];
fCellOffset2[i*2+1][j] = buf[2*1024+(i*1024+j)*2+1];
}
} else if (fBoardType == 6) {
ReadEEPROM(0, buf, 16);
/* check voltage calibration method */
if ((buf[2] & 0xFF) == VCALIB_METHOD)
fVoltageCalibrationValid = true;
else {
fCellCalibratedRange = 0;
return;
}
/* check timing calibration method */
if ((buf[4] & 0xFF) == TCALIB_METHOD)
fTimingCalibratedFrequency = buf[6] / 1000.0; // 0 ... 6000 => 0 ... 6 GHz
else
fTimingCalibratedFrequency = 0;
fCellCalibratedRange = ((int) (buf[2] >> 8)) / 100.0; // -50 ... +50 => -0.5 V ... +0.5 V
for (chip=0 ; chip<4 ; chip++) {
ReadEEPROM(1+chip, buf, 1024*32);
for (i=0 ; i<8 ; i++)
for (j=0 ; j<1024; j++) {
fCellOffset[i+chip*9][j] = buf[(i*1024+j)*2];
fCellGain[i+chip*9][j] = buf[(i*1024+j)*2 + 1]/65535.0*0.4+0.7;
}
}
ReadEEPROM(5, buf, 1024*4*4);
for (chip=0 ; chip<4 ; chip++)
for (j=0 ; j<1024; j++) {
fCellOffset[8+chip*9][j] = buf[j*2+chip*0x0800];
fCellGain[8+chip*9][j] = buf[j*2+1+chip*0x0800]/65535.0*0.4+0.7;
}
ReadEEPROM(7, buf, 1024*32);
for (i=0 ; i<8 ; i++) {
for (j=0 ; j<1024; j++) {
fCellOffset2[i][j] = buf[i*0x800 + j*2];
fCellOffset2[i+9][j] = buf[i*0x800 + j*2+1];
}
}
ReadEEPROM(8, buf, 1024*32);
for (i=0 ; i<8 ; i++) {
for (j=0 ; j<1024; j++) {
fCellOffset2[i+18][j] = buf[i*0x800 + j*2];
fCellOffset2[i+27][j] = buf[i*0x800 + j*2+1];
}
}
} else
return;
/* read timing calibration from eeprom */
if (fBoardType == 9) {
if (fTimingCalibratedFrequency == 0) {
for (i=0 ; i<8 ; i++)
for (j=0 ; j<1024 ; j++) {
fCellDT[0][i][j] = 1/fNominalFrequency;
}
} else {
ReadEEPROM(2, buf, 1024*32);
for (i=0 ; i<8 ; i++)
for (j=0 ; j<1024; j++) {
fCellDT[0][i][j] = (buf[(i*1024+j)*2+1] - 1000) / 10000.0;
}
}
} else if (fBoardType == 5 || fBoardType == 7 || fBoardType == 8) {
if (fTimingCalibratedFrequency == 0) {
for (i=0 ; i<1024 ; i++)
fCellDT[0][0][i] = 1/fNominalFrequency;
} else {
ReadEEPROM(0, buf, 1024*sizeof(short)*2);