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This repository has been archived by the owner on Dec 1, 2018. It is now read-only.
I think this is the desired behavior. A loop that runs for 0 iters is a noop.
In codegen there is a ctr_trivial signal that is used to mask out any memory enable signals in that controller's subtree, so the register here should just hold its init value or whatever value was written in it already.
I could see the argument for the second case writing 0 to the output register though, since that's considered to be the zero value for the operation and you would probably expect a sum of an empty vector to be zero, for example, instead of undefined.
In the second case, does that zero correspond only to the zero value of the reduce, or does it also set the init value of the Reg that is created? If the Reg takes the default zero value and not the value provided to the Reduce, then I agree we need to do a write. But if we can use it for the init value of the Reg as well then we don't need to do anything
I don't think it gets reset but it's easy to make that the case if that's how we want it. I think I've seen this case in some apps and I put an explicit .reset to be sure.
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Case 1: The contents of
reg
after the loop is effectively unchanged. Is this the desired behavior?Case 2: [Needs to be confirmed] The contents of
out
is still not well defined. Should be 0?The text was updated successfully, but these errors were encountered: