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The implementation of the RISC-V CPU rv32i (integer subset of RISC-V spec) system with a multicycle core.
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Designed by Sparsh Gupta as the final project for Computer Architecture class at Olin College of Engineering - Fall 2023.
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## Instructions Supported
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### R-types
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-[x] add
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-[x] sub
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-[x] xor
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-[x] or
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-[x] and
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-[x] sll
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-[x] srl
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-[x] sra
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-[x] slt
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-[x] sltu
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### I-types
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-[x] addi
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-[x] xori
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-[x] ori
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-[x] andi
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-[x] slli
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-[x] srli
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-[x] srai
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-[x] slti
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-[x] sltiu
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### Memory-Types (Loads/Stores)
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-[x] lw
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-[x] sw
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-[x]*lb*
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-[x]*lh*
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-[x]*lbu*
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-[x]*lhu*
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-[x]*sb*
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-[x]*sh*
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### B-types (Branches)
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-[x] beq
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-[x] bne
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-[x]*blt*
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-[x]*bge*
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-[x]*bltu*
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-[x]*bgeu*
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### J-types (Jumps)
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-[x] jal
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-[x] jalr (technically an i-type)
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### U-types (Upper immediates)
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-[x]*lui*
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-[x]*auipc*
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### Pseudo-Instruction
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-[x]*li*
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## Setup
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**Please skip if you already have a setup_cafe() env configured on your machine.**
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You will need a machine/VM using Linux to simulate this CPU.
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Make sure you have OSS-cad-suite-linux-x64 installed. You can obtain it here: https://www.opensourceagenda.com/projects/oss-cad-suite-build#Installation
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Obtaining Xilinx version 2023.1 and AMD Vivado would also be helpful. (https://www.xilinx.com/support/download.html)
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If you have already completed the above steps, then setting up an environment for these tools is recommended. If you already have an env, make sure it is enabled when simulating the CPU and if you do not, you can set up an env by editing your `~/.bashrc` file.
# Setup variables for synthesis. You may need to change this based on your FPGA board.
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export FPGA_PART=xc7a35tcpg236-1
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export PS1="☕ $PS1"
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}
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# Uncomment this if you aren't using this Linux install for any other projects.
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# setup_cafe;
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```
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Make sure you are in this `submission` directory, then run `./rv32i/tools/check_install` to check whether you have all the necessary dependencies installed and ready.
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Once you have all this setup, configure your pwd to `~/submission/rv32i`. Next, just enter the command `setup_cafe()` or start your personal configured environment.
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## Simulation
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Please change your pwd to `~/submission/rv32i/core/` to access the **Makefile** and be in the same directory level (also make sure you have setup_cafe() enabled). The Makefile is capable of testing instructions and generating waveform simulations for the CPU.
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The first thing to be done is to generate the rv32i simulator, which can be done using below. (the CPU won't work if you skip this step, also if the simulator has already been generated, then this step will just make sure it is up to date)
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```
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make rv32_simulator
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```
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The rv32i assembly scripts are present in the directory `~/submission/rv32i/asm/` to test out different types of instructions.
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For example, to test the `btypes` instructions, simply run the below. This will output the register file state after the operations and will also let you generate waveform simulations for it. The sample register file is also included in the asm (.s) files.
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```
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make test_rv32_btypes
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```
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You can test out other instruction types as well once you take a look at the `Makefile`.
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To generate waveforms for simulating the CPU, make sure you have `gtkwave` installed. Then execute the command below.
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```
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make waves_rv32
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```
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## General Info
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**Components**: The required components to simulate the CPU are all present within the `~/submission/rv32i/core/` directory.
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**Filter Files**: The `~/submission/rv32i/filter_files/` directory houses some `.txt` filter files used in translating waves generated by gtkwave and makes it easier to track signals, etc.
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**Tools**: Some tools that are used in this project, such as an `assembler` to convert assembly (`.s`) files into CPU-executable (`.memh`), the tool to check install, etc. are present in `~/submission/rv32i/tools/`.
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## CPU Schematic
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Note: The schematic does not include the control unit and FSM logic and is just a reference I used for wiring the components.
-[Digital Design & Computer Architecture RISC-V Edition - Sarah L. Harris and David Harris](https://www.sciencedirect.com/book/9780128200643/digital-design-and-computer-architecture)
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