tools: Add option for using HDL blocks during TCL BD development

Author: djepson1

usrp3/tools/make/viv_ip_builder.mak

@@ -78,6 +78,7 @@ BUILD_VIVADO_BD = \
 #       $4 = BDTCL_SRC_DIR (Absolute path to the top level ip src dir)
 #       $5 = BDTCL_BUILD_DIR (Absolute path to the top level ip build dir)
 #       $6 = BD_IP_REPOS (space-separated list of absolute paths to IP repos)
+#       $7 = BD_HDL_SRCS (space-separated list of absolute paths to HDL sources)
 # Prereqs: 
 # - TOOLS_DIR must be defined globally
 # -------------------------------------------------------------------
@@ -89,6 +90,7 @@ BUILD_VIVADO_BDTCL = \
 	export BD_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).tcl); \
 	export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \
 	export BD_IP_REPOS=$(call RESOLVE_PATH,$(6)); \
+	export BD_HDL_SRCS=$(call RESOLVE_PATHS,$(7)); \
 	echo "BUILDER: Staging BD Tcl in build directory..."; \
 	rm $(5)/$(1)/* -rf; \
 	$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \

usrp3/tools/scripts/viv_generate_bd.tcl

@@ -14,34 +14,55 @@ if {[info exists env(BD_IP_REPOS)]} {
 } else {
     set ip_repos {}
 }
+if {[info exists env(BD_HDL_SRCS)]} {
+    set hdl_sources $::env(BD_HDL_SRCS);# Any supporting HDL files
+} else {
+    set hdl_sources {}
+}
 
 # Delete any previous output cookie file
 file delete -force "$bd_file.out"
 # ---------------------------------------
 # Vivado Commands
 # ---------------------------------------
+create_project -part $part_name -in_memory
+# In non-project mode, the hierarchy must be updated for the HDL source files to be
+# correctly applied to the BD. See AR:
+# https://www.xilinx.com/support/answers/63488.html
+set_property source_mgmt_mode All [current_project]
+set_property ip_repo_paths "{$ip_repos}" [current_project]
+update_ip_catalog
+# Add supplementary HDL sources, if they exist.
+foreach src_file $hdl_sources {
+    set hdl_ext [file extension $src_file ]
+    if [expr [lsearch {.vhd .vhdl} $hdl_ext] >= 0] {
+        puts "BUILDER: Adding VHDL    : $src_file"
+        read_vhdl -library work $src_file
+    } elseif [expr [lsearch {.v .vh} $hdl_ext] >= 0] {
+        puts "BUILDER: Adding Verilog : $src_file"
+        read_verilog $src_file
+    } else {
+        puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
+    }
+}
+# Open .tcl or .bd design directly.
 if [expr [lsearch {.tcl} $src_ext] >= 0] {
     puts "BUILDER: Generating Block Diagram from script: $bd_file"
-    create_project -part $part_name -in_memory
-    set_property ip_repo_paths "{$ip_repos}" [current_project]
-    update_ip_catalog
     create_bd_design -dir . $bd_name
     source $bd_file
     report_ip_status
     puts "BUILDER: Report_ip_status done"
     set bd_file $bd_name.bd
 } else {
     puts "BUILDER: Adding Block Diagram: $bd_file"
-    create_project -part $part_name -in_memory
-    set_property ip_repo_paths "{$ip_repos}" [current_project]
-    update_ip_catalog
     add_files -norecurse $bd_file
     puts "BUILDER: Generating BD Target first pass..."
     generate_target all [get_files $bd_file] -force
     report_ip_status
     puts "BUILDER: Report_ip_status done"
     open_bd_design $bd_file
 }
+# Generate outputs.
 puts "BUILDER: Generating BD Target..."
 generate_target all [get_files $bd_file]
 puts "BUILDER: Generate all done"

usrp3/tools/scripts/viv_ip_utils.tcl

@@ -75,6 +75,7 @@ if { [string compare $cmd "create"] == 0 } {
     set src_rootname [file rootname [file tail $src_file]]
     set src_ext [file extension $src_file ]
     set ip_repos [lindex $argv 3]
+    set hdl_sources "[file dirname $src_file]/hdl_sources.tcl"
     if [expr [lsearch {.tcl} $src_ext] >= 0] {
         # Create a temporary project to work on.
         set tmp_bddir "${sys_tmpdir}/.viv_${src_rootname}"
@@ -84,6 +85,12 @@ if { [string compare $cmd "create"] == 0 } {
         create_project tmp_bd $tmp_bddir -part $part_name -force
         set_property ip_repo_paths "{$ip_repos}" [current_project]
         update_ip_catalog
+        # Add any supporting HDL first
+        if {[file exists $hdl_sources] == 1} {
+          source $hdl_sources
+        } else {
+          puts "hdl_sources.tcl not found in IP directory. Skipping HDL import for BD design"
+        }
         # Recreate BD design from source file (.tcl)
         source $src_file
         regenerate_bd_layout