From 93f866cf66315bd7a33e914cfa7898508b5911ad Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Thu, 11 Jul 2024 20:44:35 -0400 Subject: [PATCH 1/2] round 1 of slang lint --- scgallery/designs/aes/aes.py | 2 ++ scgallery/designs/ariane/src/ariane.sv2v.v | 4 ++-- scgallery/designs/black_parrot/src/pickled.v | 2 +- scgallery/designs/ibex/ibex.py | 9 +++------ scgallery/designs/tiny_rocket/extra/lambda.v | 10 +++++----- 5 files changed, 13 insertions(+), 14 deletions(-) diff --git a/scgallery/designs/aes/aes.py b/scgallery/designs/aes/aes.py index d50da78..f85b6cc 100755 --- a/scgallery/designs/aes/aes.py +++ b/scgallery/designs/aes/aes.py @@ -31,6 +31,8 @@ def setup(target=asap7_demo): 'aes_sbox.v'): chip.input(os.path.join(src_root, src), package='scgallery-designs') + chip.add('option', 'idir', src_root, package='scgallery-designs') + if not chip.get('option', 'target'): chip.load_target(target) diff --git a/scgallery/designs/ariane/src/ariane.sv2v.v b/scgallery/designs/ariane/src/ariane.sv2v.v index 3f54bb5..42e9ee0 100644 --- a/scgallery/designs/ariane/src/ariane.sv2v.v +++ b/scgallery/designs/ariane/src/ariane.sv2v.v @@ -51684,7 +51684,7 @@ module instr_scan output rvc_call_o; wire [63:0] rvi_imm_o,rvc_imm_o; wire is_rvc_o,rvi_return_o,rvi_call_o,rvi_branch_o,rvi_jalr_o,rvi_jump_o, - rvc_branch_o,rvc_jump_o,rvc_jr_o,rvc_return_o,rvc_jalr_o,rvc_call_o,N0,N1,rvc_jalr_o,N2,N3, + rvc_branch_o,rvc_jump_o,rvc_jr_o,rvc_return_o,rvc_jalr_o,rvc_call_o,N0,N1,N2,N3, N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24, N25,N26,N27,N28,N29,N30,N31,N32,N33,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45, N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65, @@ -228233,7 +228233,7 @@ module controller output flush_tlb_o; output halt_o; wire set_pc_commit_o,flush_if_o,flush_unissued_instr_o,flush_id_o,flush_ex_o, - flush_icache_o,flush_tlb_o,halt_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,flush_if_o,flush_ex_o, + flush_icache_o,flush_tlb_o,halt_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9, fence_active_d,flush_dcache,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22, N23,N24,N25,N26,N27,N28,N29,N30,N31,N32; reg flush_dcache_o,fence_active_q; diff --git a/scgallery/designs/black_parrot/src/pickled.v b/scgallery/designs/black_parrot/src/pickled.v index 9ae1688..5bd7d93 100644 --- a/scgallery/designs/black_parrot/src/pickled.v +++ b/scgallery/designs/black_parrot/src/pickled.v @@ -86964,7 +86964,7 @@ module bp_cce_gad_num_way_groups_p64_num_lce_p2_lce_assoc_p8_tag_width_p10_harde wire [5:0] sharers_ways_o; wire [3:0] sharers_coh_states_o; wire transfer_flag_o,replacement_flag_o,upgrade_flag_o,invalidate_flag_o, - exclusive_flag_o,N0,N1,N2,N3,N4,exclusive_flag_o,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16, + exclusive_flag_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16, N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36, N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56, N57,N58,N59,hit,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75, diff --git a/scgallery/designs/ibex/ibex.py b/scgallery/designs/ibex/ibex.py index 1f6a596..4a95d90 100755 --- a/scgallery/designs/ibex/ibex.py +++ b/scgallery/designs/ibex/ibex.py @@ -44,12 +44,9 @@ def setup(target=asap7_demo): 'ibex_csr.sv', 'ibex_wb_stage.sv',): chip.input(os.path.join('rtl', src), package='ibex') - for src in ('hw/ip/prim/rtl/prim_assert.sv',): - chip.input(src, package='opentitan') - chip.input('hw/dv/sv/dv_utils/dv_fcov_macros.svh', - fileset='rtl', - filetype='verilog', - package='opentitan') + + chip.add('option', 'idir', 'hw/ip/prim/rtl', package='opentitan') + chip.add('option', 'idir', 'hw/dv/sv/dv_utils', package='opentitan') chip.add('option', 'define', 'SYNTHESIS') diff --git a/scgallery/designs/tiny_rocket/extra/lambda.v b/scgallery/designs/tiny_rocket/extra/lambda.v index adf0fcc..0484037 100644 --- a/scgallery/designs/tiny_rocket/extra/lambda.v +++ b/scgallery/designs/tiny_rocket/extra/lambda.v @@ -84,7 +84,7 @@ module data_arrays_0_0_ext( input [5:0] RW0_addr, input RW0_en, input RW0_wmode, - input [0:0] RW0_wmask, + input RW0_wmask, input [31:0] RW0_wdata, output [31:0] RW0_rdata ); @@ -95,10 +95,10 @@ module data_arrays_0_0_ext( .dout (RW0_rdata ), .ce (RW0_en ), .we (RW0_wmode ), - .wmask({ {8{RW0_wmask[3]}} - ,{8{RW0_wmask[2]}} - ,{8{RW0_wmask[1]}} - ,{8{RW0_wmask[0]}}} + .wmask({ {8{RW0_wmask}} + ,{8{RW0_wmask}} + ,{8{RW0_wmask}} + ,{8{RW0_wmask}}} ), .addr (RW0_addr ), .din (RW0_wdata ) From 2837f894b9ac64fe7f62029acc9045657c3ad82b Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Fri, 12 Jul 2024 08:26:38 -0400 Subject: [PATCH 2/2] cleanup gcd lint --- scgallery/designs/gcd/src/gcd.v | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/scgallery/designs/gcd/src/gcd.v b/scgallery/designs/gcd/src/gcd.v index 605122d..47a2a5b 100644 --- a/scgallery/designs/gcd/src/gcd.v +++ b/scgallery/designs/gcd/src/gcd.v @@ -6,7 +6,6 @@ // friendly to OpenROAD tools // // dump-vcd: False -// verilator-xinit: zeros //module GcdUnit module gcd ( @@ -105,7 +104,6 @@ endmodule // GcdUnit // GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e //----------------------------------------------------------------------------- // dump-vcd: False -// verilator-xinit: zeros module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e ( output reg [ 1:0] a_mux_sel, @@ -276,6 +274,8 @@ module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e // logic for state_outputs() always @ (*) begin current_state__1 = state$out; + do_swap = is_a_lt_b; + do_sub = ~is_b_zero; if ((current_state__1 == STATE_IDLE)) begin req_rdy = 1; resp_val = 0; @@ -286,8 +286,6 @@ module GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e end else begin if ((current_state__1 == STATE_CALC)) begin - do_swap = is_a_lt_b; - do_sub = ~is_b_zero; req_rdy = 0; resp_val = 0; a_mux_sel = do_swap ? A_MUX_SEL_B : A_MUX_SEL_SUB; @@ -325,7 +323,6 @@ endmodule // GcdUnitCtrlRTL_0x4d0fc71ead8d3d9e // dtype: 2 // reset_value: 0 // dump-vcd: False -// verilator-xinit: zeros module RegRst_0x9f365fdf6c8998a ( input wire [ 0:0] clk, @@ -365,7 +362,6 @@ endmodule // RegRst_0x9f365fdf6c8998a // GcdUnitDpathRTL_0x4d0fc71ead8d3d9e //----------------------------------------------------------------------------- // dump-vcd: False -// verilator-xinit: zeros module GcdUnitDpathRTL_0x4d0fc71ead8d3d9e ( input wire [ 1:0] a_mux_sel, @@ -548,7 +544,6 @@ endmodule // GcdUnitDpathRTL_0x4d0fc71ead8d3d9e //----------------------------------------------------------------------------- // dtype: 16 // dump-vcd: False -// verilator-xinit: zeros module RegEn_0x68db79c4ec1d6e5b ( input wire [ 0:0] clk, @@ -584,7 +579,6 @@ endmodule // RegEn_0x68db79c4ec1d6e5b //----------------------------------------------------------------------------- // nbits: 16 // dump-vcd: False -// verilator-xinit: zeros module LtComparator_0x422b1f52edd46a85 ( input wire [ 0:0] clk, @@ -615,7 +609,6 @@ endmodule // LtComparator_0x422b1f52edd46a85 //----------------------------------------------------------------------------- // nbits: 16 // dump-vcd: False -// verilator-xinit: zeros module ZeroComparator_0x422b1f52edd46a85 ( input wire [ 0:0] clk, @@ -646,7 +639,6 @@ endmodule // ZeroComparator_0x422b1f52edd46a85 // dtype: 16 // nports: 3 // dump-vcd: False -// verilator-xinit: zeros module Mux_0x683fa1a418b072c9 ( input wire [ 0:0] clk, @@ -689,7 +681,6 @@ endmodule // Mux_0x683fa1a418b072c9 // dtype: 16 // nports: 2 // dump-vcd: False -// verilator-xinit: zeros module Mux_0xdd6473406d1a99a ( input wire [ 0:0] clk, @@ -729,7 +720,6 @@ endmodule // Mux_0xdd6473406d1a99a //----------------------------------------------------------------------------- // nbits: 16 // dump-vcd: False -// verilator-xinit: zeros module Subtractor_0x422b1f52edd46a85 ( input wire [ 0:0] clk,